no-OS
ad3552r.h
Go to the documentation of this file.
1 /**************************************************************************/
43 #ifndef _AD3552R_H_
44 #define _AD3552R_H_
45 
46 /*****************************************************************************/
47 /***************************** Include Files *********************************/
48 /*****************************************************************************/
49 
50 #include <stdint.h>
51 #include <stdbool.h>
52 #include "no_os_spi.h"
53 #include "no_os_gpio.h"
54 #include "no_os_crc8.h"
55 
56 /*****************************************************************************/
57 /******************** Macros and Constants Definitions ***********************/
58 /*****************************************************************************/
59 
60 /* Register addresses */
61 /* Primary address space */
62 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_A 0x00
63 #define AD3552R_MASK_SOFTWARE_RESET (NO_OS_BIT(7) | NO_OS_BIT(0))
64 #define AD3552R_MASK_ADDR_ASCENSION NO_OS_BIT(5)
65 #define AD3552R_MASK_SDO_ACTIVE NO_OS_BIT(4)
66 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_B 0x01
67 #define AD3552R_MASK_SINGLE_INST NO_OS_BIT(7)
68 #define AD3552R_MASK_SHORT_INSTRUCTION NO_OS_BIT(3)
69 #define AD3552R_REG_ADDR_DEVICE_CONFIG 0x02
70 #define AD3552R_MASK_DEVICE_STATUS(n) NO_OS_BIT(4 + (n))
71 #define AD3552R_MASK_CUSTOM_MODES (NO_OS_BIT(3) | NO_OS_BIT(2))
72 #define AD3552R_MASK_OPERATING_MODES NO_OS_GENMASK(1, 0)
73 #define AD3552R_REG_ADDR_CHIP_TYPE 0x03
74 #define AD3552R_MASK_CLASS NO_OS_GENMASK(7, 0)
75 #define AD3552R_REG_ADDR_PRODUCT_ID_L 0x04
76 #define AD3552R_REG_ADDR_PRODUCT_ID_H 0x05
77 #define AD3552R_REG_ADDR_CHIP_GRADE 0x06
78 #define AD3552R_MASK_GRADE NO_OS_GENMASK(7, 4)
79 #define AD3552R_MASK_DEVICE_REVISION NO_OS_GENMASK(3, 0)
80 #define AD3552R_REG_ADDR_SCRATCH_PAD 0x0A
81 #define AD3552R_REG_ADDR_SPI_REVISION 0x0B
82 #define AD3552R_REG_ADDR_VENDOR_L 0x0C
83 #define AD3552R_REG_ADDR_VENDOR_H 0x0D
84 #define AD3552R_REG_ADDR_STREAM_MODE 0x0E
85 #define AD3552R_MASK_LENGTH 0xFF
86 #define AD3552R_REG_ADDR_TRANSFER_REGISTER 0x0F
87 #define AD3552R_MASK_MULTI_IO_MODE (NO_OS_BIT(7) | NO_OS_BIT(6))
88 #define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE NO_OS_BIT(2)
89 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_C 0x10
90 #define AD3552R_MASK_CRC_ENABLE (NO_OS_BIT(7) | NO_OS_BIT(6) | NO_OS_BIT(1) | NO_OS_BIT(0))
91 #define AD3552R_MASK_STRICT_REGISTER_ACCESS NO_OS_BIT(5)
92 #define AD3552R_REG_ADDR_INTERFACE_STATUS_A 0x11
93 #define AD3552R_MASK_INTERFACE_NOT_READY NO_OS_BIT(7)
94 #define AD3552R_MASK_CLOCK_COUNTING_ERROR NO_OS_BIT(5)
95 #define AD3552R_MASK_INVALID_OR_NO_CRC NO_OS_BIT(3)
96 #define AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER NO_OS_BIT(2)
97 #define AD3552R_MASK_PARTIAL_REGISTER_ACCESS NO_OS_BIT(1)
98 #define AD3552R_MASK_REGISTER_ADDRESS_INVALID NO_OS_BIT(0)
99 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_D 0x14
100 #define AD3552R_MASK_ALERT_ENABLE_PULLUP NO_OS_BIT(6)
101 #define AD3552R_MASK_MEM_CRC_EN NO_OS_BIT(4)
102 #define AD3552R_MASK_SDO_DRIVE_STRENGTH (NO_OS_BIT(3) | NO_OS_BIT(2))
103 #define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN NO_OS_BIT(1)
104 #define AD3552R_MASK_SPI_CONFIG_DDR NO_OS_BIT(0)
105 #define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG 0x15
106 #define AD3552R_MASK_IDUMP_FAST_MODE NO_OS_BIT(6)
107 #define AD3552R_MASK_SAMPLE_HOLD_DIFFERENTIAL_USER_EN NO_OS_BIT(5)
108 #define AD3552R_MASK_SAMPLE_HOLD_USER_TRIM (NO_OS_BIT(4) | NO_OS_BIT(3))
109 #define AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE NO_OS_BIT(2)
110 #define AD3552R_MASK_REFERENCE_VOLTAGE_SEL (NO_OS_BIT(1) | NO_OS_BIT(0))
111 #define AD3552R_REG_ADDR_ERR_ALARM_MASK 0x16
112 #define AD3552R_MASK_REF_RANGE_ALARM NO_OS_BIT(6)
113 #define AD3552R_MASK_CLOCK_COUNT_ERR_ALARM NO_OS_BIT(5)
114 #define AD3552R_MASK_MEM_CRC_ERR_ALARM NO_OS_BIT(4)
115 #define AD3552R_MASK_SPI_CRC_ERR_ALARM NO_OS_BIT(3)
116 #define AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM NO_OS_BIT(2)
117 #define AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM NO_OS_BIT(1)
118 #define AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM NO_OS_BIT(0)
119 #define AD3552R_REG_ADDR_ERR_STATUS 0x17
120 #define AD3552R_MASK_REF_RANGE_ERR_STATUS NO_OS_BIT(6)
121 #define AD3552R_MASK_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS NO_OS_BIT(5)
122 #define AD3552R_MASK_MEM_CRC_ERR_STATUS NO_OS_BIT(4)
123 #define AD3552R_MASK_RESET_STATUS NO_OS_BIT(0)
124 #define AD3552R_REG_ADDR_POWERDOWN_CONFIG 0x18
125 #define AD3552R_MASK_CH_DAC_POWERDOWN(ch) NO_OS_BIT(4 + (ch))
126 #define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch) NO_OS_BIT(ch)
127 #define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE 0x19
128 #define AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch) ((ch) ? 0xF0 : 0xF)
129 #define AD3552R_REG_ADDR_CH_OFFSET(ch) (0x1B + (ch) * 2)
130 #define AD3552R_MASK_CH_OFFSET_BITS_0_7 0xFF
131 #define AD3552R_REG_ADDR_CH_GAIN(ch) (0x1C + (ch) * 2)
132 #define AD3552R_MASK_CH_RANGE_OVERRIDE NO_OS_BIT(7)
133 #define AD3552R_MASK_CH_GAIN_SCALING_N (NO_OS_BIT(6) | NO_OS_BIT(5))
134 #define AD3552R_MASK_CH_GAIN_SCALING_P (NO_OS_BIT(4) | NO_OS_BIT(3))
135 #define AD3552R_MASK_CH_OFFSET_POLARITY NO_OS_BIT(2)
136 #define AD3552R_MASK_CH_OFFSET_BIT_8 NO_OS_BIT(0)
137 
138 /*
139  * Secondary region
140  * For multibyte registers specify the highest address because the access is
141  * done in descending order
142  */
143 #define AD3552R_SECONDARY_REGION_START 0x28
144 #define AD3552R_REG_ADDR_HW_LDAC_16B 0x28
145 #define AD3552R_REG_ADDR_CH_DAC_16B(ch) (0x2C - (1 - ch) * 2)
146 #define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B 0x2E
147 #define AD3552R_REG_ADDR_CH_SELECT_16B 0x2F
148 #define AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B 0x31
149 #define AD3552R_REG_ADDR_SW_LDAC_16B 0x32
150 #define AD3552R_REG_ADDR_CH_INPUT_16B(ch) (0x36 - (1 - ch) * 2)
151 /* 3 bytes registers */
152 #define AD3552R_REG_START_24B 0x37
153 #define AD3552R_REG_ADDR_HW_LDAC_24B 0x37
154 #define AD3552R_REG_ADDR_CH_DAC_24B(ch) (0x3D - (1 - ch) * 3)
155 #define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B 0x40
156 #define AD3552R_REG_ADDR_CH_SELECT_24B 0x41
157 #define AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B 0x44
158 #define AD3552R_REG_ADDR_SW_LDAC_24B 0x45
159 #define AD3552R_REG_ADDR_CH_INPUT_24B(ch) (0x4B - (1 - ch) * 3)
160 
161 #define AD3552R_REG_ADDR_MAX 0x4B
162 
163 /* Useful defines */
164 #define AD3552R_NUM_CH 2
165 #define AD3552R_MASK_CH(ch) NO_OS_BIT(ch)
166 #define AD3552R_MASK_ALL_CH (NO_OS_BIT(0) | NO_OS_BIT(1))
167 #define AD3552R_MASK_DAC_12B 0xFFF0
168 #define AD3552R_REAL_BITS_PREC_MODE 16
169 #define AD3552R_STORAGE_BITS_PREC_MODE 24
170 #define AD3552R_REAL_BITS_FAST_MODE 12
171 #define AD3552R_STORAGE_BITS_FAST_MODE 16
172 #define AD3552R_MAX_OFFSET 511
173 #define AD3552R_LDAC_PULSE_US 1
174 
175 /******************************************************************************/
176 /*************************** Types Declarations *******************************/
177 /******************************************************************************/
178 
182 };
183 
185  /* Internal source with Vref I/O floating */
187  /* Internal source with Vref I/O at 2.5V */
189  /* External source with Vref I/O as input */
191 };
192 
194  /* Status bits */
197 
198  /* Errors */
207 };
208 
210  /* Range from 0 V to 2.5 V. Requires Rfb1x connection */
212  /* Range from 0 V to 5 V. Requires Rfb1x connection */
214  /* Range from 0 V to 10 V. Requires Rfb2x connection */
216  /* Range from -2.5 V to 7.5 V. Requires Rfb2x connection */
218  /* Range from -6.5 V to 3.5 V. Requires Rfb4x connection */
220 };
221 
223  /* Range from 0 V to 2.5 V. Requires Rfb1x connection */
225  /* Range from 0 V to 3 V. Requires Rfb1x connection */
227  /* Range from 0 V to 5 V. Requires Rfb1x connection */
229  /* Range from 0 V to 10 V. Requires Rfb2x connection */
231  /* Range from -2.5 V to 7.5 V. Requires Rfb2x connection */
233  /* Range from -6.5 V to 3.5 V. Requires Rfb4x connection */
235 };
236 
237 #define AD3552R_CH_OUTPUT_RANGE_CUSTOM 100
238 
240  /* Gain scaling of 1 */
242  /* Gain scaling of 0.5 */
244  /* Gain scaling of 0.25 */
246  /* Gain scaling of 0.125 */
248 };
249 
251  /* Positive offset */
253  /* Negative offset */
255 };
256 
258  /* Direct register values */
259  /* From 0-3 */
261  /*
262  * 0 -> Internal Vref, vref_io pin floating (default)
263  * 1 -> Internal Vref, vref_io driven by internal vref
264  * 2 or 3 -> External Vref
265  */
267  /* Enable / Disable CRC */
269 #ifdef AD3552R_QSPI_IMPLEMENTED
270  /* Spi mode: Strandard, Dual or Quad */
271  AD3552R_SPI_MULTI_IO_MODE,
272  /* Spi data rate: Single or dual */
273  AD3552R_SPI_DATA_RATE,
274  /* Dual spi synchronous mode */
275  AD3552R_SPI_SYNCHRONOUS_ENABLE,
276 #endif
277 };
278 
280  /* DAC powerdown */
282  /* DAC amplifier powerdown */
284  /* Select from enum ad3552r_ch_output_range or ad3542r_ch_output_range */
286  /*
287  * Over-rider the range selector in order to manually set the output
288  * voltage range
289  */
291  /* Manually set the offset voltage */
293  /* Sets the polarity of the offset. */
295  /* PDAC gain scaling */
297  /* NDAC gain scaling */
299  /* Trigger a software LDAC */
301  /* Hardware LDAC Mask */
303  /* Rfb value */
305  /* Write to fast regs (only 12 bits of data) */
307  /* Channel select. When set allow Input -> DAC and Mask -> DAC */
309  /* Raw value to be set to dac */
311 };
312 
314  /* Write to DAC registers. No need to trigger LDAC */
316  /* Write to input registers. User needs to trigger LDAC */
318  /* Write to input registers. LDAC is triggered by the driver */
320 };
321 
322 /* By default all values are set to 0 */
324  /* Defines the length of the loop when streaming data */
326  /* Determines Sequential Addressing Behavior */
327  uint8_t addr_asc : 1;
328  /* Select Streaming or Single Instruction Mode */
329  uint8_t single_instr: 1;
330  /*
331  * Set this bit to prevent the STREAM_MODE LENGTH value from
332  * automatically resetting to zero
333  */
335 #ifdef AD3552R_QSPI_IMPLEMENTED
336  /* Controls the SPI. Single (0), Dual (1), Quad (2)*/
337  uint8_t multi_io_mode : 2;
338  /*
339  * When this bIt is set, the DAC word is expected in
340  * Double Data Rate(DDR) configuration
341  */
342  uint8_t ddr : 1;
343  /*
344  * When this bit is set the SPI interface is expected as a dual
345  * synchronous configuration
346  */
347  uint8_t synchronous : 1;
348 #endif
349 };
350 
352  /* Starting address for transfer */
353  uint8_t addr;
354  /* Data to transfer */
355  uint8_t *data;
356  /* Size of data to transfer */
357  uint32_t len;
358  /* Read transaction if true, write transfer otherwise */
359  uint8_t is_read : 1;
360  /* If NULL will be default or last configured will be used */
362 };
363 
365  int32_t scale_int;
366  int32_t scale_dec;
367  int32_t offset_int;
368  int32_t offset_dec;
369  int16_t gain_offset;
370  uint16_t offset;
372  uint16_t rfb;
373  uint8_t n;
374  uint8_t p;
375  uint8_t range;
376  uint8_t range_override;
377  uint8_t fast_en;
378 };
379 
380 struct ad3552r_desc {
387  uint8_t chip_id;
388  uint8_t crc_en : 1;
389 };
390 
392  int16_t gain_offset;
393  /* GainP = 1 / ( 2 ^ gain_scaling_p_inv_log2)
394  From 0 to 3 */
396  /* GainP = 1 / ( 2 ^ gain_scaling_n_inv_log2)
397  From 0 to 3 */
399  /* RFB value */
400  uint8_t rfb_ohms;
401 };
402 
404  bool en;
405  /* Use only 12 bits precision instead of 16 for data. */
406  bool fast_en;
407  /*
408  * Use enum ad3552r_ch_ouput_range or ad3542r_ch_output_range
409  * (Depending on id), or AD3552R_CH_OUTPUT_RANGE_CUSTOM to configure
410  * using custom_output_range.
411  */
412  uint8_t range;
414 };
415 
419  /* If set, reset is done with RESET pin, otherwise it will be soft */
421  /* If set, input register are used and LDAC pulse is sent */
423  /* If set, use external Vref */
425  /* If set, output internal Vref on Vref pin */
427  /* From 0 to 3 */
430  /* Set to enable CRC */
431  bool crc_en;
432 };
433 
434 /*****************************************************************************/
435 /************************* Functions Declarations ****************************/
436 /*****************************************************************************/
437 
438 int32_t ad3552r_init(struct ad3552r_desc **desc,
440 
441 int32_t ad3552r_remove(struct ad3552r_desc *desc);
442 
443 int32_t ad3552r_reset(struct ad3552r_desc *desc);
444 
445 /* Get status and error bits. If clear_errors is set, errors will be cleared */
446 int32_t ad3552r_get_status(struct ad3552r_desc *desc, uint32_t *status,
447  uint8_t clr_err);
448 
449 int32_t ad3552r_transfer(struct ad3552r_desc *desc,
450  struct ad3552_transfer_data *data);
451 
452 int32_t ad3552r_write_reg(struct ad3552r_desc *desc, uint8_t addr,
453  uint16_t val);
454 
455 int32_t ad3552r_read_reg(struct ad3552r_desc *desc, uint8_t addr,
456  uint16_t *val);
457 
458 int32_t ad3552r_get_dev_value(struct ad3552r_desc *desc,
459  enum ad3552r_dev_attributes attr,
460  uint16_t *val);
461 
462 int32_t ad3552r_set_dev_value(struct ad3552r_desc *desc,
463  enum ad3552r_dev_attributes attr,
464  uint16_t val);
465 
466 int32_t ad3552r_get_ch_value(struct ad3552r_desc *desc,
467  enum ad3552r_ch_attributes attr,
468  uint8_t ch,
469  uint16_t *val);
470 
471 int32_t ad3552r_set_ch_value(struct ad3552r_desc *desc,
472  enum ad3552r_ch_attributes attr,
473  uint8_t ch,
474  uint16_t val);
475 
476 int32_t ad3552r_get_scale(struct ad3552r_desc *desc, uint8_t ch,
477  int32_t *integer, int32_t *dec);
478 
479 int32_t ad3552r_get_offset(struct ad3552r_desc *desc, uint8_t ch,
480  int32_t *integer, int32_t *dec);
481 
482 int32_t ad3552r_ldac_trigger(struct ad3552r_desc *desc, uint16_t mask);
483 
484 /* Send one sample at a time, one after an other or at a LDAC_period interval.
485  * If LDAC pin set, send LDAC signal. Otherwise software LDAC is used. */
486 int32_t ad3552r_write_samples(struct ad3552r_desc *desc, uint16_t *data,
487  uint32_t samples, uint32_t ch_mask,
488  enum ad3552r_write_mode mode);
489 
490 #endif /* _AD3552R_H_ */
AD3552R_WRITE_DAC_REGS
@ AD3552R_WRITE_DAC_REGS
Definition: ad3552r.h:315
AD3552R_REG_ADDR_POWERDOWN_CONFIG
#define AD3552R_REG_ADDR_POWERDOWN_CONFIG
Definition: ad3552r.h:124
AD3552R_MASK_SPI_CONFIG_DDR
#define AD3552R_MASK_SPI_CONFIG_DDR
Definition: ad3552r.h:104
ad3552r_transfer
int32_t ad3552r_transfer(struct ad3552r_desc *desc, struct ad3552_transfer_data *data)
Definition: ad3552r.c:412
ad3552r_desc::spi
struct no_os_spi_desc * spi
Definition: ad3552r.h:382
no_os_put_unaligned_be16
void no_os_put_unaligned_be16(uint16_t val, uint8_t *buf)
AD3552R_CH_FAST_EN
@ AD3552R_CH_FAST_EN
Definition: ad3552r.h:306
AD3552R_CH_RANGE_OVERRIDE
@ AD3552R_CH_RANGE_OVERRIDE
Definition: ad3552r.h:290
timeout
uint32_t timeout
Definition: ad413x.c:54
ad3552r_init
int32_t ad3552r_init(struct ad3552r_desc **desc, struct ad3552r_init_param *param)
Definition: ad3552r.c:1066
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN
#define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN
Definition: ad3552r.h:103
AD3552R_SCRATCH_PAD_TEST_VAL1
#define AD3552R_SCRATCH_PAD_TEST_VAL1
Definition: ad3552r.c:90
AD3552R_MASK_INTERFACE_NOT_READY
#define AD3552R_MASK_INTERFACE_NOT_READY
Definition: ad3552r.h:93
AD3552R_CH_GAIN_SCALING_N
@ AD3552R_CH_GAIN_SCALING_N
Definition: ad3552r.h:298
AD3552R_REG_ADDR_MAX
#define AD3552R_REG_ADDR_MAX
Definition: ad3552r.h:161
AD3552R_REGISTER_ADDRESS_INVALID
@ AD3552R_REGISTER_ADDRESS_INVALID
Definition: ad3552r.h:203
AD3552R_MASK_SDO_DRIVE_STRENGTH
#define AD3552R_MASK_SDO_DRIVE_STRENGTH
Definition: ad3552r.h:102
ad3552r_desc::reset
struct no_os_gpio_desc * reset
Definition: ad3552r.h:384
ad3552r_desc::crc_table
uint8_t crc_table[NO_OS_CRC8_TABLE_SIZE]
Definition: ad3552r.h:386
AD3552R_READ_BIT
#define AD3552R_READ_BIT
Definition: ad3552r.c:79
AD3552R_INTERFACE_NOT_READY
@ AD3552R_INTERFACE_NOT_READY
Definition: ad3552r.h:196
AD3552R_CRC_ENABLE
@ AD3552R_CRC_ENABLE
Definition: ad3552r.h:268
AD3552R_REG_ADDR_CH_INPUT_16B
#define AD3552R_REG_ADDR_CH_INPUT_16B(ch)
Definition: ad3552r.h:150
ad3552r_set_dev_value
int32_t ad3552r_set_dev_value(struct ad3552r_desc *desc, enum ad3552r_dev_attributes attr, uint16_t val)
Definition: ad3552r.c:564
ad3552r_init
int32_t ad3552r_init(struct ad3552r_desc **desc, struct ad3552r_init_param *init_param)
Definition: ad3552r.c:1066
AD3552R_REG_ADDR_CH_SELECT_24B
#define AD3552R_REG_ADDR_CH_SELECT_24B
Definition: ad3552r.h:156
ad3552r_offset_polarity
ad3552r_offset_polarity
Definition: ad3552r.h:250
AD3552R_REG_ADDR_CH_DAC_16B
#define AD3552R_REG_ADDR_CH_DAC_16B(ch)
Definition: ad3552r.h:145
ad3552r_ch_output_range
ad3552r_ch_output_range
Definition: ad3552r.h:209
AD3552R_MEM_CRC_ERR_STATUS
@ AD3552R_MEM_CRC_ERR_STATUS
Definition: ad3552r.h:206
AD3552R_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS
@ AD3552R_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS
Definition: ad3552r.h:205
AD3552R_LDAC_PULSE_US
#define AD3552R_LDAC_PULSE_US
Definition: ad3552r.h:173
AD3552R_CH_DAC_POWERDOWN
@ AD3552R_CH_DAC_POWERDOWN
Definition: ad3552r.h:281
no_os_spi.h
Header file of SPI Interface.
ad3552r_read_reg
int32_t ad3552r_read_reg(struct ad3552r_desc *desc, uint8_t addr, uint16_t *val)
Definition: ad3552r.c:471
AD3552R_MASK_CH_GAIN_SCALING_P
#define AD3552R_MASK_CH_GAIN_SCALING_P
Definition: ad3552r.h:134
ad3552r_ch_data::fast_en
uint8_t fast_en
Definition: ad3552r.h:377
AD3552R_CH_GAIN_SCALING_0_125
@ AD3552R_CH_GAIN_SCALING_0_125
Definition: ad3552r.h:247
ad3552r_ch_data::range_override
uint8_t range_override
Definition: ad3552r.h:376
ad3552_transfer_config::single_instr
uint8_t single_instr
Definition: ad3552r.h:329
AD3552R_CRC_ENABLE_VALUE
#define AD3552R_CRC_ENABLE_VALUE
Definition: ad3552r.c:81
AD3552R_MASK_SOFTWARE_RESET
#define AD3552R_MASK_SOFTWARE_RESET
Definition: ad3552r.h:63
ad3552r_read_reg
int32_t ad3552r_read_reg(struct ad3552r_desc *desc, uint8_t addr, uint16_t *val)
Definition: ad3552r.c:471
pr_err
#define pr_err(fmt, args...)
Definition: no_os_print_log.h:80
ad3552_transfer_data::addr
uint8_t addr
Definition: ad3552r.h:353
ad3552r_init_param::ldac_gpio_param_optional
struct no_os_gpio_init_param * ldac_gpio_param_optional
Definition: ad3552r.h:422
AD3552R_CRC_SEED
#define AD3552R_CRC_SEED
Definition: ad3552r.c:85
no_os_spi_msg
Definition: no_os_spi.h:90
NO_OS_IS_ERR_VALUE
#define NO_OS_IS_ERR_VALUE(x)
Definition: no_os_error.h:56
ad3552_transfer_data::spi_cfg
struct ad3552_transfer_config * spi_cfg
Definition: ad3552r.h:361
AD3552R_MASK_CRC_ENABLE
#define AD3552R_MASK_CRC_ENABLE
Definition: ad3552r.h:90
no_os_delay.h
Header file of Delay functions.
AD3552R_RANGE_MAX_VALUE
#define AD3552R_RANGE_MAX_VALUE(id)
Definition: ad3552r.c:93
AD3552R_REG_ADDR_CH_DAC_24B
#define AD3552R_REG_ADDR_CH_DAC_24B(ch)
Definition: ad3552r.h:154
AD3552R_CLOCK_COUNTING_ERROR
@ AD3552R_CLOCK_COUNTING_ERROR
Definition: ad3552r.h:199
AD3552R_MASK_ADDR_ASCENSION
#define AD3552R_MASK_ADDR_ASCENSION
Definition: ad3552r.h:64
AD3552R_MASK_CH
#define AD3552R_MASK_CH(ch)
Definition: ad3552r.h:165
AD3552R_CH_HW_LDAC_MASK
@ AD3552R_CH_HW_LDAC_MASK
Definition: ad3552r.h:302
ad3552r_remove
int32_t ad3552r_remove(struct ad3552r_desc *desc)
Definition: ad3552r.c:1156
ad3552r_write_samples
int32_t ad3552r_write_samples(struct ad3552r_desc *desc, uint16_t *data, uint32_t samples, uint32_t ch_mask, enum ad3552r_write_mode mode)
Definition: ad3552r.c:1272
AD3552R_VREF_SELECT
@ AD3552R_VREF_SELECT
Definition: ad3552r.h:266
ad3552r_set_ch_value
int32_t ad3552r_set_ch_value(struct ad3552r_desc *desc, enum ad3552r_ch_attributes attr, uint8_t ch, uint16_t val)
Definition: ad3552r.c:849
NO_OS_GPIO_HIGH
@ NO_OS_GPIO_HIGH
Definition: no_os_gpio.h:123
no_os_print_log.h
Print messages helpers.
AD3552R_SDO_DRIVE_STRENGTH
@ AD3552R_SDO_DRIVE_STRENGTH
Definition: ad3552r.h:260
AD3552R_REG_ADDR_INTERFACE_CONFIG_A
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_A
Definition: ad3552r.h:62
AD3552R_SINGLE_INST
@ AD3552R_SINGLE_INST
Definition: ad3552r.c:64
AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V
@ AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V
Definition: ad3552r.h:232
AD3542R_CH_OUTPUT_RANGE_0__3V
@ AD3542R_CH_OUTPUT_RANGE_0__3V
Definition: ad3552r.h:226
no_os_timer.h
Timer control module header.
ad3552r_write_samples
int32_t ad3552r_write_samples(struct ad3552r_desc *desc, uint16_t *data, uint32_t samples, uint32_t ch_mask, enum ad3552r_write_mode mode)
Definition: ad3552r.c:1272
AD3552R_REG_ADDR_HW_LDAC_16B
#define AD3552R_REG_ADDR_HW_LDAC_16B
Definition: ad3552r.h:144
ad3552r_ch_gain_scaling
ad3552r_ch_gain_scaling
Definition: ad3552r.h:239
NO_OS_ARRAY_SIZE
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
ad3552r_status
ad3552r_status
Definition: ad3552r.h:193
AD3552R_NUM_CH
#define AD3552R_NUM_CH
Definition: ad3552r.h:164
AD3552R_PARTIAL_REGISTER_ACCESS
@ AD3552R_PARTIAL_REGISTER_ACCESS
Definition: ad3552r.h:202
AD3542R_CH_OUTPUT_RANGE_0__5V
@ AD3542R_CH_OUTPUT_RANGE_0__5V
Definition: ad3552r.h:228
AD3552R_EXTERNAL_VREF_PIN_INPUT
@ AD3552R_EXTERNAL_VREF_PIN_INPUT
Definition: ad3552r.h:190
AD3552R_REG_ADDR_CH_INPUT_24B
#define AD3552R_REG_ADDR_CH_INPUT_24B(ch)
Definition: ad3552r.h:159
ad3552r_get_offset
int32_t ad3552r_get_offset(struct ad3552r_desc *desc, uint8_t ch, int32_t *integer, int32_t *dec)
Definition: ad3552r.c:938
AD3542R_CH_OUTPUT_RANGE_0__2P5V
@ AD3542R_CH_OUTPUT_RANGE_0__2P5V
Definition: ad3552r.h:224
ad3552r_init_param::chip_id
enum ad3552r_id chip_id
Definition: ad3552r.h:417
ad3552r_ch_data::offset_int
int32_t offset_int
Definition: ad3552r.h:367
AD3552R_CH_GAIN_SCALING_0_25
@ AD3552R_CH_GAIN_SCALING_0_25
Definition: ad3552r.h:245
AD3552R_INVALID_OR_NO_CRC
@ AD3552R_INVALID_OR_NO_CRC
Definition: ad3552r.h:200
ad3552_transfer_config::stream_length_keep_value
uint8_t stream_length_keep_value
Definition: ad3552r.h:334
NO_OS_GPIO_LOW
@ NO_OS_GPIO_LOW
Definition: no_os_gpio.h:121
no_os_spi_msg::tx_buff
uint8_t * tx_buff
Definition: no_os_spi.h:92
ad3552r_desc::spi_cfg
struct ad3552_transfer_config spi_cfg
Definition: ad3552r.h:381
AD3552R_MAX_REG_SIZE
#define AD3552R_MAX_REG_SIZE
Definition: ad3552r.c:78
AD3552R_CH_OUTPUT_RANGE_NEG_5__5V
@ AD3552R_CH_OUTPUT_RANGE_NEG_5__5V
Definition: ad3552r.h:217
AD3552R_CH_GAIN_OFFSET
@ AD3552R_CH_GAIN_OFFSET
Definition: ad3552r.h:292
ad3552r_init_param::crc_en
bool crc_en
Definition: ad3552r.h:431
AD3552R_WRITE_TO_READ_ONLY_REGISTER
@ AD3552R_WRITE_TO_READ_ONLY_REGISTER
Definition: ad3552r.h:201
ad3542r_ch_output_range
ad3542r_ch_output_range
Definition: ad3552r.h:222
AD3552R_INTERNAL_VREF_PIN_FLOATING
@ AD3552R_INTERNAL_VREF_PIN_FLOATING
Definition: ad3552r.h:186
AD3552R_REG_ADDR_INTERFACE_CONFIG_C
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_C
Definition: ad3552r.h:89
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
no_os_field_prep
uint32_t no_os_field_prep(uint32_t mask, uint32_t val)
ad3552r_get_ch_value
int32_t ad3552r_get_ch_value(struct ad3552r_desc *desc, enum ad3552r_ch_attributes attr, uint8_t ch, uint16_t *val)
Definition: ad3552r.c:802
no_os_error.h
Error codes definition.
AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE
#define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE
Definition: ad3552r.h:127
AD3552R_MASK_SINGLE_INST
#define AD3552R_MASK_SINGLE_INST
Definition: ad3552r.h:67
AD3552R_MASK_CH_OFFSET_BIT_8
#define AD3552R_MASK_CH_OFFSET_BIT_8
Definition: ad3552r.h:136
ad3552r_ch_data
Definition: ad3552r.h:364
pr_debug
#define pr_debug(fmt, args...)
Definition: no_os_print_log.h:107
ad3552r_id
ad3552r_id
Definition: ad3552r.h:179
AD3552R_OFFSET_POLARITY_POSITIVE
@ AD3552R_OFFSET_POLARITY_POSITIVE
Definition: ad3552r.h:252
AD3552R_MASK_CH_GAIN_SCALING_N
#define AD3552R_MASK_CH_GAIN_SCALING_N
Definition: ad3552r.h:133
ad3552r_get_dev_value
int32_t ad3552r_get_dev_value(struct ad3552r_desc *desc, enum ad3552r_dev_attributes attr, uint16_t *val)
Definition: ad3552r.c:538
AD3552R_REG_ADDR_HW_LDAC_24B
#define AD3552R_REG_ADDR_HW_LDAC_24B
Definition: ad3552r.h:153
ad3552r_ch_data::offset_dec
int32_t offset_dec
Definition: ad3552r.h:368
ad3552r_ldac_trigger
int32_t ad3552r_ldac_trigger(struct ad3552r_desc *desc, uint16_t mask)
Definition: ad3552r.c:1211
AD3552R_REG_ADDR_INTERFACE_CONFIG_B
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_B
Definition: ad3552r.h:66
ad3552r_get_status
int32_t ad3552r_get_status(struct ad3552r_desc *desc, uint32_t *status, uint8_t clr_err)
AD3552R_WRITE_INPUT_REGS
@ AD3552R_WRITE_INPUT_REGS
Definition: ad3552r.h:317
AD3552R_SECONDARY_REGION_ADDR
#define AD3552R_SECONDARY_REGION_ADDR
Definition: ad3552r.c:86
AD3552R_MASK_CH_OUTPUT_RANGE_SEL
#define AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch)
Definition: ad3552r.h:128
no_os_crc8_populate_msb
void no_os_crc8_populate_msb(uint8_t *table, const uint8_t polynomial)
AD3552R_REG_ADDR_ERR_STATUS
#define AD3552R_REG_ADDR_ERR_STATUS
Definition: ad3552r.h:119
no_os_spi_msg::rx_buff
uint8_t * rx_buff
Definition: no_os_spi.h:94
AD3552R_ADDR_ASCENSION
@ AD3552R_ADDR_ASCENSION
Definition: ad3552r.c:61
ad3552r_channel_init::fast_en
bool fast_en
Definition: ad3552r.h:406
ad3552r_get_dev_value
int32_t ad3552r_get_dev_value(struct ad3552r_desc *desc, enum ad3552r_dev_attributes attr, uint16_t *val)
Definition: ad3552r.c:538
ad3552r_ldac_trigger
int32_t ad3552r_ldac_trigger(struct ad3552r_desc *desc, uint16_t mask)
Definition: ad3552r.c:1211
ad3552r_remove
int32_t ad3552r_remove(struct ad3552r_desc *desc)
Definition: ad3552r.c:1156
AD3552R_CH_OUTPUT_RANGE_0__10V
@ AD3552R_CH_OUTPUT_RANGE_0__10V
Definition: ad3552r.h:215
ad3552r_desc::ldac
struct no_os_gpio_desc * ldac
Definition: ad3552r.h:383
AD3552R_INTERNAL_VREF_PIN_2P5V
@ AD3552R_INTERNAL_VREF_PIN_2P5V
Definition: ad3552r.h:188
AD3552R_MASK_REFERENCE_VOLTAGE_SEL
#define AD3552R_MASK_REFERENCE_VOLTAGE_SEL
Definition: ad3552r.h:110
AD3552R_MASK_CH_OFFSET_POLARITY
#define AD3552R_MASK_CH_OFFSET_POLARITY
Definition: ad3552r.h:135
AD3552R_CH_OUTPUT_RANGE_0__5V
@ AD3552R_CH_OUTPUT_RANGE_0__5V
Definition: ad3552r.h:213
AD3552R_CH_ATTR_REG
#define AD3552R_CH_ATTR_REG(attr)
Definition: ad3552r.c:75
ad3552r_custom_output_range_cfg::gain_scaling_p_inv_log2
uint8_t gain_scaling_p_inv_log2
Definition: ad3552r.h:395
ad3552r_set_ch_value
int32_t ad3552r_set_ch_value(struct ad3552r_desc *desc, enum ad3552r_ch_attributes attr, uint8_t ch, uint16_t val)
Definition: ad3552r.c:849
AD3552R_CH_GAIN_OFFSET_POLARITY
@ AD3552R_CH_GAIN_OFFSET_POLARITY
Definition: ad3552r.h:294
ad3552_transfer_data::len
uint32_t len
Definition: ad3552r.h:357
ad3552_transfer_config::addr_asc
uint8_t addr_asc
Definition: ad3552r.h:327
AD3552R_CH_OUTPUT_RANGE_NEG_10__10V
@ AD3552R_CH_OUTPUT_RANGE_NEG_10__10V
Definition: ad3552r.h:219
AD3552R_STREAM_MODE
@ AD3552R_STREAM_MODE
Definition: ad3552r.c:66
AD3552R_REF_RANGE_ERR_STATUS
@ AD3552R_REF_RANGE_ERR_STATUS
Definition: ad3552r.h:204
ad3552_transfer_data
Definition: ad3552r.h:351
AD3552R_ATTR_MASK
#define AD3552R_ATTR_MASK(attr)
Definition: ad3552r.c:74
ad3552r_channel_init::en
bool en
Definition: ad3552r.h:404
ad3552r_init_param::channels
struct ad3552r_channel_init channels[AD3552R_NUM_CH]
Definition: ad3552r.h:429
AD3552R_CH_AMPLIFIER_POWERDOWN
@ AD3552R_CH_AMPLIFIER_POWERDOWN
Definition: ad3552r.h:283
ad3552r_channel_init::custom_range
struct ad3552r_custom_output_range_cfg custom_range
Definition: ad3552r.h:413
AD3552R_REG_ADDR_CH_GAIN
#define AD3552R_REG_ADDR_CH_GAIN(ch)
Definition: ad3552r.h:131
ad3552r_get_offset
int32_t ad3552r_get_offset(struct ad3552r_desc *desc, uint8_t ch, int32_t *integer, int32_t *dec)
Definition: ad3552r.c:938
ad3552r_custom_output_range_cfg::gain_scaling_n_inv_log2
uint8_t gain_scaling_n_inv_log2
Definition: ad3552r.h:398
no_os_gpio_remove
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:95
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:143
ad3552r_ch_attributes
ad3552r_ch_attributes
Definition: ad3552r.h:279
AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE
#define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE
Definition: ad3552r.h:88
AD3552R_SCRATCH_PAD_TEST_VAL2
#define AD3552R_SCRATCH_PAD_TEST_VAL2
Definition: ad3552r.c:91
AD3552R_CH_ATTR_MASK
#define AD3552R_CH_ATTR_MASK(ch, attr)
Definition: ad3552r.c:76
AD3552R_RESET_STATUS
@ AD3552R_RESET_STATUS
Definition: ad3552r.h:195
ad3552r_reset
int32_t ad3552r_reset(struct ad3552r_desc *desc)
Definition: ad3552r.c:1168
AD3552R_ADDR_MASK
#define AD3552R_ADDR_MASK
Definition: ad3552r.c:80
AD3552R_CH_GAIN_SCALING_0_5
@ AD3552R_CH_GAIN_SCALING_0_5
Definition: ad3552r.h:243
ad3552r_init_param::spi_param
struct no_os_spi_init_param spi_param
Definition: ad3552r.h:418
ad3552r_ch_data::n
uint8_t n
Definition: ad3552r.h:373
ad3552r_ch_data::range
uint8_t range
Definition: ad3552r.h:375
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
ad3552r_get_ch_value
int32_t ad3552r_get_ch_value(struct ad3552r_desc *desc, enum ad3552r_ch_attributes attr, uint8_t ch, uint16_t *val)
Definition: ad3552r.c:802
ad3552r_get_scale
int32_t ad3552r_get_scale(struct ad3552r_desc *desc, uint8_t ch, int32_t *integer, int32_t *dec)
Definition: ad3552r.c:926
ad3552r_dev_attributes
ad3552r_dev_attributes
Definition: ad3552r.h:257
AD3552R_WRITE_INPUT_REGS_AND_TRIGGER_LDAC
@ AD3552R_WRITE_INPUT_REGS_AND_TRIGGER_LDAC
Definition: ad3552r.h:319
AD3552R_MASK_ALL_CH
#define AD3552R_MASK_ALL_CH
Definition: ad3552r.h:166
ad3552r_init_param
Definition: ad3552r.h:416
AD3552R_CH_GAIN_SCALING_1
@ AD3552R_CH_GAIN_SCALING_1
Definition: ad3552r.h:241
no_os_spi_msg::bytes_number
uint32_t bytes_number
Definition: no_os_spi.h:96
no_os_spi_transfer
int32_t no_os_spi_transfer(struct no_os_spi_desc *desc, struct no_os_spi_msg *msgs, uint32_t len)
Iterate over head list and send all spi messages.
Definition: no_os_spi.c:97
AD3552R_REG_ADDR_STREAM_MODE
#define AD3552R_REG_ADDR_STREAM_MODE
Definition: ad3552r.h:84
AD3552R_REG_ADDR_TRANSFER_REGISTER
#define AD3552R_REG_ADDR_TRANSFER_REGISTER
Definition: ad3552r.h:86
NO_OS_CRC8_TABLE_SIZE
#define NO_OS_CRC8_TABLE_SIZE
Definition: no_os_crc8.h:45
AD3552R_GAIN_SCALE
#define AD3552R_GAIN_SCALE
Definition: ad3552r.c:100
ad3552r_ch_vref_select
ad3552r_ch_vref_select
Definition: ad3552r.h:184
ad3552r_spi_attributes
ad3552r_spi_attributes
Definition: ad3552r.c:56
ad3552r_custom_output_range_cfg::gain_offset
int16_t gain_offset
Definition: ad3552r.h:392
AD3552R_CRC_DISABLE_VALUE
#define AD3552R_CRC_DISABLE_VALUE
Definition: ad3552r.c:82
ad3552_transfer_config
Definition: ad3552r.h:323
ad3552r_set_dev_value
int32_t ad3552r_set_dev_value(struct ad3552r_desc *desc, enum ad3552r_dev_attributes attr, uint16_t val)
Definition: ad3552r.c:564
no_os_field_get
uint32_t no_os_field_get(uint32_t mask, uint32_t word)
ad3552r_custom_output_range_cfg
Definition: ad3552r.h:391
ad3552r_desc::ch_data
struct ad3552r_ch_data ch_data[AD3552R_NUM_CH]
Definition: ad3552r.h:385
no_os_crc8
uint8_t no_os_crc8(const uint8_t *table, const uint8_t *pdata, size_t nbytes, uint8_t crc)
ad3552r_ch_data::scale_int
int32_t scale_int
Definition: ad3552r.h:365
AD3552R_REG_ADDR_PRODUCT_ID_L
#define AD3552R_REG_ADDR_PRODUCT_ID_L
Definition: ad3552r.h:75
AD3542R_CH_OUTPUT_RANGE_0__10V
@ AD3542R_CH_OUTPUT_RANGE_0__10V
Definition: ad3552r.h:230
AD3552R_CH_RFB
@ AD3552R_CH_RFB
Definition: ad3552r.h:304
AD3552R_STREAM_LENGTH_KEEP_VALUE
@ AD3552R_STREAM_LENGTH_KEEP_VALUE
Definition: ad3552r.c:68
AD3552R_ATTR_REG
#define AD3552R_ATTR_REG(attr)
Definition: ad3552r.c:73
no_os_udelay
void no_os_udelay(uint32_t usecs)
Wait until usecs microseconds passed.
Definition: aducm3029_delay.c:120
AD3542R_CH_OUTPUT_RANGE_NEG_5__5V
@ AD3542R_CH_OUTPUT_RANGE_NEG_5__5V
Definition: ad3552r.h:234
AD3552R_CH_GAIN_SCALING_P
@ AD3552R_CH_GAIN_SCALING_P
Definition: ad3552r.h:296
ad3552r_write_reg
int32_t ad3552r_write_reg(struct ad3552r_desc *desc, uint8_t addr, uint16_t val)
Definition: ad3552r.c:441
AD3552R_REG_ADDR_SCRATCH_PAD
#define AD3552R_REG_ADDR_SCRATCH_PAD
Definition: ad3552r.h:80
ad3552r_ch_data::rfb
uint16_t rfb
Definition: ad3552r.h:372
no_os_gpio_set_value
int32_t no_os_gpio_set_value(struct no_os_gpio_desc *desc, uint8_t value)
Set the value of the specified GPIO.
Definition: no_os_gpio.c:160
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
AD3552R_MASK_LENGTH
#define AD3552R_MASK_LENGTH
Definition: ad3552r.h:85
AD3552R_CH_OUTPUT_RANGE_SEL
@ AD3552R_CH_OUTPUT_RANGE_SEL
Definition: ad3552r.h:285
AD3552R_ID
@ AD3552R_ID
Definition: ad3552r.h:181
AD3552R_DEFAULT_CONFIG_B_VALUE
#define AD3552R_DEFAULT_CONFIG_B_VALUE
Definition: ad3552r.c:87
ad3552r_ch_data::p
uint8_t p
Definition: ad3552r.h:374
ad3552r_reset
int32_t ad3552r_reset(struct ad3552r_desc *desc)
Definition: ad3552r.c:1168
ad3552r_ch_data::gain_offset
int16_t gain_offset
Definition: ad3552r.h:369
AD3552R_MASK_CH_RANGE_OVERRIDE
#define AD3552R_MASK_CH_RANGE_OVERRIDE
Definition: ad3552r.h:132
ad3552r_channel_init::range
uint8_t range
Definition: ad3552r.h:412
ad3552r_channel_init
Definition: ad3552r.h:403
AD3552R_REG_ADDR_INTERFACE_CONFIG_D
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_D
Definition: ad3552r.h:99
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:71
ad3552r_get_scale
int32_t ad3552r_get_scale(struct ad3552r_desc *desc, uint8_t ch, int32_t *integer, int32_t *dec)
Definition: ad3552r.c:926
no_os_gpio.h
Header file of GPIO Interface.
ad3552r_desc::crc_en
uint8_t crc_en
Definition: ad3552r.h:388
AD3552R_MASK_DAC_12B
#define AD3552R_MASK_DAC_12B
Definition: ad3552r.h:167
AD3552R_MASK_CH_DAC_POWERDOWN
#define AD3552R_MASK_CH_DAC_POWERDOWN(ch)
Definition: ad3552r.h:125
ad3552r_init_param::sdo_drive_strength
uint8_t sdo_drive_strength
Definition: ad3552r.h:428
ad3552r.h
Header file of ad3552r Driver.
AD3552R_REG_ADDR_INTERFACE_STATUS_A
#define AD3552R_REG_ADDR_INTERFACE_STATUS_A
Definition: ad3552r.h:92
ad3552r_init_param::use_external_vref
bool use_external_vref
Definition: ad3552r.h:424
AD3552R_REG_ADDR_SW_LDAC_16B
#define AD3552R_REG_ADDR_SW_LDAC_16B
Definition: ad3552r.h:149
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
no_os_get_unaligned_be16
uint16_t no_os_get_unaligned_be16(uint8_t *buf)
AD3552R_MASK_CH_OFFSET_BITS_0_7
#define AD3552R_MASK_CH_OFFSET_BITS_0_7
Definition: ad3552r.h:130
ad3552r_transfer
int32_t ad3552r_transfer(struct ad3552r_desc *desc, struct ad3552_transfer_data *data)
Definition: ad3552r.c:412
AD3552R_REG_ADDR_SH_REFERENCE_CONFIG
#define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG
Definition: ad3552r.h:105
ad3552_transfer_data::data
uint8_t * data
Definition: ad3552r.h:355
no_os_util.h
Header file of utility functions.
no_os_find_first_set_bit
uint32_t no_os_find_first_set_bit(uint32_t word)
ad3552r_ch_data::offset
uint16_t offset
Definition: ad3552r.h:370
AD3552R_MASK_CH_AMPLIFIER_POWERDOWN
#define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch)
Definition: ad3552r.h:126
AD3552R_REG_ADDR_CH_SELECT_16B
#define AD3552R_REG_ADDR_CH_SELECT_16B
Definition: ad3552r.h:147
AD3542R_ID
@ AD3542R_ID
Definition: ad3552r.h:180
AD3552R_CRC_POLY
#define AD3552R_CRC_POLY
Definition: ad3552r.c:84
ad3552r_write_mode
ad3552r_write_mode
Definition: ad3552r.h:313
AD3552R_CH_SELECT
@ AD3552R_CH_SELECT
Definition: ad3552r.h:308
ad3552r_init_param::vref_out_enable
bool vref_out_enable
Definition: ad3552r.h:426
no_os_gpio_direction_output
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:124
ad3552_transfer_data::is_read
uint8_t is_read
Definition: ad3552r.h:359
AD3552R_CH_TRIGGER_SOFTWARE_LDAC
@ AD3552R_CH_TRIGGER_SOFTWARE_LDAC
Definition: ad3552r.h:300
AD3552R_CH_CODE
@ AD3552R_CH_CODE
Definition: ad3552r.h:310
AD3552R_REG_ADDR_PRODUCT_ID_H
#define AD3552R_REG_ADDR_PRODUCT_ID_H
Definition: ad3552r.h:76
AD3552R_CH_OUTPUT_RANGE_0__2P5V
@ AD3552R_CH_OUTPUT_RANGE_0__2P5V
Definition: ad3552r.h:211
ad3552_transfer_config::stream_mode_length
uint8_t stream_mode_length
Definition: ad3552r.h:325
no_os_crc8.h
Header file of CRC-8 computation.
AD3552R_OFFSET_POLARITY_NEGATIVE
@ AD3552R_OFFSET_POLARITY_NEGATIVE
Definition: ad3552r.h:254
ad3552r_desc::chip_id
uint8_t chip_id
Definition: ad3552r.h:387
AD3552R_MASK_MULTI_IO_MODE
#define AD3552R_MASK_MULTI_IO_MODE
Definition: ad3552r.h:87
AD3552R_REG_ADDR_SW_LDAC_24B
#define AD3552R_REG_ADDR_SW_LDAC_24B
Definition: ad3552r.h:158
NO_OS_DIV_ROUND_CLOSEST
#define NO_OS_DIV_ROUND_CLOSEST(x, y)
Definition: no_os_util.h:58
ad3552r_write_reg
int32_t ad3552r_write_reg(struct ad3552r_desc *desc, uint8_t addr, uint16_t val)
Definition: ad3552r.c:441
ad3552r_ch_data::scale_dec
int32_t scale_dec
Definition: ad3552r.h:366
ad3552r_custom_output_range_cfg::rfb_ohms
uint8_t rfb_ohms
Definition: ad3552r.h:400
ad3552r_desc
Definition: ad3552r.h:380
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:121
AD3552R_CH_OUTPUT_RANGE_CUSTOM
#define AD3552R_CH_OUTPUT_RANGE_CUSTOM
Definition: ad3552r.h:237
ad3552r_ch_data::offset_polarity
uint8_t offset_polarity
Definition: ad3552r.h:371
ad3552r_init_param::reset_gpio_param_optional
struct no_os_gpio_init_param * reset_gpio_param_optional
Definition: ad3552r.h:420
no_os_gpio_get_optional
int32_t no_os_gpio_get_optional(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Get the value of an optional GPIO.
Definition: no_os_gpio.c:75