no-OS
ad4110.h
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1 /***************************************************************************/
42 #ifndef AD4110_H_
43 #define AD4110_H_
44 
45 /******************************************************************************/
46 /***************************** Include Files **********************************/
47 /******************************************************************************/
48 #include <stdint.h>
49 #include <stdbool.h>
50 #include "no_os_delay.h"
51 #include "no_os_gpio.h"
52 #include "no_os_spi.h"
53 #include "no_os_irq.h"
54 
55 /******************************************************************************/
56 /********************** Macros and Constants Definitions **********************/
57 /******************************************************************************/
58 #define AD4110_CMD_WR_COM_REG(x) (0x00 | ((x) & 0xF)) // Write to Register x
59 #define AD4110_CMD_READ_COM_REG(x) (0x40 | ((x) & 0xF)) // Read from Register x
60 #define AD4110_DEV_ADDR_MASK (0x30) // Device address mask
61 
62 /* Register map */
63 #define A4110_ADC 0x00
64 #define A4110_AFE 0x01
65 
66 /****************************** AFE Register Map ******************************/
67 #define AD4110_REG_AFE_TOP_STATUS 0x0
68 #define AD4110_REG_AFE_CNTRL1 0x1
69 #define AD4110_REG_AFE_CLK_CTRL 0x3
70 #define AD4110_REG_AFE_CNTRL2 0x4
71 #define AD4110_REG_PGA_RTD_CTRL 0x5
72 #define AD4110_REG_AFE_ERR_DISABLE 0x6
73 #define AD4110_REG_AFE_DETAIL_STATUS 0x7
74 #define AD4110_REG_AFE_CAL_DATA 0xC
75 #define AD4110_REG_AFE_RSENSE_DATA 0xD
76 #define AD4110_REG_AFE_NO_PWR_DEFAULT_SEL 0xE
77 #define AD4110_REG_AFE_NO_PWR_DEFAULT_STATUS 0xF
78 
79 /***************************** ADC Register Map *******************************/
80 #define AD4110_REG_ADC_STATUS 0x0
81 #define AD4110_REG_ADC_MODE 0x1
82 #define AD4110_REG_ADC_INTERFACE 0x2
83 #define AD4110_REG_ADC_CONFIG 0x3
84 #define AD4110_REG_DATA 0x4
85 #define AD4110_REG_FILTER 0x5
86 #define AD4110_REG_ADC_GPIO_CONFIG 0x6
87 #define AD4110_REG_ID 0x7
88 #define AD4110_ADC_OFFSET0 0x8
89 #define AD4110_ADC_OFFSET1 0x9
90 #define AD4110_ADC_OFFSET2 0xA
91 #define AD4110_ADC_OFFSET3 0xB
92 #define AD4110_ADC_GAIN0 0xC
93 #define AD4110_ADC_GAIN1 0xD
94 #define AD4110_ADC_GAIN2 0xE
95 #define AD4110_ADC_GAIN3 0xF
96 
97 /* AFE_CNTRL1 Register */
98 #define AD4110_REG_AFE_CNTRL1_CRC_EN (1 << 14)
99 #define AD4110_REG_AFE_CNTRL1_DISRTD (1 << 9)
100 
101 /* AFE_CLK_CTRL Register */
102 #define AD4110_REG_AFE_CLK_CTRL_CFG(x) (((x) & 0x3) << 3)
103 
104 /* AFE_CNTRL2 Register */
105 #define AD4110_REG_AFE_CNTRL2_IMODE_MSK (1 << 1)
106 #define AD4110_REG_AFE_CNTRL2_EXT_R_SEL_MSK (1 << 2)
107 #define AD4110_REG_AFE_CNTRL2_EN_FLD_PWR_MSK (1 << 3)
108 #define AD4110_AFE_VBIAS(x) (((x) & 0x3) << 6)
109 #define AD4110_AFE_VBIAS_ON 0x1
110 #define AD4110_AFE_VBIAS_DEFAULT_OFF 0x2
111 #define AD4110_AFE_VBIAS_OFF 0x3
112 #define AD4110_REG_AFE_CNTRL2_AINP_UP1 (1 << 8)
113 #define AD4110_REG_AFE_CNTRL2_AINP_UP100 (1 << 9)
114 #define AD4110_REG_AFE_CNTRL2_AINP_DN1 (1 << 10)
115 #define AD4110_REG_AFE_CNTRL2_AINP_DN100 (1 << 11)
116 #define AD4110_REG_AFE_CNTRL2_AINN_UP1 (1 << 12)
117 #define AD4110_REG_AFE_CNTRL2_AINN_UP100 (1 << 13)
118 #define AD4110_REG_AFE_CNTRL2_AINN_DN1 (1 << 14)
119 #define AD4110_REG_AFE_CNTRL2_AINN_DN100 (1 << 15)
120 
121 /* PGA_RTD_CTRL Register */
122 #define AD4110_REG_PGA_RTD_CTRL_23W_EN_MSK (1 << 15)
123 #define AD4110_REG_PGA_RTD_CTRL_I_COM_SEL(x) (((x) & 0x7) << 12)
124 #define AD4110_REG_PGA_RTD_CTRL_I_EXC_SEL(x) (((x) & 0x7) << 9)
125 #define AD4110_REG_PGA_RTD_CTRL_EXT_RTD (1 << 8)
126 #define AD4110_REG_PGA_RTD_CTRL_GAIN_CH(x) (((x) & 0xF) << 4)
127 #define AD4110_REG_PGA_RTD_CTRL_GAIN_CH_MSK 0xF0
128 
129 /* AFE_ERR_DISABLE Register */
130 #define AD4110_REG_AFE_ERR_DIS_AIN_OC (1 << 1)
131 #define AD4110_REG_AFE_ERR_DIS_FLD_PWR_OC (1 << 2)
132 #define AD4110_REG_AFE_ERR_DIS_I_COM (1 << 6)
133 #define AD4110_REG_AFE_ERR_DIS_I_EXC (1 << 7)
134 #define AD4110_REG_AFE_ERR_DIS_AINP_OV (1 << 8)
135 #define AD4110_REG_AFE_ERR_DIS_AINN_OV (1 << 9)
136 #define AD4110_REG_AFE_ERR_DIS_AINP_UV (1 << 10)
137 #define AD4110_REG_AFE_ERR_DIS_AINN_UV (1 << 11)
138 
139 /* NO_PWR_DEFAULT_SEL Register */
140 #define AD4110_REG_NO_PWR_DEFAULT_SEL_MSK 0xFF
141 
142 /* ADC status register */
143 #define AD4110_REG_ADC_STATUS_RDY (1 << 7)
144 
145 /* ADC_MODE Register */
146 #define AD4110_REG_ADC_MODE_MSK 0x70
147 #define AD4110_ADC_MODE(x) (((x) & 0x7) << 4)
148 #define AD4110_REG_ADC_MODE_REF_EN (1 << 15)
149 #define AD4110_REG_ADC_DELAY(x) (((x) & 0x7) << 8)
150 #define AD4110_REG_ADC_CLK_SEL(x) (((x) & 0x3) << 2)
151 
152 /* ADC_INTERFACE Register */
153 #define AD4110_REG_ADC_INTERFACE_CRC_EN_MSK 0x0C
154 #define AD4110_ADC_CRC_EN(x) (((x) & 0x3) << 2)
155 #define AD4110_REG_ADC_INTERFACE_WL16_MSK 0x01
156 #define AD4110_REG_ADC_INTERFACE_DS_MSK 0x40
157 #define AD4110_DATA_STAT_EN (1 << 6)
158 
159 /* ADC_CONFIG Register */
160 #define AD4110_REG_ADC_CONFIG_CHAN_EN_MSK 0xF
161 #define AD4110_REG_ADC_CONFIG_CHAN_EN_0 (1 << 0)
162 #define AD4110_REG_ADC_CONFIG_CHAN_EN_1 (1 << 1)
163 #define AD4110_REG_ADC_CONFIG_CHAN_EN_2 (1 << 2)
164 #define AD4110_REG_ADC_CONFIG_CHAN_EN_3 (1 << 3)
165 #define AD4110_REG_ADC_CONFIG_REF_SEL(x) (((x) & 0x3) << 4)
166 #define AD4110_REG_ADC_CONFIG_BIT_6 (1 << 6)
167 #define AD4110_REG_ADC_CONFIG_AIN_BUFF(x) ((((x) & 0x3) << 8))
168 #define AD4110_REG_ADC_CONFIG_BI_UNIPOLAR (1 << 12)
169 
170 /* ADC_FILTER Register */
171 #define AD4110_REG_ADC_FILTER_ODR(x) (((x) & 0x1F) << 0)
172 #define AD4110_REG_ADC_FILTER_ORDER(x) (((x) & 0x3) << 5)
173 #define AD4110_REG_ADC_FILTER_SEL_ENH(x) (((x) & 0x7) << 8)
174 #define AD4110_REG_ADC_FILTER_EN_ENH (1 << 11)
175 
176 /* ADC_GPIO_CONFIG Register */
177 #define AD4110_REG_GPIO_CONFIG_ERR_EN(x) (((x) & 0x3) << 9)
178 #define AD4110_REG_GPIO_CONFIG_SYNC_EN(x) (((x) & 0x1) << 11)
179 
180 /* 8-bits wide checksum generated using the polynomial */
181 #define AD4110_CRC8_POLY 0x07 // x^8 + x^2 + x^1 + x^0
182 
183 /* ADC conversion timeout */
184 #define AD4110_ADC_CONV_TIMEOUT 10000
185 
186 /******************************************************************************/
187 /*************************** Types Declarations *******************************/
188 /******************************************************************************/
189 /* If AD4110_AFE_ADC_CLOCKED selected, select AD4110_ADC_INT_CLK_CLKIO */
194 };
195 
199 };
200 
204 };
205 
210 };
211 
215 };
216 
220 };
221 
229 };
230 
240 };
241 
244  AD4110_ADC_XOR_CRC, // 8-bit XOR checksum on reads, 8-bit CRC on writes
245  AD4110_ADC_CRC_CRC // 8-bit CRC on reads and writes.
246 };
247 
250  AD4110_AFE_CRC // 8-bit CRC on reads and writes.
251 };
252 
270 };
271 
277 };
278 
301 };
302 
304  sinc5_sinc1 = 0x0,
305  sinc3 = 0x3
306 };
307 
308 struct ad4110_dev {
309  /* SPI */
311  /* Device Settings */
322  uint8_t addr;
323  bool bipolar;
327  /* GPIO - used only for continuous mode */
329  uint32_t nready_pin;
330 };
331 
333  /* SPI */
335  /* Device Settings */
346  uint8_t addr;
347  bool bipolar;
351  /* GPIO - used only for continuous mode */
353  uint32_t nready_pin;
354 };
355 
357  struct ad4110_dev *dev;
358  uint32_t *buffer;
359  uint32_t buffer_size;
360 };
361 
362 /******************************************************************************/
363 /************************ Functions Declarations ******************************/
364 /******************************************************************************/
365 /* Compute CRC8 checksum. */
366 uint8_t ad4110_compute_crc8(uint8_t *data,
367  uint8_t data_size);
368 /* Compute XOR checksum. */
369 uint8_t ad4110_compute_xor(uint8_t *data,
370  uint8_t data_size);
371 
372 /* SPI write to device using a mask. */
373 int32_t ad4110_spi_int_reg_write_msk(struct ad4110_dev *dev,
374  uint8_t reg_map,
375  uint8_t reg_addr,
376  uint32_t data,
377  uint16_t mask);
378 /* Set the mode of the ADC. */
379 int32_t ad4110_set_adc_mode(struct ad4110_dev *dev, enum ad4110_adc_mode mode);
380 
381 /* Set the gain. */
382 int32_t ad4110_set_gain(struct ad4110_dev *dev, enum ad4110_gain gain);
383 
384 /* Set ADC clock mode. */
385 int32_t ad4110_set_adc_clk(struct ad4110_dev *dev, enum ad4110_adc_clk_sel clk);
386 
387 /* Set AFE clock mode. */
388 int32_t ad4110_set_afe_clk(struct ad4110_dev *dev, enum ad4110_afe_clk_cfg clk);
389 
390 /* Set voltage reference. */
391 int32_t ad4110_set_reference(struct ad4110_dev *dev,
392  enum ad4110_voltage_reference ref);
393 
394 /* Set the operation mode. */
395 int32_t ad4110_set_op_mode(struct ad4110_dev *dev, enum ad4110_op_mode mode);
396 
397 /* Do a SPI software reset. */
398 int32_t ad4110_spi_do_soft_reset(struct ad4110_dev *dev);
399 
400 /* Get the data size of a specified register. */
401 uint8_t ad4110_get_data_size(struct ad4110_dev *dev,
402  uint8_t reg_map,
403  uint8_t reg_addr);
404 
405 /* SPI internal register write to device. */
406 int32_t ad4110_spi_int_reg_write(struct ad4110_dev *dev,
407  uint8_t reg_map,
408  uint8_t reg_addr,
409  uint32_t reg_data);
410 
411 /* SPI internal register read from device. */
412 int32_t ad4110_spi_int_reg_read(struct ad4110_dev *dev,
413  uint8_t reg_map,
414  uint8_t reg_addr,
415  uint32_t *reg_data);
416 
417 /* Fills buffer with buffer_size number of samples using irq */
418 int32_t ad4110_continuous_read(struct ad4110_dev *dev, uint32_t *buffer,
419  uint32_t buffer_size);
420 
421 /* SPI internal DATA register read from device. */
422 int32_t ad4110_spi_int_data_reg_read(struct ad4110_dev *dev,
423  uint32_t *reg_data);
424 
425 /* Initialize the device. */
426 int32_t ad4110_setup(struct ad4110_dev **device,
428 
429 /* Enable/Disable channel */
430 int ad4110_set_channel_status(struct ad4110_dev *dev, uint8_t chan_id,
431  bool status);
432 
433 /* Set analog input buffer */
435  enum ad4110_ain_buffer buffer);
436 
437 /* Set polarity */
438 int ad4110_set_bipolar(struct ad4110_dev *dev, bool bipolar);
439 
440 /* Set ODR */
441 int ad4110_set_odr(struct ad4110_dev *dev, enum ad4110_odr odr);
442 
443 /* Set filter order */
444 int ad4110_set_order(struct ad4110_dev *dev, enum ad4110_order order);
445 
446 /* Fills the buffer with a single sample */
447 int ad4110_do_single_read(struct ad4110_dev *dev, uint32_t *buffer);
448 
449 /* Wait for conversion completion */
450 int ad4110_wait_for_rdy_low(struct ad4110_dev *dev, uint32_t timeout);
451 
452 #endif // AD4110_H_
AD4110_GAIN_0_75
@ AD4110_GAIN_0_75
Definition: ad4110.h:259
ad4110_dev::bipolar
bool bipolar
Definition: ad4110.h:323
AD4110_REG_AFE_CNTRL2
#define AD4110_REG_AFE_CNTRL2
Definition: ad4110.h:70
KSPS_62P5_B
@ KSPS_62P5_B
Definition: ad4110.h:283
AD4110_SYNC_DIS
@ AD4110_SYNC_DIS
Definition: ad4110.h:202
ad4110_set_gain
int32_t ad4110_set_gain(struct ad4110_dev *dev, enum ad4110_gain gain)
Definition: ad4110.c:190
ad4110_data_word_length
ad4110_data_word_length
Definition: ad4110.h:217
AD4110_REG_AFE_CNTRL1_CRC_EN
#define AD4110_REG_AFE_CNTRL1_CRC_EN
Definition: ad4110.h:98
AD4110_CONTINOUS_CONV_MODE
@ AD4110_CONTINOUS_CONV_MODE
Definition: ad4110.h:223
AD4110_AFE_VBIAS_ON
#define AD4110_AFE_VBIAS_ON
Definition: ad4110.h:109
ad4110_init_param::spi_init
struct no_os_spi_init_param spi_init
Definition: ad4110.h:334
AD4110_SYNC_EN
@ AD4110_SYNC_EN
Definition: ad4110.h:203
AD4110_AFE_ADC_CLOCKED
@ AD4110_AFE_ADC_CLOCKED
Definition: ad4110.h:198
ad4110_dev
Definition: ad4110.h:308
ad4110_init_param::afe_clk
enum ad4110_afe_clk_cfg afe_clk
Definition: ad4110.h:344
SPS_50
@ SPS_50
Definition: ad4110.h:296
SPS_400P6
@ SPS_400P6
Definition: ad4110.h:292
ad4110_set_gain
int32_t ad4110_set_gain(struct ad4110_dev *dev, enum ad4110_gain gain)
Definition: ad4110.c:190
ad4110_callback_ctx
Definition: ad4110.h:356
AD4110_REG_AFE_CNTRL1
#define AD4110_REG_AFE_CNTRL1
Definition: ad4110.h:68
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
ad4110_init_param::gain
enum ad4110_gain gain
Definition: ad4110.h:342
KSPS_2P5
@ KSPS_2P5
Definition: ad4110.h:289
ad4110_callback_ctx::buffer_size
uint32_t buffer_size
Definition: ad4110.h:359
no_os_callback_desc
Structure describing a callback to be registered.
Definition: no_os_irq.h:134
ad4110_continuous_read
int32_t ad4110_continuous_read(struct ad4110_dev *dev, uint32_t *buffer, uint32_t buffer_size)
Definition: ad4110.c:1037
ad4110_callback_ctx::dev
struct ad4110_dev * dev
Definition: ad4110.h:357
AD4110_REG_ADC_MODE_MSK
#define AD4110_REG_ADC_MODE_MSK
Definition: ad4110.h:146
AD4110_ADC_CRC_EN
#define AD4110_ADC_CRC_EN(x)
Definition: ad4110.h:154
no_os_spi.h
Header file of SPI Interface.
no_os_irq.h
Header file of IRQ interface.
no_os_irq_register_callback
int32_t no_os_irq_register_callback(struct no_os_irq_ctrl_desc *desc, uint32_t irq_id, struct no_os_callback_desc *callback_desc)
Register a callback to handle the irq events.
Definition: no_os_irq.c:82
ad4110_compute_xor
uint8_t ad4110_compute_xor(uint8_t *data, uint8_t data_size)
Definition: ad4110.c:92
DISABLE_AIN_BUFFER
@ DISABLE_AIN_BUFFER
Definition: ad4110.h:273
ad4110_set_adc_clk
int32_t ad4110_set_adc_clk(struct ad4110_dev *dev, enum ad4110_adc_clk_sel clk)
Definition: ad4110.c:210
AD4110_GAIN_0_25
@ AD4110_GAIN_0_25
Definition: ad4110.h:255
ad4110_compute_crc8
uint8_t ad4110_compute_crc8(uint8_t *data, uint8_t data_size)
Definition: ad4110.c:64
ad4110_set_reference
int32_t ad4110_set_reference(struct ad4110_dev *dev, enum ad4110_voltage_reference ref)
Definition: ad4110.c:249
SPS_100P2
@ SPS_100P2
Definition: ad4110.h:294
AD4110_FLD_POWER_MODE
@ AD4110_FLD_POWER_MODE
Definition: ad4110.h:236
ad4110_dev::irq_desc
struct no_os_irq_ctrl_desc * irq_desc
Definition: ad4110.h:328
NO_OS_IRQ_LEVEL_LOW
@ NO_OS_IRQ_LEVEL_LOW
Definition: no_os_irq.h:77
ad4110_init_param::adc_crc_en
enum ad4110_adc_crc_mode adc_crc_en
Definition: ad4110.h:340
pr_err
#define pr_err(fmt, args...)
Definition: no_os_print_log.h:80
ad4110_set_odr
int ad4110_set_odr(struct ad4110_dev *dev, enum ad4110_odr odr)
Set Output Data Rate.
Definition: ad4110.c:793
AD4110_REG_DATA
#define AD4110_REG_DATA
Definition: ad4110.h:84
ad4110_init_param::addr
uint8_t addr
Definition: ad4110.h:346
SPS_60
@ SPS_60
Definition: ad4110.h:295
AD4110_AFE_VBIAS
#define AD4110_AFE_VBIAS(x)
Definition: ad4110.h:108
ad4110_set_adc_mode
int32_t ad4110_set_adc_mode(struct ad4110_dev *dev, enum ad4110_adc_mode mode)
Definition: ad4110.c:152
no_os_delay.h
Header file of Delay functions.
ad4110_gain
ad4110_gain
Definition: ad4110.h:253
AD4110_ENABLE
@ AD4110_ENABLE
Definition: ad4110.h:214
pr_info
#define pr_info(fmt, args...)
Definition: no_os_print_log.h:99
ad4110_set_odr
int ad4110_set_odr(struct ad4110_dev *dev, enum ad4110_odr odr)
Set Output Data Rate.
Definition: ad4110.c:793
AD4110_ADC_CRC_DISABLE
@ AD4110_ADC_CRC_DISABLE
Definition: ad4110.h:243
ad4110_init_param::order
enum ad4110_order order
Definition: ad4110.h:350
AD4110_DATA_WL24
@ AD4110_DATA_WL24
Definition: ad4110.h:218
no_os_spi_init_param::mode
enum no_os_spi_mode mode
Definition: no_os_spi.h:120
AD4110_GAIN_24
@ AD4110_GAIN_24
Definition: ad4110.h:269
ad4110_adc_crc_mode
ad4110_adc_crc_mode
Definition: ad4110.h:242
sinc5_sinc1
@ sinc5_sinc1
Definition: ad4110.h:304
ad4110_init_param::bipolar
bool bipolar
Definition: ad4110.h:347
ad4110_set_order
int ad4110_set_order(struct ad4110_dev *dev, enum ad4110_order order)
Set Order of Filter.
Definition: ad4110.c:815
ENABLE_NEG_BUFFER
@ ENABLE_NEG_BUFFER
Definition: ad4110.h:274
device
Definition: ad9361_util.h:75
AD4110_REG_ADC_INTERFACE
#define AD4110_REG_ADC_INTERFACE
Definition: ad4110.h:82
AD4110_EXT_REF
@ AD4110_EXT_REF
Definition: ad4110.h:207
ad4110_setup
int32_t ad4110_setup(struct ad4110_dev **device, struct ad4110_init_param init_param)
Definition: ad4110.c:887
AD4110_AVDD5_REF
@ AD4110_AVDD5_REF
Definition: ad4110.h:209
ad4110_ain_buffer
ad4110_ain_buffer
Definition: ad4110.h:272
ad4110_spi_int_data_reg_read
int32_t ad4110_spi_int_data_reg_read(struct ad4110_dev *dev, uint32_t *reg_data)
Definition: ad4110.c:546
no_os_print_log.h
Print messages helpers.
ad4110_set_adc_mode
int32_t ad4110_set_adc_mode(struct ad4110_dev *dev, enum ad4110_adc_mode mode)
Definition: ad4110.c:152
AD4110_REG_ADC_INTERFACE_DS_MSK
#define AD4110_REG_ADC_INTERFACE_DS_MSK
Definition: ad4110.h:156
AD4110_GAIN_4
@ AD4110_GAIN_4
Definition: ad4110.h:264
ad4110_odr
ad4110_odr
Definition: ad4110.h:279
ad4110_set_afe_clk
int32_t ad4110_set_afe_clk(struct ad4110_dev *dev, enum ad4110_afe_clk_cfg clk)
Definition: ad4110.c:229
ad4110_spi_do_soft_reset
int32_t ad4110_spi_do_soft_reset(struct ad4110_dev *dev)
Definition: ad4110.c:440
AD4110_GAIN_1_5
@ AD4110_GAIN_1_5
Definition: ad4110.h:261
ad4110_dev::afe_clk
enum ad4110_afe_clk_cfg afe_clk
Definition: ad4110.h:320
AD4110_AFE_CRC_DISABLE
@ AD4110_AFE_CRC_DISABLE
Definition: ad4110.h:249
ad4110_dev::data_length
enum ad4110_data_word_length data_length
Definition: ad4110.h:314
AD4110_REG_AFE_CNTRL2_EXT_R_SEL_MSK
#define AD4110_REG_AFE_CNTRL2_EXT_R_SEL_MSK
Definition: ad4110.h:106
AD4110_REG_AFE_CLK_CTRL_CFG
#define AD4110_REG_AFE_CLK_CTRL_CFG(x)
Definition: ad4110.h:102
AD4110_PW_DOWN_MODE
@ AD4110_PW_DOWN_MODE
Definition: ad4110.h:226
AD4110_AFE_CRC
@ AD4110_AFE_CRC
Definition: ad4110.h:250
KSPS_1
@ KSPS_1
Definition: ad4110.h:290
AD4110_AFE_INT_CLOCK
@ AD4110_AFE_INT_CLOCK
Definition: ad4110.h:197
AD4110_DISABLE
@ AD4110_DISABLE
Definition: ad4110.h:213
SPS_200
@ SPS_200
Definition: ad4110.h:293
ad4110_init_param::odr
enum ad4110_odr odr
Definition: ad4110.h:349
sinc3
@ sinc3
Definition: ad4110.h:305
AD4110_REG_ADC_INTERFACE_WL16_MSK
#define AD4110_REG_ADC_INTERFACE_WL16_MSK
Definition: ad4110.h:155
KSPS_15P625
@ KSPS_15P625
Definition: ad4110.h:286
AD4110_REG_AFE_CNTRL2_AINN_DN100
#define AD4110_REG_AFE_CNTRL2_AINN_DN100
Definition: ad4110.h:119
ad4110_op_mode
ad4110_op_mode
Definition: ad4110.h:231
KSPS_10P417
@ KSPS_10P417
Definition: ad4110.h:287
ad4110_get_data_size
uint8_t ad4110_get_data_size(struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr)
Definition: ad4110.c:461
ad4110_afe_clk_cfg
ad4110_afe_clk_cfg
Definition: ad4110.h:196
ENABLE_FULL_BUFFER
@ ENABLE_FULL_BUFFER
Definition: ad4110.h:276
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
ad4110_state
ad4110_state
Definition: ad4110.h:212
ad4110_init_param::data_stat
enum ad4110_state data_stat
Definition: ad4110.h:337
ad4110_setup
int32_t ad4110_setup(struct ad4110_dev **device, struct ad4110_init_param init_param)
Definition: ad4110.c:887
ad4110_spi_int_reg_write
int32_t ad4110_spi_int_reg_write(struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr, uint32_t reg_data)
Definition: ad4110.c:496
ad4110_set_op_mode
int32_t ad4110_set_op_mode(struct ad4110_dev *dev, enum ad4110_op_mode mode)
Definition: ad4110.c:294
AD4110_REG_ADC_MODE_REF_EN
#define AD4110_REG_ADC_MODE_REF_EN
Definition: ad4110.h:148
AD4110_ADC_OFFSET0
#define AD4110_ADC_OFFSET0
Definition: ad4110.h:88
no_os_error.h
Error codes definition.
AD4110_GAIN_0_375
@ AD4110_GAIN_0_375
Definition: ad4110.h:257
ad4110_voltage_reference
ad4110_voltage_reference
Definition: ad4110.h:206
ad4110_spi_int_data_reg_read
int32_t ad4110_spi_int_data_reg_read(struct ad4110_dev *dev, uint32_t *reg_data)
Definition: ad4110.c:546
AD4110_RTD_3W_MODE
@ AD4110_RTD_3W_MODE
Definition: ad4110.h:238
SPS_500
@ SPS_500
Definition: ad4110.h:291
ad4110_adc_mode
ad4110_adc_mode
Definition: ad4110.h:222
AD4110_ADC_CRC_CRC
@ AD4110_ADC_CRC_CRC
Definition: ad4110.h:245
AD4110_REG_PGA_RTD_CTRL_23W_EN_MSK
#define AD4110_REG_PGA_RTD_CTRL_23W_EN_MSK
Definition: ad4110.h:122
ad4110_afe_crc_mode
ad4110_afe_crc_mode
Definition: ad4110.h:248
ad4110_spi_int_reg_read
int32_t ad4110_spi_int_reg_read(struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr, uint32_t *reg_data)
Definition: ad4110.c:625
ad4110_dev::afe_crc_en
enum ad4110_afe_crc_mode afe_crc_en
Definition: ad4110.h:316
AD4110_DATA_STAT_EN
#define AD4110_DATA_STAT_EN
Definition: ad4110.h:157
ad4110_dev::addr
uint8_t addr
Definition: ad4110.h:322
AD4110_REG_ADC_INTERFACE_CRC_EN_MSK
#define AD4110_REG_ADC_INTERFACE_CRC_EN_MSK
Definition: ad4110.h:153
ad4110_set_order
int ad4110_set_order(struct ad4110_dev *dev, enum ad4110_order order)
Set Order of Filter.
Definition: ad4110.c:815
AD4110_GAIN_3
@ AD4110_GAIN_3
Definition: ad4110.h:263
no_os_callback_desc::ctx
void * ctx
Definition: no_os_irq.h:146
AD4110_GAIN_0_3
@ AD4110_GAIN_0_3
Definition: ad4110.h:256
ad4110_dev::sync
enum ad4110_sync_en sync
Definition: ad4110.h:319
AD4110_GAIN_8
@ AD4110_GAIN_8
Definition: ad4110.h:266
AD4110_REG_ADC_GPIO_CONFIG
#define AD4110_REG_ADC_GPIO_CONFIG
Definition: ad4110.h:86
KSPS_125_A
@ KSPS_125_A
Definition: ad4110.h:280
KSPS_31P25
@ KSPS_31P25
Definition: ad4110.h:284
AD4110_GAIN_1
@ AD4110_GAIN_1
Definition: ad4110.h:260
AD4110_REG_PGA_RTD_CTRL_GAIN_CH
#define AD4110_REG_PGA_RTD_CTRL_GAIN_CH(x)
Definition: ad4110.h:126
ad4110_set_analog_input_buffer
int ad4110_set_analog_input_buffer(struct ad4110_dev *dev, enum ad4110_ain_buffer buffer)
Assign analog input buffer.
Definition: ad4110.c:740
KSPS_5
@ KSPS_5
Definition: ad4110.h:288
no_os_callback_desc::legacy_callback
void(* legacy_callback)(void *ctx, uint32_t event, void *extra)
Definition: no_os_irq.h:143
AD4110_REG_ADC_CONFIG_AIN_BUFF
#define AD4110_REG_ADC_CONFIG_AIN_BUFF(x)
Definition: ad4110.h:167
ad4110_init_param::nready_pin
uint32_t nready_pin
Definition: ad4110.h:353
AD4110_SYS_GAIN_CAL
@ AD4110_SYS_GAIN_CAL
Definition: ad4110.h:228
AD4110_REG_AFE_CLK_CTRL
#define AD4110_REG_AFE_CLK_CTRL
Definition: ad4110.h:69
ad4110_compute_xor
uint8_t ad4110_compute_xor(uint8_t *data, uint8_t data_size)
Definition: ad4110.c:92
AD4110_THERMOCOUPLE
@ AD4110_THERMOCOUPLE
Definition: ad4110.h:235
AD4110_REG_ADC_FILTER_ORDER
#define AD4110_REG_ADC_FILTER_ORDER(x)
Definition: ad4110.h:172
SPS_20
@ SPS_20
Definition: ad4110.h:297
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
ad4110_get_data_size
uint8_t ad4110_get_data_size(struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr)
Definition: ad4110.c:461
ad4110_dev::gain
enum ad4110_gain gain
Definition: ad4110.h:318
ad4110_adc_clk_sel
ad4110_adc_clk_sel
Definition: ad4110.h:190
AD4110_REG_AFE_CNTRL2_EN_FLD_PWR_MSK
#define AD4110_REG_AFE_CNTRL2_EN_FLD_PWR_MSK
Definition: ad4110.h:107
AD4110_GAIN_0_5
@ AD4110_GAIN_0_5
Definition: ad4110.h:258
ad4110_dev::analog_input_buff
enum ad4110_ain_buffer analog_input_buff
Definition: ad4110.h:324
AD4110_GAIN_2
@ AD4110_GAIN_2
Definition: ad4110.h:262
ad4110_spi_do_soft_reset
int32_t ad4110_spi_do_soft_reset(struct ad4110_dev *dev)
Definition: ad4110.c:440
AD4110_AFE_VBIAS_OFF
#define AD4110_AFE_VBIAS_OFF
Definition: ad4110.h:111
KSPS_62P5_A
@ KSPS_62P5_A
Definition: ad4110.h:282
AD4110_INT_2_5V_REF
@ AD4110_INT_2_5V_REF
Definition: ad4110.h:208
ad4110_set_analog_input_buffer
int ad4110_set_analog_input_buffer(struct ad4110_dev *dev, enum ad4110_ain_buffer buffer)
Assign analog input buffer.
Definition: ad4110.c:740
ad4110_remove
int32_t ad4110_remove(struct ad4110_dev *dev)
Free the resources allocated by ad4110_setup().
Definition: ad4110.c:1084
ad4110_init_param::analog_input_buff
enum ad4110_ain_buffer analog_input_buff
Definition: ad4110.h:348
ad4110_set_reference
int32_t ad4110_set_reference(struct ad4110_dev *dev, enum ad4110_voltage_reference ref)
Definition: ad4110.c:249
AD4110_CRC8_POLY
#define AD4110_CRC8_POLY
Definition: ad4110.h:181
A4110_AFE
#define A4110_AFE
Definition: ad4110.h:64
ad4110_init_param
Definition: ad4110.h:332
ad4110_dev::spi_dev
struct no_os_spi_desc * spi_dev
Definition: ad4110.h:310
ad4110_dev::adc_clk
enum ad4110_adc_clk_sel adc_clk
Definition: ad4110.h:321
AD4110_REG_PGA_RTD_CTRL
#define AD4110_REG_PGA_RTD_CTRL
Definition: ad4110.h:71
AD4110_DEV_ADDR_MASK
#define AD4110_DEV_ADDR_MASK
Definition: ad4110.h:60
ad4110_spi_int_reg_read
int32_t ad4110_spi_int_reg_read(struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr, uint32_t *reg_data)
Definition: ad4110.c:625
ad4110_dev::volt_ref
enum ad4110_voltage_reference volt_ref
Definition: ad4110.h:312
AD4110_GAIN_16
@ AD4110_GAIN_16
Definition: ad4110.h:268
AD4110_STANDBY_MODE
@ AD4110_STANDBY_MODE
Definition: ad4110.h:225
ad4110_set_op_mode
int32_t ad4110_set_op_mode(struct ad4110_dev *dev, enum ad4110_op_mode mode)
Definition: ad4110.c:294
SPS_10
@ SPS_10
Definition: ad4110.h:299
ad4110.h
Header file of AD4110 Driver.
ENABLE_POS_BUFFER
@ ENABLE_POS_BUFFER
Definition: ad4110.h:275
ad4110_set_bipolar
int ad4110_set_bipolar(struct ad4110_dev *dev, bool bipolar)
Set polarity.
Definition: ad4110.c:763
ad4110_set_adc_clk
int32_t ad4110_set_adc_clk(struct ad4110_dev *dev, enum ad4110_adc_clk_sel clk)
Definition: ad4110.c:210
AD4110_RTD_4W_MODE
@ AD4110_RTD_4W_MODE
Definition: ad4110.h:239
AD4110_REG_ADC_MODE
#define AD4110_REG_ADC_MODE
Definition: ad4110.h:81
ad4110_dev::odr
enum ad4110_odr odr
Definition: ad4110.h:325
AD4110_REG_AFE_CNTRL2_IMODE_MSK
#define AD4110_REG_AFE_CNTRL2_IMODE_MSK
Definition: ad4110.h:105
AD4110_REG_ADC_CONFIG
#define AD4110_REG_ADC_CONFIG
Definition: ad4110.h:83
ad4110_wait_for_rdy_low
int ad4110_wait_for_rdy_low(struct ad4110_dev *dev, uint32_t timeout)
Wait for RDY bit to go low indicating conversion completion.
Definition: ad4110.c:837
AD4110_REG_ADC_STATUS
#define AD4110_REG_ADC_STATUS
Definition: ad4110.h:80
AD4110_ADC_INT_CLK_CLKIO
@ AD4110_ADC_INT_CLK_CLKIO
Definition: ad4110.h:192
AD4110_ADC_INT_CLK
@ AD4110_ADC_INT_CLK
Definition: ad4110.h:191
ad4110_dev::nready_pin
uint32_t nready_pin
Definition: ad4110.h:329
AD4110_VOLTAGE_MODE
@ AD4110_VOLTAGE_MODE
Definition: ad4110.h:232
ad4110_dev::adc_crc_en
enum ad4110_adc_crc_mode adc_crc_en
Definition: ad4110.h:315
AD4110_GAIN_12
@ AD4110_GAIN_12
Definition: ad4110.h:267
ad4110_spi_int_reg_write_msk
int32_t ad4110_spi_int_reg_write_msk(struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr, uint32_t data, uint16_t mask)
Definition: ad4110.c:121
ad4110_dev::data_stat
enum ad4110_state data_stat
Definition: ad4110.h:313
ad4110_compute_crc8
uint8_t ad4110_compute_crc8(uint8_t *data, uint8_t data_size)
Definition: ad4110.c:64
ad4110_dev::op_mode
enum ad4110_op_mode op_mode
Definition: ad4110.h:317
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
AD4110_RTD_2W_MODE
@ AD4110_RTD_2W_MODE
Definition: ad4110.h:237
SPS_16P7
@ SPS_16P7
Definition: ad4110.h:298
ad4110_init_param::data_length
enum ad4110_data_word_length data_length
Definition: ad4110.h:338
bipolar
@ bipolar
Definition: ad5446.h:79
ad4110_set_channel_status
int ad4110_set_channel_status(struct ad4110_dev *dev, uint8_t chan_id, bool status)
Enable/Disable channel.
Definition: ad4110.c:720
AD4110_GAIN_0_2
@ AD4110_GAIN_0_2
Definition: ad4110.h:254
AD4110_CMD_READ_COM_REG
#define AD4110_CMD_READ_COM_REG(x)
Definition: ad4110.h:59
KSPS_125_B
@ KSPS_125_B
Definition: ad4110.h:281
SPS_5
@ SPS_5
Definition: ad4110.h:300
AD4110_REG_ADC_CONFIG_BI_UNIPOLAR
#define AD4110_REG_ADC_CONFIG_BI_UNIPOLAR
Definition: ad4110.h:168
AD4110_ADC_MODE
#define AD4110_ADC_MODE(x)
Definition: ad4110.h:147
ad4110_init_param::volt_ref
enum ad4110_voltage_reference volt_ref
Definition: ad4110.h:336
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
AD4110_ADC_EXT_CLK
@ AD4110_ADC_EXT_CLK
Definition: ad4110.h:193
no_os_irq_enable
int32_t no_os_irq_enable(struct no_os_irq_ctrl_desc *desc, uint32_t irq_id)
Enable specific interrupt.
Definition: no_os_irq.c:144
ad4110_do_single_read
int ad4110_do_single_read(struct ad4110_dev *dev, uint32_t *buffer)
ADC data read in single conversion mode.
Definition: ad4110.c:860
no_os_gpio.h
Header file of GPIO Interface.
AD4110_ADC_XOR_CRC
@ AD4110_ADC_XOR_CRC
Definition: ad4110.h:244
ad4110_set_afe_clk
int32_t ad4110_set_afe_clk(struct ad4110_dev *dev, enum ad4110_afe_clk_cfg clk)
Definition: ad4110.c:229
AD4110_GAIN_6
@ AD4110_GAIN_6
Definition: ad4110.h:265
AD4110_REG_ADC_CLK_SEL
#define AD4110_REG_ADC_CLK_SEL(x)
Definition: ad4110.h:150
AD4110_REG_ADC_FILTER_ODR
#define AD4110_REG_ADC_FILTER_ODR(x)
Definition: ad4110.h:171
ad4110_dev::order
enum ad4110_order order
Definition: ad4110.h:326
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
AD4110_DATA_WL16
@ AD4110_DATA_WL16
Definition: ad4110.h:219
ad4110_spi_int_reg_write_msk
int32_t ad4110_spi_int_reg_write_msk(struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr, uint32_t data, uint16_t mask)
Definition: ad4110.c:121
AD4110_REG_ADC_CONFIG_REF_SEL
#define AD4110_REG_ADC_CONFIG_REF_SEL(x)
Definition: ad4110.h:165
AD4110_ADC_CONV_TIMEOUT
#define AD4110_ADC_CONV_TIMEOUT
Definition: ad4110.h:184
ad4110_init_param::adc_clk
enum ad4110_adc_clk_sel adc_clk
Definition: ad4110.h:345
AD4110_CMD_WR_COM_REG
#define AD4110_CMD_WR_COM_REG(x)
Definition: ad4110.h:58
ad4110_callback_ctx::buffer
uint32_t * buffer
Definition: ad4110.h:358
AD4110_CURRENT_MODE
@ AD4110_CURRENT_MODE
Definition: ad4110.h:233
AD4110_REG_FILTER
#define AD4110_REG_FILTER
Definition: ad4110.h:85
no_os_irq_trigger_level_set
int32_t no_os_irq_trigger_level_set(struct no_os_irq_ctrl_desc *desc, uint32_t irq_id, enum no_os_irq_trig_level trig)
Set interrupt trigger level.
Definition: no_os_irq.c:128
no_os_irq_disable
int32_t no_os_irq_disable(struct no_os_irq_ctrl_desc *desc, uint32_t irq_id)
Disable specific interrupt.
Definition: no_os_irq.c:155
ad4110_set_bipolar
int ad4110_set_bipolar(struct ad4110_dev *dev, bool bipolar)
Set polarity.
Definition: ad4110.c:763
no_os_irq_ctrl_desc
Definition: no_os_irq.h:117
AD4110_REG_GPIO_CONFIG_SYNC_EN
#define AD4110_REG_GPIO_CONFIG_SYNC_EN(x)
Definition: ad4110.h:178
ad4110_init_param::op_mode
enum ad4110_op_mode op_mode
Definition: ad4110.h:341
AD4110_SYS_OFFSET_CAL
@ AD4110_SYS_OFFSET_CAL
Definition: ad4110.h:227
ad4110_wait_for_rdy_low
int ad4110_wait_for_rdy_low(struct ad4110_dev *dev, uint32_t timeout)
Wait for RDY bit to go low indicating conversion completion.
Definition: ad4110.c:837
ad4110_set_channel_status
int ad4110_set_channel_status(struct ad4110_dev *dev, uint8_t chan_id, bool status)
Enable/Disable channel.
Definition: ad4110.c:720
ad4110_sync_en
ad4110_sync_en
Definition: ad4110.h:201
ad4110_spi_int_reg_write
int32_t ad4110_spi_int_reg_write(struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr, uint32_t reg_data)
Definition: ad4110.c:496
ad4110_init_param::afe_crc_en
enum ad4110_afe_crc_mode afe_crc_en
Definition: ad4110.h:339
ad4110_continuous_read
int32_t ad4110_continuous_read(struct ad4110_dev *dev, uint32_t *buffer, uint32_t buffer_size)
Definition: ad4110.c:1037
AD4110_CURRENT_MODE_EXT_R_SEL
@ AD4110_CURRENT_MODE_EXT_R_SEL
Definition: ad4110.h:234
ad4110_order
ad4110_order
Definition: ad4110.h:303
ad4110_init_param::irq_desc
struct no_os_irq_ctrl_desc * irq_desc
Definition: ad4110.h:352
ad4110_do_single_read
int ad4110_do_single_read(struct ad4110_dev *dev, uint32_t *buffer)
ADC data read in single conversion mode.
Definition: ad4110.c:860
ad4110_init_param::sync
enum ad4110_sync_en sync
Definition: ad4110.h:343
AD4110_REG_ADC_STATUS_RDY
#define AD4110_REG_ADC_STATUS_RDY
Definition: ad4110.h:143
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
AD4110_SINGLE_CONV_MODE
@ AD4110_SINGLE_CONV_MODE
Definition: ad4110.h:224
KSPS_25
@ KSPS_25
Definition: ad4110.h:285
A4110_ADC
#define A4110_ADC
Definition: ad4110.h:63