no-OS
Classes | Macros | Enumerations | Functions
ad5755.h File Reference

Header file of AD5755 Driver. This driver supporting the following devices: AD5755, AD5755-1 and AD5757. More...

#include <stdint.h>
#include "no-os/delay.h"
#include "no-os/gpio.h"
#include "no-os/spi.h"
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Classes

struct  ad5755_setup
 Stores the settings that will be written to the device when the "AD5755_Init" functions is called. More...
 
struct  ad5755_dev
 
struct  ad5755_init_param
 

Macros

#define AD5755_LDAC_OUT
 
#define AD5755_LDAC_LOW
 
#define AD5755_LDAC_HIGH
 
#define AD5755_RESET_OUT
 
#define AD5755_RESET_LOW
 
#define AD5755_RESET_HIGH
 
#define AD5755_CLEAR_OUT
 
#define AD5755_CLEAR_LOW
 
#define AD5755_CLEAR_HIGH
 
#define AD5755_POC_OUT
 
#define AD5755_POC_LOW
 
#define AD5755_POC_HIGH
 
#define AD5755_ISR_WRITE   (0ul << 23) /* R/nW */
 
#define AD5755_ISR_DUT_AD1(x)   (((x) & 0x1) << 22) /* Device AddrBit1*/
 
#define AD5755_ISR_DUT_AD0(x)   (((x) & 0x1) << 21) /* Device AddrBit0*/
 
#define AD5755_ISR_DREG(x)   (((x) & 0x7) << 18) /* Register AddrBits*/
 
#define AD5755_ISR_DAC_AD(x)   (((x) & 0x3) << 16) /* Channel AddrBits */
 
#define AD5755_ISR_DATA(x)   ((x) & 0xFFFF) /* Data Bits*/
 
#define AD5755_ISR_NOP   0x1CE000
 
#define AD5755_DREG_WR_DAC   0
 
#define AD5755_DREG_WR_GAIN   2
 
#define AD5755_DREG_WR_GAIN_ALL   3
 
#define AD5755_DREG_WR_OFFSET   4
 
#define AD5755_DREG_WR_OFFSET_ALL   5
 
#define AD5755_DREG_WR_CLR_CODE   6
 
#define AD5755_DREG_WR_CTRL_REG   7
 
#define AD5755_DAC_A   0
 
#define AD5755_DAC_B   1
 
#define AD5755_DAC_C   2
 
#define AD5755_DAC_D   3
 
#define AD5755_GAIN_ADJUSTMENT(x)   ((x) & 0xFFFF)
 
#define AD5755_OFFSET_ADJUSTMENT(x)   ((x) & 0xFFFF)
 
#define AD5755_CLEAR_CODE(x)   ((x) & 0xFFFF)
 
#define AD5755_CTRL_CREG(x)   (((x) & 0x7) << 13)
 
#define AD5755_CTRL_DATA(x)   ((x) & 0x1FFF)
 
#define AD5755_CREG_SLEW   0
 
#define AD5755_CREG_MAIN   1
 
#define AD5755_CREG_DAC   2
 
#define AD5755_CREG_DC_DC   3
 
#define AD5755_CREG_SOFT   4
 
#define AD5755_SLEW_SREN   (1 << 12)
 
#define AD5755_SLEW_SR_CLOCK(x)   (((x) & 0xF) << 3)
 
#define AD5755_SLEW_SR_STEP(x)   (((x) & 0x7) << 0)
 
#define AD5755_SR_CLK_64K   0
 
#define AD5755_SR_CLK_32k   1
 
#define AD5755_SR_CLK_16k   2
 
#define AD5755_SR_CLK_8K   3
 
#define AD5755_SR_CLK_4K   4
 
#define AD5755_SR_CLK_2K   5
 
#define AD5755_SR_CLK_1K   6
 
#define AD5755_SR_CLK_500   7
 
#define AD5755_SR_CLK_250   8
 
#define AD5755_SR_CLK_125   9
 
#define AD5755_SR_CLK_64   10
 
#define AD5755_SR_CLK_32   11
 
#define AD5755_SR_CLK_16   12
 
#define AD5755_SR_CLK_8   13
 
#define AD5755_SR_CLK_4   14
 
#define AD5755_SR_CLK_0_5   15
 
#define AD5755_STEP_1   0
 
#define AD5755_STEP_2   1
 
#define AD5755_STEP_4   2
 
#define AD5755_STEP_16   3
 
#define AD5755_STEP_32   4
 
#define AD5755_STEP_64   5
 
#define AD5755_STEP_128   6
 
#define AD5755_STEP_256   7
 
#define AD5755_MAIN_POC   (1 << 12)
 
#define AD5755_MAIN_STATREAD   (1 << 11)
 
#define AD5755_MAIN_EWD   (1 <<10)
 
#define AD5755_MAIN_WD(x)   (((x) & 0x3) << 8)
 
#define AD5755_MAIN_SHTCCTLIM(x)   (((x) & 0x1) << 6)
 
#define AD5755_MAIN_OUTEN_ALL   (1 << 5)
 
#define AD5755_MAIN_DCDC_ALL   (1 << 4)
 
#define AD5755_WD_5MS   0
 
#define AD5755_WD_10MS   1
 
#define AD5755_WD_100MS   2
 
#define AD5755_WD_200MS   3
 
#define AD5755_LIMIT_16_MA   0
 
#define AD5755_LIMIT_8_MA   1
 
#define AD5755_DAC_INT_ENABLE   (1 << 8)
 
#define AD5755_DAC_CLR_EN   (1 << 7)
 
#define AD5755_DAC_OUTEN   (1 << 6)
 
#define AD5755_DAC_RSET   (1 << 5)
 
#define AD5755_DAC_DC_DC   (1 << 4)
 
#define AD5755_DAC_OVRNG   (1 << 3)
 
#define AD5755_DAC_R(x)   ((x) & 0x7)
 
#define AD5755_R_0_5_V   0
 
#define AD5755_R_0_10_V   1
 
#define AD5755_R_M5_P5_V   2
 
#define AD5755_R_M10_P10_V   3
 
#define AD5755_R_4_20_MA   4
 
#define AD5755_R_0_20_MA   5
 
#define AD5755_R_0_24_MA   6
 
#define AD5755_DC_DC_COMP   (1 << 6)
 
#define AD5755_DC_DC_PHASE(x)   (((x) & 0x3) << 4)
 
#define AD5755_DC_DC_FREQ(x)   (((x) & 0x3) << 2)
 
#define AD5755_DC_DC_MAX_V(x)   (((x) & 0x3) << 0)
 
#define AD5755_PHASE_ALL_DC_DC   0
 
#define AD5755_PHASE_AB_CD   1
 
#define AD5755_PHASE_AC_BD   2
 
#define AD5755_PHASE_A_B_C_D_90   3
 
#define AD5755_FREQ_250_HZ   0
 
#define AD5755_FREQ_410_HZ   1
 
#define AD5755_FREQ_650_HZ   2
 
#define AD5755_MAX_23V   0
 
#define AD5755_MAX_24_5V   1
 
#define AD5755_MAX_27V   2
 
#define AD5755_MAX_29_5V   3
 
#define AD5755_SOFT_USER_BIT   (1 << 12)
 
#define AD5755_SOFT_RESET_CODE(x)   ((x) & 0xFFF)
 
#define AD5755_RESET_CODE   0x555
 
#define AD5755_SPI_CODE   0x195
 
#define AD5755_ISR_READ   (1 << 23)
 
#define AD5755_ISR_RD(x)   (((x) & 0x1F) << 16)
 
#define AD5755_RD_DATA_REG(x)   (((x) & 0x3) + 0)
 
#define AD5755_RD_CTRL_REG(x)   (((x) & 0x3) + 4)
 
#define AD5755_RD_GAIN_REG(x)   (((x) & 0x3) + 8)
 
#define AD5755_RD_OFFSET_REG(x)   (((x) & 0x3) + 12)
 
#define AD5755_RD_CODE_REG(x)   (((x) & 0x3) + 16)
 
#define AD5755_RD_SR_CTRL_REG(x)   (((x) & 0x3) + 20)
 
#define AD5755_RD_STATUS_REG   24
 
#define AD5755_RD_MAIN_CTRL_REG   25
 
#define AD5755_RD_Dc_DC_CTRL_REG   26
 
#define AD5755_STATUS_DC_DC(x)   (1 << (12 + (x)))
 
#define AD5755_STATUS_USER_BIT   (1 << 11)
 
#define AD5755_STATUS_PEC_ERROR   (1 << 10)
 
#define AD5755_STATUS_RAMP_ACTIVE   (1 << 9)
 
#define AD5755_STATUS_OVER_TEMP   (1 << 8)
 
#define AD5755_STATUS_VOUT_FAULT(x)   (1 << (4 + (x)))
 
#define AD5755_STATUS_IOUT_FAULT(x)   (1 << (0 + (x)))
 
#define AD5755_CRC_POLYNOMIAL   0x07
 
#define AD5755_CRC_CHECK_CODE   0x00
 

Enumerations

enum  ad5755_type_t {
  ID_AD5755,
  ID_AD5755_1,
  ID_AD5757
}
 

Functions

int8_t ad5755_init (struct ad5755_dev **device, struct ad5755_init_param init_param)
 Initializes the device and powers-up all channels. The device is initialized with the values held by AD5755_InitialSettings structure. More...
 
int32_t ad5755_remove (struct ad5755_dev *dev)
 Free the resources allocated by ad5755_init(). More...
 
int32_t ad5755_get_register_value (struct ad5755_dev *dev, uint8_t register_address)
 Reads the value of a register. More...
 
uint16_t ad5755_set_register_value (struct ad5755_dev *dev, uint8_t register_address, uint8_t channel, uint16_t register_value)
 Writes data into a register. More...
 
void ad5755_software_reset (struct ad5755_dev *dev)
 Performs a software reset to the device. More...
 
void ad5755_watch_dog_setup (struct ad5755_dev *dev, uint8_t wtd_enable, uint8_t timeout)
 Enables/Disables watchdog timer and sets the timeout period. More...
 
void ad5755_feed_watch_dog_timer (struct ad5755_dev *dev)
 Write a "service pulse" to the AD5755 watchdog timer when enabled. More...
 
void ad5755_set_control_registers (struct ad5755_dev *dev, uint8_t ctrl_reg_address, uint8_t channel, uint16_t reg_value)
 Configures one of the control registers. More...
 
uint8_t ad5755_check_crc (uint8_t *data, uint8_t bytes_number)
 Computes the CRC for a data buffer. More...
 
void ad5755_set_channel_power (struct ad5755_dev *dev, uint8_t channel, uint8_t pwr_status)
 Allows power-up/down of the dc-to-dc converter, DAC and internal amplifiers for the selected channel. More...
 
void ad5755_set_channel_range (struct ad5755_dev *dev, uint8_t channel, uint8_t range)
 Sets the range of a channel. More...
 
void ad5755_channel_clear_enable (struct ad5755_dev *dev, uint8_t channel, uint8_t clear_en)
 Selects if the channel clears when CLEAR pin is activated. More...
 
void ad5755_slew_rate_ctrl (struct ad5755_dev *dev, int8_t channel, int8_t sr_en, int8_t updt_freq, int8_t step_size)
 Configures the Digital Slew Rate Control. More...
 
float ad5755_set_voltage (struct ad5755_dev *dev, uint8_t channel, float voltage)
 Sets the output voltage of a channel. More...
 
float ad5755_set_current (struct ad5755_dev *dev, uint8_t channel, float m_acurrent)
 Sets the output current of a channel. More...
 

Detailed Description

Header file of AD5755 Driver. This driver supporting the following devices: AD5755, AD5755-1 and AD5757.

Author
Istvan Csomortani (istva.nosp@m.n.cs.nosp@m.omort.nosp@m.ani@.nosp@m.analo.nosp@m.g.co.nosp@m.m)

Copyright 2012(c) Analog Devices, Inc.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ AD5755_CLEAR_CODE

#define AD5755_CLEAR_CODE (   x)    ((x) & 0xFFFF)

◆ AD5755_CLEAR_HIGH

#define AD5755_CLEAR_HIGH
Value:
gpio_set_value(dev->gpio_clr, \

◆ AD5755_CLEAR_LOW

#define AD5755_CLEAR_LOW
Value:
gpio_set_value(dev->gpio_clr, \

◆ AD5755_CLEAR_OUT

#define AD5755_CLEAR_OUT
Value:

◆ AD5755_CRC_CHECK_CODE

#define AD5755_CRC_CHECK_CODE   0x00

◆ AD5755_CRC_POLYNOMIAL

#define AD5755_CRC_POLYNOMIAL   0x07

◆ AD5755_CREG_DAC

#define AD5755_CREG_DAC   2

◆ AD5755_CREG_DC_DC

#define AD5755_CREG_DC_DC   3

◆ AD5755_CREG_MAIN

#define AD5755_CREG_MAIN   1

◆ AD5755_CREG_SLEW

#define AD5755_CREG_SLEW   0

◆ AD5755_CREG_SOFT

#define AD5755_CREG_SOFT   4

◆ AD5755_CTRL_CREG

#define AD5755_CTRL_CREG (   x)    (((x) & 0x7) << 13)

◆ AD5755_CTRL_DATA

#define AD5755_CTRL_DATA (   x)    ((x) & 0x1FFF)

◆ AD5755_DAC_A

#define AD5755_DAC_A   0

◆ AD5755_DAC_B

#define AD5755_DAC_B   1

◆ AD5755_DAC_C

#define AD5755_DAC_C   2

◆ AD5755_DAC_CLR_EN

#define AD5755_DAC_CLR_EN   (1 << 7)

◆ AD5755_DAC_D

#define AD5755_DAC_D   3

◆ AD5755_DAC_DC_DC

#define AD5755_DAC_DC_DC   (1 << 4)

◆ AD5755_DAC_INT_ENABLE

#define AD5755_DAC_INT_ENABLE   (1 << 8)

◆ AD5755_DAC_OUTEN

#define AD5755_DAC_OUTEN   (1 << 6)

◆ AD5755_DAC_OVRNG

#define AD5755_DAC_OVRNG   (1 << 3)

◆ AD5755_DAC_R

#define AD5755_DAC_R (   x)    ((x) & 0x7)

◆ AD5755_DAC_RSET

#define AD5755_DAC_RSET   (1 << 5)

◆ AD5755_DC_DC_COMP

#define AD5755_DC_DC_COMP   (1 << 6)

◆ AD5755_DC_DC_FREQ

#define AD5755_DC_DC_FREQ (   x)    (((x) & 0x3) << 2)

◆ AD5755_DC_DC_MAX_V

#define AD5755_DC_DC_MAX_V (   x)    (((x) & 0x3) << 0)

◆ AD5755_DC_DC_PHASE

#define AD5755_DC_DC_PHASE (   x)    (((x) & 0x3) << 4)

◆ AD5755_DREG_WR_CLR_CODE

#define AD5755_DREG_WR_CLR_CODE   6

◆ AD5755_DREG_WR_CTRL_REG

#define AD5755_DREG_WR_CTRL_REG   7

◆ AD5755_DREG_WR_DAC

#define AD5755_DREG_WR_DAC   0

◆ AD5755_DREG_WR_GAIN

#define AD5755_DREG_WR_GAIN   2

◆ AD5755_DREG_WR_GAIN_ALL

#define AD5755_DREG_WR_GAIN_ALL   3

◆ AD5755_DREG_WR_OFFSET

#define AD5755_DREG_WR_OFFSET   4

◆ AD5755_DREG_WR_OFFSET_ALL

#define AD5755_DREG_WR_OFFSET_ALL   5

◆ AD5755_FREQ_250_HZ

#define AD5755_FREQ_250_HZ   0

◆ AD5755_FREQ_410_HZ

#define AD5755_FREQ_410_HZ   1

◆ AD5755_FREQ_650_HZ

#define AD5755_FREQ_650_HZ   2

◆ AD5755_GAIN_ADJUSTMENT

#define AD5755_GAIN_ADJUSTMENT (   x)    ((x) & 0xFFFF)

◆ AD5755_ISR_DAC_AD

#define AD5755_ISR_DAC_AD (   x)    (((x) & 0x3) << 16) /* Channel AddrBits */

◆ AD5755_ISR_DATA

#define AD5755_ISR_DATA (   x)    ((x) & 0xFFFF) /* Data Bits*/

◆ AD5755_ISR_DREG

#define AD5755_ISR_DREG (   x)    (((x) & 0x7) << 18) /* Register AddrBits*/

◆ AD5755_ISR_DUT_AD0

#define AD5755_ISR_DUT_AD0 (   x)    (((x) & 0x1) << 21) /* Device AddrBit0*/

◆ AD5755_ISR_DUT_AD1

#define AD5755_ISR_DUT_AD1 (   x)    (((x) & 0x1) << 22) /* Device AddrBit1*/

◆ AD5755_ISR_NOP

#define AD5755_ISR_NOP   0x1CE000

◆ AD5755_ISR_RD

#define AD5755_ISR_RD (   x)    (((x) & 0x1F) << 16)

◆ AD5755_ISR_READ

#define AD5755_ISR_READ   (1 << 23)

◆ AD5755_ISR_WRITE

#define AD5755_ISR_WRITE   (0ul << 23) /* R/nW */

◆ AD5755_LDAC_HIGH

#define AD5755_LDAC_HIGH
Value:
gpio_set_value(dev->gpio_ldac, \

◆ AD5755_LDAC_LOW

#define AD5755_LDAC_LOW
Value:
gpio_set_value(dev->gpio_ldac, \

◆ AD5755_LDAC_OUT

#define AD5755_LDAC_OUT
Value:

◆ AD5755_LIMIT_16_MA

#define AD5755_LIMIT_16_MA   0

◆ AD5755_LIMIT_8_MA

#define AD5755_LIMIT_8_MA   1

◆ AD5755_MAIN_DCDC_ALL

#define AD5755_MAIN_DCDC_ALL   (1 << 4)

◆ AD5755_MAIN_EWD

#define AD5755_MAIN_EWD   (1 <<10)

◆ AD5755_MAIN_OUTEN_ALL

#define AD5755_MAIN_OUTEN_ALL   (1 << 5)

◆ AD5755_MAIN_POC

#define AD5755_MAIN_POC   (1 << 12)

◆ AD5755_MAIN_SHTCCTLIM

#define AD5755_MAIN_SHTCCTLIM (   x)    (((x) & 0x1) << 6)

◆ AD5755_MAIN_STATREAD

#define AD5755_MAIN_STATREAD   (1 << 11)

◆ AD5755_MAIN_WD

#define AD5755_MAIN_WD (   x)    (((x) & 0x3) << 8)

◆ AD5755_MAX_23V

#define AD5755_MAX_23V   0

◆ AD5755_MAX_24_5V

#define AD5755_MAX_24_5V   1

◆ AD5755_MAX_27V

#define AD5755_MAX_27V   2

◆ AD5755_MAX_29_5V

#define AD5755_MAX_29_5V   3

◆ AD5755_OFFSET_ADJUSTMENT

#define AD5755_OFFSET_ADJUSTMENT (   x)    ((x) & 0xFFFF)

◆ AD5755_PHASE_A_B_C_D_90

#define AD5755_PHASE_A_B_C_D_90   3

◆ AD5755_PHASE_AB_CD

#define AD5755_PHASE_AB_CD   1

◆ AD5755_PHASE_AC_BD

#define AD5755_PHASE_AC_BD   2

◆ AD5755_PHASE_ALL_DC_DC

#define AD5755_PHASE_ALL_DC_DC   0

◆ AD5755_POC_HIGH

#define AD5755_POC_HIGH
Value:
gpio_set_value(dev->gpio_poc, \

◆ AD5755_POC_LOW

#define AD5755_POC_LOW
Value:
gpio_set_value(dev->gpio_poc, \

◆ AD5755_POC_OUT

#define AD5755_POC_OUT
Value:

◆ AD5755_R_0_10_V

#define AD5755_R_0_10_V   1

◆ AD5755_R_0_20_MA

#define AD5755_R_0_20_MA   5

◆ AD5755_R_0_24_MA

#define AD5755_R_0_24_MA   6

◆ AD5755_R_0_5_V

#define AD5755_R_0_5_V   0

◆ AD5755_R_4_20_MA

#define AD5755_R_4_20_MA   4

◆ AD5755_R_M10_P10_V

#define AD5755_R_M10_P10_V   3

◆ AD5755_R_M5_P5_V

#define AD5755_R_M5_P5_V   2

◆ AD5755_RD_CODE_REG

#define AD5755_RD_CODE_REG (   x)    (((x) & 0x3) + 16)

◆ AD5755_RD_CTRL_REG

#define AD5755_RD_CTRL_REG (   x)    (((x) & 0x3) + 4)

◆ AD5755_RD_DATA_REG

#define AD5755_RD_DATA_REG (   x)    (((x) & 0x3) + 0)

◆ AD5755_RD_Dc_DC_CTRL_REG

#define AD5755_RD_Dc_DC_CTRL_REG   26

◆ AD5755_RD_GAIN_REG

#define AD5755_RD_GAIN_REG (   x)    (((x) & 0x3) + 8)

◆ AD5755_RD_MAIN_CTRL_REG

#define AD5755_RD_MAIN_CTRL_REG   25

◆ AD5755_RD_OFFSET_REG

#define AD5755_RD_OFFSET_REG (   x)    (((x) & 0x3) + 12)

◆ AD5755_RD_SR_CTRL_REG

#define AD5755_RD_SR_CTRL_REG (   x)    (((x) & 0x3) + 20)

◆ AD5755_RD_STATUS_REG

#define AD5755_RD_STATUS_REG   24

◆ AD5755_RESET_CODE

#define AD5755_RESET_CODE   0x555

◆ AD5755_RESET_HIGH

#define AD5755_RESET_HIGH
Value:
gpio_set_value(dev->gpio_rst, \

◆ AD5755_RESET_LOW

#define AD5755_RESET_LOW
Value:
gpio_set_value(dev->gpio_rst, \

◆ AD5755_RESET_OUT

#define AD5755_RESET_OUT
Value:

◆ AD5755_SLEW_SR_CLOCK

#define AD5755_SLEW_SR_CLOCK (   x)    (((x) & 0xF) << 3)

◆ AD5755_SLEW_SR_STEP

#define AD5755_SLEW_SR_STEP (   x)    (((x) & 0x7) << 0)

◆ AD5755_SLEW_SREN

#define AD5755_SLEW_SREN   (1 << 12)

◆ AD5755_SOFT_RESET_CODE

#define AD5755_SOFT_RESET_CODE (   x)    ((x) & 0xFFF)

◆ AD5755_SOFT_USER_BIT

#define AD5755_SOFT_USER_BIT   (1 << 12)

◆ AD5755_SPI_CODE

#define AD5755_SPI_CODE   0x195

◆ AD5755_SR_CLK_0_5

#define AD5755_SR_CLK_0_5   15

◆ AD5755_SR_CLK_125

#define AD5755_SR_CLK_125   9

◆ AD5755_SR_CLK_16

#define AD5755_SR_CLK_16   12

◆ AD5755_SR_CLK_16k

#define AD5755_SR_CLK_16k   2

◆ AD5755_SR_CLK_1K

#define AD5755_SR_CLK_1K   6

◆ AD5755_SR_CLK_250

#define AD5755_SR_CLK_250   8

◆ AD5755_SR_CLK_2K

#define AD5755_SR_CLK_2K   5

◆ AD5755_SR_CLK_32

#define AD5755_SR_CLK_32   11

◆ AD5755_SR_CLK_32k

#define AD5755_SR_CLK_32k   1

◆ AD5755_SR_CLK_4

#define AD5755_SR_CLK_4   14

◆ AD5755_SR_CLK_4K

#define AD5755_SR_CLK_4K   4

◆ AD5755_SR_CLK_500

#define AD5755_SR_CLK_500   7

◆ AD5755_SR_CLK_64

#define AD5755_SR_CLK_64   10

◆ AD5755_SR_CLK_64K

#define AD5755_SR_CLK_64K   0

◆ AD5755_SR_CLK_8

#define AD5755_SR_CLK_8   13

◆ AD5755_SR_CLK_8K

#define AD5755_SR_CLK_8K   3

◆ AD5755_STATUS_DC_DC

#define AD5755_STATUS_DC_DC (   x)    (1 << (12 + (x)))

◆ AD5755_STATUS_IOUT_FAULT

#define AD5755_STATUS_IOUT_FAULT (   x)    (1 << (0 + (x)))

◆ AD5755_STATUS_OVER_TEMP

#define AD5755_STATUS_OVER_TEMP   (1 << 8)

◆ AD5755_STATUS_PEC_ERROR

#define AD5755_STATUS_PEC_ERROR   (1 << 10)

◆ AD5755_STATUS_RAMP_ACTIVE

#define AD5755_STATUS_RAMP_ACTIVE   (1 << 9)

◆ AD5755_STATUS_USER_BIT

#define AD5755_STATUS_USER_BIT   (1 << 11)

◆ AD5755_STATUS_VOUT_FAULT

#define AD5755_STATUS_VOUT_FAULT (   x)    (1 << (4 + (x)))

◆ AD5755_STEP_1

#define AD5755_STEP_1   0

◆ AD5755_STEP_128

#define AD5755_STEP_128   6

◆ AD5755_STEP_16

#define AD5755_STEP_16   3

◆ AD5755_STEP_2

#define AD5755_STEP_2   1

◆ AD5755_STEP_256

#define AD5755_STEP_256   7

◆ AD5755_STEP_32

#define AD5755_STEP_32   4

◆ AD5755_STEP_4

#define AD5755_STEP_4   2

◆ AD5755_STEP_64

#define AD5755_STEP_64   5

◆ AD5755_WD_100MS

#define AD5755_WD_100MS   2

◆ AD5755_WD_10MS

#define AD5755_WD_10MS   1

◆ AD5755_WD_200MS

#define AD5755_WD_200MS   3

◆ AD5755_WD_5MS

#define AD5755_WD_5MS   0

Enumeration Type Documentation

◆ ad5755_type_t

Enumerator
ID_AD5755 
ID_AD5755_1 
ID_AD5757 

Function Documentation

◆ ad5755_channel_clear_enable()

void ad5755_channel_clear_enable ( struct ad5755_dev dev,
uint8_t  channel,
uint8_t  clear_en 
)

Selects if the channel clears when CLEAR pin is activated.

Selects if the channel clears when CLEAR pin is activated.

Parameters
dev- The device structure.
channel- Channel option. Example: AD5755_DAC_A AD5755_DAC_B AD5755_DAC_C AD5755_DAC_D
clear_en- Clear Enable option. Example: 1 - channel clears when the part is cleared; 0 - channel does not clear when the part is cleared.
Returns
None.

◆ ad5755_check_crc()

uint8_t ad5755_check_crc ( uint8_t *  data,
uint8_t  bytes_number 
)

Computes the CRC for a data buffer.

Computes the CRC for a data buffer.

Parameters
data- Data buffer.
bytes_number- Data buffer size in bytes.
Returns
The computed CRC.
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◆ ad5755_feed_watch_dog_timer()

void ad5755_feed_watch_dog_timer ( struct ad5755_dev dev)

Write a "service pulse" to the AD5755 watchdog timer when enabled.

Writes a "service pulse" to the AD5755 watchdog timer when enabled.

Parameters
dev- The device structure.
Returns
None.

◆ ad5755_get_register_value()

int32_t ad5755_get_register_value ( struct ad5755_dev dev,
uint8_t  register_address 
)

Reads the value of a register.

Reads the value of a register.

Parameters
dev- The device structure.
register_address- Address of the register. Example: AD5755_RD_DATA_REG(x) AD5755_RD_CTRL_REG(x) AD5755_RD_GAIN_REG(x) AD5755_RD_OFFSET_REG(x) AD5755_RD_CODE_REG(x) AD5755_RD_SR_CTRL_REG(x) AD5755_RD_STATUS_REG AD5755_RD_MAIN_CTRL_REG AD5755_RD_Dc_DC_CTRL_REG x = any of AD5755_DAC_A, .. AD5755_DAC_D
Returns
regValue - Value of the register.
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◆ ad5755_init()

int8_t ad5755_init ( struct ad5755_dev **  device,
struct ad5755_init_param  init_param 
)

Initializes the device and powers-up all channels. The device is initialized with the values held by AD5755_InitialSettings structure.

Initializes the device and powers-up all channels.

Parameters
device- The device structure.
init_param- The structure that contains the device initial parameters.
Returns
status - Result of the initialization procedure. Example: -1 - SPI peripheral was not initialized. 0 - SPI peripheral is initialized.

◆ ad5755_remove()

int32_t ad5755_remove ( struct ad5755_dev dev)

Free the resources allocated by ad5755_init().

Free the resources allocated by ad5755_init().

Parameters
dev- The device structure.
Returns
SUCCESS in case of success, negative error code otherwise.

◆ ad5755_set_channel_power()

void ad5755_set_channel_power ( struct ad5755_dev dev,
uint8_t  channel,
uint8_t  pwr_status 
)

Allows power-up/down of the dc-to-dc converter, DAC and internal amplifiers for the selected channel.

Allows power-up/down of the dc-to-dc converter, DAC and internal amplifiers for the selected channel.

Parameters
dev- The device structure.
channel- Channel option. Example: AD5755_DAC_A AD5755_DAC_B AD5755_DAC_C AD5755_DAC_D
pwr_status- Power mode. Example: 0 - power-down the channel; 1 - power-up the channel.
Returns
None.

◆ ad5755_set_channel_range()

void ad5755_set_channel_range ( struct ad5755_dev dev,
uint8_t  channel,
uint8_t  range 
)

Sets the range of a channel.

Sets the range of a channel.

Parameters
dev- The device structure.
channel- Channel option. Example: AD5755_DAC_A AD5755_DAC_B AD5755_DAC_C AD5755_DAC_D
range- Range option. Example: AD5755_R_0_5_V - 0 V to 5 V voltage range (default) AD5755_R_0_10_V - 0 V to 10 V voltage range AD5755_R_M5_P5_V - -5 V to +5 V voltage range AD5755_R_M10_P10_V - -10 V to 10 V voltage range AD5755_R_4_20_MA - 4 mA to 20 mA current range AD5755_R_0_20_MA - 0 mA to 20 mA current range AD5755_R_0_24_MA - 0 mA to 24 mA current range
Returns
None.

◆ ad5755_set_control_registers()

void ad5755_set_control_registers ( struct ad5755_dev dev,
uint8_t  ctrl_reg_address,
uint8_t  channel,
uint16_t  reg_value 
)

Configures one of the control registers.

Configures one of the control registers.

Parameters
dev- The device structure.
ctrl_reg_address- Control Register Address. Example: AD5755_CREG_SLEW AD5755_CREG_MAIN AD5755_CREG_DAC AD5755_CREG_DC_DC AD5755_CREG_SOFT
channel- Channel option. Example: AD5755_DAC_A AD5755_DAC_B AD5755_DAC_C AD5755_DAC_D
reg_value- Value to be written to the selected Control Register.
Returns
None.
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◆ ad5755_set_current()

float ad5755_set_current ( struct ad5755_dev dev,
uint8_t  channel,
float  m_acurrent 
)

Sets the output current of a channel.

Sets the output current of a channel.

Parameters
dev- The device structure.
channel- Channel option. Example: AD5755_DAC_A AD5755_DAC_B AD5755_DAC_C AD5755_DAC_D
m_acurrent- Value to be outputted by the DAC(milliampere).
Returns
The actual current value that can be outputted by the channel.

◆ ad5755_set_register_value()

uint16_t ad5755_set_register_value ( struct ad5755_dev dev,
uint8_t  register_address,
uint8_t  channel,
uint16_t  register_value 
)

Writes data into a register.

Writes data into a register.

Parameters
dev- The device structure.
register_address- Address of the register. Example: AD5755_DREG_WR_DAC AD5755_DREG_WR_GAIN AD5755_DREG_WR_GAIN_ALL AD5755_DREG_WR_OFFSET AD5755_DREG_WR_OFFSET_ALL AD5755_DREG_WR_CLR_CODE AD5755_DREG_WR_CTRL_REG
channel- Channel option. Example: AD5755_DAC_A AD5755_DAC_B AD5755_DAC_C AD5755_DAC_D
register_value- Data value to write.
Returns
None.
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◆ ad5755_set_voltage()

float ad5755_set_voltage ( struct ad5755_dev dev,
uint8_t  channel,
float  voltage 
)

Sets the output voltage of a channel.

Sets the output voltage of a channel.

Parameters
dev- The device structure.
channel- Channel option. Example: AD5755_DAC_A AD5755_DAC_B AD5755_DAC_C AD5755_DAC_D
voltage- Value to be outputted by the DAC(Volts).
Returns
The actual voltage value that can be outputted by the channel.

◆ ad5755_slew_rate_ctrl()

void ad5755_slew_rate_ctrl ( struct ad5755_dev dev,
int8_t  channel,
int8_t  sr_en,
int8_t  updt_freq,
int8_t  step_size 
)

Configures the Digital Slew Rate Control.

Configures the Digital Slew Rate Control.

Parameters
dev- The device structure.
channel- Channel option. Example: AD5755_DAC_A AD5755_DAC_B AD5755_DAC_C AD5755_DAC_D
sr_en- Enable/Disable the Slew Rate Control. Example: 0 - disable feature; 1 - enable feature.
updt_freq- Update Clock Frequency(Hz). Example: AD5755_SR_CLK_64K AD5755_SR_CLK_32k ... AD5755_SR_CLK_8 AD5755_SR_CLK_4 AD5755_SR_CLK_0_5
step_size- Step Size (LSBs). Example: AD5755_STEP_1 AD5755_STEP_2 ... AD5755_STEP_128 AD5755_STEP_256
Returns
None.

◆ ad5755_software_reset()

void ad5755_software_reset ( struct ad5755_dev dev)

Performs a software reset to the device.

Performs a software reset to the device.

Parameters
dev- The device structure.
Returns
None.
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◆ ad5755_watch_dog_setup()

void ad5755_watch_dog_setup ( struct ad5755_dev dev,
uint8_t  wtd_enable,
uint8_t  timeout 
)

Enables/Disables watchdog timer and sets the timeout period.

Enables/Disables watchdog timer and sets the timeout period.

Parameters
dev- The device structure.
wtd_enable- Watchdog enable option. Example: 0 - disables watchdog timer 1 - enabled watchdog timer
timeout- Timeout period for the watchdog timer. Example: AD5755_WD_5MS AD5755_WD_10MS AD5755_WD_100MS AD5755_WD_200MS
Returns
None.
gpio_direction_output
int32_t gpio_direction_output(struct gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: gpio.c:124
GPIO_LOW
@ GPIO_LOW
Definition: gpio.h:99
gpio_set_value
int32_t gpio_set_value(struct gpio_desc *desc, uint8_t value)
Set the value of the specified GPIO.
Definition: gpio.c:160
GPIO_HIGH
@ GPIO_HIGH
Definition: gpio.h:101
iio_app_device::dev
void * dev
Definition: iio_app.h:60