no-OS
ad5755.h
Go to the documentation of this file.
1 /***************************************************************************/
40 #ifndef __AD5755_H__
41 #define __AD5755_H__
42 
43 /******************************************************************************/
44 /***************************** Include Files **********************************/
45 /******************************************************************************/
46 #include <stdint.h>
47 #include "no_os_delay.h"
48 #include "no_os_gpio.h"
49 #include "no_os_spi.h"
50 
51 /******************************************************************************/
52 /******************* Macros and Constants Definitions *************************/
53 /******************************************************************************/
54 
55 /******************************************************************************/
56 /******************************** AD5755 **************************************/
57 /******************************************************************************/
58 
59 /* LDAC */
60 #define AD5755_LDAC_OUT no_os_gpio_direction_output(dev->gpio_ldac, \
61  NO_OS_GPIO_HIGH);
62 #define AD5755_LDAC_LOW no_os_gpio_set_value(dev->gpio_ldac, \
63  NO_OS_GPIO_LOW)
64 #define AD5755_LDAC_HIGH no_os_gpio_set_value(dev->gpio_ldac, \
65  NO_OS_GPIO_HIGH)
66 
67 /* RESET */
68 #define AD5755_RESET_OUT no_os_gpio_direction_output(dev->gpio_rst, \
69  NO_OS_GPIO_HIGH);
70 #define AD5755_RESET_LOW no_os_gpio_set_value(dev->gpio_rst, \
71  NO_OS_GPIO_LOW)
72 #define AD5755_RESET_HIGH no_os_gpio_set_value(dev->gpio_rst, \
73  NO_OS_GPIO_HIGH)
74 
75 /* CLEAR */
76 #define AD5755_CLEAR_OUT no_os_gpio_direction_output(dev->gpio_clr, \
77  NO_OS_GPIO_HIGH);
78 #define AD5755_CLEAR_LOW no_os_gpio_set_value(dev->gpio_clr, \
79  NO_OS_GPIO_LOW)
80 #define AD5755_CLEAR_HIGH no_os_gpio_set_value(dev->gpio_clr, \
81  NO_OS_GPIO_HIGH)
82 
83 /* POC */
84 #define AD5755_POC_OUT no_os_gpio_direction_output(dev->gpio_poc, \
85  NO_OS_GPIO_HIGH);
86 #define AD5755_POC_LOW no_os_gpio_set_value(dev->gpio_poc, \
87  NO_OS_GPIO_LOW)
88 #define AD5755_POC_HIGH no_os_gpio_set_value(dev->gpio_poc, \
89  NO_OS_GPIO_HIGH)
90 
91 /* Input Shift Register Contents for a Write Operation. */
92 #define AD5755_ISR_WRITE (0ul << 23) /* R/nW */
93 #define AD5755_ISR_DUT_AD1(x) (((x) & 0x1) << 22) /* Device AddrBit1*/
94 #define AD5755_ISR_DUT_AD0(x) (((x) & 0x1) << 21) /* Device AddrBit0*/
95 #define AD5755_ISR_DREG(x) (((x) & 0x7) << 18) /* Register AddrBits*/
96 #define AD5755_ISR_DAC_AD(x) (((x) & 0x3) << 16) /* Channel AddrBits */
97 #define AD5755_ISR_DATA(x) ((x) & 0xFFFF) /* Data Bits*/
98 
99 /* Nop operation code. */
100 #define AD5755_ISR_NOP 0x1CE000
101 
102 /* AD5755_ISR_DREG(x) options. (Register addresses) */
103 #define AD5755_DREG_WR_DAC 0
104 #define AD5755_DREG_WR_GAIN 2
105 #define AD5755_DREG_WR_GAIN_ALL 3
106 #define AD5755_DREG_WR_OFFSET 4
107 #define AD5755_DREG_WR_OFFSET_ALL 5
108 #define AD5755_DREG_WR_CLR_CODE 6
109 #define AD5755_DREG_WR_CTRL_REG 7
110 
111 /* AD5755_ISR_DAC_AD(x) options. (Channel addresses) */
112 #define AD5755_DAC_A 0
113 #define AD5755_DAC_B 1
114 #define AD5755_DAC_C 2
115 #define AD5755_DAC_D 3
116 
117 /* Gain register definition. */
118 #define AD5755_GAIN_ADJUSTMENT(x) ((x) & 0xFFFF)
119 
120 /* Offset register definition. */
121 #define AD5755_OFFSET_ADJUSTMENT(x) ((x) & 0xFFFF)
122 
123 /* Clear Code Register definition. */
124 #define AD5755_CLEAR_CODE(x) ((x) & 0xFFFF)
125 
126 /* Control Register definition. */
127 #define AD5755_CTRL_CREG(x) (((x) & 0x7) << 13)
128 #define AD5755_CTRL_DATA(x) ((x) & 0x1FFF)
129 
130 /* AD5755_CTRL_CREG(x) options. */
131 #define AD5755_CREG_SLEW 0 // Slew rate control register(one per channel)
132 #define AD5755_CREG_MAIN 1 // Main control register
133 #define AD5755_CREG_DAC 2 // DAC control register(one per channel)
134 #define AD5755_CREG_DC_DC 3 // DC-to-dc control register
135 #define AD5755_CREG_SOFT 4 // Software register
136 
137 /* Slew Rate Control Register definition. */
138 #define AD5755_SLEW_SREN (1 << 12)
139 #define AD5755_SLEW_SR_CLOCK(x) (((x) & 0xF) << 3)
140 #define AD5755_SLEW_SR_STEP(x) (((x) & 0x7) << 0)
141 
142 /* AD5755_SLEW_SR_CLOCK(x) options. */
143 #define AD5755_SR_CLK_64K 0
144 #define AD5755_SR_CLK_32k 1
145 #define AD5755_SR_CLK_16k 2
146 #define AD5755_SR_CLK_8K 3
147 #define AD5755_SR_CLK_4K 4
148 #define AD5755_SR_CLK_2K 5
149 #define AD5755_SR_CLK_1K 6
150 #define AD5755_SR_CLK_500 7
151 #define AD5755_SR_CLK_250 8
152 #define AD5755_SR_CLK_125 9
153 #define AD5755_SR_CLK_64 10
154 #define AD5755_SR_CLK_32 11
155 #define AD5755_SR_CLK_16 12
156 #define AD5755_SR_CLK_8 13
157 #define AD5755_SR_CLK_4 14
158 #define AD5755_SR_CLK_0_5 15
159 
160 /* AD5755_SLEW_SR_STEP(x) options. */
161 #define AD5755_STEP_1 0
162 #define AD5755_STEP_2 1
163 #define AD5755_STEP_4 2
164 #define AD5755_STEP_16 3
165 #define AD5755_STEP_32 4
166 #define AD5755_STEP_64 5
167 #define AD5755_STEP_128 6
168 #define AD5755_STEP_256 7
169 
170 /* Main Control Register definition. */
171 #define AD5755_MAIN_POC (1 << 12)
172 #define AD5755_MAIN_STATREAD (1 << 11)
173 #define AD5755_MAIN_EWD (1 <<10)
174 #define AD5755_MAIN_WD(x) (((x) & 0x3) << 8)
175 #define AD5755_MAIN_SHTCCTLIM(x) (((x) & 0x1) << 6)
176 #define AD5755_MAIN_OUTEN_ALL (1 << 5)
177 #define AD5755_MAIN_DCDC_ALL (1 << 4)
178 
179 /* AD5755_MAIN_WD(x) options. */
180 #define AD5755_WD_5MS 0 // 5 ms timeout period
181 #define AD5755_WD_10MS 1 // 10 ms timeout period
182 #define AD5755_WD_100MS 2 // 100 ms timeout period
183 #define AD5755_WD_200MS 3 // 200 ms timeout period
184 
185 /* AD5755_MAIN_SHTCCTLIM(x) options. */
186 #define AD5755_LIMIT_16_MA 0 // 16 mA (default)
187 #define AD5755_LIMIT_8_MA 1 // 8 mA
188 
189 /* DAC Control Register definition. */
190 #define AD5755_DAC_INT_ENABLE (1 << 8)
191 #define AD5755_DAC_CLR_EN (1 << 7)
192 #define AD5755_DAC_OUTEN (1 << 6)
193 #define AD5755_DAC_RSET (1 << 5)
194 #define AD5755_DAC_DC_DC (1 << 4)
195 #define AD5755_DAC_OVRNG (1 << 3)
196 #define AD5755_DAC_R(x) ((x) & 0x7)
197 
198 /* AD5755_DAC_R(x) options. */
199 #define AD5755_R_0_5_V 0 // 0 V to 5 V voltage range (default)
200 #define AD5755_R_0_10_V 1 // 0 V to 10 V voltage range
201 #define AD5755_R_M5_P5_V 2 // -5 V to +5 V voltage range
202 #define AD5755_R_M10_P10_V 3 // -10 V to 10 V voltage range
203 #define AD5755_R_4_20_MA 4 // 4 mA to 20 mA current range
204 #define AD5755_R_0_20_MA 5 // 0 mA to 20 mA current range
205 #define AD5755_R_0_24_MA 6 // 0 mA to 24 mA current range
206 
207 /* DC-to-DC Control Register definition. */
208 #define AD5755_DC_DC_COMP (1 << 6)
209 #define AD5755_DC_DC_PHASE(x) (((x) & 0x3) << 4)
210 #define AD5755_DC_DC_FREQ(x) (((x) & 0x3) << 2)
211 #define AD5755_DC_DC_MAX_V(x) (((x) & 0x3) << 0)
212 
213 /* AD5755_DC_DC_PHASE(x) options. */
214 #define AD5755_PHASE_ALL_DC_DC 0 // all dc-dc converters clock on same edge
215 #define AD5755_PHASE_AB_CD 1 // Ch A,B clk same edge, C,D opposite edge
216 #define AD5755_PHASE_AC_BD 2 // Ch A,C clk same edge, B,D opposite edge
217 #define AD5755_PHASE_A_B_C_D_90 3 // A,B,C,D clock 90 degree out of phase
218 
219 /* AD5755_DC_DC_FREQ(x) options. */
220 #define AD5755_FREQ_250_HZ 0 // 250 +/- 10% kHz
221 #define AD5755_FREQ_410_HZ 1 // 410 +/- 10% kHz
222 #define AD5755_FREQ_650_HZ 2 // 650 +/- 10% kHz
223 
224 /* AD5755_DC_DC_MAX_V(x) options. */
225 #define AD5755_MAX_23V 0 // 23 V + 1 V/-1.5 V (default)
226 #define AD5755_MAX_24_5V 1 // 24.5 V +/- 1 V
227 #define AD5755_MAX_27V 2 // 27 V +/- 1 V
228 #define AD5755_MAX_29_5V 3 // 29.5 V +/- 1V
229 
230 /* Software Register definition. */
231 #define AD5755_SOFT_USER_BIT (1 << 12)
232 #define AD5755_SOFT_RESET_CODE(x) ((x) & 0xFFF)
233 
234 /* AD5755_SOFT_RESET_CODE(x) options. */
235 #define AD5755_RESET_CODE 0x555 // Performs a reset of the AD5755.
236 #define AD5755_SPI_CODE 0x195 // If watchdog is enabled, 0x195 must be
237 // written to the software register within
238 // the programmed timeout period.
239 
240 /* Input Shift Register Contents for a Read Operation. */
241 #define AD5755_ISR_READ (1 << 23)
242 /* Same as Input Shift Register Contents for a Write Operation. */
243 /*
244 #define AD5755_ISR_DUT_AD1(x) (((x) & 0x1) << 22)
245 #define AD5755_ISR_DUT_AD0(x) (((x) & 0x1) << 21)
246 */
247 #define AD5755_ISR_RD(x) (((x) & 0x1F) << 16)
248 
249 /* AD5755_ISR_RD(x) options. (Read address decoding) */
250 #define AD5755_RD_DATA_REG(x) (((x) & 0x3) + 0)
251 #define AD5755_RD_CTRL_REG(x) (((x) & 0x3) + 4)
252 #define AD5755_RD_GAIN_REG(x) (((x) & 0x3) + 8)
253 #define AD5755_RD_OFFSET_REG(x) (((x) & 0x3) + 12)
254 #define AD5755_RD_CODE_REG(x) (((x) & 0x3) + 16)
255 #define AD5755_RD_SR_CTRL_REG(x) (((x) & 0x3) + 20)
256 #define AD5755_RD_STATUS_REG 24
257 #define AD5755_RD_MAIN_CTRL_REG 25
258 #define AD5755_RD_Dc_DC_CTRL_REG 26
259 
260 /* Status Register definition. */
261 /* channelA = 0 ... channelD = 3 */
262 #define AD5755_STATUS_DC_DC(x) (1 << (12 + (x)))
263 #define AD5755_STATUS_USER_BIT (1 << 11)
264 #define AD5755_STATUS_PEC_ERROR (1 << 10)
265 #define AD5755_STATUS_RAMP_ACTIVE (1 << 9)
266 #define AD5755_STATUS_OVER_TEMP (1 << 8)
267 /* channelA = 0 ... channelD = 3 */
268 #define AD5755_STATUS_VOUT_FAULT(x) (1 << (4 + (x)))
269 #define AD5755_STATUS_IOUT_FAULT(x) (1 << (0 + (x)))
270 
271 #define AD5755_CRC_POLYNOMIAL 0x07 // P(x)=x^8+x^2+x^1+1 = 100000111
272 #define AD5755_CRC_CHECK_CODE 0x00
273 
274 /*****************************************************************************/
275 /************************** Types Declarations *******************************/
276 /*****************************************************************************/
282 struct ad5755_setup {
284  uint8_t pin_ad0state;
286  uint8_t pin_ad1state;
291 
299  uint8_t poc_bit;
301  uint8_t stat_readbit;
306  uint8_t sht_cc_lim_bit;
307 
312  uint8_t rset_bits[4];
314  uint8_t ovrng_bits[4];
315 
319  uint8_t dc_dc_comp_bit;
325  uint8_t dc_dc_freq_bit;
329  uint8_t dc_dc_max_vbit;
330 };
331 
332 /* Supported devices */
337 };
338 
339 struct ad5755_dev {
340  /* SPI */
342  /* GPIO */
347  /* Device Settings */
350 };
351 
353  /* SPI */
355  /* GPIO */
360  /* Device Settings */
362 };
363 
364 /******************************************************************************/
365 /************************ Functions Declarations ******************************/
366 /******************************************************************************/
367 
369 int8_t ad5755_init(struct ad5755_dev **device,
371 
373 int32_t ad5755_remove(struct ad5755_dev *dev);
374 
376 int32_t ad5755_get_register_value(struct ad5755_dev *dev,
377  uint8_t register_address);
378 
380 uint16_t ad5755_set_register_value(struct ad5755_dev *dev,
381  uint8_t register_address,
382  uint8_t channel,
383  uint16_t register_value);
384 
386 void ad5755_software_reset(struct ad5755_dev *dev);
387 
389 void ad5755_watch_dog_setup(struct ad5755_dev *dev,
390  uint8_t wtd_enable,
391  uint8_t timeout);
392 
394 void ad5755_feed_watch_dog_timer(struct ad5755_dev *dev);
395 
398  uint8_t ctrl_reg_address,
399  uint8_t channel,
400  uint16_t reg_value);
401 
403 uint8_t ad5755_check_crc(uint8_t* data,
404  uint8_t bytes_number);
405 
408 void ad5755_set_channel_power(struct ad5755_dev *dev,
409  uint8_t channel,
410  uint8_t pwr_status);
411 
413 void ad5755_set_channel_range(struct ad5755_dev *dev,
414  uint8_t channel,
415  uint8_t range);
416 
418 void ad5755_channel_clear_enable(struct ad5755_dev *dev,
419  uint8_t channel,
420  uint8_t clear_en);
421 
423 void ad5755_slew_rate_ctrl(struct ad5755_dev *dev,
424  int8_t channel,
425  int8_t sr_en,
426  int8_t updt_freq,
427  int8_t step_size);
428 
430 float ad5755_set_voltage(struct ad5755_dev *dev,
431  uint8_t channel,
432  float voltage);
433 
435 float ad5755_set_current(struct ad5755_dev *dev,
436  uint8_t channel,
437  float m_acurrent);
438 
439 #endif // __AD5755_H__
ad5755_setup::rset_bits
uint8_t rset_bits[4]
Definition: ad5755.h:312
ad5755_set_current
float ad5755_set_current(struct ad5755_dev *dev, uint8_t channel, float m_acurrent)
Sets the output current of a channel.
Definition: ad5755.c:716
ad5755_set_voltage
float ad5755_set_voltage(struct ad5755_dev *dev, uint8_t channel, float voltage)
Sets the output voltage of a channel.
Definition: ad5755.c:624
timeout
uint32_t timeout
Definition: ad413x.c:54
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
ad5755_setup::dc_dc_max_vbit
uint8_t dc_dc_max_vbit
Definition: ad5755.h:329
ad5755_setup::dc_dc_freq_bit
uint8_t dc_dc_freq_bit
Definition: ad5755.h:325
ad5755_set_voltage
float ad5755_set_voltage(struct ad5755_dev *dev, uint8_t channel, float voltage)
Sets the output voltage of a channel.
Definition: ad5755.c:624
AD5755_RD_MAIN_CTRL_REG
#define AD5755_RD_MAIN_CTRL_REG
Definition: ad5755.h:257
ad5755_dev::gpio_ldac
struct no_os_gpio_desc * gpio_ldac
Definition: ad5755.h:343
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:83
ad5755_dev::spi_desc
struct no_os_spi_desc * spi_desc
Definition: ad5755.h:341
no_os_spi.h
Header file of SPI Interface.
AD5755_DAC_INT_ENABLE
#define AD5755_DAC_INT_ENABLE
Definition: ad5755.h:190
AD5755_CRC_CHECK_CODE
#define AD5755_CRC_CHECK_CODE
Definition: ad5755.h:272
ad5755_set_current
float ad5755_set_current(struct ad5755_dev *dev, uint8_t channel, float m_acurrent)
Sets the output current of a channel.
Definition: ad5755.c:716
ad5755_dev::gpio_rst
struct no_os_gpio_desc * gpio_rst
Definition: ad5755.h:344
AD5755_DAC_CLR_EN
#define AD5755_DAC_CLR_EN
Definition: ad5755.h:191
ad5755_dev::p_ad5755_st
struct ad5755_setup * p_ad5755_st
Definition: ad5755.h:348
ad5755_type_t
ad5755_type_t
Definition: ad5755.h:333
ad5755_cfg.h
Header file of AD5755 Driver Configuration.
AD5755_SLEW_SREN
#define AD5755_SLEW_SREN
Definition: ad5755.h:138
no_os_delay.h
Header file of Delay functions.
ad5755_software_reset
void ad5755_software_reset(struct ad5755_dev *dev)
Performs a software reset to the device.
Definition: ad5755.c:309
AD5755_RD_GAIN_REG
#define AD5755_RD_GAIN_REG(x)
Definition: ad5755.h:252
AD5755_MAIN_WD
#define AD5755_MAIN_WD(x)
Definition: ad5755.h:174
ad5755_dev::this_device
enum ad5755_type_t this_device
Definition: ad5755.h:349
AD5755_DC_DC_FREQ
#define AD5755_DC_DC_FREQ(x)
Definition: ad5755.h:210
AD5755_DAC_A
#define AD5755_DAC_A
Definition: ad5755.h:112
AD5755_ISR_RD
#define AD5755_ISR_RD(x)
Definition: ad5755.h:247
ad5755_init_param::gpio_clr
struct no_os_gpio_init_param gpio_clr
Definition: ad5755.h:358
device
Definition: ad9361_util.h:75
AD5755_MAIN_POC
#define AD5755_MAIN_POC
Definition: ad5755.h:171
AD5755_LDAC_OUT
#define AD5755_LDAC_OUT
Definition: ad5755.h:60
AD5755_ISR_DATA
#define AD5755_ISR_DATA(x)
Definition: ad5755.h:97
AD5755_CREG_DC_DC
#define AD5755_CREG_DC_DC
Definition: ad5755.h:134
ad5755_setup::dc_dc_comp_bit
uint8_t dc_dc_comp_bit
Definition: ad5755.h:319
ad5755_channel_clear_enable
void ad5755_channel_clear_enable(struct ad5755_dev *dev, uint8_t channel, uint8_t clear_en)
Selects if the channel clears when CLEAR pin is activated.
Definition: ad5755.c:550
ad5755_get_register_value
int32_t ad5755_get_register_value(struct ad5755_dev *dev, uint8_t register_address)
Reads the value of a register.
Definition: ad5755.c:198
ad5755_feed_watch_dog_timer
void ad5755_feed_watch_dog_timer(struct ad5755_dev *dev)
Write a "service pulse" to the AD5755 watchdog timer when enabled.
Definition: ad5755.c:358
AD5755_ISR_DUT_AD0
#define AD5755_ISR_DUT_AD0(x)
Definition: ad5755.h:94
AD5755_DREG_WR_DAC
#define AD5755_DREG_WR_DAC
Definition: ad5755.h:103
ad5755_setup::sht_cc_lim_bit
uint8_t sht_cc_lim_bit
Definition: ad5755.h:306
ad5755_dev::gpio_clr
struct no_os_gpio_desc * gpio_clr
Definition: ad5755.h:345
AD5755_CREG_MAIN
#define AD5755_CREG_MAIN
Definition: ad5755.h:132
AD5755_ISR_DREG
#define AD5755_ISR_DREG(x)
Definition: ad5755.h:95
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
AD5755_POC_LOW
#define AD5755_POC_LOW
Definition: ad5755.h:86
AD5755_DC_DC_MAX_V
#define AD5755_DC_DC_MAX_V(x)
Definition: ad5755.h:211
ad5755_watch_dog_setup
void ad5755_watch_dog_setup(struct ad5755_dev *dev, uint8_t wtd_enable, uint8_t timeout)
Enables/Disables watchdog timer and sets the timeout period.
Definition: ad5755.c:332
AD5755_R_0_10_V
#define AD5755_R_0_10_V
Definition: ad5755.h:200
ID_AD5757
@ ID_AD5757
Definition: ad5755.h:336
ad5755_channel_clear_enable
void ad5755_channel_clear_enable(struct ad5755_dev *dev, uint8_t channel, uint8_t clear_en)
Selects if the channel clears when CLEAR pin is activated.
Definition: ad5755.c:550
AD5755_DREG_WR_CTRL_REG
#define AD5755_DREG_WR_CTRL_REG
Definition: ad5755.h:109
ad5755_setup::poc_bit
uint8_t poc_bit
Definition: ad5755.h:299
ID_AD5755
@ ID_AD5755
Definition: ad5755.h:334
ad5755_slew_rate_ctrl
void ad5755_slew_rate_ctrl(struct ad5755_dev *dev, int8_t channel, int8_t sr_en, int8_t updt_freq, int8_t step_size)
Configures the Digital Slew Rate Control.
Definition: ad5755.c:597
ad5755.h
Header file of AD5755 Driver. This driver supporting the following devices: AD5755,...
ad5755_dev
Definition: ad5755.h:339
AD5755_ISR_DAC_AD
#define AD5755_ISR_DAC_AD(x)
Definition: ad5755.h:96
ad5755_init_param::gpio_poc
struct no_os_gpio_init_param gpio_poc
Definition: ad5755.h:359
AD5755_MAIN_STATREAD
#define AD5755_MAIN_STATREAD
Definition: ad5755.h:172
AD5755_MAIN_EWD
#define AD5755_MAIN_EWD
Definition: ad5755.h:173
ad5755_init_param::this_device
enum ad5755_type_t this_device
Definition: ad5755.h:361
ad5755_set_channel_range
void ad5755_set_channel_range(struct ad5755_dev *dev, uint8_t channel, uint8_t range)
Sets the range of a channel.
Definition: ad5755.c:487
ad5755_setup::dc_dc_phase_bit
uint8_t dc_dc_phase_bit
Definition: ad5755.h:323
AD5755_st
struct ad5755_setup AD5755_st
Definition: ad5755_cfg.h:43
AD5755_ISR_DUT_AD1
#define AD5755_ISR_DUT_AD1(x)
Definition: ad5755.h:93
AD5755_ISR_READ
#define AD5755_ISR_READ
Definition: ad5755.h:241
AD5755_DC_DC_PHASE
#define AD5755_DC_DC_PHASE(x)
Definition: ad5755.h:209
AD5755_RD_CTRL_REG
#define AD5755_RD_CTRL_REG(x)
Definition: ad5755.h:251
AD5755_LDAC_LOW
#define AD5755_LDAC_LOW
Definition: ad5755.h:62
ad5755_feed_watch_dog_timer
void ad5755_feed_watch_dog_timer(struct ad5755_dev *dev)
Write a "service pulse" to the AD5755 watchdog timer when enabled.
Definition: ad5755.c:358
AD5755_CLEAR_OUT
#define AD5755_CLEAR_OUT
Definition: ad5755.h:76
AD5755_ISR_NOP
#define AD5755_ISR_NOP
Definition: ad5755.h:100
ad5755_init_param::spi_init
struct no_os_spi_init_param spi_init
Definition: ad5755.h:354
ad5755_set_register_value
uint16_t ad5755_set_register_value(struct ad5755_dev *dev, uint8_t register_address, uint8_t channel, uint16_t register_value)
Writes data into a register.
Definition: ad5755.c:266
AD5755_SLEW_SR_STEP
#define AD5755_SLEW_SR_STEP(x)
Definition: ad5755.h:140
AD5755_SPI_CODE
#define AD5755_SPI_CODE
Definition: ad5755.h:236
ad5755_slew_rate_ctrl
void ad5755_slew_rate_ctrl(struct ad5755_dev *dev, int8_t channel, int8_t sr_en, int8_t updt_freq, int8_t step_size)
Configures the Digital Slew Rate Control.
Definition: ad5755.c:597
no_os_gpio_remove
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:95
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:143
AD5755_DAC_OUTEN
#define AD5755_DAC_OUTEN
Definition: ad5755.h:192
ad5755_dev::gpio_poc
struct no_os_gpio_desc * gpio_poc
Definition: ad5755.h:346
ad5755_remove
int32_t ad5755_remove(struct ad5755_dev *dev)
Free the resources allocated by ad5755_init().
Definition: ad5755.c:163
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
AD5755_ISR_WRITE
#define AD5755_ISR_WRITE
Definition: ad5755.h:92
ad5755_setup
Stores the settings that will be written to the device when the "AD5755_Init" functions is called.
Definition: ad5755.h:282
ad5755_setup::pin_ad1state
uint8_t pin_ad1state
Definition: ad5755.h:286
ad5755_check_crc
uint8_t ad5755_check_crc(uint8_t *data, uint8_t bytes_number)
Computes the CRC for a data buffer.
Definition: ad5755.c:406
AD5755_RD_OFFSET_REG
#define AD5755_RD_OFFSET_REG(x)
Definition: ad5755.h:253
no_os_gpio_get
int32_t no_os_gpio_get(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Obtain the GPIO decriptor.
Definition: no_os_gpio.c:55
ad5755_set_control_registers
void ad5755_set_control_registers(struct ad5755_dev *dev, uint8_t ctrl_reg_address, uint8_t channel, uint16_t reg_value)
Configures one of the control registers.
Definition: ad5755.c:387
ad5755_setup::stat_readbit
uint8_t stat_readbit
Definition: ad5755.h:301
ad5755_init
int8_t ad5755_init(struct ad5755_dev **device, struct ad5755_init_param init_param)
Initializes the device and powers-up all channels. The device is initialized with the values held by ...
Definition: ad5755.c:63
ad5755_set_channel_range
void ad5755_set_channel_range(struct ad5755_dev *dev, uint8_t channel, uint8_t range)
Sets the range of a channel.
Definition: ad5755.c:487
AD5755_DAC_D
#define AD5755_DAC_D
Definition: ad5755.h:115
ad5755_get_register_value
int32_t ad5755_get_register_value(struct ad5755_dev *dev, uint8_t register_address)
Reads the value of a register.
Definition: ad5755.c:198
AD5755_RESET_CODE
#define AD5755_RESET_CODE
Definition: ad5755.h:235
AD5755_POC_OUT
#define AD5755_POC_OUT
Definition: ad5755.h:84
AD5755_DC_DC_COMP
#define AD5755_DC_DC_COMP
Definition: ad5755.h:208
AD5755_R_M10_P10_V
#define AD5755_R_M10_P10_V
Definition: ad5755.h:202
AD5755_R_0_5_V
#define AD5755_R_0_5_V
Definition: ad5755.h:199
ad5755_remove
int32_t ad5755_remove(struct ad5755_dev *dev)
Free the resources allocated by ad5755_init().
Definition: ad5755.c:163
AD5755_R_0_20_MA
#define AD5755_R_0_20_MA
Definition: ad5755.h:204
AD5755_CREG_SLEW
#define AD5755_CREG_SLEW
Definition: ad5755.h:131
ad5755_setup::pin_ad0state
uint8_t pin_ad0state
Definition: ad5755.h:284
AD5755_DAC_DC_DC
#define AD5755_DAC_DC_DC
Definition: ad5755.h:194
AD5755_R_4_20_MA
#define AD5755_R_4_20_MA
Definition: ad5755.h:203
ad5755_check_crc
uint8_t ad5755_check_crc(uint8_t *data, uint8_t bytes_number)
Computes the CRC for a data buffer.
Definition: ad5755.c:406
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
ad5755_watch_dog_setup
void ad5755_watch_dog_setup(struct ad5755_dev *dev, uint8_t wtd_enable, uint8_t timeout)
Enables/Disables watchdog timer and sets the timeout period.
Definition: ad5755.c:332
ad5755_set_control_registers
void ad5755_set_control_registers(struct ad5755_dev *dev, uint8_t ctrl_reg_address, uint8_t channel, uint16_t reg_value)
Configures one of the control registers.
Definition: ad5755.c:387
ad5755_software_reset
void ad5755_software_reset(struct ad5755_dev *dev)
Performs a software reset to the device.
Definition: ad5755.c:309
AD5755_MAIN_SHTCCTLIM
#define AD5755_MAIN_SHTCCTLIM(x)
Definition: ad5755.h:175
ad5755_init
int8_t ad5755_init(struct ad5755_dev **device, struct ad5755_init_param init_param)
Initializes the device and powers-up all channels. The device is initialized with the values held by ...
Definition: ad5755.c:63
ad5755_setup::enable_packet_error_check
uint8_t enable_packet_error_check
Definition: ad5755.h:290
AD5755_R_0_24_MA
#define AD5755_R_0_24_MA
Definition: ad5755.h:205
AD5755_SLEW_SR_CLOCK
#define AD5755_SLEW_SR_CLOCK(x)
Definition: ad5755.h:139
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:71
no_os_gpio.h
Header file of GPIO Interface.
AD5755_RESET_OUT
#define AD5755_RESET_OUT
Definition: ad5755.h:68
AD5755_DAC_R
#define AD5755_DAC_R(x)
Definition: ad5755.h:196
ID_AD5755_1
@ ID_AD5755_1
Definition: ad5755.h:335
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
ad5755_init_param::gpio_rst
struct no_os_gpio_init_param gpio_rst
Definition: ad5755.h:357
AD5755_CTRL_CREG
#define AD5755_CTRL_CREG(x)
Definition: ad5755.h:127
AD5755_RESET_HIGH
#define AD5755_RESET_HIGH
Definition: ad5755.h:72
ad5755_init_param
Definition: ad5755.h:352
ad5755_setup::ovrng_bits
uint8_t ovrng_bits[4]
Definition: ad5755.h:314
AD5755_R_M5_P5_V
#define AD5755_R_M5_P5_V
Definition: ad5755.h:201
ad5755_set_channel_power
void ad5755_set_channel_power(struct ad5755_dev *dev, uint8_t channel, uint8_t pwr_status)
Allows power-up/down of the dc-to-dc converter, DAC and internal amplifiers for the selected channel.
Definition: ad5755.c:444
ad5755_set_register_value
uint16_t ad5755_set_register_value(struct ad5755_dev *dev, uint8_t register_address, uint8_t channel, uint16_t register_value)
Writes data into a register.
Definition: ad5755.c:266
ad5755_init_param::gpio_ldac
struct no_os_gpio_init_param gpio_ldac
Definition: ad5755.h:356
AD5755_CREG_SOFT
#define AD5755_CREG_SOFT
Definition: ad5755.h:135
AD5755_CRC_POLYNOMIAL
#define AD5755_CRC_POLYNOMIAL
Definition: ad5755.h:271
ad5755_set_channel_power
void ad5755_set_channel_power(struct ad5755_dev *dev, uint8_t channel, uint8_t pwr_status)
Allows power-up/down of the dc-to-dc converter, DAC and internal amplifiers for the selected channel.
Definition: ad5755.c:444
AD5755_CREG_DAC
#define AD5755_CREG_DAC
Definition: ad5755.h:133
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:121
AD5755_CLEAR_LOW
#define AD5755_CLEAR_LOW
Definition: ad5755.h:78