no-OS
ad713x.h
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1 /***************************************************************************/
41 /*
42  * Supported parts:
43  * - AD7134;
44  * - AD4134.
45  */
46 
47 #ifndef SRC_AD713X_H_
48 #define SRC_AD713X_H_
49 
50 /******************************************************************************/
51 /***************************** Include Files **********************************/
52 /******************************************************************************/
53 
54 #include <stdbool.h>
55 #include <stdio.h>
56 #include "no_os_spi.h"
57 #include "no_os_gpio.h"
58 #include "no_os_util.h"
59 
60 /******************************************************************************/
61 /********************** Macros and Constants Definitions **********************/
62 /******************************************************************************/
63 /*
64  * AD713X registers definition
65  */
66 #define AD713X_REG_INTERFACE_CONFIG_A 0x00
67 #define AD713X_REG_INTERFACE_CONFIG_B 0x01
68 #define AD713X_REG_DEVICE_CONFIG 0x02
69 #define AD713X_REG_CHIP_TYPE 0x03
70 #define AD713X_REG_PRODUCT_ID_LSB 0x04
71 #define AD713X_REG_PRODUCT_ID_MSB 0x05
72 #define AD713X_REG_CHIP_GRADE 0x06
73 #define AD713X_REG_CHIP_INDEX 0x07
74 #define AD713X_REG_SCTATCH_PAD 0x0A
75 #define AD713X_REG_SPI_REVISION 0x0B
76 #define AD713X_REG_VENDOR_ID_LSB 0x0C
77 #define AD713X_REG_VENDOR_ID_MSB 0x0D
78 #define AD713X_REG_STREAM_MODE 0x0E
79 #define AD713X_REG_TRANSFER_REGISTER 0x0F
80 #define AD713X_REG_DEVICE_CONFIG1 0x10
81 #define AD713X_REG_DATA_PACKET_CONFIG 0x11
82 #define AD713X_REG_DIGITAL_INTERFACE_CONFIG 0x12
83 #define AD713X_REG_POWER_DOWN_CONTROL 0x13
84 #define AD713X_REG_AIN_RANGE_SELECT 0x14
85 #define AD713X_REG_DEVICE_STATUS 0x15
86 #define AD713X_REG_ODR_VAL_INT_LSB 0x16
87 #define AD713X_REG_ODR_VAL_INT_MID 0x17
88 #define AD713X_REG_ODR_VAL_INT_MSB 0x18
89 #define AD713X_REG_ODR_VAL_FLT_LSB 0x19
90 #define AD713X_REG_ODR_VAL_FLT_MID0 0x1A
91 #define AD713X_REG_ODR_VAL_FLT_MID1 0x1B
92 #define AD713X_REG_ODR_VAL_FLT_MSB 0x1C
93 #define AD713X_REG_CHANNEL_ODR_SELECT 0x1D
94 #define AD713X_REG_CHAN_DIG_FILTER_SEL 0x1E
95 #define AD713X_REG_FIR_BW_SEL 0x1F
96 #define AD713X_REG_GPIO_DIR_CTRL 0x20
97 #define AD713X_REG_GPIO_DATA 0x21
98 #define AD713X_REG_ERROR_PIN_SRC_CONTROL 0x22
99 #define AD713X_REG_ERROR_PIN_CONTROL 0x23
100 #define AD713X_REG_VCMBUF_CTRL 0x24
101 #define AD713X_REG_DIAGNOSTIC_CONTROL 0x25
102 #define AD713X_REG_MPC_CONFIG 0x26
103 #define AD713X_REG_CH0_GAIN_LSB 0x27
104 #define AD713X_REG_CH0_GAIN_MID 0x28
105 #define AD713X_REG_CH0_GAIN_MSB 0x29
106 #define AD713X_REG_CH0_OFFSET_LSB 0x2A
107 #define AD713X_REG_CH0_OFFSET_MID 0x2B
108 #define AD713X_REG_CH0_OFFSET_MSB 0x2C
109 #define AD713X_REG_CH1_GAIN_LSB 0x2D
110 #define AD713X_REG_CH1_GAIN_MID 0x2E
111 #define AD713X_REG_CH1_GAIN_MSB 0x2F
112 #define AD713X_REG_CH1_OFFSET_LSB 0x30
113 #define AD713X_REG_CH1_OFFSET_MID 0x31
114 #define AD713X_REG_CH1_OFFSET_MSB 0x32
115 #define AD713X_REG_CH2_GAIN_LSB 0x33
116 #define AD713X_REG_CH2_GAIN_MID 0x34
117 #define AD713X_REG_CH2_GAIN_MSB 0x35
118 #define AD713X_REG_CH2_OFFSET_LSB 0x36
119 #define AD713X_REG_CH2_OFFSET_MID 0x37
120 #define AD713X_REG_CH2_OFFSET_MSB 0x38
121 #define AD713X_REG_CH3_GAIN_LSB 0x39
122 #define AD713X_REG_CH3_GAIN_MID 0x3A
123 #define AD713X_REG_CH3_GAIN_MSB 0x3B
124 #define AD713X_REG_CH3_OFFSET_LSB 0x3C
125 #define AD713X_REG_CH3_OFFSET_MID 0x3D
126 #define AD713X_REG_CH3_OFFSET_MSB 0x3E
127 #define AD713X_REG_MCLK_COUNTER 0x3F
128 #define AD713X_REG_DIG_FILTER_OFUF 0x40
129 #define AD713X_REG_DIG_FILTER_SETTLED 0x41
130 #define AD713X_REG_INTERNAL_ERROR 0x42
131 #define AD713X_REG_POWER_OV_ERROR_1 0x43
132 #define AD713X_REG_POWER_UV_ERROR_1 0x44
133 #define AD713X_REG_POWER_OV_ERROR_2 0x45
134 #define AD713X_REG_POWER_UV_ERROR_2 0x46
135 #define AD713X_REG_SPI_ERROR 0x47
136 #define AD713X_REG_AIN_OR_ERROR 0x48
137 #define AD713X_REG_AVDD5_VALUE 0x49
138 #define AD713X_REG_DVDD5_VALUE 0x4A
139 #define AD713X_REG_VREF_VALUE 0x4B
140 #define AD713X_REG_LDOIN_VALUE 0x4C
141 #define AD713X_REG_AVDD1V8_VALUE 0x4D
142 #define AD713X_REG_DVDD1V8_VALUE 0x4E
143 #define AD713X_REG_CLKVDD_VALUE 0x4F
144 #define AD713X_REG_IOVDD_VALUE 0x50
145 #define AD713X_REG_TEMPERATURE_DATA 0x51
146 
147 /*
148  * AD713X_REG_INTERFACE_CONFIG_A
149  */
150 #define AD713X_INT_CONFIG_A_SOFT_RESET_MSK NO_OS_BIT(7)
151 #define AD713X_INT_CONFIG_A_ADDR_ASC_BIT_MSK NO_OS_BIT(5)
152 #define AD713X_INT_CONFIG_A_SDO_ACTIVE_BIT_MSK NO_OS_BIT(4)
153 #define AD713X_INT_CONFIG_A_SOFT_RESET_MIRR_MSK NO_OS_BIT(0)
154 #define AD713X_INT_CONFIG_A_ADDR_ASC_MIRR_MSK NO_OS_BIT(2)
155 #define AD713X_INT_CONFIG_A_SDO_ACTIVE_MIRR_MSK NO_OS_BIT(3)
156 
157 /*
158  * AD713X_REG_INTERFACE_CONFIG_B
159  */
160 #define AD713X_INT_CONFIG_B_SINGLE_INSTR_MSK NO_OS_BIT(7)
161 #define AD713X_INT_CONFIG_B_M_S_RD_CTRL_MSK NO_OS_BIT(5)
162 #define AD713X_INT_CONFIG_B_DIG_IF_RST_MSK NO_OS_BIT(1)
163 
164 /*
165  * AD713X_REG_DEVICE_CONFIG
166  */
167 #define AD713X_DEV_CONFIG_OP_IN_PROGRESS_MSK NO_OS_BIT(5)
168 #define AD713X_DEV_CONFIG_NO_CHIP_ERR_MSK NO_OS_BIT(4)
169 #define AD713X_DEV_CONFIG_PWR_MODE_MSK NO_OS_BIT(0)
170 
171 /*
172  * AD713X_REG_CHIP_TYPE
173  */
174 #define AD713X_CHIP_TYPE_BITS_MSK NO_OS_GENMASK(7, 0)
175 #define AD713X_CHIP_TYPE_BITS_MODE(x) (((x) & 0xFF) << 0)
176 #define AD713X_CHIP_TYPE 0x07
177 
178 /*
179  * AD713X_REG_PRODUCT_ID_LSB
180  */
181 #define AD713X_PRODUCT_ID_LSB_BITS_MSK NO_OS_GENMASK(7, 0)
182 #define AD713X_PRODUCT_ID_LSB_BITS_MODE(x) (((x) & 0xFF) << 0)
183 
184 /*
185  * AD713X_REG_PRODUCT_ID_MSB
186  */
187 #define AD713X_PRODUCT_ID_MSB_BITS_MSK NO_OS_GENMASK(7, 0)
188 #define AD713X_PRODUCT_ID_MSB_BITS_MODE(x) (((x) & 0xFF) << 0)
189 
190 /*
191  * AD713X_REG_CHIP_GRADE
192  */
193 #define AD713X_CHIP_GRADE_PROD_GRADE_BITS_MSK NO_OS_GENMASK(7, 4)
194 #define AD713X_CHIP_GRADE_PROD_GRADE_BITS_MODE(x) (((x) & 0x0F) << 4)
195 #define AD713X_CHIP_GRADE_DEV_VERSION_BITS_MSK NO_OS_GENMASK(3, 0)
196 #define AD713X_CHIP_GRADE_DEV_VERSION_BITS_MODE(x) (((x) & 0x0F) << 0)
197 
198 /*
199  * AD713X_REG_CHIP_INDEX
200  */
201 #define AD713X_SILICON_REV_ID_BITS_MSK NO_OS_GENMASK(7, 0)
202 #define AD713X_SILICON_REV_ID_BITS_MODE(x) (((x) & 0xFF) << 0)
203 
204 /*
205  * AD713X_REG_SCRATCH_PAD
206  */
207 #define AD713X_SCRATCH_PAD_BITS_MSK NO_OS_GENMASK(7, 0)
208 #define AD713X_SCRATCH_PAD_BITS_MODE(x) (((x) & 0xFF) << 0)
209 
210 /*
211  * AD713X_REG_SPI_REVISION
212  */
213 #define AD713X_SPI_REVISION_BITS_MSK NO_OS_GENMASK(7, 0)
214 #define AD713X_SPI_REVISION_BITS_MODE(x) (((x) & 0xFF) << 0)
215 
216 /*
217  * AD713X_REG_VENDOR_ID_LSB
218  */
219 #define AD713X_VENDOR_ID_LSB_BITS_MSK NO_OS_GENMASK(7, 0)
220 #define AD713X_VENDOR_ID_LSB_BITS_MODE(x) (((x) & 0xFF) << 0)
221 
222 /*
223  * AD713X_REG_VENDOR_ID_MSB
224  */
225 #define AD713X_VENDOR_ID_MSB_BITS_MSK NO_OS_GENMASK(7, 0)
226 #define AD713X_VENDOR_ID_MSB_BITS_MODE(x) (((x) & 0xFF) << 0)
227 
228 /*
229  * AD713X_REG_STREAM_MODE
230  */
231 #define AD713X_STREAM_MODE_BITS_MSK NO_OS_GENMASK(7, 0)
232 #define AD713X_STREAM_MODE_BITS_MODE(x) (((x) & 0xFF) << 0)
233 
234 /*
235  * AD713X_REG_TRANSFER_REGISTER
236  */
237 #define AD713X_TRANSFER_MASTER_SLAVE_TX_BIT_MSK NO_OS_BIT(0)
238 
239 /*
240  * AD713X_REG_DEVICE_CONFIG1
241  */
242 #define AD713X_DEV_CONFIG1_MPC_MAGPHA_EN_MSK NO_OS_BIT(6)
243 #define AD713X_DEV_CONFIG1_MPC_MAG_EN_MSK NO_OS_BIT(5)
244 #define AD713X_DEV_CONFIG1_AA_MODE_MSK NO_OS_BIT(4)
245 #define AD713X_DEV_CONFIG1_SDO_PIN_SRC_SEL_MSK NO_OS_BIT(2)
246 #define AD713X_DEV_CONFIG1_REF_GAIN_CORR_EN_MSK NO_OS_BIT(1)
247 #define AD713X_DEV_CONFIG1_CLKOUT_EN_MSK NO_OS_BIT(0)
248 
249 /*
250  * AD713X_REG_DATA_PACKET_CONFIG
251  */
252 #define AD713X_DATA_PACKET_CONFIG_CRC_POLY_RST_MSK NO_OS_BIT(7)
253 #define AD713X_DATA_PACKET_CONFIG_FRAME_MSK NO_OS_GENMASK(6, 4)
254 #define AD713X_DATA_PACKET_CONFIG_FRAME_MODE(x) (((x) & 0x7) << 4)
255 #define AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MSK NO_OS_GENMASK(3, 0)
256 #define AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MODE(x) (((x) & 0xF) << 0)
257 
258 /*
259  * AD713X_REG_DIGITAL_INTERFACE_CONFIG
260  */
261 #define AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MSK NO_OS_GENMASK(7, 4)
262 #define AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MODE(x) (((x) & 0xF) << 4)
263 #define AD713X_DIG_INT_CONFIG_AVG_SEL_MSK NO_OS_GENMASK(3, 2)
264 #define AD713X_DIG_INT_CONFIG_AVG_SEL_MODE(x) (((x) & 0x3) << 2)
265 #define AD713X_DIG_INT_CONFIG_FORMAT_MSK NO_OS_GENMASK(1, 0)
266 #define AD713X_DIG_INT_CONFIG_FORMAT_MODE(x) (((x) & 0x3) << 0)
267 
268 /*
269  * AD713X_REG_POWER_DOWN_CONTROL
270  */
271 #define AD713X_PWRDN_CTRL_PWRDN_CH_MSK(ch) NO_OS_BIT(ch)
272 #define AD713X_PWRDN_CTRL_PWRDN_AUXADC_MSK NO_OS_BIT(2)
273 #define AD713X_PWRDN_CTRL_PWRDN_LDO_MSK NO_OS_BIT(1)
274 #define AD713X_PWRDN_CTRL_PWRDN_SLEEP_MODE_EN_MSK NO_OS_BIT(0)
275 
276 /*
277  * AD713X_REG_AIN_RANGE_SELECT
278  */
279 #define AD713X_AIN_RANGE_SEL_CH_MSK(ch) NO_OS_BIT(ch)
280 
281 /*
282  * AD713X_REG_DEVICE_STATUS
283  */
284 #define AD713X_DEV_STAT_DCLKMODE_MSK NO_OS_BIT(5)
285 #define AD713X_DEV_STAT_DCLKIO_MSK NO_OS_BIT(4)
286 #define AD713X_DEV_STAT_MODE_MSK NO_OS_BIT(3)
287 #define AD713X_DEV_STAT_CLKSEL_MSK NO_OS_BIT(2)
288 #define AD713X_DEV_STAT_FUSE_ECC_MSK NO_OS_BIT(1)
289 #define AD713X_DEV_STAT_PLL_LOCK_MSK NO_OS_BIT(0)
290 
291 /*
292  * AD713X_REG_ODR_VAL_INT_LSB
293  */
294 #define AD713X_ODR_VAL_INT_LSB_MSK NO_OS_GENMASK(7, 0)
295 #define AD713X_ODR_VAL_INT_LSB_MODE(x) (((x) & 0xFF) << 0)
296 
297 /*
298  * AD713X_REG_ODR_VAL_INT_MID
299  */
300 #define AD713X_ODR_VAL_INT_MID_MSK NO_OS_GENMASK(7, 0)
301 #define AD713X_ODR_VAL_INT_MID_MODE(x) (((x) & 0xFF) << 0)
302 
303 /*
304  * AD713X_REG_ODR_VAL_INT_MSB
305  */
306 #define AD713X_ODR_VAL_INT_MSB_MSK NO_OS_GENMASK(7, 0)
307 #define AD713X_ODR_VAL_INT_MSB_MODE(x) (((x) & 0xFF) << 0)
308 
309 /*
310  * AD713X_REG_ODR_VAL_FLT_LSB
311  */
312 #define AD713X_ODR_VAL_FLT_LSB_MSK NO_OS_GENMASK(7, 0)
313 #define AD713X_ODR_VAL_FLT_LSB_MODE(x) (((x) & 0xFF) << 0)
314 
315 /*
316  * AD713X_REG_ODR_VAL_FLT_MID0
317  */
318 #define AD713X_ODR_VAL_FLT_MID0_MSK NO_OS_GENMASK(7, 0)
319 #define AD713X_ODR_VAL_FLT_MID0_MODE(x) (((x) & 0xFF) << 0)
320 
321 /*
322  * AD713X_REG_ODR_VAL_FLT_MID1
323  */
324 #define AD713X_ODR_VAL_FLT_MID1_MSK NO_OS_GENMASK(7, 0)
325 #define AD713X_ODR_VAL_FLT_MID1_MODE(x) (((x) & 0xFF) << 0)
326 
327 /*
328  * AD713X_REG_ODR_VAL_FLT_MSB
329  */
330 #define AD713X_ODR_VAL_FLT_MSB_MSK NO_OS_GENMASK(7, 0)
331 #define AD713X_ODR_VAL_FLT_MSB_MODE(x) (((x) & 0xFF) << 0)
332 
333 /*
334  * AD713X_REG_CHANNEL_ODR_SELECT
335  */
336 #define AD713X_ODR_RATE_SEL_CH_MSK(ch) (NO_OS_GENMASK(1, 0) << (2 * ch))
337 #define AD713X_ODR_RATE_SEL_CH_MODE(x, ch) (((x) & 0x3) << (2 * ch))
338 
339 /*
340  * AD713X_REG_CHAN_DIG_FILTER_SEL
341  */
342 #define AD713X_DIGFILTER_SEL_CH_MSK(ch) (NO_OS_GENMASK(1, 0) << (2 * ch))
343 #define AD713X_DIGFILTER_SEL_CH_MODE(x, ch) (((x) & 0x3) << (2 * ch))
344 
345 /*
346  * AD713X_REG_FIR_BW_SEL
347  */
348 #define AD713X_FIR_BW_SEL_CH_MSK(ch) NO_OS_BIT(ch)
349 
350 /*
351  * AD713X_REG_GPIO_DIR_CTRL
352  */
353 #define AD713X_GPIO_IO_CTRL_MSK NO_OS_GENMASK(7, 0)
354 #define AD713X_GPIO_IO_CTRL_MODE(x) (((x) & 0xFF) << 0)
355 
356 /*
357  * AD713X_REG_GPIO_DATA
358  */
359 #define AD713X_GPIO_DATA_MSK NO_OS_GENMASK(7, 0)
360 #define AD713X_GPIO_DATA_MODE(x) (((x) & 0xFF) << 0)
361 
362 /*
363  * AD713X_REG_ERROR_PIN_SRC_CONTROL
364  */
365 #define AD713X_ERR_PIN_EN_OR_AIN_MSK NO_OS_BIT(5)
366 #define AD713X_ERR_PIN_EN_INTERNAL_MSK NO_OS_BIT(4)
367 #define AD713X_ERR_PIN_EN_SPI_MSK NO_OS_BIT(3)
368 #define AD713X_ERR_PIN_EN_LDO_XOSC_MSK NO_OS_BIT(2)
369 #define AD713X_ERR_PIN_EN_TEMP_MSK NO_OS_BIT(1)
370 #define AD713X_ERR_PIN_EN_PWR_MSK NO_OS_BIT(0)
371 
372 /*
373  * AD713X_REG_ERROR_PIN_CONTROL
374  */
375 #define AD713X_ERR_PIN_IN_STATUS_MSK NO_OS_BIT(2)
376 #define AD713X_ERR_PIN_IN_EN_MSK NO_OS_BIT(1)
377 #define AD713X_ERR_PIN_OUT_EN_MSK NO_OS_BIT(0)
378 
379 /*
380  * AD713X_REG_VCMBUF_CTRL
381  */
382 #define AD713X_VCMBUF_CTRL_PWRDN_MSK NO_OS_BIT(6)
383 #define AD713X_VCMBUF_CTRL_REF_DIV_SEL_MSK NO_OS_GENMASK(5, 1)
384 #define AD713X_VCMBUF_CTRL_REF_DIV_SEL_MODE(x) (((x) & 0x1F) << 1)
385 #define AD713X_VCMBUF_CTRL_REF_SEL_MSK NO_OS_BIT(0)
386 
387 /*
388  * AD713X_REG_DIAGNOSTIC_CONTROL
389  */
390 #define AD713X_DIAGCTRL_ERR_OR_AIN_EN_MSK NO_OS_BIT(5)
391 #define AD713X_DIAGCTRL_ERR_PWR_MON_EN_MSK NO_OS_BIT(4)
392 #define AD713X_DIAGCTRL_MCLK_CNT_EN_MSK NO_OS_BIT(3)
393 #define AD713X_DIAGCTRL_ERR_SPI_CRC_EN_MSK NO_OS_BIT(2)
394 #define AD713X_DIAGCTRL_ERR_MM_CRC_EN_MSK NO_OS_BIT(1)
395 #define AD713X_DIAGCTRL_FUSE_CRC_CHECK_MSK NO_OS_BIT(0)
396 
397 /*
398  * AD713X_REG_MPC_CONFIG
399  */
400 #define AD713X_MPC_CLKDEL_EN_CH_MSK(ch) (NO_OS_GENMASK(1, 0) << (2 * ch))
401 #define AD713X_MPC_CLKDEL_EN_CH_MODE(x, ch) (((x) & 0x3) << (2 * ch))
402 
403 /*
404  * AD713X_REG_CHx_GAIN_LSB
405  */
406 #define AD713X_CH_GAIN_LSB_MSK NO_OS_GENMASK(7, 0)
407 #define AD713X_CH_GAIN_LSB_MODE(x) (((x) & 0xFF) << 0)
408 
409 /*
410  * AD713X_REG_CHx_GAIN_MID
411  */
412 #define AD713X_CH_GAIN_MID_MSK NO_OS_GENMASK(7, 0)
413 #define AD713X_CH_GAIN_MID_MODE(x) (((x) & 0xFF) << 0)
414 
415 /*
416  * AD713X_REG_CHx_GAIN_MSB
417  */
418 #define AD713X_CH_GAIN_CAL_SEL_MSK NO_OS_BIT(4)
419 #define AD713X_CH_GAIN_MSB_MSK NO_OS_GENMASK(3, 0)
420 #define AD713X_CH_GAIN_MSB_MODE(x) (((x) & 0xF) << 0)
421 
422 /*
423  * AD713X_REG_CHx_OFFSET_LSB
424  */
425 #define AD713X_CH_OFFSET_LSB_MSK NO_OS_GENMASK(7, 0)
426 #define AD713X_CH_OFFSET_LSB_MODE(x) (((x) & 0xFF) << 0)
427 
428 /*
429  * AD713X_REG_CHx_OFFSET_MID
430  */
431 #define AD713X_CH_OFFSET_MID_MSK NO_OS_GENMASK(7, 0)
432 #define AD713X_CH_OFFSET_MID_MODE(x) (((x) & 0xFF) << 0)
433 
434 /*
435  * AD713X_REG_CHx_OFFSET_MSB
436  */
437 #define AD713X_CH_OFFSET_CAL_EN_MSK NO_OS_BIT(7)
438 #define AD713X_CH_OFFSET_MSB_MSK NO_OS_GENMASK(6, 0)
439 #define AD713X_CH_OFFSET_MSB_MODE(x) (((x) & 0x7F) << 0)
440 
441 /*
442  * AD713X_REG_MCLK_COUNTER
443  */
444 #define AD713X_MCLK_COUNT_MSK NO_OS_GENMASK(7, 0)
445 #define AD713X_MCLK_COUNT_MODE(x) (((x) & 0xFF) << 0)
446 
447 /*
448  * AD713X_REG_DIG_FILTER_OFUF
449  */
450 #define AD713X_DIGFILTER_ERR_OFUF_CH_MSK(ch) NO_OS_BIT(ch)
451 
452 /*
453  * AD713X_REG_DIG_FILTER_SETTLED
454  */
455 #define AD713X_DIGFILTER_CH_SETTLED_MSK(ch) NO_OS_BIT(ch)
456 
457 /*
458  * AD713X_REG_INTERNAL_ERROR
459  */
460 #define AD713X_INT_ERR_NO_CLOCK_MSK NO_OS_BIT(5)
461 #define AD713X_INT_ERR_TEMP_MSK NO_OS_BIT(4)
462 #define AD713X_INT_ERR_DCLK_MSK NO_OS_BIT(3)
463 #define AD713X_INT_ERR_FUSE_CRC_MSK NO_OS_BIT(2)
464 #define AD713X_INT_ERR_ASRC_MSK NO_OS_BIT(1)
465 #define AD713X_INT_ERR_MM_CRC_MSK NO_OS_BIT(0)
466 
467 /*
468  * AD713X_REG_POWER_OV_ERROR_1
469  */
470 #define AD713X_POWER_ERR_OV_IOVDD_MSK NO_OS_BIT(3)
471 #define AD713X_POWER_ERR_OV_CLKVDD_MSK NO_OS_BIT(2)
472 #define AD713X_POWER_ERR_OV_DVDD1V8_MSK NO_OS_BIT(1)
473 #define AD713X_POWER_ERR_OV_AVDD1V8_MSK NO_OS_BIT(0)
474 
475 /*
476  * AD713X_REG_POWER_UV_ERROR_1
477  */
478 #define AD713X_POWER_ERR_UV_IOVDD_MSK NO_OS_BIT(3)
479 #define AD713X_POWER_ERR_UV_CLKVDD_MSK NO_OS_BIT(2)
480 #define AD713X_POWER_ERR_UV_DVDD1V8_MSK NO_OS_BIT(1)
481 #define AD713X_POWER_ERR_UV_AVDD1V8_MSK NO_OS_BIT(0)
482 
483 /*
484  * AD713X_REG_POWER_OV_ERROR_2
485  */
486 #define AD713X_POWER_ERR_OV_VREF_MSK NO_OS_BIT(3)
487 #define AD713X_POWER_ERR_OV_LDOIN_MSK NO_OS_BIT(2)
488 #define AD713X_POWER_ERR_OV_DVDD5_MSK NO_OS_BIT(1)
489 #define AD713X_POWER_ERR_OV_AVDD5_MSK NO_OS_BIT(0)
490 
491 /*
492  * AD713X_REG_POWER_UV_ERROR_2
493  */
494 #define AD713X_POWER_ERR_UV_VREF_MSK NO_OS_BIT(3)
495 #define AD713X_POWER_ERR_UV_LDOIN_MSK NO_OS_BIT(2)
496 #define AD713X_POWER_ERR_UV_DVDD5_MSK NO_OS_BIT(1)
497 #define AD713X_POWER_ERR_UV_AVDD5_MSK NO_OS_BIT(0)
498 
499 /*
500  * AD713X_REG_SPI_ERROR
501  */
502 #define AD713X_SPI_ERROR_CRC_MSK NO_OS_BIT(3)
503 #define AD713X_SPI_ERROR_SCLK_CNT_MSK NO_OS_BIT(2)
504 #define AD713X_SPI_ERROR_WRITE_MSK NO_OS_BIT(1)
505 #define AD713X_SPI_ERROR_READ_MSK NO_OS_BIT(0)
506 
507 /*
508  * AD713X_REG_AIN_OR_ERROR
509  */
510 #define AD713X_ERR_OR_AIN_MSK(ch) NO_OS_BIT(ch)
511 
512 /*
513  * AD713X_REG_AVDD5_VALUE
514  */
515 #define AD713X_AVDD5_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)
516 #define AD713X_AVDD5_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
517 
518 /*
519  * AD713X_REG_DVDD5_VALUE
520  */
521 #define AD713X_DVDD5_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)
522 #define AD713X_DVDD5_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
523 
524 /*
525  * AD713X_REG_VREF_VALUE
526  */
527 #define AD713X_VREF_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)
528 #define AD713X_VREF_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
529 
530 /*
531  * AD713X_REG_LDOIN_VALUE
532  */
533 #define AD713X_LDOIN_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)
534 #define AD713X_LDOIN_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
535 
536 /*
537  * AD713X_REG_AVDD1V8_VALUE
538  */
539 #define AD713X_AVDD1V8_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)
540 #define AD713X_AVDD1V8_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
541 
542 /*
543  * AD713X_REG_DVDD1V8_VALUE
544  */
545 #define AD713X_DVDD1V8_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)
546 #define AD713X_DVDD1V8_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
547 
548 /*
549  * AD713X_REG_CLKVDD_VALUE
550  */
551 #define AD713X_CLKVDD_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)
552 #define AD713X_CLKVDD_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
553 
554 /*
555  * AD713X_REG_IOVDD_VALUE
556  */
557 #define AD713X_IOVDD_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)
558 #define AD713X_IOVDD_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
559 
560 /*
561  * AD713X_REG_TEMPERATURE_DATA
562  */
563 #define AD713X_TEMP_DATA_MSK NO_OS_GENMASK(7, 0)
564 #define AD713X_TEMP_DATA_MODE(x) (((x) & 0xFF) << 0)
565 
566 #define AD713X_REG_READ(x) ((1 << 7) | (x & 0x7F))
567 
568 /******************************************************************************/
569 /*************************** Types Declarations *******************************/
570 /******************************************************************************/
571 
581 };
582 
592 };
593 
607 };
608 
620 };
621 
635 };
636 
650 };
651 
667 };
668 
680 };
681 
686 struct ad713x_dev {
707 };
708 
733  bool pnd;
746 };
747 
748 /******************************************************************************/
749 /************************ Functions Declarations ******************************/
750 /******************************************************************************/
751 
753 int32_t ad713x_spi_reg_read(struct ad713x_dev *dev, uint8_t reg_addr,
754  uint8_t *reg_data);
755 
757 int32_t ad713x_spi_reg_write(struct ad713x_dev *dev, uint8_t reg_addr,
758  uint8_t reg_data);
759 
761 int32_t ad713x_spi_write_mask(struct ad713x_dev *dev, uint8_t reg_addr,
762  uint32_t mask, uint8_t data);
763 
765 int32_t ad713x_set_power_mode(struct ad713x_dev *dev,
766  enum ad713x_power_mode mode);
767 
769 int32_t ad713x_set_out_data_frame(struct ad713x_dev *dev,
770  enum ad713x_adc_data_len adc_data_len,
771  enum ad713x_crc_header crc_header);
772 
774 int32_t ad713x_dout_format_config(struct ad713x_dev *dev,
775  enum ad713x_doutx_format format);
776 
779 int32_t ad713x_mag_phase_clk_delay(struct ad713x_dev *dev, bool clk_delay_en);
780 
782 int32_t ad713x_dig_filter_sel_ch(struct ad713x_dev *dev,
783  enum ad713x_dig_filter_sel filter, enum ad713x_channels ch);
784 
786 int32_t ad713x_clkout_output_en(struct ad713x_dev *dev, bool enable);
787 
789 int32_t ad713x_ref_gain_correction_en(struct ad713x_dev *dev, bool enable);
790 
792 int32_t ad713x_wideband_bw_sel(struct ad713x_dev *dev,
793  enum ad713x_channels ch, uint8_t wb_opt);
794 
796 int32_t ad713x_init(struct ad713x_dev **device,
797  struct ad713x_init_param *init_param);
798 
800 int32_t ad713x_remove(struct ad713x_dev *dev);
801 
802 #endif /* SRC_AD713X_H_ */
ad713x_init_param::gpio_dclkmode
struct no_os_gpio_init_param * gpio_dclkmode
Definition: ad713x.h:719
ad717x_mpc_clkdel
ad717x_mpc_clkdel
AD713x list of clock delays.
Definition: ad713x.h:673
AD713X_MPC_CLKDEL_EN_CH_MSK
#define AD713X_MPC_CLKDEL_EN_CH_MSK(ch)
Definition: ad713x.h:400
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
ad713x.h
Header file for the ad713x Driver.
ad713x_dig_filter_sel_ch
int32_t ad713x_dig_filter_sel_ch(struct ad713x_dev *dev, enum ad713x_dig_filter_sel filter, enum ad713x_channels ch)
Digital filter type selection for each channel.
Definition: ad713x.c:311
SINC6
@ SINC6
Definition: ad713x.h:645
ad713x_doutx_format
ad713x_doutx_format
AD713x list for possible output modes.
Definition: ad713x.h:626
ad713x_init_param::clk_delay_en
bool clk_delay_en
Definition: ad713x.h:742
CH1
@ CH1
Definition: ad713x.h:660
SINC3
@ SINC3
Definition: ad713x.h:647
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
ad713x_dout_format_config
int32_t ad713x_dout_format_config(struct ad713x_dev *dev, enum ad713x_doutx_format format)
DOUTx output format configuration.
Definition: ad713x.c:231
ad713x_mag_phase_clk_delay_chan
int32_t ad713x_mag_phase_clk_delay_chan(struct ad713x_dev *dev, enum ad713x_channels chan, enum ad717x_mpc_clkdel mode)
Change magnitude and phase calibration clock delay mode for a specific channel.
Definition: ad713x.c:286
no_os_spi.h
Header file of SPI Interface.
ad713x_init_param::dev_id
enum ad713x_supported_dev_ids dev_id
Definition: ad713x.h:735
ID_AD7134
@ ID_AD7134
Definition: ad713x.h:578
ad713x_dout_format_config
int32_t ad713x_dout_format_config(struct ad713x_dev *dev, enum ad713x_doutx_format format)
DOUTx output format configuration.
Definition: ad713x.c:231
QUAD_CH_PO
@ QUAD_CH_PO
Definition: ad713x.h:632
ADC_16_BIT_DATA
@ ADC_16_BIT_DATA
Definition: ad713x.h:600
ad713x_wideband_bw_sel
int32_t ad713x_wideband_bw_sel(struct ad713x_dev *dev, enum ad713x_channels ch, uint8_t wb_opt)
Select the wideband filter bandwidth for a channel. The option is relative to ODR,...
Definition: ad713x.c:360
ad713x_init_param
AD713x driver initialization structure.
Definition: ad713x.h:713
NO_OS_IS_ERR_VALUE
#define NO_OS_IS_ERR_VALUE(x)
Definition: no_os_error.h:56
ad713x_channels
ad713x_channels
AD713x list of channels.
Definition: ad713x.h:656
no_os_delay.h
Header file of Delay functions.
CH_AVG_MODE
@ CH_AVG_MODE
Definition: ad713x.h:634
ad713x_dig_filter_sel
ad713x_dig_filter_sel
AD713x list of input filters.
Definition: ad713x.h:641
ADC_24_BIT_DATA
@ ADC_24_BIT_DATA
Definition: ad713x.h:602
ad713x_init_param::crc_header
enum ad713x_crc_header crc_header
Definition: ad713x.h:739
ad713x_set_power_mode
int32_t ad713x_set_power_mode(struct ad713x_dev *dev, enum ad713x_power_mode mode)
Device power mode control.
Definition: ad713x.c:170
AD713X_CH_MAX
@ AD713X_CH_MAX
Definition: ad713x.h:666
ad713x_clkout_output_en
int32_t ad713x_clkout_output_en(struct ad713x_dev *dev, bool enable)
Enable/Disable CLKOUT output.
Definition: ad713x.c:327
ad713x_init_param::pnd
bool pnd
Definition: ad713x.h:733
ad713x_init_param::dclkio_out_nin
bool dclkio_out_nin
Definition: ad713x.h:731
ad713x_set_out_data_frame
int32_t ad713x_set_out_data_frame(struct ad713x_dev *dev, enum ad713x_adc_data_len adc_data_len, enum ad713x_crc_header crc_header)
ADC conversion data output frame control.
Definition: ad713x.c:197
ad713x_power_mode
ad713x_power_mode
AD713x power modes.
Definition: ad713x.h:587
device
Definition: ad9361_util.h:75
ad713x_spi_write_mask
int32_t ad713x_spi_write_mask(struct ad713x_dev *dev, uint8_t reg_addr, uint32_t mask, uint8_t data)
SPI write to device using a mask.
Definition: ad713x.c:145
AD713X_REG_DATA_PACKET_CONFIG
#define AD713X_REG_DATA_PACKET_CONFIG
Definition: ad713x.h:81
ad713x_init_param::gpio_pnd
struct no_os_gpio_init_param * gpio_pnd
Definition: ad713x.h:725
FIR
@ FIR
Definition: ad713x.h:643
ad713x_init_param::adc_data_len
enum ad713x_adc_data_len adc_data_len
Definition: ad713x.h:737
ad713x_set_out_data_frame
int32_t ad713x_set_out_data_frame(struct ad713x_dev *dev, enum ad713x_adc_data_len adc_data_len, enum ad713x_crc_header crc_header)
ADC conversion data output frame control.
Definition: ad713x.c:197
ad7616_init_param::mode
enum ad7616_mode mode
Definition: ad7616.h:180
AD713X_DIG_INT_CONFIG_FORMAT_MSK
#define AD713X_DIG_INT_CONFIG_FORMAT_MSK
Definition: ad713x.h:265
ad713x_dev::dev_id
enum ad713x_supported_dev_ids dev_id
Definition: ad713x.h:700
ad713x_dev::gpio_dclkio
struct no_os_gpio_desc * gpio_dclkio
Definition: ad713x.h:694
ad713x_clkout_output_en
int32_t ad713x_clkout_output_en(struct ad713x_dev *dev, bool enable)
Enable/Disable CLKOUT output.
Definition: ad713x.c:327
ad713x_remove
int32_t ad713x_remove(struct ad713x_dev *dev)
Free the resources allocated by ad713x_init().
Definition: ad713x.c:601
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
AD713X_REG_DEVICE_CONFIG
#define AD713X_REG_DEVICE_CONFIG
Definition: ad713x.h:68
no_os_spi_desc::chip_select
uint8_t chip_select
Definition: no_os_spi.h:138
ad713x_dev::spi_desc
struct no_os_spi_desc * spi_desc
Definition: ad713x.h:688
ad713x_dev::gpio_mode
struct no_os_gpio_desc * gpio_mode
Definition: ad713x.h:690
ad713x_crc_header
ad713x_crc_header
AD713x possible data CRC header choices.
Definition: ad713x.h:613
no_os_error.h
Error codes definition.
ad713x_spi_reg_write
int32_t ad713x_spi_reg_write(struct ad713x_dev *dev, uint8_t reg_addr, uint8_t reg_data)
Write to device.
Definition: ad713x.c:125
AD713X_DIGFILTER_SEL_CH_MODE
#define AD713X_DIGFILTER_SEL_CH_MODE(x, ch)
Definition: ad713x.h:343
ad713x_remove
int32_t ad713x_remove(struct ad713x_dev *dev)
Free the resources allocated by ad713x_init().
Definition: ad713x.c:601
SINC3_50_60_REJ
@ SINC3_50_60_REJ
Definition: ad713x.h:649
AD713X_DEV_CONFIG1_REF_GAIN_CORR_EN_MSK
#define AD713X_DEV_CONFIG1_REF_GAIN_CORR_EN_MSK
Definition: ad713x.h:246
AD713X_MPC_CLKDEL_EN_CH_MODE
#define AD713X_MPC_CLKDEL_EN_CH_MODE(x, ch)
Definition: ad713x.h:401
NO_CRC
@ NO_CRC
Definition: ad713x.h:615
DELAY_NONE
@ DELAY_NONE
Definition: ad713x.h:675
ad713x_dev::crc_header
enum ad713x_crc_header crc_header
Definition: ad713x.h:704
ad713x_wideband_bw_sel
int32_t ad713x_wideband_bw_sel(struct ad713x_dev *dev, enum ad713x_channels ch, uint8_t wb_opt)
Select the wideband filter bandwidth for a channel. The option is relative to ODR,...
Definition: ad713x.c:360
AD713X_FIR_BW_SEL_CH_MSK
#define AD713X_FIR_BW_SEL_CH_MSK(ch)
Definition: ad713x.h:348
ad713x_ref_gain_correction_en
int32_t ad713x_ref_gain_correction_en(struct ad713x_dev *dev, bool enable)
Enable/Disable reference gain correction.
Definition: ad713x.c:341
ad713x_dev::gpio_resetn
struct no_os_gpio_desc * gpio_resetn
Definition: ad713x.h:696
CH0
@ CH0
Definition: ad713x.h:658
ad713x_spi_reg_write
int32_t ad713x_spi_reg_write(struct ad713x_dev *dev, uint8_t reg_addr, uint8_t reg_data)
Write to device.
Definition: ad713x.c:125
ADC_32_BIT_DATA
@ ADC_32_BIT_DATA
Definition: ad713x.h:604
CRC_6
@ CRC_6
Definition: ad713x.h:617
ad713x_init_param::spi_init_prm
struct no_os_spi_init_param spi_init_prm
Definition: ad713x.h:715
ad713x_adc_data_len
ad713x_adc_data_len
AD713x possible number of bits per data sample.
Definition: ad713x.h:598
ad713x_dig_filter_sel_ch
int32_t ad713x_dig_filter_sel_ch(struct ad713x_dev *dev, enum ad713x_dig_filter_sel filter, enum ad713x_channels ch)
Digital filter type selection for each channel.
Definition: ad713x.c:311
no_os_gpio_remove
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:95
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
ad713x_init_param::gpio_dclkio
struct no_os_gpio_init_param * gpio_dclkio
Definition: ad713x.h:721
DELAY_1_CLOCKS
@ DELAY_1_CLOCKS
Definition: ad713x.h:677
ad713x_dev::gpio_dclkmode
struct no_os_gpio_desc * gpio_dclkmode
Definition: ad713x.h:692
AD713X_DEV_CONFIG_PWR_MODE_MSK
#define AD713X_DEV_CONFIG_PWR_MODE_MSK
Definition: ad713x.h:169
AD713X_REG_FIR_BW_SEL
#define AD713X_REG_FIR_BW_SEL
Definition: ad713x.h:95
ID_AD4134
@ ID_AD4134
Definition: ad713x.h:580
ad713x_spi_reg_read
int32_t ad713x_spi_reg_read(struct ad713x_dev *dev, uint8_t reg_addr, uint8_t *reg_data)
Read from device.
Definition: ad713x.c:100
AD713X_REG_DEVICE_CONFIG1
#define AD713X_REG_DEVICE_CONFIG1
Definition: ad713x.h:80
ad713x_init_param::gpio_mode
struct no_os_gpio_init_param * gpio_mode
Definition: ad713x.h:717
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
AD713X_DIGFILTER_SEL_CH_MSK
#define AD713X_DIGFILTER_SEL_CH_MSK(ch)
Definition: ad713x.h:342
AD713X_REG_DIGITAL_INTERFACE_CONFIG
#define AD713X_REG_DIGITAL_INTERFACE_CONFIG
Definition: ad713x.h:82
AD713X_DATA_PACKET_CONFIG_FRAME_MSK
#define AD713X_DATA_PACKET_CONFIG_FRAME_MSK
Definition: ad713x.h:253
ad713x_spi_reg_read
int32_t ad713x_spi_reg_read(struct ad713x_dev *dev, uint8_t reg_addr, uint8_t *reg_data)
Read from device.
Definition: ad713x.c:100
DELAY_2_CLOCKS
@ DELAY_2_CLOCKS
Definition: ad713x.h:679
no_os_spi_desc::extra
void * extra
Definition: no_os_spi.h:145
ad713x_dev::mode_master_nslave
bool mode_master_nslave
Definition: ad713x.h:706
AD713X_CHIP_TYPE
#define AD713X_CHIP_TYPE
Definition: ad713x.h:176
HIGH_POWER
@ HIGH_POWER
Definition: ad713x.h:591
CRC_8
@ CRC_8
Definition: ad713x.h:619
ad713x_mag_phase_clk_delay
int32_t ad713x_mag_phase_clk_delay(struct ad713x_dev *dev, bool clk_delay_en)
Magnitude and phase matching calibration clock delay enable for all channels at 2 clock delay....
Definition: ad713x.c:251
AD713X_REG_CHAN_DIG_FILTER_SEL
#define AD713X_REG_CHAN_DIG_FILTER_SEL
Definition: ad713x.h:94
ad713x_dev
AD713x driver handler structure.
Definition: ad713x.h:686
LOW_POWER
@ LOW_POWER
Definition: ad713x.h:589
ad713x_spi_write_mask
int32_t ad713x_spi_write_mask(struct ad713x_dev *dev, uint8_t reg_addr, uint32_t mask, uint8_t data)
SPI write to device using a mask.
Definition: ad713x.c:145
no_os_gpio_set_value
int32_t no_os_gpio_set_value(struct no_os_gpio_desc *desc, uint8_t value)
Set the value of the specified GPIO.
Definition: no_os_gpio.c:160
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
ad713x_supported_dev_ids
ad713x_supported_dev_ids
ID of devices supported by the driver.
Definition: ad713x.h:576
ad713x_mag_phase_clk_delay
int32_t ad713x_mag_phase_clk_delay(struct ad713x_dev *dev, bool clk_delay_en)
Magnitude and phase matching calibration clock delay enable for all channels at 2 clock delay....
Definition: ad713x.c:251
AD713X_REG_CHIP_TYPE
#define AD713X_REG_CHIP_TYPE
Definition: ad713x.h:69
ad713x_init_param::format
enum ad713x_doutx_format format
Definition: ad713x.h:740
AD713X_DATA_PACKET_CONFIG_FRAME_MODE
#define AD713X_DATA_PACKET_CONFIG_FRAME_MODE(x)
Definition: ad713x.h:254
ad713x_dev::adc_data_len
enum ad713x_adc_data_len adc_data_len
Definition: ad713x.h:702
CH3
@ CH3
Definition: ad713x.h:664
ad713x_init
int32_t ad713x_init(struct ad713x_dev **device, struct ad713x_init_param *init_param)
Initialize the device.
Definition: ad713x.c:514
AD713X_REG_READ
#define AD713X_REG_READ(x)
Definition: ad713x.h:566
ad713x_ref_gain_correction_en
int32_t ad713x_ref_gain_correction_en(struct ad713x_dev *dev, bool enable)
Enable/Disable reference gain correction.
Definition: ad713x.c:341
ad713x_init_param::spi_common_dev
struct no_os_spi_desc * spi_common_dev
Definition: ad713x.h:745
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
ad713x_init_param::dclkmode_free_ngated
bool dclkmode_free_ngated
Definition: ad713x.h:729
no_os_spi_desc::platform_ops
const struct no_os_spi_platform_ops * platform_ops
Definition: no_os_spi.h:143
no_os_gpio.h
Header file of GPIO Interface.
ID_AD7136
@ ID_AD7136
Definition: ad713x.h:579
AD713X_DEV_CONFIG1_CLKOUT_EN_MSK
#define AD713X_DEV_CONFIG1_CLKOUT_EN_MSK
Definition: ad713x.h:247
no_os_spi_desc::max_speed_hz
uint32_t max_speed_hz
Definition: no_os_spi.h:136
DUAL_CH_DC
@ DUAL_CH_DC
Definition: ad713x.h:630
ad713x_init_param::gpio_resetn
struct no_os_gpio_init_param * gpio_resetn
Definition: ad713x.h:723
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
ID_AD7132
@ ID_AD7132
Definition: ad713x.h:577
no_os_util.h
Implementation of utility functions.
ad713x_set_power_mode
int32_t ad713x_set_power_mode(struct ad713x_dev *dev, enum ad713x_power_mode mode)
Device power mode control.
Definition: ad713x.c:170
AD713X_CHIP_TYPE_BITS_MODE
#define AD713X_CHIP_TYPE_BITS_MODE(x)
Definition: ad713x.h:175
AD713X_REG_MPC_CONFIG
#define AD713X_REG_MPC_CONFIG
Definition: ad713x.h:102
SINGLE_CH_DC
@ SINGLE_CH_DC
Definition: ad713x.h:628
no_os_spi_desc::mode
enum no_os_spi_mode mode
Definition: no_os_spi.h:140
AD713X_DIG_INT_CONFIG_FORMAT_MODE
#define AD713X_DIG_INT_CONFIG_FORMAT_MODE(x)
Definition: ad713x.h:266
no_os_gpio_direction_output
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:124
ad713x_init
int32_t ad713x_init(struct ad713x_dev **device, struct ad713x_init_param *init_param)
Initialize the device.
Definition: ad713x.c:514
INVALID
@ INVALID
Definition: ad713x.h:606
CH2
@ CH2
Definition: ad713x.h:662
ad713x_init_param::mode_master_nslave
bool mode_master_nslave
Definition: ad713x.h:727
ad713x_dev::gpio_pnd
struct no_os_gpio_desc * gpio_pnd
Definition: ad713x.h:698
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
no_os_gpio_get_optional
int32_t no_os_gpio_get_optional(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Get the value of an optional GPIO.
Definition: no_os_gpio.c:75