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ad77681.h File Reference

Header file of the AD7768-1 Driver. More...

#include "no-os/spi.h"
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Classes

struct  adc_data
 
struct  ad77681_status_registers
 
struct  ad77681_dev
 
struct  ad77681_init_param
 

Macros

#define AD77681_REG_CHIP_TYPE   0x3
 
#define AD77681_REG_PROD_ID_L   0x4
 
#define AD77681_REG_PROD_ID_H   0x5
 
#define AD77681_REG_CHIP_GRADE   0x6
 
#define AD77681_REG_SCRATCH_PAD   0x0A
 
#define AD77681_REG_VENDOR_L   0x0C
 
#define AD77681_REG_VENDOR_H   0x0D
 
#define AD77681_REG_INTERFACE_FORMAT   0x14
 
#define AD77681_REG_POWER_CLOCK   0x15
 
#define AD77681_REG_ANALOG   0x16
 
#define AD77681_REG_ANALOG2   0x17
 
#define AD77681_REG_CONVERSION   0x18
 
#define AD77681_REG_DIGITAL_FILTER   0x19
 
#define AD77681_REG_SINC3_DEC_RATE_MSB   0x1A
 
#define AD77681_REG_SINC3_DEC_RATE_LSB   0x1B
 
#define AD77681_REG_DUTY_CYCLE_RATIO   0x1C
 
#define AD77681_REG_SYNC_RESET   0x1D
 
#define AD77681_REG_GPIO_CONTROL   0x1E
 
#define AD77681_REG_GPIO_WRITE   0x1F
 
#define AD77681_REG_GPIO_READ   0x20
 
#define AD77681_REG_OFFSET_HI   0x21
 
#define AD77681_REG_OFFSET_MID   0x22
 
#define AD77681_REG_OFFSET_LO   0x23
 
#define AD77681_REG_GAIN_HI   0x24
 
#define AD77681_REG_GAIN_MID   0x25
 
#define AD77681_REG_GAIN_LO   0x26
 
#define AD77681_REG_SPI_DIAG_ENABLE   0x28
 
#define AD77681_REG_ADC_DIAG_ENABLE   0x29
 
#define AD77681_REG_DIG_DIAG_ENABLE   0x2A
 
#define AD77681_REG_ADC_DATA   0x2C
 
#define AD77681_REG_MASTER_STATUS   0x2D
 
#define AD77681_REG_SPI_DIAG_STATUS   0x2E
 
#define AD77681_REG_ADC_DIAG_STATUS   0x2F
 
#define AD77681_REG_DIG_DIAG_STATUS   0x30
 
#define AD77681_REG_MCLK_COUNTER   0x31
 
#define AD77681_INTERFACE_CRC_EN_MSK   (0x1 << 6)
 
#define AD77681_INTERFACE_CRC_EN(x)   (((x) & 0x1) << 6)
 
#define AD77681_INTERFACE_CRC_TYPE_MSK   (0x1 << 5)
 
#define AD77681_INTERFACE_CRC_TYPE(x)   (((x) & 0x1) << 5)
 
#define AD77681_INTERFACE_STATUS_EN_MSK   (0x1 << 4)
 
#define AD77681_INTERFACE_STATUS_EN(x)   (((x) & 0x1) << 4)
 
#define AD77681_INTERFACE_CONVLEN_MSK   (0x1 << 3)
 
#define AD77681_INTERFACE_CONVLEN(x)   (((x) & 0x1) << 3)
 
#define AD77681_INTERFACE_RDY_EN_MSK   (0x1 << 2)
 
#define AD77681_INTERFACE_RDY_EN(x)   (((x) & 0x1) << 3)
 
#define AD77681_INTERFACE_CONT_READ_MSK   (0x1 << 0)
 
#define AD77681_INTERFACE_CONT_READ_EN(x)   (((x) & 0x1) << 0)
 
#define AD77681_REG_COEFF_CONTROL   0x32
 
#define AD77681_REG_COEFF_DATA   0x33
 
#define AD77681_REG_ACCESS_KEY   0x34
 
#define AD77681_SCRATCHPAD_MSK   (0xFF << 0)
 
#define AD77681_SCRATCHPAD(x)   (((x) & 0xFF) << 0)
 
#define AD77681_POWER_CLK_PWRMODE_MSK   0x3
 
#define AD77681_POWER_CLK_PWRMODE(x)   (((x) & 0x3) << 0)
 
#define AD77681_POWER_CLK_MOD_OUT_MSK   (0x1 << 2)
 
#define AD77681_POWER_CLK_MOD_OUT(x)   (((x) & 0x1) << 2)
 
#define AD77681_POWER_CLK_POWER_DOWN   0x08
 
#define AD77681_POWER_CLK_MCLK_DIV_MSK   (0x3 << 4)
 
#define AD77681_POWER_CLK_MCLK_DIV(x)   (((x) & 0x3) << 4)
 
#define AD77681_POWER_CLK_CLOCK_SEL_MSK   (0x3 << 6)
 
#define AD77681_POWER_CLK_CLOCK_SEL(x)   (((x) & 0x3) << 6)
 
#define AD77681_CONVERSION_DIAG_MUX_MSK   (0xF << 4)
 
#define AD77681_CONVERSION_DIAG_MUX_SEL(x)   (((x) & 0xF) << 4)
 
#define AD77681_CONVERSION_DIAG_SEL_MSK   (0x1 << 3)
 
#define AD77681_CONVERSION_DIAG_SEL(x)   (((x) & 0x1) << 3)
 
#define AD77681_CONVERSION_MODE_MSK   (0x7 << 0)
 
#define AD77681_CONVERSION_MODE(x)   (((x) & 0x7) << 0)
 
#define AD77681_ANALOG_REF_BUF_POS_MSK   (0x3 << 6)
 
#define AD77681_ANALOG_REF_BUF_POS(x)   (((x) & 0x3) << 6)
 
#define AD77681_ANALOG_REF_BUF_NEG_MSK   (0x3 << 4)
 
#define AD77681_ANALOG_REF_BUF_NEG(x)   (((x) & 0x3) << 4)
 
#define AD77681_ANALOG_AIN_BUF_POS_OFF_MSK   (0x1 << 1)
 
#define AD77681_ANALOG_AIN_BUF_POS_OFF(x)   (((x) & 0x1) << 1)
 
#define AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK   (0x1 << 0)
 
#define AD77681_ANALOG_AIN_BUF_NEG_OFF(x)   (((x) & 0x1) << 0)
 
#define AD77681_ANALOG2_VCM_MSK   (0x7 << 0)
 
#define AD77681_ANALOG2_VCM(x)   (((x) & 0x7) << 0)
 
#define AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK   (0x1 << 7)
 
#define AD77681_DIGI_FILTER_60HZ_REJ_EN(x)   (((x) & 0x1) << 7)
 
#define AD77681_DIGI_FILTER_FILTER_MSK   (0x7 << 4)
 
#define AD77681_DIGI_FILTER_FILTER(x)   (((x) & 0x7) << 4)
 
#define AD77681_DIGI_FILTER_DEC_RATE_MSK   (0x7 << 0)
 
#define AD77681_DIGI_FILTER_DEC_RATE(x)   (((x) & 0x7) << 0)
 
#define AD77681_SINC3_DEC_RATE_MSB_MSK   (0x0F << 0)
 
#define AD77681_SINC3_DEC_RATE_MSB(x)   (((x) & 0x0F) << 0)
 
#define AD77681_SINC3_DEC_RATE_LSB_MSK   (0xFF << 0)
 
#define AD77681_SINC3_DEC_RATE_LSB(x)   (((x) & 0xFF) << 0)
 
#define AD77681_DC_RATIO_IDLE_TIME_MSK   (0xFF << 0)
 
#define AD77681_DC_RATIO_IDLE_TIME(x)   (((x) & 0xFF) << 0)
 
#define AD77681_SYNC_RST_SPI_STARTB_MSK   (0x1 << 7)
 
#define AD77681_SYNC_RST_SPI_STARTB(x)   (((x) & 0x1) << 7)
 
#define AD77681_SYNC_RST_SYNCOUT_EDGE_MSK   (0x1 << 6)
 
#define AD77681_SYNC_RST_SYNCOUT_EDGE(x)   (((x) & 0x1) << 6)
 
#define AD77681_SYNC_RST_GPIO_START_EN_MSK   (0x1 << 3)
 
#define AD77681_SYNC_RST_GPIO_START_EN(x)   (((x) & 0x1) << 3)
 
#define AD77681_SYNC_RST_SPI_RESET_MSK   (0x3 << 0)
 
#define AD77681_SYNC_RST_SPI_RESET(x)   (((x) & 0x3) << 0)
 
#define AD77681_GPIO_CNTRL_UGPIO_EN_MSK   (0x1 << 7)
 
#define AD77681_GPIO_CNTRL_UGPIO_EN(x)   (((x) & 0x1) << 7)
 
#define AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK   (0x1 << 6)
 
#define AD77681_GPIO_CNTRL_GPIO2_OD_EN(x)   (((x) & 0x1) << 6)
 
#define AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK   (0x1 << 5)
 
#define AD77681_GPIO_CNTRL_GPIO1_OD_EN(x)   (((x) & 0x1) << 5)
 
#define AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK   (0x1 << 4)
 
#define AD77681_GPIO_CNTRL_GPIO0_OD_EN(x)   (((x) & 0x1) << 4)
 
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK   (0x7 << 4)
 
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN(x)   (((x) & 0x7) << 4)
 
#define AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK   (0x1 << 3)
 
#define AD77681_GPIO_CNTRL_GPIO3_OP_EN(x)   (((x) & 0x1) << 3)
 
#define AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK   (0x1 << 2)
 
#define AD77681_GPIO_CNTRL_GPIO2_OP_EN(x)   (((x) & 0x1) << 2)
 
#define AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK   (0x1 << 1)
 
#define AD77681_GPIO_CNTRL_GPIO1_OP_EN(x)   (((x) & 0x1) << 1)
 
#define AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK   (0x1 << 0)
 
#define AD77681_GPIO_CNTRL_GPIO0_OP_EN(x)   (((x) & 0x1) << 0)
 
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK   (0xF << 0)
 
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN(x)   (((x) & 0xF) << 0)
 
#define AD77681_GPIO_WRITE_3_MSK   (0x1 << 3)
 
#define AD77681_GPIO_WRITE_3(x)   (((x) & 0x1) << 3)
 
#define AD77681_GPIO_WRITE_2_MSK   (0x1 << 2)
 
#define AD77681_GPIO_WRITE_2(x)   (((x) & 0x1) << 2)
 
#define AD77681_GPIO_WRITE_1_MSK   (0x1 << 1)
 
#define AD77681_GPIO_WRITE_1(x)   (((x) & 0x1) << 1)
 
#define AD77681_GPIO_WRITE_0_MSK   (0x1 << 0)
 
#define AD77681_GPIO_WRITE_0(x)   (((x) & 0x1) << 0)
 
#define AD77681_GPIO_WRITE_ALL_MSK   (0xF << 0)
 
#define AD77681_GPIO_WRITE_ALL(x)   (((x) & 0xF))
 
#define AD77681_GPIO_READ_3_MSK   (0x1 << 3)
 
#define AD77681_GPIO_READ_2_MSK   (0x1 << 2)
 
#define AD77681_GPIO_READ_1_MSK   (0x1 << 1)
 
#define AD77681_GPIO_READ_0_MSK   (0x1 << 0)
 
#define AD77681_GPIO_READ_ALL_MSK   (0xF << 0)
 
#define AD77681_OFFSET_HI_MSK   (0xFF << 0)
 
#define AD77681_OFFSET_HI(x)   (((x) & 0xFF) << 0)
 
#define AD77681_OFFSET_MID_MSK   (0xFF << 0)
 
#define AD77681_OFFSET_MID(x)   (((x) & 0xFF) << 0)
 
#define AD77681_OFFSET_LO_MSK   (0xFF << 0)
 
#define AD77681_OFFSET_LO(x)   (((x) & 0xFF) << 0)
 
#define AD77681_GAIN_HI_MSK   (0xFF << 0)
 
#define AD77681_GAIN_HI(x)   (((x) & 0xFF) << 0)
 
#define AD77681_GAIN_MID_MSK   (0xFF << 0)
 
#define AD77681_GAIN_MID(x)   (((x) & 0xFF) << 0)
 
#define AD77681_GAIN_LOW_MSK   (0xFF << 0)
 
#define AD77681_GAIN_LOW(x)   (((x) & 0xFF) << 0)
 
#define AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK   (0x1 << 4)
 
#define AD77681_SPI_DIAG_ERR_SPI_IGNORE(x)   (((x) & 0x1) << 4)
 
#define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK   (0x1 << 3)
 
#define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT(x)   (((x) & 0x1) << 3)
 
#define AD77681_SPI_DIAG_ERR_SPI_RD_MSK   (0x1 << 2)
 
#define AD77681_SPI_DIAG_ERR_SPI_RD(x)   (((x) & 0x1) << 2)
 
#define AD77681_SPI_DIAG_ERR_SPI_WR_MSK   (0x1 << 1)
 
#define AD77681_SPI_DIAG_ERR_SPI_WR(x)   (((x) & 0x1) << 1)
 
#define AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK   (0x1 << 5)
 
#define AD77681_ADC_DIAG_ERR_DLDO_PSM(x)   (((x) & 0x1) << 5)
 
#define AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK   (0x1 << 4)
 
#define AD77681_ADC_DIAG_ERR_ALDO_PSM(x)   (((x) & 0x1) << 4)
 
#define AD77681_ADC_DIAG_ERR_FILT_SAT_MSK   (0x1 << 2)
 
#define AD77681_ADC_DIAG_ERR_FILT_SAT(x)   (((x) & 0x1) << 2)
 
#define AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK   (0x1 << 1)
 
#define AD77681_ADC_DIAG_ERR_FILT_NOT_SET(x)   (((x) & 0x1) << 1)
 
#define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK   (0x1 << 0)
 
#define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL(x)   (((x) & 0x1) << 0)
 
#define AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK   (0x1 << 4)
 
#define AD77681_DIG_DIAG_ERR_MEMMAP_CRC(x)   (((x) & 0x1) << 4)
 
#define AD77681_DIG_DIAG_ERR_RAM_CRC_MSK   (0x1 << 3)
 
#define AD77681_DIG_DIAG_ERR_RAM_CRC(x)   (((x) & 0x1) << 3)
 
#define AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK   (0x1 << 2)
 
#define AD77681_DIG_DIAG_ERR_FUSE_CRC(x)   (((x) & 0x1) << 2)
 
#define AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK   (0x1 << 0)
 
#define AD77681_DIG_DIAG_FREQ_COUNT_EN(x)   (((x) & 0x1) << 0)
 
#define AD77681_MASTER_ERROR_MSK   (0x1 << 7)
 
#define AD77681_MASTER_ADC_ERROR_MSK   (0x1 << 6)
 
#define AD77681_MASTER_DIG_ERROR_MSK   (0x1 << 5)
 
#define AD77681_MASTER_DIG_ERR_EXT_CLK_MSK   (0x1 << 4)
 
#define AD77681_MASTER_FILT_SAT_MSK   (0x1 << 3)
 
#define AD77681_MASTER_FILT_NOT_SET_MSK   (0x1 << 2)
 
#define AD77681_MASTER_SPI_ERROR_MSK   (0x1 << 1)
 
#define AD77681_MASTER_POR_FLAG_MSK   (0x1 << 0)
 
#define AD77681_SPI_IGNORE_ERROR_MSK   (0x1 << 4)
 
#define AD77681_SPI_IGNORE_ERROR_CLR(x)   (((x) & 0x1) << 4)
 
#define AD77681_SPI_CLK_CNT_ERROR_MSK   (0x1 << 3)
 
#define AD77681_SPI_READ_ERROR_MSK   (0x1 << 2)
 
#define AD77681_SPI_READ_ERROR_CLR(x)   (((x) & 0x1) << 2)
 
#define AD77681_SPI_WRITE_ERROR_MSK   (0x1 << 1)
 
#define AD77681_SPI_WRITE_ERROR_CLR(x)   (((x) & 0x1) << 1)
 
#define AD77681_SPI_CRC_ERROR_MSK   (0x1 << 0)
 
#define AD77681_SPI_CRC_ERROR_CLR(x)   (((x) & 0x1) << 0)
 
#define AD77681_ADC_DLDO_PSM_ERROR_MSK   (0x1 << 5)
 
#define AD77681_ADC_ALDO_PSM_ERROR_MSK   (0x1 << 4)
 
#define AD77681_ADC_REF_DET_ERROR_MSK   (0x1 << 3)
 
#define AD77681_ADC_FILT_SAT_MSK   (0x1 << 2)
 
#define AD77681_ADC_FILT_NOT_SET_MSK   (0x1 << 1)
 
#define AD77681_ADC_DIG_ERR_EXT_CLK_MSK   (0x1 << 0)
 
#define AD77681_DIG_MEMMAP_CRC_ERROR_MSK   (0x1 << 4)
 
#define AD77681_DIG_RAM_CRC_ERROR_MSK   (0x1 << 3)
 
#define AD77681_DIG_FUS_CRC_ERROR_MSK   (0x1 << 2)
 
#define AD77681_MCLK_COUNTER_MSK   (0xFF << 0)
 
#define AD77681_MCLK_COUNTER(x)   (((x) & 0xFF) << 0)
 
#define AD77681_COEF_CONTROL_COEFFACCESSEN_MSK   (0x1 << 7)
 
#define AD77681_COEF_CONTROL_COEFFACCESSEN(x)   (((x) & 0x1) << 7)
 
#define AD77681_COEF_CONTROL_COEFFWRITEEN_MSK   (0x1 << 6)
 
#define AD77681_COEF_CONTROL_COEFFWRITEEN(x)   (((x) & 0x1) << 6)
 
#define AD77681_COEF_CONTROL_COEFFADDR_MSK   (0x3F << 5)
 
#define AD77681_COEF_CONTROL_COEFFADDR(x)   (((x) & 0x3F) << 5)
 
#define AD77681_COEFF_DATA_USERCOEFFEN_MSK   (0x1 << 23)
 
#define AD77681_COEFF_DATA_USERCOEFFEN(x)   (((x) & 0x1) << 23)
 
#define AD77681_COEFF_DATA_COEFFDATA_MSK   (0x7FFFFF << 22)
 
#define AD77681_COEFF_DATA_COEFFDATA(x)   (((x) & 0x7FFFFF) << 22)
 
#define AD77681_ACCESS_KEY_MSK   (0xFF << 0)
 
#define AD77681_ACCESS_KEY(x)   (((x) & 0xFF) << 0)
 
#define AD77681_ACCESS_KEY_CHECK_MSK   (0x1 << 0)
 
#define AD77681_REG_READ(x)   ( (1 << 6) | (x & 0xFF) )
 
#define AD77681_REG_WRITE(x)   ( (~(1 << 6)) & (x & 0xFF) )
 
#define AD77681_CRC8_POLY   0x07
 
#define INITIAL_CRC_CRC8   0x03
 
#define INITIAL_CRC_XOR   0x6C
 
#define INITIAL_CRC   0x00
 
#define CRC_DEBUG
 
#define EXIT_CONT_READ   0x6C
 
#define AD7768_N_BITS   24
 
#define AD7768_FULL_SCALE   (1 << AD7768_N_BITS)
 
#define AD7768_HALF_SCALE   (1 << (AD7768_N_BITS - 1))
 
#define ARRAY_SIZE(x)   (sizeof(x) / sizeof((x)[0]))
 
#define ENABLE   1
 
#define DISABLE   0
 

Enumerations

enum  ad77681_power_mode {
  AD77681_ECO = 0,
  AD77681_MEDIAN = 2,
  AD77681_FAST = 3
}
 
enum  ad77681_mclk_div {
  AD77681_MCLK_DIV_16 = 0,
  AD77681_MCLK_DIV_8 = 1,
  AD77681_MCLK_DIV_4 = 2,
  AD77681_MCLK_DIV_2 = 3
}
 
enum  ad77681_conv_mode {
  AD77681_CONV_CONTINUOUS = 0,
  AD77681_CONV_ONE_SHOT = 1,
  AD77681_CONV_SINGLE = 2,
  AD77681_CONV_PERIODIC = 3,
  AD77681_CONV_STANDBY = 4
}
 
enum  ad77681_conv_len {
  AD77681_CONV_24BIT = 0,
  AD77681_CONV_16BIT = 1
}
 
enum  ad77681_rdy_dout {
  AD77681_RDY_DOUT_EN,
  AD77681_RDY_DOUT_DIS
}
 
enum  ad77681_conv_diag_mux {
  AD77681_TEMP_SENSOR = 0x0,
  AD77681_AIN_SHORT = 0x8,
  AD77681_POSITIVE_FS = 0x9,
  AD77681_NEGATIVE_FS = 0xA
}
 
enum  ad77681_crc_sel {
  AD77681_CRC,
  AD77681_XOR,
  AD77681_NO_CRC
}
 
enum  ad77681_filter_type {
  AD77681_SINC5 = 0,
  AD77681_SINC5_DECx8 = 1,
  AD77681_SINC5_DECx16 = 2,
  AD77681_SINC3 = 3,
  AD77681_FIR = 4
}
 
enum  ad77681_sinc5_fir_decimate {
  AD77681_SINC5_FIR_DECx32 = 0,
  AD77681_SINC5_FIR_DECx64 = 1,
  AD77681_SINC5_FIR_DECx128 = 2,
  AD77681_SINC5_FIR_DECx256 = 3,
  AD77681_SINC5_FIR_DECx512 = 4,
  AD77681_SINC5_FIR_DECx1024 = 5
}
 
enum  ad77681_sleep_wake {
  AD77681_SLEEP = 1,
  AD77681_WAKE = 0
}
 
enum  ad7761_reset_option {
  AD77681_SOFT_RESET,
  AD77681_HARD_RESET
}
 
enum  ad77681_AINn_precharge {
  AD77681_AINn_ENABLED = 0,
  AD77681_AINn_DISABLED = 1
}
 
enum  ad77681_AINp_precharge {
  AD77681_AINp_ENABLED = 0,
  AD77681_AINp_DISABLED = 1
}
 
enum  ad77681_REFn_buffer {
  AD77681_BUFn_ENABLED = 0,
  AD77681_BUFn_DISABLED = 1,
  AD77681_BUFn_FULL_BUFFER_ON = 2
}
 
enum  ad77681_REFp_buffer {
  AD77681_BUFp_ENABLED = 0,
  AD77681_BUFp_DISABLED = 1,
  AD77681_BUFp_FULL_BUFFER_ON = 2
}
 
enum  ad77681_VCM_out {
  AD77681_VCM_HALF_VCC = 0,
  AD77681_VCM_2_5V = 1,
  AD77681_VCM_2_05V = 2,
  AD77681_VCM_1_9V = 3,
  AD77681_VCM_1_65V = 4,
  AD77681_VCM_1_1V = 5,
  AD77681_VCM_0_9V = 6,
  AD77681_VCM_OFF = 7
}
 
enum  ad77681_gobal_gpio_enable {
  AD77681_GLOBAL_GPIO_ENABLE = 1,
  AD77681_GLOBAL_GPIO_DISABLE = 0
}
 
enum  ad77681_gpios {
  AD77681_GPIO0 = 0,
  AD77681_GPIO1 = 1,
  AD77681_GPIO2 = 2,
  AD77681_GPIO3 = 3,
  AD77681_ALL_GPIOS = 4
}
 
enum  ad77681_gpio_output_type {
  AD77681_GPIO_STRONG_DRIVER = 0,
  AD77681_GPIO_OPEN_DRAIN = 1
}
 
enum  ad77681_continuous_read {
  AD77681_CONTINUOUS_READ_ENABLE = 1,
  AD77681_CONTINUOUS_READ_DISABLE = 0
}
 
enum  ad77681_data_read_mode {
  AD77681_REGISTER_DATA_READ = 0,
  AD77681_CONTINUOUS_DATA_READ = 1
}
 

Functions

uint8_t ad77681_compute_crc8 (uint8_t *data, uint8_t data_size, uint8_t init_val)
 
uint8_t ad77681_compute_xor (uint8_t *data, uint8_t data_size, uint8_t init_val)
 
int32_t ad77681_setup (struct ad77681_dev **device, struct ad77681_init_param init_param, struct ad77681_status_registers **status)
 
int32_t ad77681_spi_reg_read (struct ad77681_dev *dev, uint8_t reg_addr, uint8_t *reg_data)
 
int32_t ad77681_spi_read_mask (struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t *data)
 
int32_t ad77681_spi_reg_write (struct ad77681_dev *dev, uint8_t reg_addr, uint8_t reg_data)
 
int32_t ad77681_spi_write_mask (struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t data)
 
int32_t ad77681_set_power_mode (struct ad77681_dev *dev, enum ad77681_power_mode mode)
 
int32_t ad77681_set_mclk_div (struct ad77681_dev *dev, enum ad77681_mclk_div clk_div)
 
int32_t ad77681_spi_read_adc_data (struct ad77681_dev *dev, uint8_t *adc_data, enum ad77681_data_read_mode mode)
 
int32_t ad77681_set_conv_mode (struct ad77681_dev *dev, enum ad77681_conv_mode conv_mode, enum ad77681_conv_diag_mux diag_mux_sel, bool conv_diag_sel)
 
int32_t ad77681_set_convlen (struct ad77681_dev *dev, enum ad77681_conv_len conv_len)
 
int32_t ad77681_soft_reset (struct ad77681_dev *dev)
 
int32_t ad77681_initiate_sync (struct ad77681_dev *dev)
 
int32_t ad77681_programmable_filter (struct ad77681_dev *dev, const float *coeffs, uint8_t num_coeffs)
 
int32_t ad77681_gpio_read (struct ad77681_dev *dev, uint8_t *value, enum ad77681_gpios gpio_number)
 
int32_t ad77681_apply_offset (struct ad77681_dev *dev, uint32_t value)
 
int32_t ad77681_apply_gain (struct ad77681_dev *dev, uint32_t value)
 
int32_t ad77681_set_crc_sel (struct ad77681_dev *dev, enum ad77681_crc_sel crc_sel)
 
int32_t ad77681_gpio_open_drain (struct ad77681_dev *dev, enum ad77681_gpios gpio_number, enum ad77681_gpio_output_type output_type)
 
int32_t ad77681_set_continuos_read (struct ad77681_dev *dev, enum ad77681_continuous_read continuous_enable)
 
int32_t ad77681_clear_error_flags (struct ad77681_dev *dev)
 
int32_t ad77681_data_to_voltage (struct ad77681_dev *dev, uint32_t *raw_code, double *voltage)
 
int32_t ad77681_CRC_status_handling (struct ad77681_dev *dev, uint16_t *data_buffer)
 
int32_t ad77681_set_AINn_buffer (struct ad77681_dev *dev, enum ad77681_AINn_precharge AINn)
 
int32_t ad77681_set_AINp_buffer (struct ad77681_dev *dev, enum ad77681_AINp_precharge AINp)
 
int32_t ad77681_set_REFn_buffer (struct ad77681_dev *dev, enum ad77681_REFn_buffer REFn)
 
int32_t ad77681_set_REFp_buffer (struct ad77681_dev *dev, enum ad77681_REFp_buffer REFp)
 
int32_t ad77681_set_filter_type (struct ad77681_dev *dev, enum ad77681_sinc5_fir_decimate decimate, enum ad77681_filter_type filter, uint16_t sinc3_osr)
 
int32_t ad77681_set_50HZ_rejection (struct ad77681_dev *dev, uint8_t enable)
 
int32_t ad77681_power_down (struct ad77681_dev *dev, enum ad77681_sleep_wake sleep_wake)
 
int32_t ad77681_set_status_bit (struct ad77681_dev *dev, bool status_bit)
 
int32_t ad77681_set_VCM_output (struct ad77681_dev *dev, enum ad77681_VCM_out VCM_out)
 
int32_t ad77681_gpio_write (struct ad77681_dev *dev, uint8_t value, enum ad77681_gpios gpio_number)
 
int32_t ad77681_gpio_inout (struct ad77681_dev *dev, uint8_t direction, enum ad77681_gpios gpio_number)
 
int32_t ad77681_global_gpio (struct ad77681_dev *devices, enum ad77681_gobal_gpio_enable gpio_enable)
 
int32_t ad77681_scratchpad (struct ad77681_dev *dev, uint8_t *sequence)
 
int32_t ad77681_error_flags_enabe (struct ad77681_dev *dev)
 
int32_t ad77681_update_sample_rate (struct ad77681_dev *dev)
 
int32_t ad77681_SINC3_ODR (struct ad77681_dev *dev, uint16_t *sinc3_dec_reg, float sinc3_odr)
 
int32_t ad77681_status (struct ad77681_dev *dev, struct ad77681_status_registers *status)
 

Detailed Description

Header file of the AD7768-1 Driver.

Author
SPopa (stefa.nosp@m.n.po.nosp@m.pa@an.nosp@m.alog.nosp@m..com)

Copyright 2017(c) Analog Devices, Inc.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ AD77681_ACCESS_KEY

#define AD77681_ACCESS_KEY (   x)    (((x) & 0xFF) << 0)

◆ AD77681_ACCESS_KEY_CHECK_MSK

#define AD77681_ACCESS_KEY_CHECK_MSK   (0x1 << 0)

◆ AD77681_ACCESS_KEY_MSK

#define AD77681_ACCESS_KEY_MSK   (0xFF << 0)

◆ AD77681_ADC_ALDO_PSM_ERROR_MSK

#define AD77681_ADC_ALDO_PSM_ERROR_MSK   (0x1 << 4)

◆ AD77681_ADC_DIAG_ERR_ALDO_PSM

#define AD77681_ADC_DIAG_ERR_ALDO_PSM (   x)    (((x) & 0x1) << 4)

◆ AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK

#define AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK   (0x1 << 4)

◆ AD77681_ADC_DIAG_ERR_DLDO_PSM

#define AD77681_ADC_DIAG_ERR_DLDO_PSM (   x)    (((x) & 0x1) << 5)

◆ AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK

#define AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK   (0x1 << 5)

◆ AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL

#define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL (   x)    (((x) & 0x1) << 0)

◆ AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK

#define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK   (0x1 << 0)

◆ AD77681_ADC_DIAG_ERR_FILT_NOT_SET

#define AD77681_ADC_DIAG_ERR_FILT_NOT_SET (   x)    (((x) & 0x1) << 1)

◆ AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK

#define AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK   (0x1 << 1)

◆ AD77681_ADC_DIAG_ERR_FILT_SAT

#define AD77681_ADC_DIAG_ERR_FILT_SAT (   x)    (((x) & 0x1) << 2)

◆ AD77681_ADC_DIAG_ERR_FILT_SAT_MSK

#define AD77681_ADC_DIAG_ERR_FILT_SAT_MSK   (0x1 << 2)

◆ AD77681_ADC_DIG_ERR_EXT_CLK_MSK

#define AD77681_ADC_DIG_ERR_EXT_CLK_MSK   (0x1 << 0)

◆ AD77681_ADC_DLDO_PSM_ERROR_MSK

#define AD77681_ADC_DLDO_PSM_ERROR_MSK   (0x1 << 5)

◆ AD77681_ADC_FILT_NOT_SET_MSK

#define AD77681_ADC_FILT_NOT_SET_MSK   (0x1 << 1)

◆ AD77681_ADC_FILT_SAT_MSK

#define AD77681_ADC_FILT_SAT_MSK   (0x1 << 2)

◆ AD77681_ADC_REF_DET_ERROR_MSK

#define AD77681_ADC_REF_DET_ERROR_MSK   (0x1 << 3)

◆ AD77681_ANALOG2_VCM

#define AD77681_ANALOG2_VCM (   x)    (((x) & 0x7) << 0)

◆ AD77681_ANALOG2_VCM_MSK

#define AD77681_ANALOG2_VCM_MSK   (0x7 << 0)

◆ AD77681_ANALOG_AIN_BUF_NEG_OFF

#define AD77681_ANALOG_AIN_BUF_NEG_OFF (   x)    (((x) & 0x1) << 0)

◆ AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK

#define AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK   (0x1 << 0)

◆ AD77681_ANALOG_AIN_BUF_POS_OFF

#define AD77681_ANALOG_AIN_BUF_POS_OFF (   x)    (((x) & 0x1) << 1)

◆ AD77681_ANALOG_AIN_BUF_POS_OFF_MSK

#define AD77681_ANALOG_AIN_BUF_POS_OFF_MSK   (0x1 << 1)

◆ AD77681_ANALOG_REF_BUF_NEG

#define AD77681_ANALOG_REF_BUF_NEG (   x)    (((x) & 0x3) << 4)

◆ AD77681_ANALOG_REF_BUF_NEG_MSK

#define AD77681_ANALOG_REF_BUF_NEG_MSK   (0x3 << 4)

◆ AD77681_ANALOG_REF_BUF_POS

#define AD77681_ANALOG_REF_BUF_POS (   x)    (((x) & 0x3) << 6)

◆ AD77681_ANALOG_REF_BUF_POS_MSK

#define AD77681_ANALOG_REF_BUF_POS_MSK   (0x3 << 6)

◆ AD77681_COEF_CONTROL_COEFFACCESSEN

#define AD77681_COEF_CONTROL_COEFFACCESSEN (   x)    (((x) & 0x1) << 7)

◆ AD77681_COEF_CONTROL_COEFFACCESSEN_MSK

#define AD77681_COEF_CONTROL_COEFFACCESSEN_MSK   (0x1 << 7)

◆ AD77681_COEF_CONTROL_COEFFADDR

#define AD77681_COEF_CONTROL_COEFFADDR (   x)    (((x) & 0x3F) << 5)

◆ AD77681_COEF_CONTROL_COEFFADDR_MSK

#define AD77681_COEF_CONTROL_COEFFADDR_MSK   (0x3F << 5)

◆ AD77681_COEF_CONTROL_COEFFWRITEEN

#define AD77681_COEF_CONTROL_COEFFWRITEEN (   x)    (((x) & 0x1) << 6)

◆ AD77681_COEF_CONTROL_COEFFWRITEEN_MSK

#define AD77681_COEF_CONTROL_COEFFWRITEEN_MSK   (0x1 << 6)

◆ AD77681_COEFF_DATA_COEFFDATA

#define AD77681_COEFF_DATA_COEFFDATA (   x)    (((x) & 0x7FFFFF) << 22)

◆ AD77681_COEFF_DATA_COEFFDATA_MSK

#define AD77681_COEFF_DATA_COEFFDATA_MSK   (0x7FFFFF << 22)

◆ AD77681_COEFF_DATA_USERCOEFFEN

#define AD77681_COEFF_DATA_USERCOEFFEN (   x)    (((x) & 0x1) << 23)

◆ AD77681_COEFF_DATA_USERCOEFFEN_MSK

#define AD77681_COEFF_DATA_USERCOEFFEN_MSK   (0x1 << 23)

◆ AD77681_CONVERSION_DIAG_MUX_MSK

#define AD77681_CONVERSION_DIAG_MUX_MSK   (0xF << 4)

◆ AD77681_CONVERSION_DIAG_MUX_SEL

#define AD77681_CONVERSION_DIAG_MUX_SEL (   x)    (((x) & 0xF) << 4)

◆ AD77681_CONVERSION_DIAG_SEL

#define AD77681_CONVERSION_DIAG_SEL (   x)    (((x) & 0x1) << 3)

◆ AD77681_CONVERSION_DIAG_SEL_MSK

#define AD77681_CONVERSION_DIAG_SEL_MSK   (0x1 << 3)

◆ AD77681_CONVERSION_MODE

#define AD77681_CONVERSION_MODE (   x)    (((x) & 0x7) << 0)

◆ AD77681_CONVERSION_MODE_MSK

#define AD77681_CONVERSION_MODE_MSK   (0x7 << 0)

◆ AD77681_CRC8_POLY

#define AD77681_CRC8_POLY   0x07

◆ AD77681_DC_RATIO_IDLE_TIME

#define AD77681_DC_RATIO_IDLE_TIME (   x)    (((x) & 0xFF) << 0)

◆ AD77681_DC_RATIO_IDLE_TIME_MSK

#define AD77681_DC_RATIO_IDLE_TIME_MSK   (0xFF << 0)

◆ AD77681_DIG_DIAG_ERR_FUSE_CRC

#define AD77681_DIG_DIAG_ERR_FUSE_CRC (   x)    (((x) & 0x1) << 2)

◆ AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK

#define AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK   (0x1 << 2)

◆ AD77681_DIG_DIAG_ERR_MEMMAP_CRC

#define AD77681_DIG_DIAG_ERR_MEMMAP_CRC (   x)    (((x) & 0x1) << 4)

◆ AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK

#define AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK   (0x1 << 4)

◆ AD77681_DIG_DIAG_ERR_RAM_CRC

#define AD77681_DIG_DIAG_ERR_RAM_CRC (   x)    (((x) & 0x1) << 3)

◆ AD77681_DIG_DIAG_ERR_RAM_CRC_MSK

#define AD77681_DIG_DIAG_ERR_RAM_CRC_MSK   (0x1 << 3)

◆ AD77681_DIG_DIAG_FREQ_COUNT_EN

#define AD77681_DIG_DIAG_FREQ_COUNT_EN (   x)    (((x) & 0x1) << 0)

◆ AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK

#define AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK   (0x1 << 0)

◆ AD77681_DIG_FUS_CRC_ERROR_MSK

#define AD77681_DIG_FUS_CRC_ERROR_MSK   (0x1 << 2)

◆ AD77681_DIG_MEMMAP_CRC_ERROR_MSK

#define AD77681_DIG_MEMMAP_CRC_ERROR_MSK   (0x1 << 4)

◆ AD77681_DIG_RAM_CRC_ERROR_MSK

#define AD77681_DIG_RAM_CRC_ERROR_MSK   (0x1 << 3)

◆ AD77681_DIGI_FILTER_60HZ_REJ_EN

#define AD77681_DIGI_FILTER_60HZ_REJ_EN (   x)    (((x) & 0x1) << 7)

◆ AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK

#define AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK   (0x1 << 7)

◆ AD77681_DIGI_FILTER_DEC_RATE

#define AD77681_DIGI_FILTER_DEC_RATE (   x)    (((x) & 0x7) << 0)

◆ AD77681_DIGI_FILTER_DEC_RATE_MSK

#define AD77681_DIGI_FILTER_DEC_RATE_MSK   (0x7 << 0)

◆ AD77681_DIGI_FILTER_FILTER

#define AD77681_DIGI_FILTER_FILTER (   x)    (((x) & 0x7) << 4)

◆ AD77681_DIGI_FILTER_FILTER_MSK

#define AD77681_DIGI_FILTER_FILTER_MSK   (0x7 << 4)

◆ AD77681_GAIN_HI

#define AD77681_GAIN_HI (   x)    (((x) & 0xFF) << 0)

◆ AD77681_GAIN_HI_MSK

#define AD77681_GAIN_HI_MSK   (0xFF << 0)

◆ AD77681_GAIN_LOW

#define AD77681_GAIN_LOW (   x)    (((x) & 0xFF) << 0)

◆ AD77681_GAIN_LOW_MSK

#define AD77681_GAIN_LOW_MSK   (0xFF << 0)

◆ AD77681_GAIN_MID

#define AD77681_GAIN_MID (   x)    (((x) & 0xFF) << 0)

◆ AD77681_GAIN_MID_MSK

#define AD77681_GAIN_MID_MSK   (0xFF << 0)

◆ AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN

#define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN (   x)    (((x) & 0x7) << 4)

◆ AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK

#define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK   (0x7 << 4)

◆ AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN

#define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN (   x)    (((x) & 0xF) << 0)

◆ AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK

#define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK   (0xF << 0)

◆ AD77681_GPIO_CNTRL_GPIO0_OD_EN

#define AD77681_GPIO_CNTRL_GPIO0_OD_EN (   x)    (((x) & 0x1) << 4)

◆ AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK

#define AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK   (0x1 << 4)

◆ AD77681_GPIO_CNTRL_GPIO0_OP_EN

#define AD77681_GPIO_CNTRL_GPIO0_OP_EN (   x)    (((x) & 0x1) << 0)

◆ AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK

#define AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK   (0x1 << 0)

◆ AD77681_GPIO_CNTRL_GPIO1_OD_EN

#define AD77681_GPIO_CNTRL_GPIO1_OD_EN (   x)    (((x) & 0x1) << 5)

◆ AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK

#define AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK   (0x1 << 5)

◆ AD77681_GPIO_CNTRL_GPIO1_OP_EN

#define AD77681_GPIO_CNTRL_GPIO1_OP_EN (   x)    (((x) & 0x1) << 1)

◆ AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK

#define AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK   (0x1 << 1)

◆ AD77681_GPIO_CNTRL_GPIO2_OD_EN

#define AD77681_GPIO_CNTRL_GPIO2_OD_EN (   x)    (((x) & 0x1) << 6)

◆ AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK

#define AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK   (0x1 << 6)

◆ AD77681_GPIO_CNTRL_GPIO2_OP_EN

#define AD77681_GPIO_CNTRL_GPIO2_OP_EN (   x)    (((x) & 0x1) << 2)

◆ AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK

#define AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK   (0x1 << 2)

◆ AD77681_GPIO_CNTRL_GPIO3_OP_EN

#define AD77681_GPIO_CNTRL_GPIO3_OP_EN (   x)    (((x) & 0x1) << 3)

◆ AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK

#define AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK   (0x1 << 3)

◆ AD77681_GPIO_CNTRL_UGPIO_EN

#define AD77681_GPIO_CNTRL_UGPIO_EN (   x)    (((x) & 0x1) << 7)

◆ AD77681_GPIO_CNTRL_UGPIO_EN_MSK

#define AD77681_GPIO_CNTRL_UGPIO_EN_MSK   (0x1 << 7)

◆ AD77681_GPIO_READ_0_MSK

#define AD77681_GPIO_READ_0_MSK   (0x1 << 0)

◆ AD77681_GPIO_READ_1_MSK

#define AD77681_GPIO_READ_1_MSK   (0x1 << 1)

◆ AD77681_GPIO_READ_2_MSK

#define AD77681_GPIO_READ_2_MSK   (0x1 << 2)

◆ AD77681_GPIO_READ_3_MSK

#define AD77681_GPIO_READ_3_MSK   (0x1 << 3)

◆ AD77681_GPIO_READ_ALL_MSK

#define AD77681_GPIO_READ_ALL_MSK   (0xF << 0)

◆ AD77681_GPIO_WRITE_0

#define AD77681_GPIO_WRITE_0 (   x)    (((x) & 0x1) << 0)

◆ AD77681_GPIO_WRITE_0_MSK

#define AD77681_GPIO_WRITE_0_MSK   (0x1 << 0)

◆ AD77681_GPIO_WRITE_1

#define AD77681_GPIO_WRITE_1 (   x)    (((x) & 0x1) << 1)

◆ AD77681_GPIO_WRITE_1_MSK

#define AD77681_GPIO_WRITE_1_MSK   (0x1 << 1)

◆ AD77681_GPIO_WRITE_2

#define AD77681_GPIO_WRITE_2 (   x)    (((x) & 0x1) << 2)

◆ AD77681_GPIO_WRITE_2_MSK

#define AD77681_GPIO_WRITE_2_MSK   (0x1 << 2)

◆ AD77681_GPIO_WRITE_3

#define AD77681_GPIO_WRITE_3 (   x)    (((x) & 0x1) << 3)

◆ AD77681_GPIO_WRITE_3_MSK

#define AD77681_GPIO_WRITE_3_MSK   (0x1 << 3)

◆ AD77681_GPIO_WRITE_ALL

#define AD77681_GPIO_WRITE_ALL (   x)    (((x) & 0xF))

◆ AD77681_GPIO_WRITE_ALL_MSK

#define AD77681_GPIO_WRITE_ALL_MSK   (0xF << 0)

◆ AD77681_INTERFACE_CONT_READ_EN

#define AD77681_INTERFACE_CONT_READ_EN (   x)    (((x) & 0x1) << 0)

◆ AD77681_INTERFACE_CONT_READ_MSK

#define AD77681_INTERFACE_CONT_READ_MSK   (0x1 << 0)

◆ AD77681_INTERFACE_CONVLEN

#define AD77681_INTERFACE_CONVLEN (   x)    (((x) & 0x1) << 3)

◆ AD77681_INTERFACE_CONVLEN_MSK

#define AD77681_INTERFACE_CONVLEN_MSK   (0x1 << 3)

◆ AD77681_INTERFACE_CRC_EN

#define AD77681_INTERFACE_CRC_EN (   x)    (((x) & 0x1) << 6)

◆ AD77681_INTERFACE_CRC_EN_MSK

#define AD77681_INTERFACE_CRC_EN_MSK   (0x1 << 6)

◆ AD77681_INTERFACE_CRC_TYPE

#define AD77681_INTERFACE_CRC_TYPE (   x)    (((x) & 0x1) << 5)

◆ AD77681_INTERFACE_CRC_TYPE_MSK

#define AD77681_INTERFACE_CRC_TYPE_MSK   (0x1 << 5)

◆ AD77681_INTERFACE_RDY_EN

#define AD77681_INTERFACE_RDY_EN (   x)    (((x) & 0x1) << 3)

◆ AD77681_INTERFACE_RDY_EN_MSK

#define AD77681_INTERFACE_RDY_EN_MSK   (0x1 << 2)

◆ AD77681_INTERFACE_STATUS_EN

#define AD77681_INTERFACE_STATUS_EN (   x)    (((x) & 0x1) << 4)

◆ AD77681_INTERFACE_STATUS_EN_MSK

#define AD77681_INTERFACE_STATUS_EN_MSK   (0x1 << 4)

◆ AD77681_MASTER_ADC_ERROR_MSK

#define AD77681_MASTER_ADC_ERROR_MSK   (0x1 << 6)

◆ AD77681_MASTER_DIG_ERR_EXT_CLK_MSK

#define AD77681_MASTER_DIG_ERR_EXT_CLK_MSK   (0x1 << 4)

◆ AD77681_MASTER_DIG_ERROR_MSK

#define AD77681_MASTER_DIG_ERROR_MSK   (0x1 << 5)

◆ AD77681_MASTER_ERROR_MSK

#define AD77681_MASTER_ERROR_MSK   (0x1 << 7)

◆ AD77681_MASTER_FILT_NOT_SET_MSK

#define AD77681_MASTER_FILT_NOT_SET_MSK   (0x1 << 2)

◆ AD77681_MASTER_FILT_SAT_MSK

#define AD77681_MASTER_FILT_SAT_MSK   (0x1 << 3)

◆ AD77681_MASTER_POR_FLAG_MSK

#define AD77681_MASTER_POR_FLAG_MSK   (0x1 << 0)

◆ AD77681_MASTER_SPI_ERROR_MSK

#define AD77681_MASTER_SPI_ERROR_MSK   (0x1 << 1)

◆ AD77681_MCLK_COUNTER

#define AD77681_MCLK_COUNTER (   x)    (((x) & 0xFF) << 0)

◆ AD77681_MCLK_COUNTER_MSK

#define AD77681_MCLK_COUNTER_MSK   (0xFF << 0)

◆ AD77681_OFFSET_HI

#define AD77681_OFFSET_HI (   x)    (((x) & 0xFF) << 0)

◆ AD77681_OFFSET_HI_MSK

#define AD77681_OFFSET_HI_MSK   (0xFF << 0)

◆ AD77681_OFFSET_LO

#define AD77681_OFFSET_LO (   x)    (((x) & 0xFF) << 0)

◆ AD77681_OFFSET_LO_MSK

#define AD77681_OFFSET_LO_MSK   (0xFF << 0)

◆ AD77681_OFFSET_MID

#define AD77681_OFFSET_MID (   x)    (((x) & 0xFF) << 0)

◆ AD77681_OFFSET_MID_MSK

#define AD77681_OFFSET_MID_MSK   (0xFF << 0)

◆ AD77681_POWER_CLK_CLOCK_SEL

#define AD77681_POWER_CLK_CLOCK_SEL (   x)    (((x) & 0x3) << 6)

◆ AD77681_POWER_CLK_CLOCK_SEL_MSK

#define AD77681_POWER_CLK_CLOCK_SEL_MSK   (0x3 << 6)

◆ AD77681_POWER_CLK_MCLK_DIV

#define AD77681_POWER_CLK_MCLK_DIV (   x)    (((x) & 0x3) << 4)

◆ AD77681_POWER_CLK_MCLK_DIV_MSK

#define AD77681_POWER_CLK_MCLK_DIV_MSK   (0x3 << 4)

◆ AD77681_POWER_CLK_MOD_OUT

#define AD77681_POWER_CLK_MOD_OUT (   x)    (((x) & 0x1) << 2)

◆ AD77681_POWER_CLK_MOD_OUT_MSK

#define AD77681_POWER_CLK_MOD_OUT_MSK   (0x1 << 2)

◆ AD77681_POWER_CLK_POWER_DOWN

#define AD77681_POWER_CLK_POWER_DOWN   0x08

◆ AD77681_POWER_CLK_PWRMODE

#define AD77681_POWER_CLK_PWRMODE (   x)    (((x) & 0x3) << 0)

◆ AD77681_POWER_CLK_PWRMODE_MSK

#define AD77681_POWER_CLK_PWRMODE_MSK   0x3

◆ AD77681_REG_ACCESS_KEY

#define AD77681_REG_ACCESS_KEY   0x34

◆ AD77681_REG_ADC_DATA

#define AD77681_REG_ADC_DATA   0x2C

◆ AD77681_REG_ADC_DIAG_ENABLE

#define AD77681_REG_ADC_DIAG_ENABLE   0x29

◆ AD77681_REG_ADC_DIAG_STATUS

#define AD77681_REG_ADC_DIAG_STATUS   0x2F

◆ AD77681_REG_ANALOG

#define AD77681_REG_ANALOG   0x16

◆ AD77681_REG_ANALOG2

#define AD77681_REG_ANALOG2   0x17

◆ AD77681_REG_CHIP_GRADE

#define AD77681_REG_CHIP_GRADE   0x6

◆ AD77681_REG_CHIP_TYPE

#define AD77681_REG_CHIP_TYPE   0x3

◆ AD77681_REG_COEFF_CONTROL

#define AD77681_REG_COEFF_CONTROL   0x32

◆ AD77681_REG_COEFF_DATA

#define AD77681_REG_COEFF_DATA   0x33

◆ AD77681_REG_CONVERSION

#define AD77681_REG_CONVERSION   0x18

◆ AD77681_REG_DIG_DIAG_ENABLE

#define AD77681_REG_DIG_DIAG_ENABLE   0x2A

◆ AD77681_REG_DIG_DIAG_STATUS

#define AD77681_REG_DIG_DIAG_STATUS   0x30

◆ AD77681_REG_DIGITAL_FILTER

#define AD77681_REG_DIGITAL_FILTER   0x19

◆ AD77681_REG_DUTY_CYCLE_RATIO

#define AD77681_REG_DUTY_CYCLE_RATIO   0x1C

◆ AD77681_REG_GAIN_HI

#define AD77681_REG_GAIN_HI   0x24

◆ AD77681_REG_GAIN_LO

#define AD77681_REG_GAIN_LO   0x26

◆ AD77681_REG_GAIN_MID

#define AD77681_REG_GAIN_MID   0x25

◆ AD77681_REG_GPIO_CONTROL

#define AD77681_REG_GPIO_CONTROL   0x1E

◆ AD77681_REG_GPIO_READ

#define AD77681_REG_GPIO_READ   0x20

◆ AD77681_REG_GPIO_WRITE

#define AD77681_REG_GPIO_WRITE   0x1F

◆ AD77681_REG_INTERFACE_FORMAT

#define AD77681_REG_INTERFACE_FORMAT   0x14

◆ AD77681_REG_MASTER_STATUS

#define AD77681_REG_MASTER_STATUS   0x2D

◆ AD77681_REG_MCLK_COUNTER

#define AD77681_REG_MCLK_COUNTER   0x31

◆ AD77681_REG_OFFSET_HI

#define AD77681_REG_OFFSET_HI   0x21

◆ AD77681_REG_OFFSET_LO

#define AD77681_REG_OFFSET_LO   0x23

◆ AD77681_REG_OFFSET_MID

#define AD77681_REG_OFFSET_MID   0x22

◆ AD77681_REG_POWER_CLOCK

#define AD77681_REG_POWER_CLOCK   0x15

◆ AD77681_REG_PROD_ID_H

#define AD77681_REG_PROD_ID_H   0x5

◆ AD77681_REG_PROD_ID_L

#define AD77681_REG_PROD_ID_L   0x4

◆ AD77681_REG_READ

#define AD77681_REG_READ (   x)    ( (1 << 6) | (x & 0xFF) )

◆ AD77681_REG_SCRATCH_PAD

#define AD77681_REG_SCRATCH_PAD   0x0A

◆ AD77681_REG_SINC3_DEC_RATE_LSB

#define AD77681_REG_SINC3_DEC_RATE_LSB   0x1B

◆ AD77681_REG_SINC3_DEC_RATE_MSB

#define AD77681_REG_SINC3_DEC_RATE_MSB   0x1A

◆ AD77681_REG_SPI_DIAG_ENABLE

#define AD77681_REG_SPI_DIAG_ENABLE   0x28

◆ AD77681_REG_SPI_DIAG_STATUS

#define AD77681_REG_SPI_DIAG_STATUS   0x2E

◆ AD77681_REG_SYNC_RESET

#define AD77681_REG_SYNC_RESET   0x1D

◆ AD77681_REG_VENDOR_H

#define AD77681_REG_VENDOR_H   0x0D

◆ AD77681_REG_VENDOR_L

#define AD77681_REG_VENDOR_L   0x0C

◆ AD77681_REG_WRITE

#define AD77681_REG_WRITE (   x)    ( (~(1 << 6)) & (x & 0xFF) )

◆ AD77681_SCRATCHPAD

#define AD77681_SCRATCHPAD (   x)    (((x) & 0xFF) << 0)

◆ AD77681_SCRATCHPAD_MSK

#define AD77681_SCRATCHPAD_MSK   (0xFF << 0)

◆ AD77681_SINC3_DEC_RATE_LSB

#define AD77681_SINC3_DEC_RATE_LSB (   x)    (((x) & 0xFF) << 0)

◆ AD77681_SINC3_DEC_RATE_LSB_MSK

#define AD77681_SINC3_DEC_RATE_LSB_MSK   (0xFF << 0)

◆ AD77681_SINC3_DEC_RATE_MSB

#define AD77681_SINC3_DEC_RATE_MSB (   x)    (((x) & 0x0F) << 0)

◆ AD77681_SINC3_DEC_RATE_MSB_MSK

#define AD77681_SINC3_DEC_RATE_MSB_MSK   (0x0F << 0)

◆ AD77681_SPI_CLK_CNT_ERROR_MSK

#define AD77681_SPI_CLK_CNT_ERROR_MSK   (0x1 << 3)

◆ AD77681_SPI_CRC_ERROR_CLR

#define AD77681_SPI_CRC_ERROR_CLR (   x)    (((x) & 0x1) << 0)

◆ AD77681_SPI_CRC_ERROR_MSK

#define AD77681_SPI_CRC_ERROR_MSK   (0x1 << 0)

◆ AD77681_SPI_DIAG_ERR_SPI_CLK_CNT

#define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT (   x)    (((x) & 0x1) << 3)

◆ AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK

#define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK   (0x1 << 3)

◆ AD77681_SPI_DIAG_ERR_SPI_IGNORE

#define AD77681_SPI_DIAG_ERR_SPI_IGNORE (   x)    (((x) & 0x1) << 4)

◆ AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK

#define AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK   (0x1 << 4)

◆ AD77681_SPI_DIAG_ERR_SPI_RD

#define AD77681_SPI_DIAG_ERR_SPI_RD (   x)    (((x) & 0x1) << 2)

◆ AD77681_SPI_DIAG_ERR_SPI_RD_MSK

#define AD77681_SPI_DIAG_ERR_SPI_RD_MSK   (0x1 << 2)

◆ AD77681_SPI_DIAG_ERR_SPI_WR

#define AD77681_SPI_DIAG_ERR_SPI_WR (   x)    (((x) & 0x1) << 1)

◆ AD77681_SPI_DIAG_ERR_SPI_WR_MSK

#define AD77681_SPI_DIAG_ERR_SPI_WR_MSK   (0x1 << 1)

◆ AD77681_SPI_IGNORE_ERROR_CLR

#define AD77681_SPI_IGNORE_ERROR_CLR (   x)    (((x) & 0x1) << 4)

◆ AD77681_SPI_IGNORE_ERROR_MSK

#define AD77681_SPI_IGNORE_ERROR_MSK   (0x1 << 4)

◆ AD77681_SPI_READ_ERROR_CLR

#define AD77681_SPI_READ_ERROR_CLR (   x)    (((x) & 0x1) << 2)

◆ AD77681_SPI_READ_ERROR_MSK

#define AD77681_SPI_READ_ERROR_MSK   (0x1 << 2)

◆ AD77681_SPI_WRITE_ERROR_CLR

#define AD77681_SPI_WRITE_ERROR_CLR (   x)    (((x) & 0x1) << 1)

◆ AD77681_SPI_WRITE_ERROR_MSK

#define AD77681_SPI_WRITE_ERROR_MSK   (0x1 << 1)

◆ AD77681_SYNC_RST_GPIO_START_EN

#define AD77681_SYNC_RST_GPIO_START_EN (   x)    (((x) & 0x1) << 3)

◆ AD77681_SYNC_RST_GPIO_START_EN_MSK

#define AD77681_SYNC_RST_GPIO_START_EN_MSK   (0x1 << 3)

◆ AD77681_SYNC_RST_SPI_RESET

#define AD77681_SYNC_RST_SPI_RESET (   x)    (((x) & 0x3) << 0)

◆ AD77681_SYNC_RST_SPI_RESET_MSK

#define AD77681_SYNC_RST_SPI_RESET_MSK   (0x3 << 0)

◆ AD77681_SYNC_RST_SPI_STARTB

#define AD77681_SYNC_RST_SPI_STARTB (   x)    (((x) & 0x1) << 7)

◆ AD77681_SYNC_RST_SPI_STARTB_MSK

#define AD77681_SYNC_RST_SPI_STARTB_MSK   (0x1 << 7)

◆ AD77681_SYNC_RST_SYNCOUT_EDGE

#define AD77681_SYNC_RST_SYNCOUT_EDGE (   x)    (((x) & 0x1) << 6)

◆ AD77681_SYNC_RST_SYNCOUT_EDGE_MSK

#define AD77681_SYNC_RST_SYNCOUT_EDGE_MSK   (0x1 << 6)

◆ AD7768_FULL_SCALE

#define AD7768_FULL_SCALE   (1 << AD7768_N_BITS)

◆ AD7768_HALF_SCALE

#define AD7768_HALF_SCALE   (1 << (AD7768_N_BITS - 1))

◆ AD7768_N_BITS

#define AD7768_N_BITS   24

◆ ARRAY_SIZE

#define ARRAY_SIZE (   x)    (sizeof(x) / sizeof((x)[0]))

◆ CRC_DEBUG

#define CRC_DEBUG

◆ DISABLE

#define DISABLE   0

◆ ENABLE

#define ENABLE   1

◆ EXIT_CONT_READ

#define EXIT_CONT_READ   0x6C

◆ INITIAL_CRC

#define INITIAL_CRC   0x00

◆ INITIAL_CRC_CRC8

#define INITIAL_CRC_CRC8   0x03

◆ INITIAL_CRC_XOR

#define INITIAL_CRC_XOR   0x6C

Enumeration Type Documentation

◆ ad7761_reset_option

Enumerator
AD77681_SOFT_RESET 
AD77681_HARD_RESET 

◆ ad77681_AINn_precharge

Enumerator
AD77681_AINn_ENABLED 
AD77681_AINn_DISABLED 

◆ ad77681_AINp_precharge

Enumerator
AD77681_AINp_ENABLED 
AD77681_AINp_DISABLED 

◆ ad77681_continuous_read

Enumerator
AD77681_CONTINUOUS_READ_ENABLE 
AD77681_CONTINUOUS_READ_DISABLE 

◆ ad77681_conv_diag_mux

Enumerator
AD77681_TEMP_SENSOR 
AD77681_AIN_SHORT 
AD77681_POSITIVE_FS 
AD77681_NEGATIVE_FS 

◆ ad77681_conv_len

Enumerator
AD77681_CONV_24BIT 
AD77681_CONV_16BIT 

◆ ad77681_conv_mode

Enumerator
AD77681_CONV_CONTINUOUS 
AD77681_CONV_ONE_SHOT 
AD77681_CONV_SINGLE 
AD77681_CONV_PERIODIC 
AD77681_CONV_STANDBY 

◆ ad77681_crc_sel

Enumerator
AD77681_CRC 
AD77681_XOR 
AD77681_NO_CRC 

◆ ad77681_data_read_mode

Enumerator
AD77681_REGISTER_DATA_READ 
AD77681_CONTINUOUS_DATA_READ 

◆ ad77681_filter_type

Enumerator
AD77681_SINC5 
AD77681_SINC5_DECx8 
AD77681_SINC5_DECx16 
AD77681_SINC3 
AD77681_FIR 

◆ ad77681_gobal_gpio_enable

Enumerator
AD77681_GLOBAL_GPIO_ENABLE 
AD77681_GLOBAL_GPIO_DISABLE 

◆ ad77681_gpio_output_type

Enumerator
AD77681_GPIO_STRONG_DRIVER 
AD77681_GPIO_OPEN_DRAIN 

◆ ad77681_gpios

Enumerator
AD77681_GPIO0 
AD77681_GPIO1 
AD77681_GPIO2 
AD77681_GPIO3 
AD77681_ALL_GPIOS 

◆ ad77681_mclk_div

Enumerator
AD77681_MCLK_DIV_16 
AD77681_MCLK_DIV_8 
AD77681_MCLK_DIV_4 
AD77681_MCLK_DIV_2 

◆ ad77681_power_mode

Enumerator
AD77681_ECO 
AD77681_MEDIAN 
AD77681_FAST 

◆ ad77681_rdy_dout

Enumerator
AD77681_RDY_DOUT_EN 
AD77681_RDY_DOUT_DIS 

◆ ad77681_REFn_buffer

Enumerator
AD77681_BUFn_ENABLED 
AD77681_BUFn_DISABLED 
AD77681_BUFn_FULL_BUFFER_ON 

◆ ad77681_REFp_buffer

Enumerator
AD77681_BUFp_ENABLED 
AD77681_BUFp_DISABLED 
AD77681_BUFp_FULL_BUFFER_ON 

◆ ad77681_sinc5_fir_decimate

Enumerator
AD77681_SINC5_FIR_DECx32 
AD77681_SINC5_FIR_DECx64 
AD77681_SINC5_FIR_DECx128 
AD77681_SINC5_FIR_DECx256 
AD77681_SINC5_FIR_DECx512 
AD77681_SINC5_FIR_DECx1024 

◆ ad77681_sleep_wake

Enumerator
AD77681_SLEEP 
AD77681_WAKE 

◆ ad77681_VCM_out

Enumerator
AD77681_VCM_HALF_VCC 
AD77681_VCM_2_5V 
AD77681_VCM_2_05V 
AD77681_VCM_1_9V 
AD77681_VCM_1_65V 
AD77681_VCM_1_1V 
AD77681_VCM_0_9V 
AD77681_VCM_OFF 

Function Documentation

◆ ad77681_apply_gain()

int32_t ad77681_apply_gain ( struct ad77681_dev dev,
uint32_t  value 
)

Write to gain registers

Parameters
dev- The device structure.
value- The desired value of the whole 24-bit gain register
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_apply_offset()

int32_t ad77681_apply_offset ( struct ad77681_dev dev,
uint32_t  value 
)

Write to offset registers

Parameters
devThe device structure.
valueThe desired value of the whole 24-bit offset register
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_clear_error_flags()

int32_t ad77681_clear_error_flags ( struct ad77681_dev dev)

Clear all error flags at once

Parameters
dev- The device structure.
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_compute_crc8()

uint8_t ad77681_compute_crc8 ( uint8_t *  data,
uint8_t  data_size,
uint8_t  init_val 
)

Compute CRC8 checksum.

Parameters
data- The data buffer.
data_size- The size of the data buffer.
init_val- CRC initial value.
Returns
CRC8 checksum.
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◆ ad77681_compute_xor()

uint8_t ad77681_compute_xor ( uint8_t *  data,
uint8_t  data_size,
uint8_t  init_val 
)

Compute XOR checksum.

Parameters
data- The data buffer.
data_size- The size of the data buffer.
init_val- CRC initial value.
Returns
XOR checksum.
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◆ ad77681_CRC_status_handling()

int32_t ad77681_CRC_status_handling ( struct ad77681_dev dev,
uint16_t *  data_buffer 
)

CRC and status bit handling after each readout form the ADC

Parameters
dev- The device structure.
*data_buffer- 16-bit buffer readed from the ADC containing the CRC, data and the stattus bit.
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_data_to_voltage()

int32_t ad77681_data_to_voltage ( struct ad77681_dev dev,
uint32_t *  raw_code,
double *  voltage 
)

Conversion from measured data to voltage

Parameters
dev- The device structure.
raw_code- ADC raw code measurements
voltage- Converted ADC code to voltage
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_error_flags_enabe()

int32_t ad77681_error_flags_enabe ( struct ad77681_dev dev)

Enabling error flags. All error flags enabled by default

Parameters
dev- The device structure.
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_global_gpio()

int32_t ad77681_global_gpio ( struct ad77681_dev dev,
enum ad77681_gobal_gpio_enable  gpio_enable 
)

Enable global GPIO bit. This bit must be set high to change GPIO settings.

Parameters
dev- The device structure.
gpio_enable- Enable or diable the global GPIO pin Accepted values: AD77681_GLOBAL_GPIO_ENABLE AD77681_GLOBAL_GPIO_DISABLE
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_gpio_inout()

int32_t ad77681_gpio_inout ( struct ad77681_dev dev,
uint8_t  direction,
enum ad77681_gpios  gpio_number 
)

Set AD7768-1s GPIO as input or output.

Parameters
dev- The device structure.
direction- Direction of the GPIO Accepted values: GPIO_INPUT GPIO_OUTPUT 4-bit value for all gpios
gpio_number- Number of GPIO, which will be affected Accepted values: AD77681_GPIO0 AD77681_GPIO1 AD77681_GPIO2 AD77681_GPIO3 AD77681_ALL_GPIOS
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_gpio_open_drain()

int32_t ad77681_gpio_open_drain ( struct ad77681_dev dev,
enum ad77681_gpios  gpio_number,
enum ad77681_gpio_output_type  output_type 
)

Set AD7768-1s GPIO output type between strong driver and open drain. GPIO3 can not be accessed!

Parameters
dev- The device structure.
gpio_number- AD7768-1s GPIO to be affected (Only GPIO0, GPIO1 and GPIO2) Accepted values: AD77681_GPIO0 AD77681_GPIO1 AD77681_GPIO2 AD77681_ALL_GPIOS
output_type- Output type of the GPIO Accepted values: AD77681_GPIO_STRONG_DRIVER AD77681_GPIO_OPEN_DRAIN
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_gpio_read()

int32_t ad77681_gpio_read ( struct ad77681_dev dev,
uint8_t *  value,
enum ad77681_gpios  gpio_number 
)

Read value from GPIOs present in AD7768-1 separately, or all GPIOS at once.

Parameters
dev- The device structure.
value- Readed value.
gpio_number- Number of GPIO, the value will be written into Accepted values: AD77681_GPIO0 AD77681_GPIO1 AD77681_GPIO2 AD77681_GPIO3 AD77681_ALL_GPIOS
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_gpio_write()

int32_t ad77681_gpio_write ( struct ad77681_dev dev,
uint8_t  value,
enum ad77681_gpios  gpio_number 
)

Write value to GPIOs present in AD7768-1 separately, or all GPIOS at once.

Parameters
dev- The device structure.
value- Value to be written into GPIO Accepted values: GPIO_HIGH GPIO_LOW 4-bit value for all gpios
gpio_number- Number of GPIO, the value will be written into Accepted values: AD77681_GPIO0 AD77681_GPIO1 AD77681_GPIO2 AD77681_GPIO3 AD77681_ALL_GPIOS
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_initiate_sync()

int32_t ad77681_initiate_sync ( struct ad77681_dev dev)

Initiate a SYNC_OUT pulse over spi

Parameters
dev- The device structure.
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_power_down()

int32_t ad77681_power_down ( struct ad77681_dev dev,
enum ad77681_sleep_wake  sleep_wake 
)

Power down / power up the device

Parameters
dev- The device structure.
sleep_wake- Power down, or power up the ADC Accepted values: AD77681_SLEEP AD77681_WAKE
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_programmable_filter()

int32_t ad77681_programmable_filter ( struct ad77681_dev dev,
const float *  coeffs,
uint8_t  num_coeffs 
)

Upload sequence for Programmamble FIR filter

Parameters
dev- The device structure.
coeffs- Pointer to the desired filter coefficients array to be written
num_coeffs- Count of active filter coeffs
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_scratchpad()

int32_t ad77681_scratchpad ( struct ad77681_dev dev,
uint8_t *  sequence 
)

Read and write from ADC scratchpad register to check SPI Communication in the very beginning, during inicialization.

Parameters
dev- The device structure.
sequence- The sequence which will be written into scratchpad and the readed sequence will be returned
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_50HZ_rejection()

int32_t ad77681_set_50HZ_rejection ( struct ad77681_dev dev,
uint8_t  enable 
)

Enable 50/60 Hz rejection

Parameters
dev- The device structure.
enable- The positive reference buffer selector Accepted values: true false
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_set_AINn_buffer()

int32_t ad77681_set_AINn_buffer ( struct ad77681_dev dev,
enum ad77681_AINn_precharge  AINn 
)

Set the AIN- precharge buffer.

Parameters
dev- The device structure.
AINn- The negative analog input precharge buffer selector Accepted values: AD77681_AINn_ENABLED AD77681_AINn_DISABLED
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_AINp_buffer()

int32_t ad77681_set_AINp_buffer ( struct ad77681_dev dev,
enum ad77681_AINp_precharge  AINp 
)

Set the AIN+ precharge buffer.

Parameters
dev- The device structure.
AINp- The positive analog input precharge buffer selector Accepted values: AD77681_AINp_ENABLED AD77681_AINp_DISABLED
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_continuos_read()

int32_t ad77681_set_continuos_read ( struct ad77681_dev dev,
enum ad77681_continuous_read  continuous_enable 
)

Set the REF- reference buffer

Parameters
dev- The device structure.
continuous_enable- Continous read enable Accepted values: AD77681_CONTINUOUS_READ_ENABLE AD77681_CONTINUOUS_READ_DISABLE
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_set_conv_mode()

int32_t ad77681_set_conv_mode ( struct ad77681_dev dev,
enum ad77681_conv_mode  conv_mode,
enum ad77681_conv_diag_mux  diag_mux_sel,
bool  conv_diag_sel 
)

Conversion mode and source select

Parameters
dev- The device structure.
conv_mode- Sets the conversion mode of the ADC Accepted values: AD77681_CONV_CONTINUOUS AD77681_CONV_ONE_SHOT AD77681_CONV_SINGLE AD77681_CONV_PERIODIC
diag_mux_sel- Selects which signal to route through diagnostic mux Accepted values: AD77681_TEMP_SENSOR AD77681_AIN_SHORT AD77681_POSITIVE_FS AD77681_NEGATIVE_FS
conv_diag_sel- Select the input for conversion as AIN or diagnostic mux Accepted values: true false
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_convlen()

int32_t ad77681_set_convlen ( struct ad77681_dev dev,
enum ad77681_conv_len  conv_len 
)

Set the Conversion Result Output Length.

Parameters
dev- The device structure.
conv_len- The MCLK divider. Accepted values: AD77681_CONV_24BIT AD77681_CONV_16BIT
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_crc_sel()

int32_t ad77681_set_crc_sel ( struct ad77681_dev dev,
enum ad77681_crc_sel  crc_sel 
)

Activates CRC on all SPI transactions and Selects CRC method as XOR or 8-bit polynomial

Parameters
dev- The device structure.
crc_sel- The CRC type. Accepted values: AD77681_CRC AD77681_XOR AD77681_NO_CRC
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_filter_type()

int32_t ad77681_set_filter_type ( struct ad77681_dev dev,
enum ad77681_sinc5_fir_decimate  decimate,
enum ad77681_filter_type  filter,
uint16_t  sinc3_osr 
)

Set filter type and decimation ratio

Parameters
dev- The device structure.
decimate- Decimation ratio of filter Accepted values: AD77681_SINC5_FIR_DECx32 AD77681_SINC5_FIR_DECx64 AD77681_SINC5_FIR_DECx128 AD77681_SINC5_FIR_DECx256 AD77681_SINC5_FIR_DECx512 AD77681_SINC5_FIR_DECx1024
filter- Select filter type Accepted values: AD77681_SINC5 AD77681_SINC5_DECx8 AD77681_SINC5_DECx16 AD77681_SINC3 AD77681_FIR
sinc3_osr- Select decimation ratio for SINC3 filter separately as integer from 0 to 8192. See the AD7768-1 datasheet for more info
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_mclk_div()

int32_t ad77681_set_mclk_div ( struct ad77681_dev dev,
enum ad77681_mclk_div  clk_div 
)

Set the MCLK divider.

Parameters
dev- The device structure.
clk_div- The MCLK divider. Accepted values: AD77681_MCLK_DIV_16 AD77681_MCLK_DIV_8 AD77681_MCLK_DIV_4 AD77681_MCLK_DIV_2
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_power_mode()

int32_t ad77681_set_power_mode ( struct ad77681_dev dev,
enum ad77681_power_mode  mode 
)

Set the power consumption mode of the ADC core.

Parameters
dev- The device structure.
mode- The power mode. Accepted values: AD77681_ECO AD77681_MEDIAN AD77681_FAST
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_REFn_buffer()

int32_t ad77681_set_REFn_buffer ( struct ad77681_dev dev,
enum ad77681_REFn_buffer  REFn 
)

Set the REF- reference buffer

Parameters
dev- The device structure.
REFn- The negative reference buffer selector Accepted values: AD77681_BUFn_DISABLED AD77681_BUFn_ENABLED AD77681_BUFn_FULL_BUFFER_ON
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_REFp_buffer()

int32_t ad77681_set_REFp_buffer ( struct ad77681_dev dev,
enum ad77681_REFp_buffer  REFp 
)

Set the REF+ reference buffer

Parameters
dev- The device structure.
REFp- The positive reference buffer selector Accepted values: AD77681_BUFp_DISABLED AD77681_BUFp_ENABLED AD77681_BUFp_FULL_BUFFER_ON
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_status_bit()

int32_t ad77681_set_status_bit ( struct ad77681_dev dev,
bool  status_bit 
)

Enables Status bits output

Parameters
dev- The device structure.
status_bit- enable or disable status bit Accepted values: true false
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_set_VCM_output()

int32_t ad77681_set_VCM_output ( struct ad77681_dev dev,
enum ad77681_VCM_out  VCM_out 
)

Set the VCM output.

Parameters
dev- The device structure.
VCM_out- The VCM output voltage. Accepted values: AD77681_VCM_HALF_VCC AD77681_VCM_2_5V AD77681_VCM_2_05V AD77681_VCM_1_9V AD77681_VCM_1_65V AD77681_VCM_1_1V AD77681_VCM_0_9V AD77681_VCM_OFF
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_setup()

int32_t ad77681_setup ( struct ad77681_dev **  device,
struct ad77681_init_param  init_param,
struct ad77681_status_registers **  status 
)

Initialize the device.

Parameters
device- The device structure.
init_param- The structure that contains the device initial parameters.
status- The structure that will contains the ADC status
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_SINC3_ODR()

int32_t ad77681_SINC3_ODR ( struct ad77681_dev dev,
uint16_t *  sinc3_dec_reg,
float  sinc3_odr 
)

Get SINC3 filter oversampling ratio register value based on user's inserted output data rate ODR

Parameters
dev- The device structure.
sinc3_dec_reg- Returned closest value of SINC3 register
sinc3_odr- Desired output data rage
Returns
0 in case of success, negative error code otherwise.

◆ ad77681_soft_reset()

int32_t ad77681_soft_reset ( struct ad77681_dev dev)

Device reset over SPI.

Parameters
dev- The device structure.
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_spi_read_adc_data()

int32_t ad77681_spi_read_adc_data ( struct ad77681_dev dev,
uint8_t *  adc_data,
enum ad77681_data_read_mode  mode 
)

Read conversion result from device.

Parameters
dev- The device structure.
adc_data- The conversion result data
mode- Data read mode Accepted values: AD77681_REGISTER_DATA_READ AD77681_CONTINUOUS_DATA_READ
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_spi_read_mask()

int32_t ad77681_spi_read_mask ( struct ad77681_dev dev,
uint8_t  reg_addr,
uint8_t  mask,
uint8_t *  data 
)

SPI read from device using a mask.

Parameters
dev- The device structure.
reg_addr- The register address.
mask- The mask.
data- The register data.
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_spi_reg_read()

int32_t ad77681_spi_reg_read ( struct ad77681_dev dev,
uint8_t  reg_addr,
uint8_t *  reg_data 
)

Read from device.

Parameters
dev- The device structure.
reg_addr- The register address.
reg_data- The register data.
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_spi_reg_write()

int32_t ad77681_spi_reg_write ( struct ad77681_dev dev,
uint8_t  reg_addr,
uint8_t  reg_data 
)

Write to device.

Parameters
dev- The device structure.
reg_addr- The register address.
reg_data- The register data.
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_spi_write_mask()

int32_t ad77681_spi_write_mask ( struct ad77681_dev dev,
uint8_t  reg_addr,
uint8_t  mask,
uint8_t  data 
)

SPI write to device using a mask.

Parameters
dev- The device structure.
reg_addr- The register address.
mask- The mask.
data- The register data.
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_status()

int32_t ad77681_status ( struct ad77681_dev dev,
struct ad77681_status_registers status 
)

Read from all ADC status registers

Parameters
dev- The device structure.
status- Structure with all satuts bits
Returns
0 in case of success, negative error code otherwise.
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◆ ad77681_update_sample_rate()

int32_t ad77681_update_sample_rate ( struct ad77681_dev dev)

Update ADCs sample rate depending on MCLK, MCLK_DIV and filter settings

Parameters
dev- The device structure.
Returns
0 in case of success, negative error code otherwise.
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