no-OS
ad77681.h
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1 /***************************************************************************/
40 #ifndef SRC_AD77681_H_
41 #define SRC_AD77681_H_
42 
43 #include "no_os_spi.h"
44 
45 /******************************************************************************/
46 /********************** Macros and Constants Definitions **********************/
47 /******************************************************************************/
48 #define AD77681_REG_CHIP_TYPE 0x3
49 #define AD77681_REG_PROD_ID_L 0x4
50 #define AD77681_REG_PROD_ID_H 0x5
51 #define AD77681_REG_CHIP_GRADE 0x6
52 #define AD77681_REG_SCRATCH_PAD 0x0A
53 #define AD77681_REG_VENDOR_L 0x0C
54 #define AD77681_REG_VENDOR_H 0x0D
55 #define AD77681_REG_INTERFACE_FORMAT 0x14
56 #define AD77681_REG_POWER_CLOCK 0x15
57 #define AD77681_REG_ANALOG 0x16
58 #define AD77681_REG_ANALOG2 0x17
59 #define AD77681_REG_CONVERSION 0x18
60 #define AD77681_REG_DIGITAL_FILTER 0x19
61 #define AD77681_REG_SINC3_DEC_RATE_MSB 0x1A
62 #define AD77681_REG_SINC3_DEC_RATE_LSB 0x1B
63 #define AD77681_REG_DUTY_CYCLE_RATIO 0x1C
64 #define AD77681_REG_SYNC_RESET 0x1D
65 #define AD77681_REG_GPIO_CONTROL 0x1E
66 #define AD77681_REG_GPIO_WRITE 0x1F
67 #define AD77681_REG_GPIO_READ 0x20
68 #define AD77681_REG_OFFSET_HI 0x21
69 #define AD77681_REG_OFFSET_MID 0x22
70 #define AD77681_REG_OFFSET_LO 0x23
71 #define AD77681_REG_GAIN_HI 0x24
72 #define AD77681_REG_GAIN_MID 0x25
73 #define AD77681_REG_GAIN_LO 0x26
74 #define AD77681_REG_SPI_DIAG_ENABLE 0x28
75 #define AD77681_REG_ADC_DIAG_ENABLE 0x29
76 #define AD77681_REG_DIG_DIAG_ENABLE 0x2A
77 #define AD77681_REG_ADC_DATA 0x2C
78 #define AD77681_REG_MASTER_STATUS 0x2D
79 #define AD77681_REG_SPI_DIAG_STATUS 0x2E
80 #define AD77681_REG_ADC_DIAG_STATUS 0x2F
81 #define AD77681_REG_DIG_DIAG_STATUS 0x30
82 #define AD77681_REG_MCLK_COUNTER 0x31
83 
84 /* AD77681_REG_INTERFACE_FORMAT */
85 #define AD77681_INTERFACE_CRC_EN_MSK (0x1 << 6)
86 #define AD77681_INTERFACE_CRC_EN(x) (((x) & 0x1) << 6)
87 #define AD77681_INTERFACE_CRC_TYPE_MSK (0x1 << 5)
88 #define AD77681_INTERFACE_CRC_TYPE(x) (((x) & 0x1) << 5)
89 #define AD77681_INTERFACE_STATUS_EN_MSK (0x1 << 4)
90 #define AD77681_INTERFACE_STATUS_EN(x) (((x) & 0x1) << 4)
91 #define AD77681_INTERFACE_CONVLEN_MSK (0x1 << 3)
92 #define AD77681_INTERFACE_CONVLEN(x) (((x) & 0x1) << 3)
93 #define AD77681_INTERFACE_RDY_EN_MSK (0x1 << 2)
94 #define AD77681_INTERFACE_RDY_EN(x) (((x) & 0x1) << 3)
95 #define AD77681_INTERFACE_CONT_READ_MSK (0x1 << 0)
96 #define AD77681_INTERFACE_CONT_READ_EN(x) (((x) & 0x1) << 0)
97 #define AD77681_REG_COEFF_CONTROL 0x32
98 #define AD77681_REG_COEFF_DATA 0x33
99 #define AD77681_REG_ACCESS_KEY 0x34
100 
101 /* AD77681_REG_SCRATCH_PAD*/
102 #define AD77681_SCRATCHPAD_MSK (0xFF << 0)
103 #define AD77681_SCRATCHPAD(x) (((x) & 0xFF) << 0)
104 
105 /* AD77681_REG_POWER_CLOCK */
106 #define AD77681_POWER_CLK_PWRMODE_MSK 0x3
107 #define AD77681_POWER_CLK_PWRMODE(x) (((x) & 0x3) << 0)
108 #define AD77681_POWER_CLK_MOD_OUT_MSK (0x1 << 2)
109 #define AD77681_POWER_CLK_MOD_OUT(x) (((x) & 0x1) << 2)
110 #define AD77681_POWER_CLK_POWER_DOWN 0x08
111 #define AD77681_POWER_CLK_MCLK_DIV_MSK (0x3 << 4)
112 #define AD77681_POWER_CLK_MCLK_DIV(x) (((x) & 0x3) << 4)
113 #define AD77681_POWER_CLK_CLOCK_SEL_MSK (0x3 << 6)
114 #define AD77681_POWER_CLK_CLOCK_SEL(x) (((x) & 0x3) << 6)
115 
116 /* AD77681_CONVERSION_REG */
117 #define AD77681_CONVERSION_DIAG_MUX_MSK (0xF << 4)
118 #define AD77681_CONVERSION_DIAG_MUX_SEL(x) (((x) & 0xF) << 4)
119 #define AD77681_CONVERSION_DIAG_SEL_MSK (0x1 << 3)
120 #define AD77681_CONVERSION_DIAG_SEL(x) (((x) & 0x1) << 3)
121 #define AD77681_CONVERSION_MODE_MSK (0x7 << 0)
122 #define AD77681_CONVERSION_MODE(x) (((x) & 0x7) << 0)
123 
124 /* AD77681_REG_ANALOG */
125 #define AD77681_ANALOG_REF_BUF_POS_MSK (0x3 << 6)
126 #define AD77681_ANALOG_REF_BUF_POS(x) (((x) & 0x3) << 6)
127 #define AD77681_ANALOG_REF_BUF_NEG_MSK (0x3 << 4)
128 #define AD77681_ANALOG_REF_BUF_NEG(x) (((x) & 0x3) << 4)
129 #define AD77681_ANALOG_AIN_BUF_POS_OFF_MSK (0x1 << 1)
130 #define AD77681_ANALOG_AIN_BUF_POS_OFF(x) (((x) & 0x1) << 1)
131 #define AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK (0x1 << 0)
132 #define AD77681_ANALOG_AIN_BUF_NEG_OFF(x) (((x) & 0x1) << 0)
133 
134 /* AD77681_REG_ANALOG2 */
135 #define AD77681_ANALOG2_VCM_MSK (0x7 << 0)
136 #define AD77681_ANALOG2_VCM(x) (((x) & 0x7) << 0)
137 
138 /* AD77681_REG_DIGITAL_FILTER */
139 #define AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK (0x1 << 7)
140 #define AD77681_DIGI_FILTER_60HZ_REJ_EN(x) (((x) & 0x1) << 7)
141 #define AD77681_DIGI_FILTER_FILTER_MSK (0x7 << 4)
142 #define AD77681_DIGI_FILTER_FILTER(x) (((x) & 0x7) << 4)
143 #define AD77681_DIGI_FILTER_DEC_RATE_MSK (0x7 << 0)
144 #define AD77681_DIGI_FILTER_DEC_RATE(x) (((x) & 0x7) << 0)
145 
146 /* AD77681_REG_SINC3_DEC_RATE_MSB */
147 #define AD77681_SINC3_DEC_RATE_MSB_MSK (0x0F << 0)
148 #define AD77681_SINC3_DEC_RATE_MSB(x) (((x) & 0x0F) << 0)
149 
150 /* AD77681_REG_SINC3_DEC_RATE_LSB */
151 #define AD77681_SINC3_DEC_RATE_LSB_MSK (0xFF << 0)
152 #define AD77681_SINC3_DEC_RATE_LSB(x) (((x) & 0xFF) << 0)
153 
154 /* AD77681_REG_DUTY_CYCLE_RATIO */
155 #define AD77681_DC_RATIO_IDLE_TIME_MSK (0xFF << 0)
156 #define AD77681_DC_RATIO_IDLE_TIME(x) (((x) & 0xFF) << 0)
157 
158 /* AD77681_REG_SYNC_RESET */
159 #define AD77681_SYNC_RST_SPI_STARTB_MSK (0x1 << 7)
160 #define AD77681_SYNC_RST_SPI_STARTB(x) (((x) & 0x1) << 7)
161 #define AD77681_SYNC_RST_SYNCOUT_EDGE_MSK (0x1 << 6)
162 #define AD77681_SYNC_RST_SYNCOUT_EDGE(x) (((x) & 0x1) << 6)
163 #define AD77681_SYNC_RST_GPIO_START_EN_MSK (0x1 << 3)
164 #define AD77681_SYNC_RST_GPIO_START_EN(x) (((x) & 0x1) << 3)
165 #define AD77681_SYNC_RST_SPI_RESET_MSK (0x3 << 0)
166 #define AD77681_SYNC_RST_SPI_RESET(x) (((x) & 0x3) << 0)
167 
168 /* AD77681_REG_GPIO_CONTROL */
169 #define AD77681_GPIO_CNTRL_UGPIO_EN_MSK (0x1 << 7)
170 #define AD77681_GPIO_CNTRL_UGPIO_EN(x) (((x) & 0x1) << 7)
171 #define AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK (0x1 << 6)
172 #define AD77681_GPIO_CNTRL_GPIO2_OD_EN(x) (((x) & 0x1) << 6)
173 #define AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK (0x1 << 5)
174 #define AD77681_GPIO_CNTRL_GPIO1_OD_EN(x) (((x) & 0x1) << 5)
175 #define AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK (0x1 << 4)
176 #define AD77681_GPIO_CNTRL_GPIO0_OD_EN(x) (((x) & 0x1) << 4)
177 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK (0x7 << 4)
178 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN(x) (((x) & 0x7) << 4)
179 #define AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK (0x1 << 3)
180 #define AD77681_GPIO_CNTRL_GPIO3_OP_EN(x) (((x) & 0x1) << 3)
181 #define AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK (0x1 << 2)
182 #define AD77681_GPIO_CNTRL_GPIO2_OP_EN(x) (((x) & 0x1) << 2)
183 #define AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK (0x1 << 1)
184 #define AD77681_GPIO_CNTRL_GPIO1_OP_EN(x) (((x) & 0x1) << 1)
185 #define AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK (0x1 << 0)
186 #define AD77681_GPIO_CNTRL_GPIO0_OP_EN(x) (((x) & 0x1) << 0)
187 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK (0xF << 0)
188 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN(x) (((x) & 0xF) << 0)
189 
190 /* AD77681_REG_GPIO_WRITE */
191 #define AD77681_GPIO_WRITE_3_MSK (0x1 << 3)
192 #define AD77681_GPIO_WRITE_3(x) (((x) & 0x1) << 3)
193 #define AD77681_GPIO_WRITE_2_MSK (0x1 << 2)
194 #define AD77681_GPIO_WRITE_2(x) (((x) & 0x1) << 2)
195 #define AD77681_GPIO_WRITE_1_MSK (0x1 << 1)
196 #define AD77681_GPIO_WRITE_1(x) (((x) & 0x1) << 1)
197 #define AD77681_GPIO_WRITE_0_MSK (0x1 << 0)
198 #define AD77681_GPIO_WRITE_0(x) (((x) & 0x1) << 0)
199 #define AD77681_GPIO_WRITE_ALL_MSK (0xF << 0)
200 #define AD77681_GPIO_WRITE_ALL(x) (((x) & 0xF))
201 
202 /* AD77681_REG_GPIO_READ */
203 #define AD77681_GPIO_READ_3_MSK (0x1 << 3)
204 #define AD77681_GPIO_READ_2_MSK (0x1 << 2)
205 #define AD77681_GPIO_READ_1_MSK (0x1 << 1)
206 #define AD77681_GPIO_READ_0_MSK (0x1 << 0)
207 #define AD77681_GPIO_READ_ALL_MSK (0xF << 0)
208 
209 /* AD77681_REG_OFFSET_HI */
210 #define AD77681_OFFSET_HI_MSK (0xFF << 0)
211 #define AD77681_OFFSET_HI(x) (((x) & 0xFF) << 0)
212 
213 /* AD77681_REG_OFFSET_MID */
214 #define AD77681_OFFSET_MID_MSK (0xFF << 0)
215 #define AD77681_OFFSET_MID(x) (((x) & 0xFF) << 0)
216 
217 /* AD77681_REG_OFFSET_LO */
218 #define AD77681_OFFSET_LO_MSK (0xFF << 0)
219 #define AD77681_OFFSET_LO(x) (((x) & 0xFF) << 0)
220 
221 /* AD77681_REG_GAIN_HI */
222 #define AD77681_GAIN_HI_MSK (0xFF << 0)
223 #define AD77681_GAIN_HI(x) (((x) & 0xFF) << 0)
224 
225 /* AD77681_REG_GAIN_MID */
226 #define AD77681_GAIN_MID_MSK (0xFF << 0)
227 #define AD77681_GAIN_MID(x) (((x) & 0xFF) << 0)
228 
229 /* AD77681_REG_GAIN_HI */
230 #define AD77681_GAIN_LOW_MSK (0xFF << 0)
231 #define AD77681_GAIN_LOW(x) (((x) & 0xFF) << 0)
232 
233 /* AD77681_REG_SPI_DIAG_ENABLE */
234 #define AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK (0x1 << 4)
235 #define AD77681_SPI_DIAG_ERR_SPI_IGNORE(x) (((x) & 0x1) << 4)
236 #define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK (0x1 << 3)
237 #define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT(x) (((x) & 0x1) << 3)
238 #define AD77681_SPI_DIAG_ERR_SPI_RD_MSK (0x1 << 2)
239 #define AD77681_SPI_DIAG_ERR_SPI_RD(x) (((x) & 0x1) << 2)
240 #define AD77681_SPI_DIAG_ERR_SPI_WR_MSK (0x1 << 1)
241 #define AD77681_SPI_DIAG_ERR_SPI_WR(x) (((x) & 0x1) << 1)
242 
243 /* AD77681_REG_ADC_DIAG_ENABLE */
244 #define AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK (0x1 << 5)
245 #define AD77681_ADC_DIAG_ERR_DLDO_PSM(x) (((x) & 0x1) << 5)
246 #define AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK (0x1 << 4)
247 #define AD77681_ADC_DIAG_ERR_ALDO_PSM(x) (((x) & 0x1) << 4)
248 #define AD77681_ADC_DIAG_ERR_FILT_SAT_MSK (0x1 << 2)
249 #define AD77681_ADC_DIAG_ERR_FILT_SAT(x) (((x) & 0x1) << 2)
250 #define AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK (0x1 << 1)
251 #define AD77681_ADC_DIAG_ERR_FILT_NOT_SET(x) (((x) & 0x1) << 1)
252 #define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK (0x1 << 0)
253 #define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL(x) (((x) & 0x1) << 0)
254 
255 /* AD77681_REG_DIG_DIAG_ENABLE */
256 #define AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK (0x1 << 4)
257 #define AD77681_DIG_DIAG_ERR_MEMMAP_CRC(x) (((x) & 0x1) << 4)
258 #define AD77681_DIG_DIAG_ERR_RAM_CRC_MSK (0x1 << 3)
259 #define AD77681_DIG_DIAG_ERR_RAM_CRC(x) (((x) & 0x1) << 3)
260 #define AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK (0x1 << 2)
261 #define AD77681_DIG_DIAG_ERR_FUSE_CRC(x) (((x) & 0x1) << 2)
262 #define AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK (0x1 << 0)
263 #define AD77681_DIG_DIAG_FREQ_COUNT_EN(x) (((x) & 0x1) << 0)
264 
265 /* AD77681_REG_MASTER_STATUS */
266 #define AD77681_MASTER_ERROR_MSK (0x1 << 7)
267 #define AD77681_MASTER_ADC_ERROR_MSK (0x1 << 6)
268 #define AD77681_MASTER_DIG_ERROR_MSK (0x1 << 5)
269 #define AD77681_MASTER_DIG_ERR_EXT_CLK_MSK (0x1 << 4)
270 #define AD77681_MASTER_FILT_SAT_MSK (0x1 << 3)
271 #define AD77681_MASTER_FILT_NOT_SET_MSK (0x1 << 2)
272 #define AD77681_MASTER_SPI_ERROR_MSK (0x1 << 1)
273 #define AD77681_MASTER_POR_FLAG_MSK (0x1 << 0)
274 
275 /* AD77681_REG_SPI_DIAG_STATUS */
276 #define AD77681_SPI_IGNORE_ERROR_MSK (0x1 << 4)
277 #define AD77681_SPI_IGNORE_ERROR_CLR(x) (((x) & 0x1) << 4)
278 #define AD77681_SPI_CLK_CNT_ERROR_MSK (0x1 << 3)
279 #define AD77681_SPI_READ_ERROR_MSK (0x1 << 2)
280 #define AD77681_SPI_READ_ERROR_CLR(x) (((x) & 0x1) << 2)
281 #define AD77681_SPI_WRITE_ERROR_MSK (0x1 << 1)
282 #define AD77681_SPI_WRITE_ERROR_CLR(x) (((x) & 0x1) << 1)
283 #define AD77681_SPI_CRC_ERROR_MSK (0x1 << 0)
284 #define AD77681_SPI_CRC_ERROR_CLR(x) (((x) & 0x1) << 0)
285 
286 /* AD77681_REG_ADC_DIAG_STATUS */
287 #define AD77681_ADC_DLDO_PSM_ERROR_MSK (0x1 << 5)
288 #define AD77681_ADC_ALDO_PSM_ERROR_MSK (0x1 << 4)
289 #define AD77681_ADC_REF_DET_ERROR_MSK (0x1 << 3)
290 #define AD77681_ADC_FILT_SAT_MSK (0x1 << 2)
291 #define AD77681_ADC_FILT_NOT_SET_MSK (0x1 << 1)
292 #define AD77681_ADC_DIG_ERR_EXT_CLK_MSK (0x1 << 0)
293 
294 /* AD77681_REG_DIG_DIAG_STATUS */
295 #define AD77681_DIG_MEMMAP_CRC_ERROR_MSK (0x1 << 4)
296 #define AD77681_DIG_RAM_CRC_ERROR_MSK (0x1 << 3)
297 #define AD77681_DIG_FUS_CRC_ERROR_MSK (0x1 << 2)
298 
299 /* AD77681_REG_MCLK_COUNTER */
300 #define AD77681_MCLK_COUNTER_MSK (0xFF << 0)
301 #define AD77681_MCLK_COUNTER(x) (((x) & 0xFF) << 0)
302 
303 /* AD77681_REG_COEFF_CONTROL */
304 #define AD77681_COEF_CONTROL_COEFFACCESSEN_MSK (0x1 << 7)
305 #define AD77681_COEF_CONTROL_COEFFACCESSEN(x) (((x) & 0x1) << 7)
306 #define AD77681_COEF_CONTROL_COEFFWRITEEN_MSK (0x1 << 6)
307 #define AD77681_COEF_CONTROL_COEFFWRITEEN(x) (((x) & 0x1) << 6)
308 #define AD77681_COEF_CONTROL_COEFFADDR_MSK (0x3F << 5)
309 #define AD77681_COEF_CONTROL_COEFFADDR(x) (((x) & 0x3F) << 5)
310 
311 /* AD77681_REG_COEFF_DATA */
312 #define AD77681_COEFF_DATA_USERCOEFFEN_MSK (0x1 << 23)
313 #define AD77681_COEFF_DATA_USERCOEFFEN(x) (((x) & 0x1) << 23)
314 #define AD77681_COEFF_DATA_COEFFDATA_MSK (0x7FFFFF << 22)
315 #define AD77681_COEFF_DATA_COEFFDATA(x) (((x) & 0x7FFFFF) << 22)
316 
317 /* AD77681_REG_ACCESS_KEY */
318 #define AD77681_ACCESS_KEY_MSK (0xFF << 0)
319 #define AD77681_ACCESS_KEY(x) (((x) & 0xFF) << 0)
320 #define AD77681_ACCESS_KEY_CHECK_MSK (0x1 << 0)
321 
322 #define AD77681_REG_READ(x) ( (1 << 6) | (x & 0xFF) ) // Read from register x
323 #define AD77681_REG_WRITE(x) ( (~(1 << 6)) & (x & 0xFF) ) // Write to register x
324 
325 /* 8-bits wide checksum generated using the polynomial */
326 #define AD77681_CRC8_POLY 0x07 // x^8 + x^2 + x^1 + x^0
327 
328 /* Initial CRC for continuous read mode */
329 #define INITIAL_CRC_CRC8 0x03
330 #define INITIAL_CRC_XOR 0x6C
331 #define INITIAL_CRC 0x00
332 
333 #define CRC_DEBUG
334 
335 /* AD7768-1 */
336 /* A special key for exit the contiuous read mode, taken from the AD7768-1 datasheet */
337 #define EXIT_CONT_READ 0x6C
338 /* Bit resolution of the AD7768-1 */
339 #define AD7768_N_BITS 24
340 /* Full scale of the AD7768-1 = 2^24 = 16777216 */
341 #define AD7768_FULL_SCALE (1 << AD7768_N_BITS)
342 /* Half scale of the AD7768-1 = 2^23 = 8388608 */
343 #define AD7768_HALF_SCALE (1 << (AD7768_N_BITS - 1))
344 
345 #define ENABLE 1
346 #define DISABLE 0
347 
348 /*****************************************************************************/
349 /*************************** Types Declarations *******************************/
350 /******************************************************************************/
355 };
356 
362 };
363 
370 };
371 
375 };
376 
380 };
381 
387 };
388 
393 };
394 
395 /* Filter tye FIR, SINC3, SINC5 */
402 };
403 
404 /* Dectimation ratios for SINC5 and FIR */
412 };
413 
414 /* Sleep / Power up */
418 };
419 
420 /* Reset option */
424 };
425 /* AIN- precharge */
429 };
430 
431 /* AIN+ precharge */
435 };
436 
437 /* REF- buffer */
442 };
443 
444 /* REF+ buffer */
449 };
450 
451 /* VCM output voltage */
461 };
462 
463 /* Global GPIO enable/disable */
467 };
468 
469 /* ADCs GPIO numbering */
476 };
477 
481 };
482 
483 /* Continuous ADC read */
487 };
488 
489 /* ADC data read mode */
493 };
494 
495 /* ADC data structure */
496 struct adc_data {
497  bool finish;
498  uint16_t count;
499  uint16_t samples;
500  uint32_t raw_data[4096];
501 };
502 /* ADC status registers structure */
505  bool adc_error;
506  bool dig_error;
510  bool spi_error;
511  bool por_flag;
526 };
527 
528 struct ad77681_dev {
529  /* SPI */
531  /* Configuration */
539  uint8_t status_bit;
547  uint16_t sinc3_osr;
548  uint16_t vref; /* Reference voltage*/
549  uint16_t mclk; /* Mater clock*/
550  uint32_t sample_rate; /* Sample rate*/
551  uint8_t data_frame_byte; /* SPI 8bit frames*/
552 };
553 
555  /* SPI */
557  /* Configuration */
565  uint8_t status_bit;
573  uint16_t sinc3_osr;
574  uint16_t vref;
575  uint16_t mclk;
576  uint32_t sample_rate;
578 };
579 
580 /******************************************************************************/
581 /************************ Functions Declarations ******************************/
582 /******************************************************************************/
583 uint8_t ad77681_compute_crc8(uint8_t *data,
584  uint8_t data_size,
585  uint8_t init_val);
586 uint8_t ad77681_compute_xor(uint8_t *data,
587  uint8_t data_size,
588  uint8_t init_val);
589 int32_t ad77681_setup(struct ad77681_dev **device,
591  struct ad77681_status_registers **status);
592 int32_t ad77681_spi_reg_read(struct ad77681_dev *dev,
593  uint8_t reg_addr,
594  uint8_t *reg_data);
595 int32_t ad77681_spi_read_mask(struct ad77681_dev *dev,
596  uint8_t reg_addr,
597  uint8_t mask,
598  uint8_t *data);
599 int32_t ad77681_spi_reg_write(struct ad77681_dev *dev,
600  uint8_t reg_addr,
601  uint8_t reg_data);
602 int32_t ad77681_spi_write_mask(struct ad77681_dev *dev,
603  uint8_t reg_addr,
604  uint8_t mask,
605  uint8_t data);
606 int32_t ad77681_set_power_mode(struct ad77681_dev *dev,
607  enum ad77681_power_mode mode);
608 int32_t ad77681_set_mclk_div(struct ad77681_dev *dev,
609  enum ad77681_mclk_div clk_div);
610 int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev,
611  uint8_t *adc_data,
613 int32_t ad77681_set_conv_mode(struct ad77681_dev *dev,
614  enum ad77681_conv_mode conv_mode,
615  enum ad77681_conv_diag_mux diag_mux_sel,
616  bool conv_diag_sel);
617 int32_t ad77681_set_convlen(struct ad77681_dev *dev,
618  enum ad77681_conv_len conv_len);
619 int32_t ad77681_soft_reset(struct ad77681_dev *dev);
620 int32_t ad77681_initiate_sync(struct ad77681_dev *dev);
621 int32_t ad77681_programmable_filter(struct ad77681_dev *dev,
622  const float *coeffs,
623  uint8_t num_coeffs);
624 int32_t ad77681_gpio_read(struct ad77681_dev *dev,
625  uint8_t *value,
626  enum ad77681_gpios gpio_number);
627 int32_t ad77681_apply_offset(struct ad77681_dev *dev,
628  uint32_t value);
629 int32_t ad77681_apply_gain(struct ad77681_dev *dev,
630  uint32_t value);
631 int32_t ad77681_set_crc_sel(struct ad77681_dev *dev,
632  enum ad77681_crc_sel crc_sel);
633 int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev,
634  enum ad77681_gpios gpio_number,
635  enum ad77681_gpio_output_type output_type);
636 int32_t ad77681_set_continuos_read(struct ad77681_dev *dev,
637  enum ad77681_continuous_read continuous_enable);
638 int32_t ad77681_clear_error_flags(struct ad77681_dev *dev);
639 int32_t ad77681_data_to_voltage(struct ad77681_dev *dev,
640  uint32_t *raw_code,
641  double *voltage);
642 int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev,
643  uint16_t *data_buffer);
644 int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev,
645  enum ad77681_AINn_precharge AINn);
646 int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev,
647  enum ad77681_AINp_precharge AINp);
648 int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev,
649  enum ad77681_REFn_buffer REFn);
650 int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev,
651  enum ad77681_REFp_buffer REFp);
652 int32_t ad77681_set_filter_type(struct ad77681_dev *dev,
653  enum ad77681_sinc5_fir_decimate decimate,
654  enum ad77681_filter_type filter,
655  uint16_t sinc3_osr);
656 int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev,
657  uint8_t enable);
658 int32_t ad77681_power_down(struct ad77681_dev *dev,
659  enum ad77681_sleep_wake sleep_wake);
660 int32_t ad77681_set_status_bit(struct ad77681_dev *dev,
661  bool status_bit);
662 int32_t ad77681_set_VCM_output(struct ad77681_dev *dev,
663  enum ad77681_VCM_out VCM_out);
664 int32_t ad77681_gpio_write(struct ad77681_dev *dev,
665  uint8_t value,
666  enum ad77681_gpios gpio_number);
667 int32_t ad77681_gpio_inout(struct ad77681_dev *dev,
668  uint8_t direction,
669  enum ad77681_gpios gpio_number);
670 int32_t ad77681_global_gpio(struct ad77681_dev *devices,
671  enum ad77681_gobal_gpio_enable gpio_enable);
672 int32_t ad77681_scratchpad(struct ad77681_dev *dev,
673  uint8_t *sequence);
674 int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev);
675 int32_t ad77681_update_sample_rate(struct ad77681_dev *dev);
676 int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev,
677  uint16_t *sinc3_dec_reg,
678  float sinc3_odr);
679 int32_t ad77681_status(struct ad77681_dev *dev,
680  struct ad77681_status_registers *status);
681 #endif /* SRC_AD77681_H_ */
AD77681_SCRATCHPAD_MSK
#define AD77681_SCRATCHPAD_MSK
Definition: ad77681.h:102
AD77681_FIR
@ AD77681_FIR
Definition: ad77681.h:401
ad77681_data_to_voltage
int32_t ad77681_data_to_voltage(struct ad77681_dev *dev, uint32_t *raw_code, double *voltage)
Definition: ad77681.c:411
ad77681_clear_error_flags
int32_t ad77681_clear_error_flags(struct ad77681_dev *dev)
Definition: ad77681.c:1586
AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK
#define AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK
Definition: ad77681.h:256
adc_data
Definition: ad77681.h:496
AD77681_GAIN_MID
#define AD77681_GAIN_MID(x)
Definition: ad77681.h:227
ad77681_dev
Definition: ad77681.h:528
ad77681_status_registers::adc_filt_not_settled
bool adc_filt_not_settled
Definition: ad77681.h:509
AD77681_GPIO_WRITE_ALL_MSK
#define AD77681_GPIO_WRITE_ALL_MSK
Definition: ad77681.h:199
AD77681_ANALOG_REF_BUF_NEG_MSK
#define AD77681_ANALOG_REF_BUF_NEG_MSK
Definition: ad77681.h:127
AD77681_GLOBAL_GPIO_DISABLE
@ AD77681_GLOBAL_GPIO_DISABLE
Definition: ad77681.h:466
AD7768_FULL_SCALE
#define AD7768_FULL_SCALE
Definition: ad77681.h:341
AD77681_REG_COEFF_DATA
#define AD77681_REG_COEFF_DATA
Definition: ad77681.h:98
AD77681_GPIO_WRITE_2_MSK
#define AD77681_GPIO_WRITE_2_MSK
Definition: ad77681.h:193
AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK
#define AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK
Definition: ad77681.h:262
AD77681_REG_DIG_DIAG_STATUS
#define AD77681_REG_DIG_DIAG_STATUS
Definition: ad77681.h:81
ad77681_initiate_sync
int32_t ad77681_initiate_sync(struct ad77681_dev *dev)
Definition: ad77681.c:1062
ad77681_gpio_write
int32_t ad77681_gpio_write(struct ad77681_dev *dev, uint8_t value, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1376
ad77681_error_flags_enabe
int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev)
Definition: ad77681.c:1619
ad77681_setup
int32_t ad77681_setup(struct ad77681_dev **device, struct ad77681_init_param init_param, struct ad77681_status_registers **status)
Definition: ad77681.c:1751
AD77681_SOFT_RESET
@ AD77681_SOFT_RESET
Definition: ad77681.h:422
AD77681_GPIO_CNTRL_GPIO2_OP_EN
#define AD77681_GPIO_CNTRL_GPIO2_OP_EN(x)
Definition: ad77681.h:182
AD77681_MASTER_FILT_NOT_SET_MSK
#define AD77681_MASTER_FILT_NOT_SET_MSK
Definition: ad77681.h:271
ad77681_status_registers::fuse_crc_error
bool fuse_crc_error
Definition: ad77681.h:525
ad77681_power_down
int32_t ad77681_power_down(struct ad77681_dev *dev, enum ad77681_sleep_wake sleep_wake)
Definition: ad77681.c:871
AD77681_MASTER_ERROR_MSK
#define AD77681_MASTER_ERROR_MSK
Definition: ad77681.h:266
ad77681_spi_reg_write
int32_t ad77681_spi_reg_write(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t reg_data)
Definition: ad77681.c:162
AD77681_MASTER_POR_FLAG_MSK
#define AD77681_MASTER_POR_FLAG_MSK
Definition: ad77681.h:273
AD77681_ACCESS_KEY_CHECK_MSK
#define AD77681_ACCESS_KEY_CHECK_MSK
Definition: ad77681.h:320
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:83
AD77681_CONVERSION_DIAG_SEL
#define AD77681_CONVERSION_DIAG_SEL(x)
Definition: ad77681.h:120
ad77681_initiate_sync
int32_t ad77681_initiate_sync(struct ad77681_dev *dev)
Definition: ad77681.c:1062
AD77681_SYNC_RST_SPI_STARTB
#define AD77681_SYNC_RST_SPI_STARTB(x)
Definition: ad77681.h:160
ad77681_status_registers::spi_ignore
bool spi_ignore
Definition: ad77681.h:512
AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK
Definition: ad77681.h:187
AD77681_OFFSET_MID_MSK
#define AD77681_OFFSET_MID_MSK
Definition: ad77681.h:214
ad77681_status_registers
Definition: ad77681.h:503
ad77681_setup
int32_t ad77681_setup(struct ad77681_dev **device, struct ad77681_init_param init_param, struct ad77681_status_registers **status)
Definition: ad77681.c:1751
ad77681_set_crc_sel
int32_t ad77681_set_crc_sel(struct ad77681_dev *dev, enum ad77681_crc_sel crc_sel)
Definition: ad77681.c:977
ad77681_spi_read_adc_data
int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev, uint8_t *adc_data, enum ad77681_data_read_mode mode)
Definition: ad77681.c:279
AD77681_BUFn_FULL_BUFFER_ON
@ AD77681_BUFn_FULL_BUFFER_ON
Definition: ad77681.h:441
AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK
#define AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK
Definition: ad77681.h:181
no_os_spi.h
Header file of SPI Interface.
AD77681_OFFSET_LO_MSK
#define AD77681_OFFSET_LO_MSK
Definition: ad77681.h:218
AD77681_TEMP_SENSOR
@ AD77681_TEMP_SENSOR
Definition: ad77681.h:383
AD77681_GAIN_LOW_MSK
#define AD77681_GAIN_LOW_MSK
Definition: ad77681.h:230
ad77681_filter_type
ad77681_filter_type
Definition: ad77681.h:396
AD77681_AINn_DISABLED
@ AD77681_AINn_DISABLED
Definition: ad77681.h:428
ad77681_data_to_voltage
int32_t ad77681_data_to_voltage(struct ad77681_dev *dev, uint32_t *raw_code, double *voltage)
Definition: ad77681.c:411
AD77681_DIG_DIAG_ERR_MEMMAP_CRC
#define AD77681_DIG_DIAG_ERR_MEMMAP_CRC(x)
Definition: ad77681.h:257
AD77681_GPIO_READ_0_MSK
#define AD77681_GPIO_READ_0_MSK
Definition: ad77681.h:206
AD77681_REG_ADC_DIAG_STATUS
#define AD77681_REG_ADC_DIAG_STATUS
Definition: ad77681.h:80
AD77681_GPIO_WRITE_1
#define AD77681_GPIO_WRITE_1(x)
Definition: ad77681.h:196
ad77681_scratchpad
int32_t ad77681_scratchpad(struct ad77681_dev *dev, uint8_t *sequence)
Definition: ad77681.c:1505
AD77681_REG_GAIN_LO
#define AD77681_REG_GAIN_LO
Definition: ad77681.h:73
AD77681_CONTINUOUS_READ_DISABLE
@ AD77681_CONTINUOUS_READ_DISABLE
Definition: ad77681.h:486
AD77681_REG_GAIN_MID
#define AD77681_REG_GAIN_MID
Definition: ad77681.h:72
AD77681_SINC3
@ AD77681_SINC3
Definition: ad77681.h:400
AD77681_SPI_DIAG_ERR_SPI_IGNORE
#define AD77681_SPI_DIAG_ERR_SPI_IGNORE(x)
Definition: ad77681.h:235
AD77681_SINC5_FIR_DECx512
@ AD77681_SINC5_FIR_DECx512
Definition: ad77681.h:410
AD77681_GPIO_CNTRL_GPIO0_OD_EN
#define AD77681_GPIO_CNTRL_GPIO0_OD_EN(x)
Definition: ad77681.h:176
AD77681_DIG_DIAG_FREQ_COUNT_EN
#define AD77681_DIG_DIAG_FREQ_COUNT_EN(x)
Definition: ad77681.h:263
AD77681_BUFp_DISABLED
@ AD77681_BUFp_DISABLED
Definition: ad77681.h:447
AD77681_REG_GPIO_WRITE
#define AD77681_REG_GPIO_WRITE
Definition: ad77681.h:66
AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL
#define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL(x)
Definition: ad77681.h:253
AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK
#define AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK
Definition: ad77681.h:234
ad77681_set_REFn_buffer
int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev, enum ad77681_REFn_buffer REFn)
Definition: ad77681.c:691
AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK
#define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK
Definition: ad77681.h:252
AD77681_FAST
@ AD77681_FAST
Definition: ad77681.h:354
ad77681_dev::crc_sel
enum ad77681_crc_sel crc_sel
Definition: ad77681.h:538
AD77681_DIGI_FILTER_FILTER_MSK
#define AD77681_DIGI_FILTER_FILTER_MSK
Definition: ad77681.h:141
AD77681_GPIO_WRITE_3
#define AD77681_GPIO_WRITE_3(x)
Definition: ad77681.h:192
ad77681_spi_reg_read
int32_t ad77681_spi_reg_read(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t *reg_data)
Definition: ad77681.c:112
ad77681_set_REFp_buffer
int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev, enum ad77681_REFp_buffer REFp)
Definition: ad77681.c:716
ad77681_sinc5_fir_decimate
ad77681_sinc5_fir_decimate
Definition: ad77681.h:405
no_os_delay.h
Header file of Delay functions.
ad77681_CRC_status_handling
int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev, uint16_t *data_buffer)
Definition: ad77681.c:337
AD77681_MASTER_DIG_ERROR_MSK
#define AD77681_MASTER_DIG_ERROR_MSK
Definition: ad77681.h:268
ad77681_AINp_precharge
ad77681_AINp_precharge
Definition: ad77681.h:432
ad77681_init_param::conv_mode
enum ad77681_conv_mode conv_mode
Definition: ad77681.h:560
AD77681_BUFn_ENABLED
@ AD77681_BUFn_ENABLED
Definition: ad77681.h:439
ad77681_error_flags_enabe
int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev)
Definition: ad77681.c:1619
AD77681_REG_COEFF_CONTROL
#define AD77681_REG_COEFF_CONTROL
Definition: ad77681.h:97
AD77681_ANALOG_REF_BUF_NEG
#define AD77681_ANALOG_REF_BUF_NEG(x)
Definition: ad77681.h:128
AD77681_CONVERSION_MODE
#define AD77681_CONVERSION_MODE(x)
Definition: ad77681.h:122
AD77681_OFFSET_HI_MSK
#define AD77681_OFFSET_HI_MSK
Definition: ad77681.h:210
AD77681_DIGI_FILTER_60HZ_REJ_EN
#define AD77681_DIGI_FILTER_60HZ_REJ_EN(x)
Definition: ad77681.h:140
ad77681_status_registers::adc_err_ext_clk_qual
bool adc_err_ext_clk_qual
Definition: ad77681.h:507
AD77681_AINp_DISABLED
@ AD77681_AINp_DISABLED
Definition: ad77681.h:434
AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK
#define AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK
Definition: ad77681.h:244
ad77681_set_REFn_buffer
int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev, enum ad77681_REFn_buffer REFn)
Definition: ad77681.c:691
AD77681_GPIO1
@ AD77681_GPIO1
Definition: ad77681.h:472
AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK
#define AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK
Definition: ad77681.h:260
AD77681_SYNC_RST_SPI_RESET_MSK
#define AD77681_SYNC_RST_SPI_RESET_MSK
Definition: ad77681.h:165
no_os_spi_init_param::mode
enum no_os_spi_mode mode
Definition: no_os_spi.h:129
ad77681_init_param::filter
enum ad77681_filter_type filter
Definition: ad77681.h:571
ENABLE
#define ENABLE
Definition: ad77681.h:345
AD77681_REG_SPI_DIAG_ENABLE
#define AD77681_REG_SPI_DIAG_ENABLE
Definition: ad77681.h:74
AD77681_COEF_CONTROL_COEFFWRITEEN
#define AD77681_COEF_CONTROL_COEFFWRITEEN(x)
Definition: ad77681.h:307
AD77681_VCM_1_9V
@ AD77681_VCM_1_9V
Definition: ad77681.h:456
device
Definition: ad9361_util.h:75
ad77681_gpio_open_drain
int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev, enum ad77681_gpios gpio_number, enum ad77681_gpio_output_type output_type)
Definition: ad77681.c:1543
ad77681_gpio_inout
int32_t ad77681_gpio_inout(struct ad77681_dev *dev, uint8_t direction, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1435
ad77681_init_param::AINn
enum ad77681_AINn_precharge AINn
Definition: ad77681.h:567
AD77681_SPI_DIAG_ERR_SPI_RD_MSK
#define AD77681_SPI_DIAG_ERR_SPI_RD_MSK
Definition: ad77681.h:238
AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK
#define AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK
Definition: ad77681.h:171
AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK
#define AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK
Definition: ad77681.h:175
AD77681_REG_WRITE
#define AD77681_REG_WRITE(x)
Definition: ad77681.h:323
ad77681_status
int32_t ad77681_status(struct ad77681_dev *dev, struct ad77681_status_registers *status)
Definition: ad77681.c:1703
AD77681_WAKE
@ AD77681_WAKE
Definition: ad77681.h:417
ad77681_set_50HZ_rejection
int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev, uint8_t enable)
Definition: ad77681.c:822
ad77681_set_crc_sel
int32_t ad77681_set_crc_sel(struct ad77681_dev *dev, enum ad77681_crc_sel crc_sel)
Definition: ad77681.c:977
AD77681_REG_DIGITAL_FILTER
#define AD77681_REG_DIGITAL_FILTER
Definition: ad77681.h:60
ad77681_dev::AINn
enum ad77681_AINn_precharge AINn
Definition: ad77681.h:541
AD77681_REG_CONVERSION
#define AD77681_REG_CONVERSION
Definition: ad77681.h:59
AD77681_POSITIVE_FS
@ AD77681_POSITIVE_FS
Definition: ad77681.h:385
ad77681_power_mode
ad77681_power_mode
Definition: ad77681.h:351
ad77681_init_param::AINp
enum ad77681_AINp_precharge AINp
Definition: ad77681.h:568
AD77681_SINC5_FIR_DECx128
@ AD77681_SINC5_FIR_DECx128
Definition: ad77681.h:408
AD77681_ECO
@ AD77681_ECO
Definition: ad77681.h:352
ad77681_set_AINn_buffer
int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev, enum ad77681_AINn_precharge AINn)
Definition: ad77681.c:642
AD77681_REG_POWER_CLOCK
#define AD77681_REG_POWER_CLOCK
Definition: ad77681.h:56
AD77681_REG_SPI_DIAG_STATUS
#define AD77681_REG_SPI_DIAG_STATUS
Definition: ad77681.h:79
AD77681_CONTINUOUS_DATA_READ
@ AD77681_CONTINUOUS_DATA_READ
Definition: ad77681.h:492
AD77681_GPIO_WRITE_1_MSK
#define AD77681_GPIO_WRITE_1_MSK
Definition: ad77681.h:195
AD77681_MASTER_FILT_SAT_MSK
#define AD77681_MASTER_FILT_SAT_MSK
Definition: ad77681.h:270
ad77681_compute_xor
uint8_t ad77681_compute_xor(uint8_t *data, uint8_t data_size, uint8_t init_val)
Definition: ad77681.c:89
ad77681_gpio_open_drain
int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev, enum ad77681_gpios gpio_number, enum ad77681_gpio_output_type output_type)
Definition: ad77681.c:1543
AD77681_REG_ANALOG
#define AD77681_REG_ANALOG
Definition: ad77681.h:57
ad77681_gpio_inout
int32_t ad77681_gpio_inout(struct ad77681_dev *dev, uint8_t direction, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1435
AD77681_CONV_CONTINUOUS
@ AD77681_CONV_CONTINUOUS
Definition: ad77681.h:365
AD77681_NEGATIVE_FS
@ AD77681_NEGATIVE_FS
Definition: ad77681.h:386
AD77681_POWER_CLK_POWER_DOWN
#define AD77681_POWER_CLK_POWER_DOWN
Definition: ad77681.h:110
ad77681_set_filter_type
int32_t ad77681_set_filter_type(struct ad77681_dev *dev, enum ad77681_sinc5_fir_decimate decimate, enum ad77681_filter_type filter, uint16_t sinc3_osr)
Definition: ad77681.c:755
AD77681_VCM_2_05V
@ AD77681_VCM_2_05V
Definition: ad77681.h:455
AD77681_REG_ADC_DIAG_ENABLE
#define AD77681_REG_ADC_DIAG_ENABLE
Definition: ad77681.h:75
AD77681_GPIO_WRITE_3_MSK
#define AD77681_GPIO_WRITE_3_MSK
Definition: ad77681.h:191
AD77681_AIN_SHORT
@ AD77681_AIN_SHORT
Definition: ad77681.h:384
ad77681_rdy_dout
ad77681_rdy_dout
Definition: ad77681.h:377
AD77681_SINC5_FIR_DECx64
@ AD77681_SINC5_FIR_DECx64
Definition: ad77681.h:407
AD77681_GPIO_WRITE_0_MSK
#define AD77681_GPIO_WRITE_0_MSK
Definition: ad77681.h:197
ad77681_set_convlen
int32_t ad77681_set_convlen(struct ad77681_dev *dev, enum ad77681_conv_len conv_len)
Definition: ad77681.c:949
AD77681_INTERFACE_CONT_READ_MSK
#define AD77681_INTERFACE_CONT_READ_MSK
Definition: ad77681.h:95
ad77681_set_REFp_buffer
int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev, enum ad77681_REFp_buffer REFp)
Definition: ad77681.c:716
ad77681_set_AINp_buffer
int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev, enum ad77681_AINp_precharge AINp)
Definition: ad77681.c:666
ad77681_status_registers::ref_det_error
bool ref_det_error
Definition: ad77681.h:519
AD77681_REG_MASTER_STATUS
#define AD77681_REG_MASTER_STATUS
Definition: ad77681.h:78
AD77681_GLOBAL_GPIO_ENABLE
@ AD77681_GLOBAL_GPIO_ENABLE
Definition: ad77681.h:465
ad77681_CRC_status_handling
int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev, uint16_t *data_buffer)
Definition: ad77681.c:337
ad77681_init_param::REFp
enum ad77681_REFp_buffer REFp
Definition: ad77681.h:570
AD77681_REG_INTERFACE_FORMAT
#define AD77681_REG_INTERFACE_FORMAT
Definition: ad77681.h:55
AD77681_REG_OFFSET_LO
#define AD77681_REG_OFFSET_LO
Definition: ad77681.h:70
ad77681_spi_read_mask
int32_t ad77681_spi_read_mask(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t *data)
Definition: ad77681.c:188
AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK
#define AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK
Definition: ad77681.h:250
ad77681_set_mclk_div
int32_t ad77681_set_mclk_div(struct ad77681_dev *dev, enum ad77681_mclk_div clk_div)
Definition: ad77681.c:588
ad77681_dev::conv_diag_sel
bool conv_diag_sel
Definition: ad77681.h:536
ad77681_programmable_filter
int32_t ad77681_programmable_filter(struct ad77681_dev *dev, const float *coeffs, uint8_t num_coeffs)
Definition: ad77681.c:1145
ad77681_set_status_bit
int32_t ad77681_set_status_bit(struct ad77681_dev *dev, bool status_bit)
Definition: ad77681.c:1015
ad77681_set_convlen
int32_t ad77681_set_convlen(struct ad77681_dev *dev, enum ad77681_conv_len conv_len)
Definition: ad77681.c:949
AD77681_GPIO_CNTRL_UGPIO_EN_MSK
#define AD77681_GPIO_CNTRL_UGPIO_EN_MSK
Definition: ad77681.h:169
ad77681_set_continuos_read
int32_t ad77681_set_continuos_read(struct ad77681_dev *dev, enum ad77681_continuous_read continuous_enable)
Definition: ad77681.c:843
ad77681_set_AINp_buffer
int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev, enum ad77681_AINp_precharge AINp)
Definition: ad77681.c:666
ad77681_dev::mclk_div
enum ad77681_mclk_div mclk_div
Definition: ad77681.h:533
AD77681_REG_OFFSET_HI
#define AD77681_REG_OFFSET_HI
Definition: ad77681.h:68
AD77681_INTERFACE_STATUS_EN_MSK
#define AD77681_INTERFACE_STATUS_EN_MSK
Definition: ad77681.h:89
AD77681_ANALOG_AIN_BUF_POS_OFF_MSK
#define AD77681_ANALOG_AIN_BUF_POS_OFF_MSK
Definition: ad77681.h:129
AD77681_SINC5_DECx16
@ AD77681_SINC5_DECx16
Definition: ad77681.h:399
AD77681_REG_SINC3_DEC_RATE_LSB
#define AD77681_REG_SINC3_DEC_RATE_LSB
Definition: ad77681.h:62
ad77681_conv_mode
ad77681_conv_mode
Definition: ad77681.h:364
AD77681_POWER_CLK_PWRMODE
#define AD77681_POWER_CLK_PWRMODE(x)
Definition: ad77681.h:107
ad77681_init_param::vref
uint16_t vref
Definition: ad77681.h:574
AD77681_SPI_DIAG_ERR_SPI_WR
#define AD77681_SPI_DIAG_ERR_SPI_WR(x)
Definition: ad77681.h:241
ad77681_set_50HZ_rejection
int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev, uint8_t enable)
Definition: ad77681.c:822
no_os_error.h
Error codes definition.
ad77681_dev::diag_mux_sel
enum ad77681_conv_diag_mux diag_mux_sel
Definition: ad77681.h:535
ad77681_init_param::mclk_div
enum ad77681_mclk_div mclk_div
Definition: ad77681.h:559
ad77681_spi_read_mask
int32_t ad77681_spi_read_mask(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t *data)
Definition: ad77681.c:188
ad77681_dev::conv_len
enum ad77681_conv_len conv_len
Definition: ad77681.h:537
AD77681_GPIO_WRITE_ALL
#define AD77681_GPIO_WRITE_ALL(x)
Definition: ad77681.h:200
AD77681_AINn_ENABLED
@ AD77681_AINn_ENABLED
Definition: ad77681.h:427
ad77681_set_mclk_div
int32_t ad77681_set_mclk_div(struct ad77681_dev *dev, enum ad77681_mclk_div clk_div)
Definition: ad77681.c:588
ad77681_dev::AINp
enum ad77681_AINp_precharge AINp
Definition: ad77681.h:542
AD77681_REG_GAIN_HI
#define AD77681_REG_GAIN_HI
Definition: ad77681.h:71
AD77681_OFFSET_LO
#define AD77681_OFFSET_LO(x)
Definition: ad77681.h:219
ad77681_init_param::VCM_out
enum ad77681_VCM_out VCM_out
Definition: ad77681.h:566
ad77681.h
Header file of the AD7768-1 Driver.
AD77681_REG_GPIO_CONTROL
#define AD77681_REG_GPIO_CONTROL
Definition: ad77681.h:65
AD77681_VCM_1_1V
@ AD77681_VCM_1_1V
Definition: ad77681.h:458
ad77681_gobal_gpio_enable
ad77681_gobal_gpio_enable
Definition: ad77681.h:464
ad77681_init_param::crc_sel
enum ad77681_crc_sel crc_sel
Definition: ad77681.h:564
AD77681_DIGI_FILTER_DEC_RATE
#define AD77681_DIGI_FILTER_DEC_RATE(x)
Definition: ad77681.h:144
ad77681_status_registers::spi_crc_error
bool spi_crc_error
Definition: ad77681.h:516
AD77681_RDY_DOUT_DIS
@ AD77681_RDY_DOUT_DIS
Definition: ad77681.h:379
AD77681_REG_ACCESS_KEY
#define AD77681_REG_ACCESS_KEY
Definition: ad77681.h:99
ad77681_gpio_read
int32_t ad77681_gpio_read(struct ad77681_dev *dev, uint8_t *value, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1317
ad77681_status_registers::memoy_map_crc_error
bool memoy_map_crc_error
Definition: ad77681.h:523
AD77681_VCM_0_9V
@ AD77681_VCM_0_9V
Definition: ad77681.h:459
AD77681_ACCESS_KEY_MSK
#define AD77681_ACCESS_KEY_MSK
Definition: ad77681.h:318
AD77681_INTERFACE_CRC_EN_MSK
#define AD77681_INTERFACE_CRC_EN_MSK
Definition: ad77681.h:85
ad77681_dev::conv_mode
enum ad77681_conv_mode conv_mode
Definition: ad77681.h:534
AD77681_BUFp_ENABLED
@ AD77681_BUFp_ENABLED
Definition: ad77681.h:446
AD77681_GPIO_CNTRL_GPIO0_OP_EN
#define AD77681_GPIO_CNTRL_GPIO0_OP_EN(x)
Definition: ad77681.h:186
AD77681_CONTINUOUS_READ_ENABLE
@ AD77681_CONTINUOUS_READ_ENABLE
Definition: ad77681.h:485
adc_data::raw_data
uint32_t raw_data[4096]
Definition: ad77681.h:500
AD77681_SINC5_FIR_DECx256
@ AD77681_SINC5_FIR_DECx256
Definition: ad77681.h:409
ad77681_apply_offset
int32_t ad77681_apply_offset(struct ad77681_dev *dev, uint32_t value)
Definition: ad77681.c:1076
adc_data::count
uint16_t count
Definition: ad77681.h:498
AD77681_GPIO3
@ AD77681_GPIO3
Definition: ad77681.h:474
AD77681_POWER_CLK_PWRMODE_MSK
#define AD77681_POWER_CLK_PWRMODE_MSK
Definition: ad77681.h:106
ad77681_dev::power_mode
enum ad77681_power_mode power_mode
Definition: ad77681.h:532
ad77681_set_VCM_output
int32_t ad77681_set_VCM_output(struct ad77681_dev *dev, enum ad77681_VCM_out VCM_out)
Definition: ad77681.c:618
AD77681_GPIO_OPEN_DRAIN
@ AD77681_GPIO_OPEN_DRAIN
Definition: ad77681.h:480
ad77681_set_power_mode
int32_t ad77681_set_power_mode(struct ad77681_dev *dev, enum ad77681_power_mode mode)
Definition: ad77681.c:562
AD77681_VCM_HALF_VCC
@ AD77681_VCM_HALF_VCC
Definition: ad77681.h:453
AD77681_MASTER_ADC_ERROR_MSK
#define AD77681_MASTER_ADC_ERROR_MSK
Definition: ad77681.h:267
ad77681_conv_diag_mux
ad77681_conv_diag_mux
Definition: ad77681.h:382
AD77681_CONV_24BIT
@ AD77681_CONV_24BIT
Definition: ad77681.h:373
AD77681_HARD_RESET
@ AD77681_HARD_RESET
Definition: ad77681.h:423
AD77681_RDY_DOUT_EN
@ AD77681_RDY_DOUT_EN
Definition: ad77681.h:378
ad77681_init_param
Definition: ad77681.h:554
ad77681_crc_sel
ad77681_crc_sel
Definition: ad77681.h:389
ad77681_apply_gain
int32_t ad77681_apply_gain(struct ad77681_dev *dev, uint32_t value)
Definition: ad77681.c:1110
AD77681_REG_SINC3_DEC_RATE_MSB
#define AD77681_REG_SINC3_DEC_RATE_MSB
Definition: ad77681.h:61
ad77681_dev::filter
enum ad77681_filter_type filter
Definition: ad77681.h:545
AD77681_REG_OFFSET_MID
#define AD77681_REG_OFFSET_MID
Definition: ad77681.h:69
AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK
#define AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK
Definition: ad77681.h:185
AD77681_GPIO_CNTRL_GPIO1_OP_EN
#define AD77681_GPIO_CNTRL_GPIO1_OP_EN(x)
Definition: ad77681.h:184
ad77681_init_param::decimate
enum ad77681_sinc5_fir_decimate decimate
Definition: ad77681.h:572
ad77681_init_param::conv_diag_sel
bool conv_diag_sel
Definition: ad77681.h:562
ad77681_status_registers::spi_read_error
bool spi_read_error
Definition: ad77681.h:514
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:143
ad77681_set_conv_mode
int32_t ad77681_set_conv_mode(struct ad77681_dev *dev, enum ad77681_conv_mode conv_mode, enum ad77681_conv_diag_mux diag_mux_sel, bool conv_diag_sel)
Definition: ad77681.c:910
AD77681_SYNC_RST_SPI_STARTB_MSK
#define AD77681_SYNC_RST_SPI_STARTB_MSK
Definition: ad77681.h:159
ad77681_status_registers::spi_error
bool spi_error
Definition: ad77681.h:510
AD77681_ADC_DIAG_ERR_FILT_NOT_SET
#define AD77681_ADC_DIAG_ERR_FILT_NOT_SET(x)
Definition: ad77681.h:251
ad77681_init_param::sample_rate
uint32_t sample_rate
Definition: ad77681.h:576
ad77681_gpio_write
int32_t ad77681_gpio_write(struct ad77681_dev *dev, uint8_t value, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1376
AD77681_COEF_CONTROL_COEFFACCESSEN
#define AD77681_COEF_CONTROL_COEFFACCESSEN(x)
Definition: ad77681.h:305
AD77681_MCLK_DIV_2
@ AD77681_MCLK_DIV_2
Definition: ad77681.h:361
ad77681_status_registers::dldo_psm_error
bool dldo_psm_error
Definition: ad77681.h:517
ad77681_status_registers::por_flag
bool por_flag
Definition: ad77681.h:511
ad77681_dev::REFp
enum ad77681_REFp_buffer REFp
Definition: ad77681.h:544
AD77681_DIG_MEMMAP_CRC_ERROR_MSK
#define AD77681_DIG_MEMMAP_CRC_ERROR_MSK
Definition: ad77681.h:295
AD77681_SLEEP
@ AD77681_SLEEP
Definition: ad77681.h:416
AD77681_SPI_READ_ERROR_CLR
#define AD77681_SPI_READ_ERROR_CLR(x)
Definition: ad77681.h:280
AD77681_ADC_FILT_NOT_SET_MSK
#define AD77681_ADC_FILT_NOT_SET_MSK
Definition: ad77681.h:291
AD77681_ANALOG_AIN_BUF_POS_OFF
#define AD77681_ANALOG_AIN_BUF_POS_OFF(x)
Definition: ad77681.h:130
ad77681_status_registers::ext_clk_qual_error
bool ext_clk_qual_error
Definition: ad77681.h:522
AD77681_ANALOG_REF_BUF_POS_MSK
#define AD77681_ANALOG_REF_BUF_POS_MSK
Definition: ad77681.h:125
ad77681_apply_gain
int32_t ad77681_apply_gain(struct ad77681_dev *dev, uint32_t value)
Definition: ad77681.c:1110
ad77681_power_down
int32_t ad77681_power_down(struct ad77681_dev *dev, enum ad77681_sleep_wake sleep_wake)
Definition: ad77681.c:871
ad77681_spi_reg_write
int32_t ad77681_spi_reg_write(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t reg_data)
Definition: ad77681.c:162
AD77681_SPI_CLK_CNT_ERROR_MSK
#define AD77681_SPI_CLK_CNT_ERROR_MSK
Definition: ad77681.h:278
AD77681_COEF_CONTROL_COEFFWRITEEN_MSK
#define AD77681_COEF_CONTROL_COEFFWRITEEN_MSK
Definition: ad77681.h:306
AD77681_MASTER_DIG_ERR_EXT_CLK_MSK
#define AD77681_MASTER_DIG_ERR_EXT_CLK_MSK
Definition: ad77681.h:269
AD77681_DIGI_FILTER_FILTER
#define AD77681_DIGI_FILTER_FILTER(x)
Definition: ad77681.h:142
AD77681_SPI_WRITE_ERROR_CLR
#define AD77681_SPI_WRITE_ERROR_CLR(x)
Definition: ad77681.h:282
AD77681_CONV_PERIODIC
@ AD77681_CONV_PERIODIC
Definition: ad77681.h:368
ad77681_gpios
ad77681_gpios
Definition: ad77681.h:470
AD77681_POWER_CLK_MCLK_DIV
#define AD77681_POWER_CLK_MCLK_DIV(x)
Definition: ad77681.h:112
ad77681_gpio_output_type
ad77681_gpio_output_type
Definition: ad77681.h:478
ad77681_init_param::power_mode
enum ad77681_power_mode power_mode
Definition: ad77681.h:558
AD77681_VCM_OFF
@ AD77681_VCM_OFF
Definition: ad77681.h:460
AD77681_GPIO0
@ AD77681_GPIO0
Definition: ad77681.h:471
ad77681_VCM_out
ad77681_VCM_out
Definition: ad77681.h:452
AD77681_SINC3_DEC_RATE_LSB_MSK
#define AD77681_SINC3_DEC_RATE_LSB_MSK
Definition: ad77681.h:151
ad77681_set_filter_type
int32_t ad77681_set_filter_type(struct ad77681_dev *dev, enum ad77681_sinc5_fir_decimate decimate, enum ad77681_filter_type filter, uint16_t sinc3_osr)
Definition: ad77681.c:755
AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK
#define AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK
Definition: ad77681.h:131
ad77681_dev::mclk
uint16_t mclk
Definition: ad77681.h:549
INITIAL_CRC
#define INITIAL_CRC
Definition: ad77681.h:331
AD77681_GPIO_CNTRL_GPIO3_OP_EN
#define AD77681_GPIO_CNTRL_GPIO3_OP_EN(x)
Definition: ad77681.h:180
AD77681_BUFp_FULL_BUFFER_ON
@ AD77681_BUFp_FULL_BUFFER_ON
Definition: ad77681.h:448
ad77681_set_power_mode
int32_t ad77681_set_power_mode(struct ad77681_dev *dev, enum ad77681_power_mode mode)
Definition: ad77681.c:562
ad77681_init_param::mclk
uint16_t mclk
Definition: ad77681.h:575
AD77681_SINC3_DEC_RATE_LSB
#define AD77681_SINC3_DEC_RATE_LSB(x)
Definition: ad77681.h:152
AD77681_SPI_READ_ERROR_MSK
#define AD77681_SPI_READ_ERROR_MSK
Definition: ad77681.h:279
ad7761_reset_option
ad7761_reset_option
Definition: ad77681.h:421
AD77681_REG_READ
#define AD77681_REG_READ(x)
Definition: ad77681.h:322
AD77681_SINC3_DEC_RATE_MSB_MSK
#define AD77681_SINC3_DEC_RATE_MSB_MSK
Definition: ad77681.h:147
AD77681_GPIO_WRITE_2
#define AD77681_GPIO_WRITE_2(x)
Definition: ad77681.h:194
AD77681_INTERFACE_CRC_TYPE_MSK
#define AD77681_INTERFACE_CRC_TYPE_MSK
Definition: ad77681.h:87
AD77681_GPIO_READ_3_MSK
#define AD77681_GPIO_READ_3_MSK
Definition: ad77681.h:203
AD77681_GPIO_READ_1_MSK
#define AD77681_GPIO_READ_1_MSK
Definition: ad77681.h:205
ad77681_scratchpad
int32_t ad77681_scratchpad(struct ad77681_dev *dev, uint8_t *sequence)
Definition: ad77681.c:1505
AD77681_DIG_DIAG_ERR_FUSE_CRC
#define AD77681_DIG_DIAG_ERR_FUSE_CRC(x)
Definition: ad77681.h:261
AD77681_ADC_DIG_ERR_EXT_CLK_MSK
#define AD77681_ADC_DIG_ERR_EXT_CLK_MSK
Definition: ad77681.h:292
AD77681_MEDIAN
@ AD77681_MEDIAN
Definition: ad77681.h:353
AD77681_REGISTER_DATA_READ
@ AD77681_REGISTER_DATA_READ
Definition: ad77681.h:491
ad77681_soft_reset
int32_t ad77681_soft_reset(struct ad77681_dev *dev)
Definition: ad77681.c:1039
ad77681_get_frame_byte
uint8_t ad77681_get_frame_byte(struct ad77681_dev *dev)
Definition: ad77681.c:252
AD77681_DIG_RAM_CRC_ERROR_MSK
#define AD77681_DIG_RAM_CRC_ERROR_MSK
Definition: ad77681.h:296
INITIAL_CRC_CRC8
#define INITIAL_CRC_CRC8
Definition: ad77681.h:329
AD77681_POWER_CLK_MCLK_DIV_MSK
#define AD77681_POWER_CLK_MCLK_DIV_MSK
Definition: ad77681.h:111
AD77681_ANALOG2_VCM
#define AD77681_ANALOG2_VCM(x)
Definition: ad77681.h:136
AD77681_INTERFACE_CONT_READ_EN
#define AD77681_INTERFACE_CONT_READ_EN(x)
Definition: ad77681.h:96
ad77681_spi_reg_read
int32_t ad77681_spi_reg_read(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t *reg_data)
Definition: ad77681.c:112
ad77681_AINn_precharge
ad77681_AINn_precharge
Definition: ad77681.h:426
ad77681_init_param::sinc3_osr
uint16_t sinc3_osr
Definition: ad77681.h:573
AD77681_CRC
@ AD77681_CRC
Definition: ad77681.h:390
AD77681_SPI_DIAG_ERR_SPI_CLK_CNT
#define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT(x)
Definition: ad77681.h:237
ad77681_set_conv_mode
int32_t ad77681_set_conv_mode(struct ad77681_dev *dev, enum ad77681_conv_mode conv_mode, enum ad77681_conv_diag_mux diag_mux_sel, bool conv_diag_sel)
Definition: ad77681.c:910
ad77681_status_registers::master_error
bool master_error
Definition: ad77681.h:504
AD77681_ADC_DIAG_ERR_FILT_SAT_MSK
#define AD77681_ADC_DIAG_ERR_FILT_SAT_MSK
Definition: ad77681.h:248
AD77681_ADC_FILT_SAT_MSK
#define AD77681_ADC_FILT_SAT_MSK
Definition: ad77681.h:290
AD77681_MCLK_DIV_16
@ AD77681_MCLK_DIV_16
Definition: ad77681.h:358
AD77681_GPIO_CNTRL_GPIO1_OD_EN
#define AD77681_GPIO_CNTRL_GPIO1_OD_EN(x)
Definition: ad77681.h:174
AD77681_ALL_GPIOS
@ AD77681_ALL_GPIOS
Definition: ad77681.h:475
AD77681_ADC_DIAG_ERR_ALDO_PSM
#define AD77681_ADC_DIAG_ERR_ALDO_PSM(x)
Definition: ad77681.h:247
AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN(x)
Definition: ad77681.h:188
AD77681_GPIO_READ_ALL_MSK
#define AD77681_GPIO_READ_ALL_MSK
Definition: ad77681.h:207
ad77681_sleep_wake
ad77681_sleep_wake
Definition: ad77681.h:415
ad77681_dev::REFn
enum ad77681_REFn_buffer REFn
Definition: ad77681.h:543
AD77681_ADC_ALDO_PSM_ERROR_MSK
#define AD77681_ADC_ALDO_PSM_ERROR_MSK
Definition: ad77681.h:288
AD77681_VCM_1_65V
@ AD77681_VCM_1_65V
Definition: ad77681.h:457
AD77681_DIG_DIAG_ERR_RAM_CRC
#define AD77681_DIG_DIAG_ERR_RAM_CRC(x)
Definition: ad77681.h:259
AD77681_REG_SCRATCH_PAD
#define AD77681_REG_SCRATCH_PAD
Definition: ad77681.h:52
AD77681_CONVERSION_DIAG_SEL_MSK
#define AD77681_CONVERSION_DIAG_SEL_MSK
Definition: ad77681.h:119
AD77681_OFFSET_HI
#define AD77681_OFFSET_HI(x)
Definition: ad77681.h:211
no_os_udelay
void no_os_udelay(uint32_t usecs)
Wait until usecs microseconds passed.
Definition: aducm3029_delay.c:120
ad77681_get_rx_buf_len
uint8_t ad77681_get_rx_buf_len(struct ad77681_dev *dev)
Definition: ad77681.c:231
AD77681_SPI_CRC_ERROR_CLR
#define AD77681_SPI_CRC_ERROR_CLR(x)
Definition: ad77681.h:284
AD77681_ADC_REF_DET_ERROR_MSK
#define AD77681_ADC_REF_DET_ERROR_MSK
Definition: ad77681.h:289
AD77681_COEF_CONTROL_COEFFACCESSEN_MSK
#define AD77681_COEF_CONTROL_COEFFACCESSEN_MSK
Definition: ad77681.h:304
AD77681_CONVERSION_DIAG_MUX_SEL
#define AD77681_CONVERSION_DIAG_MUX_SEL(x)
Definition: ad77681.h:118
AD77681_NO_CRC
@ AD77681_NO_CRC
Definition: ad77681.h:392
AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK
#define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK
Definition: ad77681.h:236
ad77681_REFn_buffer
ad77681_REFn_buffer
Definition: ad77681.h:438
AD77681_SYNC_RST_SPI_RESET
#define AD77681_SYNC_RST_SPI_RESET(x)
Definition: ad77681.h:166
AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK
#define AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK
Definition: ad77681.h:139
AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK
Definition: ad77681.h:177
AD77681_SINC5_DECx8
@ AD77681_SINC5_DECx8
Definition: ad77681.h:398
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK
#define AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK
Definition: ad77681.h:173
AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK
#define AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK
Definition: ad77681.h:246
AD77681_REG_GPIO_READ
#define AD77681_REG_GPIO_READ
Definition: ad77681.h:67
AD77681_VCM_2_5V
@ AD77681_VCM_2_5V
Definition: ad77681.h:454
ad77681_status_registers::dig_error
bool dig_error
Definition: ad77681.h:506
ad77681_init_param::conv_len
enum ad77681_conv_len conv_len
Definition: ad77681.h:563
AD77681_CRC8_POLY
#define AD77681_CRC8_POLY
Definition: ad77681.h:326
AD77681_DIG_FUS_CRC_ERROR_MSK
#define AD77681_DIG_FUS_CRC_ERROR_MSK
Definition: ad77681.h:297
ad77681_dev::decimate
enum ad77681_sinc5_fir_decimate decimate
Definition: ad77681.h:546
AD77681_CONV_ONE_SHOT
@ AD77681_CONV_ONE_SHOT
Definition: ad77681.h:366
AD77681_DIGI_FILTER_DEC_RATE_MSK
#define AD77681_DIGI_FILTER_DEC_RATE_MSK
Definition: ad77681.h:143
AD77681_GPIO_READ_2_MSK
#define AD77681_GPIO_READ_2_MSK
Definition: ad77681.h:204
ad77681_status_registers::ram_crc_error
bool ram_crc_error
Definition: ad77681.h:524
AD77681_SINC5_FIR_DECx1024
@ AD77681_SINC5_FIR_DECx1024
Definition: ad77681.h:411
ad77681_update_sample_rate
int32_t ad77681_update_sample_rate(struct ad77681_dev *dev)
Definition: ad77681.c:434
AD77681_MCLK_DIV_4
@ AD77681_MCLK_DIV_4
Definition: ad77681.h:360
ad77681_global_gpio
int32_t ad77681_global_gpio(struct ad77681_dev *dev, enum ad77681_gobal_gpio_enable gpio_enable)
Definition: ad77681.c:1488
AD77681_SINC5_FIR_DECx32
@ AD77681_SINC5_FIR_DECx32
Definition: ad77681.h:406
AD77681_SPI_IGNORE_ERROR_CLR
#define AD77681_SPI_IGNORE_ERROR_CLR(x)
Definition: ad77681.h:277
AD77681_CONV_SINGLE
@ AD77681_CONV_SINGLE
Definition: ad77681.h:367
ad77681_spi_read_adc_data
int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev, uint8_t *adc_data, enum ad77681_data_read_mode mode)
Definition: ad77681.c:279
AD77681_ANALOG_AIN_BUF_NEG_OFF
#define AD77681_ANALOG_AIN_BUF_NEG_OFF(x)
Definition: ad77681.h:132
AD77681_ANALOG_REF_BUF_POS
#define AD77681_ANALOG_REF_BUF_POS(x)
Definition: ad77681.h:126
ad77681_dev::data_frame_byte
uint8_t data_frame_byte
Definition: ad77681.h:551
AD77681_GPIO_WRITE_0
#define AD77681_GPIO_WRITE_0(x)
Definition: ad77681.h:198
AD77681_ADC_DIAG_ERR_FILT_SAT
#define AD77681_ADC_DIAG_ERR_FILT_SAT(x)
Definition: ad77681.h:249
ad77681_compute_crc8
uint8_t ad77681_compute_crc8(uint8_t *data, uint8_t data_size, uint8_t init_val)
Definition: ad77681.c:61
AD77681_SPI_CRC_ERROR_MSK
#define AD77681_SPI_CRC_ERROR_MSK
Definition: ad77681.h:283
AD77681_GAIN_LOW
#define AD77681_GAIN_LOW(x)
Definition: ad77681.h:231
AD77681_SINC3_DEC_RATE_MSB
#define AD77681_SINC3_DEC_RATE_MSB(x)
Definition: ad77681.h:148
AD77681_ANALOG2_VCM_MSK
#define AD77681_ANALOG2_VCM_MSK
Definition: ad77681.h:135
AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN(x)
Definition: ad77681.h:178
adc_data::samples
uint16_t samples
Definition: ad77681.h:499
ad77681_init_param::data_frame_byte
uint8_t data_frame_byte
Definition: ad77681.h:577
AD77681_SPI_DIAG_ERR_SPI_WR_MSK
#define AD77681_SPI_DIAG_ERR_SPI_WR_MSK
Definition: ad77681.h:240
AD77681_SPI_WRITE_ERROR_MSK
#define AD77681_SPI_WRITE_ERROR_MSK
Definition: ad77681.h:281
ad77681_SINC3_ODR
int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev, uint16_t *sinc3_dec_reg, float sinc3_odr)
Definition: ad77681.c:515
ad77681_dev::spi_desc
struct no_os_spi_desc * spi_desc
Definition: ad77681.h:530
AD77681_GAIN_MID_MSK
#define AD77681_GAIN_MID_MSK
Definition: ad77681.h:226
AD77681_ADC_DIAG_ERR_DLDO_PSM
#define AD77681_ADC_DIAG_ERR_DLDO_PSM(x)
Definition: ad77681.h:245
ad77681_init_param::REFn
enum ad77681_REFn_buffer REFn
Definition: ad77681.h:569
AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK
#define AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK
Definition: ad77681.h:183
AD77681_CONV_16BIT
@ AD77681_CONV_16BIT
Definition: ad77681.h:374
AD77681_REG_ADC_DATA
#define AD77681_REG_ADC_DATA
Definition: ad77681.h:77
ad77681_spi_write_mask
int32_t ad77681_spi_write_mask(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t data)
Definition: ad77681.c:210
ad77681_programmable_filter
int32_t ad77681_programmable_filter(struct ad77681_dev *dev, const float *coeffs, uint8_t num_coeffs)
Definition: ad77681.c:1145
AD77681_ACCESS_KEY
#define AD77681_ACCESS_KEY(x)
Definition: ad77681.h:319
AD77681_CONV_STANDBY
@ AD77681_CONV_STANDBY
Definition: ad77681.h:369
ad77681_set_status_bit
int32_t ad77681_set_status_bit(struct ad77681_dev *dev, bool status_bit)
Definition: ad77681.c:1015
ad77681_compute_crc8
uint8_t ad77681_compute_crc8(uint8_t *data, uint8_t data_size, uint8_t init_val)
Definition: ad77681.c:61
AD77681_CONVERSION_MODE_MSK
#define AD77681_CONVERSION_MODE_MSK
Definition: ad77681.h:121
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
ad77681_set_continuos_read
int32_t ad77681_set_continuos_read(struct ad77681_dev *dev, enum ad77681_continuous_read continuous_enable)
Definition: ad77681.c:843
ad77681_conv_len
ad77681_conv_len
Definition: ad77681.h:372
ad77681_status_registers::filt_not_set_error
bool filt_not_set_error
Definition: ad77681.h:521
AD77681_SINC5
@ AD77681_SINC5
Definition: ad77681.h:397
AD77681_GPIO_STRONG_DRIVER
@ AD77681_GPIO_STRONG_DRIVER
Definition: ad77681.h:479
ad77681_continuous_read
ad77681_continuous_read
Definition: ad77681.h:484
AD77681_MASTER_SPI_ERROR_MSK
#define AD77681_MASTER_SPI_ERROR_MSK
Definition: ad77681.h:272
ad77681_dev::status_bit
uint8_t status_bit
Definition: ad77681.h:539
AD77681_INTERFACE_CRC_EN
#define AD77681_INTERFACE_CRC_EN(x)
Definition: ad77681.h:86
AD77681_ADC_DLDO_PSM_ERROR_MSK
#define AD77681_ADC_DLDO_PSM_ERROR_MSK
Definition: ad77681.h:287
AD77681_XOR
@ AD77681_XOR
Definition: ad77681.h:391
AD77681_GAIN_HI_MSK
#define AD77681_GAIN_HI_MSK
Definition: ad77681.h:222
ad77681_status_registers::adc_error
bool adc_error
Definition: ad77681.h:505
ad77681_init_param::diag_mux_sel
enum ad77681_conv_diag_mux diag_mux_sel
Definition: ad77681.h:561
ad77681_dev::sinc3_osr
uint16_t sinc3_osr
Definition: ad77681.h:547
AD77681_REG_SYNC_RESET
#define AD77681_REG_SYNC_RESET
Definition: ad77681.h:64
AD77681_INTERFACE_CONVLEN_MSK
#define AD77681_INTERFACE_CONVLEN_MSK
Definition: ad77681.h:91
ad77681_spi_write_mask
int32_t ad77681_spi_write_mask(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t data)
Definition: ad77681.c:210
AD77681_GPIO_CNTRL_GPIO2_OD_EN
#define AD77681_GPIO_CNTRL_GPIO2_OD_EN(x)
Definition: ad77681.h:172
ad77681_global_gpio
int32_t ad77681_global_gpio(struct ad77681_dev *devices, enum ad77681_gobal_gpio_enable gpio_enable)
Definition: ad77681.c:1488
AD77681_GPIO2
@ AD77681_GPIO2
Definition: ad77681.h:473
AD77681_GAIN_HI
#define AD77681_GAIN_HI(x)
Definition: ad77681.h:223
no_os_spi_desc::mode
enum no_os_spi_mode mode
Definition: no_os_spi.h:151
AD77681_GPIO_CNTRL_UGPIO_EN
#define AD77681_GPIO_CNTRL_UGPIO_EN(x)
Definition: ad77681.h:170
adc_data::finish
bool finish
Definition: ad77681.h:497
ad77681_update_sample_rate
int32_t ad77681_update_sample_rate(struct ad77681_dev *dev)
Definition: ad77681.c:434
AD77681_SCRATCHPAD
#define AD77681_SCRATCHPAD(x)
Definition: ad77681.h:103
ad77681_status_registers::adc_filt_saturated
bool adc_filt_saturated
Definition: ad77681.h:508
ad77681_status
int32_t ad77681_status(struct ad77681_dev *dev, struct ad77681_status_registers *status)
Definition: ad77681.c:1703
ad77681_dev::VCM_out
enum ad77681_VCM_out VCM_out
Definition: ad77681.h:540
ad77681_dev::sample_rate
uint32_t sample_rate
Definition: ad77681.h:550
INITIAL_CRC_XOR
#define INITIAL_CRC_XOR
Definition: ad77681.h:330
ad77681_status_registers::aldo_psm_error
bool aldo_psm_error
Definition: ad77681.h:518
AD77681_SPI_DIAG_ERR_SPI_RD
#define AD77681_SPI_DIAG_ERR_SPI_RD(x)
Definition: ad77681.h:239
AD77681_SPI_IGNORE_ERROR_MSK
#define AD77681_SPI_IGNORE_ERROR_MSK
Definition: ad77681.h:276
EXIT_CONT_READ
#define EXIT_CONT_READ
Definition: ad77681.h:337
AD77681_MCLK_DIV_8
@ AD77681_MCLK_DIV_8
Definition: ad77681.h:359
AD77681_INTERFACE_STATUS_EN
#define AD77681_INTERFACE_STATUS_EN(x)
Definition: ad77681.h:90
ad77681_status_registers::spi_clock_count
bool spi_clock_count
Definition: ad77681.h:513
ad77681_gpio_read
int32_t ad77681_gpio_read(struct ad77681_dev *dev, uint8_t *value, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1317
AD77681_OFFSET_MID
#define AD77681_OFFSET_MID(x)
Definition: ad77681.h:215
ad77681_status_registers::spi_write_error
bool spi_write_error
Definition: ad77681.h:515
AD77681_INTERFACE_CONVLEN
#define AD77681_INTERFACE_CONVLEN(x)
Definition: ad77681.h:92
ad77681_set_AINn_buffer
int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev, enum ad77681_AINn_precharge AINn)
Definition: ad77681.c:642
ad77681_init_param::spi_eng_dev_init
struct no_os_spi_init_param spi_eng_dev_init
Definition: ad77681.h:556
ad77681_clear_error_flags
int32_t ad77681_clear_error_flags(struct ad77681_dev *dev)
Definition: ad77681.c:1586
ad77681_compute_xor
uint8_t ad77681_compute_xor(uint8_t *data, uint8_t data_size, uint8_t init_val)
Definition: ad77681.c:89
AD77681_CONVERSION_DIAG_MUX_MSK
#define AD77681_CONVERSION_DIAG_MUX_MSK
Definition: ad77681.h:117
AD77681_AINp_ENABLED
@ AD77681_AINp_ENABLED
Definition: ad77681.h:433
ad77681_dev::vref
uint16_t vref
Definition: ad77681.h:548
AD77681_DIG_DIAG_ERR_RAM_CRC_MSK
#define AD77681_DIG_DIAG_ERR_RAM_CRC_MSK
Definition: ad77681.h:258
ad77681_REFp_buffer
ad77681_REFp_buffer
Definition: ad77681.h:445
AD77681_BUFn_DISABLED
@ AD77681_BUFn_DISABLED
Definition: ad77681.h:440
ad77681_data_read_mode
ad77681_data_read_mode
Definition: ad77681.h:490
ad77681_soft_reset
int32_t ad77681_soft_reset(struct ad77681_dev *dev)
Definition: ad77681.c:1039
ad77681_status_registers::filt_sat_error
bool filt_sat_error
Definition: ad77681.h:520
AD77681_REG_DIG_DIAG_ENABLE
#define AD77681_REG_DIG_DIAG_ENABLE
Definition: ad77681.h:76
ad77681_apply_offset
int32_t ad77681_apply_offset(struct ad77681_dev *dev, uint32_t value)
Definition: ad77681.c:1076
ad77681_SINC3_ODR
int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev, uint16_t *sinc3_dec_reg, float sinc3_odr)
Definition: ad77681.c:515
ad77681_mclk_div
ad77681_mclk_div
Definition: ad77681.h:357
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:121
AD77681_INTERFACE_CRC_TYPE
#define AD77681_INTERFACE_CRC_TYPE(x)
Definition: ad77681.h:88
AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK
#define AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK
Definition: ad77681.h:179
ad77681_set_VCM_output
int32_t ad77681_set_VCM_output(struct ad77681_dev *dev, enum ad77681_VCM_out VCM_out)
Definition: ad77681.c:618
AD77681_REG_ANALOG2
#define AD77681_REG_ANALOG2
Definition: ad77681.h:58
ad77681_init_param::status_bit
uint8_t status_bit
Definition: ad77681.h:565