no-OS
ad7779.h
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1 /***************************************************************************/
39 #ifndef AD7779_H_
40 #define AD7779_H_
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include <stdint.h>
46 #include "no_os_delay.h"
47 #include "no_os_gpio.h"
48 #include "no_os_spi.h"
49 
50 /******************************************************************************/
51 /********************** Macros and Constants Definitions **********************/
52 /******************************************************************************/
53 #define AD7779_REG_CH_CONFIG(ch) (0x00 + (ch)) // Channel Configuration
54 #define AD7779_REG_CH_DISABLE 0x08 // Disable clocks to ADC channel
55 #define AD7779_REG_CH_SYNC_OFFSET(ch) (0x09 + (ch)) // Channel SYNC Offset
56 #define AD7779_REG_GENERAL_USER_CONFIG_1 0x11 // General User Config 1
57 #define AD7779_REG_GENERAL_USER_CONFIG_2 0x12 // General User Config 2
58 #define AD7779_REG_GENERAL_USER_CONFIG_3 0x13 // General User Config 3
59 #define AD7779_REG_DOUT_FORMAT 0x14 // Data out format
60 #define AD7779_REG_ADC_MUX_CONFIG 0x15 // Main ADC meter and reference Mux control
61 #define AD7779_REG_GLOBAL_MUX_CONFIG 0x16 // Global diagnostics mux
62 #define AD7779_REG_GPIO_CONFIG 0x17 // GPIO config
63 #define AD7779_REG_GPIO_DATA 0x18 // GPIO Data
64 #define AD7779_REG_BUFFER_CONFIG_1 0x19 // Buffer Config 1
65 #define AD7779_REG_BUFFER_CONFIG_2 0x1A // Buffer Config 2
66 #define AD7779_REG_CH_OFFSET_UPPER_BYTE(ch) (0x1C + (ch) * 6) // Channel offset upper byte
67 #define AD7779_REG_CH_OFFSET_MID_BYTE(ch) (0x1D + (ch) * 6) // Channel offset middle byte
68 #define AD7779_REG_CH_OFFSET_LOWER_BYTE(ch) (0x1E + (ch) * 6) // Channel offset lower byte
69 #define AD7779_REG_CH_GAIN_UPPER_BYTE(ch) (0x1F + (ch) * 6) // Channel gain upper byte
70 #define AD7779_REG_CH_GAIN_MID_BYTE(ch) (0x20 + (ch) * 6) // Channel gain middle byte
71 #define AD7779_REG_CH_GAIN_LOWER_BYTE(ch) (0x21 + (ch) * 6) // Channel gain lower byte
72 #define AD7779_REG_CH_ERR_REG(ch) (0x4C + (ch)) // Channel Status Register
73 #define AD7779_REG_CH0_1_SAT_ERR 0x54 // Channel 0/1 DSP errors
74 #define AD7779_REG_CH2_3_SAT_ERR 0x55 // Channel 2/3 DSP errors
75 #define AD7779_REG_CH4_5_SAT_ERR 0x56 // Channel 4/5 DSP errors
76 #define AD7779_REG_CH6_7_SAT_ERR 0x57 // Channel 6/7 DSP errors
77 #define AD7779_REG_CHX_ERR_REG_EN 0x58 // Channel 0-7 Error Reg Enable
78 #define AD7779_REG_GEN_ERR_REG_1 0x59 // General Errors Register 1
79 #define AD7779_REG_GEN_ERR_REG_1_EN 0x5A // General Errors Register 1 Enable
80 #define AD7779_REG_GEN_ERR_REG_2 0x5B // General Errors Register 2
81 #define AD7779_REG_GEN_ERR_REG_2_EN 0x5C // General Errors Register 2 Enable
82 #define AD7779_REG_STATUS_REG_1 0x5D // Error Status Register 1
83 #define AD7779_REG_STATUS_REG_2 0x5E // Error Status Register 2
84 #define AD7779_REG_STATUS_REG_3 0x5F // Error Status Register 3
85 #define AD7779_REG_SRC_N_MSB 0x60 // Decimation Rate (N) MSB
86 #define AD7779_REG_SRC_N_LSB 0x61 // Decimation Rate (N) LSB
87 #define AD7779_REG_SRC_IF_MSB 0x62 // Decimation Rate (IF) MSB
88 #define AD7779_REG_SRC_IF_LSB 0x63 // Decimation Rate (IF) LSB
89 #define AD7779_REG_SRC_UPDATE 0x64 // SRC load source and load update
90 
91 /* AD7779_REG_CHx_CONFIG */
92 #define AD7779_CH_GAIN(x) (((x) & 0x3) << 6)
93 #define AD7779_CH_RX (1 << 4)
94 
95 /* AD7779_REG_CH_DISABLE */
96 #define AD7779_CH_DISABLE(x) (1 << (x))
97 
98 /* AD7779_REG_GENERAL_USER_CONFIG_1 */
99 #define AD7779_ALL_CH_DIS_MCLK_EN (1 << 7)
100 #define AD7779_MOD_POWERMODE (1 << 6)
101 #define AD7779_PDB_VCM (1 << 5)
102 #define AD7779_PDB_REFOUT_BUF (1 << 4)
103 #define AD7779_PDB_SAR (1 << 3)
104 #define AD7779_PDB_RC_OSC (1 << 2)
105 #define AD7779_SOFT_RESET(x) (((x) & 0x3) << 0)
106 
107 /* AD7779_REG_GENERAL_USER_CONFIG_2 */
108 #define AD7771_FILTER_MODE (1 << 6)
109 #define AD7779_SAR_DIAG_MODE_EN (1 << 5)
110 #define AD7779_SDO_DRIVE_STR(x) (((x) & 0x3) << 3)
111 #define AD7779_DOUT_DRIVE_STR(x) (((x) & 0x3) << 1)
112 #define AD7779_SPI_SYNC (1 << 0)
113 
114 /* AD7779_REG_GENERAL_USER_CONFIG_3 */
115 #define AD7779_CONVST_DEGLITCH_DIS(x) (((x) & 0x3) << 6)
116 #define AD7779_SPI_SLAVE_MODE_EN (1 << 4)
117 #define AD7779_CLK_QUAL_DIS (1 << 0)
118 
119 /* AD7779_REG_DOUT_FORMAT */
120 #define AD7779_DOUT_FORMAT(x) (((x) & 0x3) << 6)
121 #define AD7779_DOUT_HEADER_FORMAT (1 << 5)
122 #define AD7779_DCLK_CLK_DIV(x) (((x) & 0x3) << 1)
123 
124 /* AD7779_REG_GLOBAL_MUX_CONFIG */
125 #define AD7779_GLOBAL_MUX_CTRL(x) (((x) & 0x1F) << 3)
126 
127 /* AD7779_REG_BUFFER_CONFIG_1 */
128 #define AD7779_REF_BUF_POS_EN (1 << 4)
129 #define AD7779_REF_BUF_NEG_EN (1 << 3)
130 
131 /* AD7779_REG_BUFFER_CONFIG_2 */
132 #define AD7779_REFBUFP_PREQ (1 << 7)
133 #define AD7779_REFBUFN_PREQ (1 << 6)
134 #define AD7779_PDB_ALDO1_OVRDRV (1 << 2)
135 #define AD7779_PDB_ALDO2_OVRDRV (1 << 1)
136 #define AD7779_PDB_DLDO_OVRDRV (1 << 0)
137 
138 /* AD7779_REG_GEN_ERR_REG_1_EN */
139 #define AD7779_MEMMAP_CRC_TEST_EN (1 << 5)
140 #define AD7779_ROM_CRC_TEST_EN (1 << 4)
141 #define AD7779_SPI_CLK_COUNT_TEST_EN (1 << 3)
142 #define AD7779_SPI_INVALID_READ_TEST_EN (1 << 2)
143 #define AD7779_SPI_INVALID_WRITE_TEST_EN (1 << 1)
144 #define AD7779_SPI_CRC_TEST_EN (1 << 0)
145 
146 #define AD7779_CRC8_POLY 0x07
147 
148 /******************************************************************************/
149 /*************************** Types Declarations *******************************/
150 /******************************************************************************/
151 typedef enum {
155 
156 typedef enum {
161 
162 typedef enum {
171 } ad7779_ch;
172 
173 typedef enum {
176 } ad7779_state;
177 
178 typedef enum {
183 } ad7779_gain;
184 
185 typedef enum {
195 
196 typedef enum {
200 
201 typedef enum {
205 
206 typedef enum {
210 
211 typedef enum {
216 
217 typedef enum {
241 
242 typedef struct {
243  /* SPI */
245  /* GPIO */
256  /* Device Settings */
260  ad7779_state state[8];
261  ad7779_gain gain[8];
262  uint16_t dec_rate_int;
263  uint16_t dec_rate_dec;
267  uint8_t sync_offset[8];
268  uint32_t offset_corr[8];
269  uint32_t gain_corr[8];
270  ad7779_ref_buf_op_mode ref_buf_op_mode[2];
273  ad7779_state sinc5_state; // Can be enabled only for AD7771
274  uint8_t cached_reg_val[AD7779_REG_SRC_UPDATE + 1];
275 } ad7779_dev;
276 
277 typedef struct {
278  /* SPI */
280  /* GPIO */
281  struct no_os_gpio_init_param gpio_reset;
282  struct no_os_gpio_init_param gpio_mode0;
283  struct no_os_gpio_init_param gpio_mode1;
284  struct no_os_gpio_init_param gpio_mode2;
285  struct no_os_gpio_init_param gpio_mode3;
286  struct no_os_gpio_init_param gpio_dclk0;
287  struct no_os_gpio_init_param gpio_dclk1;
288  struct no_os_gpio_init_param gpio_dclk2;
289  struct no_os_gpio_init_param gpio_sync_in;
290  struct no_os_gpio_init_param gpio_convst_sar;
291  /* Device Settings */
294  ad7779_state state[8];
295  ad7779_gain gain[8];
296  uint16_t dec_rate_int;
297  uint16_t dec_rate_dec;
301  uint8_t sync_offset[8];
302  uint32_t offset_corr[8];
303  uint32_t gain_corr[8];
304  ad7779_ref_buf_op_mode ref_buf_op_mode[2];
305  ad7779_state sinc5_state; // Can be enabled only for AD7771
307 
308 /******************************************************************************/
309 /************************ Functions Declarations ******************************/
310 /******************************************************************************/
311 /* Compute CRC8 checksum. */
312 uint8_t ad7779_compute_crc8(uint8_t *data,
313  uint8_t data_size);
314 /* SPI read from device. */
316  uint8_t reg_addr,
317  uint8_t *reg_data);
318 /* SPI write to device. */
320  uint8_t reg_addr,
321  uint8_t reg_data);
322 /* SPI read from device using a mask. */
324  uint8_t reg_addr,
325  uint8_t mask,
326  uint8_t *data);
327 /* SPI write to device using a mask. */
329  uint8_t reg_addr,
330  uint8_t mask,
331  uint8_t data);
332 /* SPI SAR conversion code read. */
334  ad7779_sar_mux mux_next_conv,
335  uint16_t *sar_code);
336 /* Set SPI operation mode. */
338  ad7779_spi_op_mode mode);
339 /* Get SPI operation mode. */
341  ad7779_spi_op_mode *mode);
342 /* Set the state (enable, disable) of the channel. */
343 int32_t ad7779_set_state(ad7779_dev *dev,
344  ad7779_ch ch,
345  ad7779_state state);
346 /* Get the state (enable, disable) of the selected channel. */
347 int32_t ad7779_get_state(ad7779_dev *dev,
348  ad7779_ch ch,
349  ad7779_state *state);
350 /* Update the state of the MODEx pins according to the settings specified in
351  * the device structure. */
353 /* Set the gain of the selected channel. */
354 int32_t ad7779_set_gain(ad7779_dev *dev,
355  ad7779_ch ch,
356  ad7779_gain gain);
357 /* Get the gain of the selected channel. */
358 int32_t ad7779_get_gain(ad7779_dev *dev,
359  ad7779_ch ch,
360  ad7779_gain *gain);
361 /* Set the decimation rate. */
362 int32_t ad7779_set_dec_rate(ad7779_dev *dev,
363  uint16_t int_val,
364  uint16_t dec_val);
365 /* Get the decimation rate. */
366 int32_t ad7779_get_dec_rate(ad7779_dev *dev,
367  uint16_t *int_val,
368  uint16_t *dec_val);
369 /* Set the power mode. */
370 int32_t ad7779_set_power_mode(ad7779_dev *dev,
371  ad7779_pwr_mode pwr_mode);
372 /* Get the power mode. */
373 int32_t ad7779_get_power_mode(ad7779_dev *dev,
374  ad7779_pwr_mode *pwr_mode);
375 /* Set the reference type. */
377  ad7779_ref_type ref_type);
378 /* Get the reference type. */
380  ad7779_ref_type *ref_type);
381 /* Set the DCLK divider. */
382 int32_t ad7779_set_dclk_div(ad7779_dev *dev,
383  ad7779_dclk_div div);
384 /* Get the DCLK divider. */
385 int32_t ad7779_get_dclk_div(ad7779_dev *dev,
386  ad7779_dclk_div *div);
387 /* Set the synchronization offset of the selected channel. */
389  ad7779_ch ch,
390  uint8_t sync_offset);
391 /* Get the synchronization offset of the selected channel. */
393  ad7779_ch ch,
394  uint8_t *sync_offset);
395 /* Set the offset correction of the selected channel. */
397  ad7779_ch ch,
398  uint32_t offset);
399 /* Get the offset correction of the selected channel. */
401  ad7779_ch ch,
402  uint32_t *offset);
403 /* Set the gain correction of the selected channel. */
404 int32_t ad7779_set_gain_corr(ad7779_dev *dev,
405  ad7779_ch ch,
406  uint32_t gain);
407 /* Get the gain correction of the selected channel. */
408 int32_t ad7779_get_gain_corr(ad7779_dev *dev,
409  ad7779_ch ch,
410  uint32_t *gain);
411 /* Set the reference buffer operation mode of the selected pin. */
413  ad7779_refx_pin refx_pin,
415 /* Get the reference buffer operation mode of the selected pin. */
417  ad7779_refx_pin refx_pin,
418  ad7779_ref_buf_op_mode *mode);
419 /* Set the SAR ADC configuration. */
420 int32_t ad7779_set_sar_cfg(ad7779_dev *dev,
421  ad7779_state state,
422  ad7779_sar_mux mux);
423 /* Get the SAR ADC configuration. */
424 int32_t ad7779_get_sar_cfg(ad7779_dev *dev,
425  ad7779_state *state,
426  ad7779_sar_mux *mux);
427 /* Do a single SAR conversion. */
429  ad7779_sar_mux mux,
430  uint16_t *sar_code);
431 /* Do a SPI software reset. */
433 /* Set the state (enable, disable) of the SINC5 filter. */
435  ad7779_state state);
436 /* Get the state (enable, disable) of the SINC5 filter. */
438  ad7779_state *state);
439 /* Initialize the device. */
440 int32_t ad7779_init(ad7779_dev **device,
442 
443 /* Free the resources allocated by ad7779_init(). */
444 int32_t ad7779_remove(ad7779_dev *dev);
445 
446 #endif // AD7779_H_
AD7779_REG_GLOBAL_MUX_CONFIG
#define AD7779_REG_GLOBAL_MUX_CONFIG
Definition: ad7779.h:61
ad7779_init_param::ctrl_mode
ad7779_ctrl_mode ctrl_mode
Definition: ad7779.h:292
AD7779_MOD_POWERMODE
#define AD7779_MOD_POWERMODE
Definition: ad7779.h:100
AD7779_AVDD2A_AVSSX_ATT
@ AD7779_AVDD2A_AVSSX_ATT
Definition: ad7779.h:229
ad7779_init_param::ref_type
ad7779_ref_type ref_type
Definition: ad7779.h:298
ad7779_spi_int_reg_read_mask
int32_t ad7779_spi_int_reg_read_mask(ad7779_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t *data)
Definition: ad7779.c:172
AD7779_REG_CH_SYNC_OFFSET
#define AD7779_REG_CH_SYNC_OFFSET(ch)
Definition: ad7779.h:55
ad7779_get_sar_cfg
int32_t ad7779_get_sar_cfg(ad7779_dev *dev, ad7779_state *state, ad7779_sar_mux *mux)
Definition: ad7779.c:1111
ad7779_init_param::pwr_mode
ad7779_pwr_mode pwr_mode
Definition: ad7779.h:299
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
AD7779_PIN_CTRL
@ AD7779_PIN_CTRL
Definition: ad7779.h:152
AD7779_REG_BUFFER_CONFIG_2
#define AD7779_REG_BUFFER_CONFIG_2
Definition: ad7779.h:65
ad7779_compute_crc8
uint8_t ad7779_compute_crc8(uint8_t *data, uint8_t data_size)
Definition: ad7779.c:80
AD7779_REG_CH_GAIN_UPPER_BYTE
#define AD7779_REG_CH_GAIN_UPPER_BYTE(ch)
Definition: ad7779.h:69
ad7779_dev::dec_rate_int
uint16_t dec_rate_int
Definition: ad7779.h:262
ad7779_get_gain
int32_t ad7779_get_gain(ad7779_dev *dev, ad7779_ch ch, ad7779_gain *gain)
Definition: ad7779.c:523
ad7779_dev::sinc5_state
ad7779_state sinc5_state
Definition: ad7779.h:273
AD7779_REG_CH_OFFSET_UPPER_BYTE
#define AD7779_REG_CH_OFFSET_UPPER_BYTE(ch)
Definition: ad7779.h:66
ad7779_dev::gpio_dclk0
struct no_os_gpio_desc * gpio_dclk0
Definition: ad7779.h:251
ad7779_get_state
int32_t ad7779_get_state(ad7779_dev *dev, ad7779_ch ch, ad7779_state *state)
Definition: ad7779.c:450
ad7779_spi_int_reg_write
int32_t ad7779_spi_int_reg_write(ad7779_dev *dev, uint8_t reg_addr, uint8_t reg_data)
Definition: ad7779.c:144
AD7779_REG_SRC_UPDATE
#define AD7779_REG_SRC_UPDATE
Definition: ad7779.h:89
ad7779_dev::cached_reg_val
uint8_t cached_reg_val[AD7779_REG_SRC_UPDATE+1]
Definition: ad7779.h:274
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
AD7779_CRC8_POLY
#define AD7779_CRC8_POLY
Definition: ad7779.h:146
ad7779_spi_sar_read_code
int32_t ad7779_spi_sar_read_code(ad7779_dev *dev, ad7779_sar_mux mux_next_conv, uint16_t *sar_code)
Definition: ad7779.c:240
ad7779_init_param::dec_rate_dec
uint16_t dec_rate_dec
Definition: ad7779.h:297
ad7779_get_dec_rate
int32_t ad7779_get_dec_rate(ad7779_dev *dev, uint16_t *int_val, uint16_t *dec_val)
Definition: ad7779.c:597
AD7779_DCLK_DIV_32
@ AD7779_DCLK_DIV_32
Definition: ad7779.h:191
ad7779_dev::gpio_reset
struct no_os_gpio_desc * gpio_reset
Definition: ad7779.h:246
ad7779_spi_int_reg_write_mask
int32_t ad7779_spi_int_reg_write_mask(ad7779_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t data)
Definition: ad7779.c:194
ad7779_get_state
int32_t ad7779_get_state(ad7779_dev *dev, ad7779_ch ch, ad7779_state *state)
Definition: ad7779.c:450
AD7779_SD_CONV
@ AD7779_SD_CONV
Definition: ad7779.h:158
no_os_spi.h
Header file of SPI Interface.
ad7779_set_sync_offset
int32_t ad7779_set_sync_offset(ad7779_dev *dev, ad7779_ch ch, uint8_t sync_offset)
Definition: ad7779.c:745
ad7779_get_sync_offset
int32_t ad7779_get_sync_offset(ad7779_dev *dev, ad7779_ch ch, uint8_t *sync_offset)
Definition: ad7779.c:780
AD7779_REFX_N
@ AD7779_REFX_N
Definition: ad7779.h:208
ad7779_set_dclk_div
int32_t ad7779_set_dclk_div(ad7779_dev *dev, ad7779_dclk_div div)
Definition: ad7779.c:693
ad7779_dev::sar_mux
ad7779_sar_mux sar_mux
Definition: ad7779.h:272
AD7779_DGND_AVSS1A_ATT
@ AD7779_DGND_AVSS1A_ATT
Definition: ad7779.h:233
ad7779_spi_int_reg_read
int32_t ad7779_spi_int_reg_read(ad7779_dev *dev, uint8_t reg_addr, uint8_t *reg_data)
Definition: ad7779.c:108
AD7779_ENABLE
@ AD7779_ENABLE
Definition: ad7779.h:174
ad7779_get_ref_buf_op_mode
int32_t ad7779_get_ref_buf_op_mode(ad7779_dev *dev, ad7779_refx_pin refx_pin, ad7779_ref_buf_op_mode *mode)
Definition: ad7779.c:1038
ad7779_init_param::spi_crc_en
ad7779_state spi_crc_en
Definition: ad7779.h:293
AD7779_INT_REF
@ AD7779_INT_REF
Definition: ad7779.h:203
AD7779_REG_SRC_N_LSB
#define AD7779_REG_SRC_N_LSB
Definition: ad7779.h:86
AD7779_REG_CH_OFFSET_LOWER_BYTE
#define AD7779_REG_CH_OFFSET_LOWER_BYTE(ch)
Definition: ad7779.h:68
ad7779_set_reference_type
int32_t ad7779_set_reference_type(ad7779_dev *dev, ad7779_ref_type ref_type)
Definition: ad7779.c:651
ad7779_get_sync_offset
int32_t ad7779_get_sync_offset(ad7779_dev *dev, ad7779_ch ch, uint8_t *sync_offset)
Definition: ad7779.c:780
ad7779_set_ref_buf_op_mode
int32_t ad7779_set_ref_buf_op_mode(ad7779_dev *dev, ad7779_refx_pin refx_pin, ad7779_ref_buf_op_mode mode)
Definition: ad7779.c:962
ad7779_dev::dclk_div
ad7779_dclk_div dclk_div
Definition: ad7779.h:266
AD7779_DVBE_AVSSX
@ AD7779_DVBE_AVSSX
Definition: ad7779.h:219
ad7779_set_dec_rate
int32_t ad7779_set_dec_rate(ad7779_dev *dev, uint16_t int_val, uint16_t dec_val)
Definition: ad7779.c:539
ad7779_refx_pin
ad7779_refx_pin
Definition: ad7779.h:206
ad7771_set_sinc5_filter_state
int32_t ad7771_set_sinc5_filter_state(ad7779_dev *dev, ad7779_state state)
Definition: ad7779.c:1198
ad7779_remove
int32_t ad7779_remove(ad7779_dev *dev)
Free the resources allocated by ad7779_init().
Definition: ad7779.c:1389
ad7779_set_gain
int32_t ad7779_set_gain(ad7779_dev *dev, ad7779_ch ch, ad7779_gain gain)
Definition: ad7779.c:478
ad7779_dev::offset_corr
uint32_t offset_corr[8]
Definition: ad7779.h:268
no_os_delay.h
Header file of Delay functions.
pin_mode_options
const uint8_t pin_mode_options[16][4]
Definition: ad7779.c:51
ad7779_init_param::sinc5_state
ad7779_state sinc5_state
Definition: ad7779.h:305
ad7779_init
int32_t ad7779_init(ad7779_dev **device, ad7779_init_param init_param)
Definition: ad7779.c:1246
ad7779_get_dclk_div
int32_t ad7779_get_dclk_div(ad7779_dev *dev, ad7779_dclk_div *div)
Definition: ad7779.c:722
ad7779_spi_int_reg_write
int32_t ad7779_spi_int_reg_write(ad7779_dev *dev, uint8_t reg_addr, uint8_t reg_data)
Definition: ad7779.c:144
ad7779_get_spi_op_mode
int32_t ad7779_get_spi_op_mode(ad7779_dev *dev, ad7779_spi_op_mode *mode)
Definition: ad7779.c:319
ad7779_get_gain_corr
int32_t ad7779_get_gain_corr(ad7779_dev *dev, ad7779_ch ch, uint32_t *gain)
Definition: ad7779.c:935
device
Definition: ad9361_util.h:75
ad7779_dev::spi_crc_en
ad7779_state spi_crc_en
Definition: ad7779.h:258
NO_OS_GPIO_HIGH
@ NO_OS_GPIO_HIGH
Definition: no_os_gpio.h:123
AD7779_REFBUFN_PREQ
#define AD7779_REFBUFN_PREQ
Definition: ad7779.h:133
AD7779_REG_SRC_N_MSB
#define AD7779_REG_SRC_N_MSB
Definition: ad7779.h:85
AD7779_REG_DOUT_FORMAT
#define AD7779_REG_DOUT_FORMAT
Definition: ad7779.h:59
AD7779_GLOBAL_MUX_CTRL
#define AD7779_GLOBAL_MUX_CTRL(x)
Definition: ad7779.h:125
AD7779_REF2P_AVSSX
@ AD7779_REF2P_AVSSX
Definition: ad7779.h:238
AD7779_REF_BUF_PRECHARGED
@ AD7779_REF_BUF_PRECHARGED
Definition: ad7779.h:213
ad7779_set_power_mode
int32_t ad7779_set_power_mode(ad7779_dev *dev, ad7779_pwr_mode pwr_mode)
Definition: ad7779.c:615
ad7779_get_power_mode
int32_t ad7779_get_power_mode(ad7779_dev *dev, ad7779_pwr_mode *pwr_mode)
Definition: ad7779.c:635
AD7779_CH5
@ AD7779_CH5
Definition: ad7779.h:168
ad7779_set_gain_corr
int32_t ad7779_set_gain_corr(ad7779_dev *dev, ad7779_ch ch, uint32_t gain)
Definition: ad7779.c:887
ad7779_dev::gpio_convst_sar
struct no_os_gpio_desc * gpio_convst_sar
Definition: ad7779.h:255
AD7779_VCM_AVSSX
@ AD7779_VCM_AVSSX
Definition: ad7779.h:223
ad7779_dev::gain
ad7779_gain gain[8]
Definition: ad7779.h:261
ad7779_dev::state
ad7779_state state[8]
Definition: ad7779.h:260
ad7779_state
ad7779_state
Definition: ad7779.h:173
ad7779_dev::sync_offset
uint8_t sync_offset[8]
Definition: ad7779.h:267
AD7779_REG_CH_GAIN_MID_BYTE
#define AD7779_REG_CH_GAIN_MID_BYTE(ch)
Definition: ad7779.h:70
AD7779_REG_GENERAL_USER_CONFIG_1
#define AD7779_REG_GENERAL_USER_CONFIG_1
Definition: ad7779.h:56
AD7779_AUXAINP_AUXAINN
@ AD7779_AUXAINP_AUXAINN
Definition: ad7779.h:218
ad7779_dev::gpio_mode1
struct no_os_gpio_desc * gpio_mode1
Definition: ad7779.h:248
ad7779_set_power_mode
int32_t ad7779_set_power_mode(ad7779_dev *dev, ad7779_pwr_mode pwr_mode)
Definition: ad7779.c:615
ad7779_set_reference_type
int32_t ad7779_set_reference_type(ad7779_dev *dev, ad7779_ref_type ref_type)
Definition: ad7779.c:651
AD7779_REG_CH_DISABLE
#define AD7779_REG_CH_DISABLE
Definition: ad7779.h:54
ad7779_do_update_mode_pins
int32_t ad7779_do_update_mode_pins(ad7779_dev *dev)
Definition: ad7779.c:333
ad7779_set_dec_rate
int32_t ad7779_set_dec_rate(ad7779_dev *dev, uint16_t int_val, uint16_t dec_val)
Definition: ad7779.c:539
AD7779_PDB_REFOUT_BUF
#define AD7779_PDB_REFOUT_BUF
Definition: ad7779.h:102
NO_OS_GPIO_LOW
@ NO_OS_GPIO_LOW
Definition: no_os_gpio.h:121
AD7779_AVDD1A_AVSSX_ATT
@ AD7779_AVDD1A_AVSSX_ATT
Definition: ad7779.h:227
ad7779_set_spi_op_mode
int32_t ad7779_set_spi_op_mode(ad7779_dev *dev, ad7779_spi_op_mode mode)
Definition: ad7779.c:280
AD7779_DCLK_DIV_64
@ AD7779_DCLK_DIV_64
Definition: ad7779.h:192
ad7779_ch
ad7779_ch
Definition: ad7779.h:162
AD7779_SPI_CTRL
@ AD7779_SPI_CTRL
Definition: ad7779.h:153
ad7779_init_param::dec_rate_int
uint16_t dec_rate_int
Definition: ad7779.h:296
AD7779_REG_GENERAL_USER_CONFIG_3
#define AD7779_REG_GENERAL_USER_CONFIG_3
Definition: ad7779.h:58
AD7779_DCLK_DIV_8
@ AD7779_DCLK_DIV_8
Definition: ad7779.h:189
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
ad7779_dev::gpio_mode2
struct no_os_gpio_desc * gpio_mode2
Definition: ad7779.h:249
ad7779_spi_op_mode
ad7779_spi_op_mode
Definition: ad7779.h:156
ad7779_do_update_mode_pins
int32_t ad7779_do_update_mode_pins(ad7779_dev *dev)
Definition: ad7779.c:333
AD7779_REF2P_REF2N
@ AD7779_REF2P_REF2N
Definition: ad7779.h:221
AD7779_REF1P_AVSSX
@ AD7779_REF1P_AVSSX
Definition: ad7779.h:237
no_os_error.h
Error codes definition.
ad7779_dev::ref_buf_op_mode
ad7779_ref_buf_op_mode ref_buf_op_mode[2]
Definition: ad7779.h:270
AD7779_GAIN_2
@ AD7779_GAIN_2
Definition: ad7779.h:180
ad7779_ref_type
ad7779_ref_type
Definition: ad7779.h:201
AD7779_REG_GENERAL_USER_CONFIG_2
#define AD7779_REG_GENERAL_USER_CONFIG_2
Definition: ad7779.h:57
AD7779_REG_CH_OFFSET_MID_BYTE
#define AD7779_REG_CH_OFFSET_MID_BYTE(ch)
Definition: ad7779.h:67
AD7779_LOW_PWR
@ AD7779_LOW_PWR
Definition: ad7779.h:197
AD7779_REFX_P
@ AD7779_REFX_P
Definition: ad7779.h:207
AD7779_IOVDD_DGND_ATT
@ AD7779_IOVDD_DGND_ATT
Definition: ad7779.h:231
AD7779_REF_BUF_DISABLED
@ AD7779_REF_BUF_DISABLED
Definition: ad7779.h:214
AD7779_AVDD4_AVSSX
@ AD7779_AVDD4_AVSSX
Definition: ad7779.h:232
ad7779_dev::pwr_mode
ad7779_pwr_mode pwr_mode
Definition: ad7779.h:265
AD7779_DCLK_DIV_1
@ AD7779_DCLK_DIV_1
Definition: ad7779.h:186
ad7771_get_sinc5_filter_state
int32_t ad7771_get_sinc5_filter_state(ad7779_dev *dev, ad7779_state *state)
Definition: ad7779.c:1225
ad7779_set_sync_offset
int32_t ad7779_set_sync_offset(ad7779_dev *dev, ad7779_ch ch, uint8_t sync_offset)
Definition: ad7779.c:745
ad7779_dev::ref_type
ad7779_ref_type ref_type
Definition: ad7779.h:264
AD7779_REG_SRC_IF_MSB
#define AD7779_REG_SRC_IF_MSB
Definition: ad7779.h:87
ad7779_dev::spi_desc
no_os_spi_desc * spi_desc
Definition: ad7779.h:244
ad7779_spi_int_reg_read
int32_t ad7779_spi_int_reg_read(ad7779_dev *dev, uint8_t reg_addr, uint8_t *reg_data)
Definition: ad7779.c:108
AD7779_DREGCAP_DGND_ATT
@ AD7779_DREGCAP_DGND_ATT
Definition: ad7779.h:226
AD7779_AVDD4_AVSSX_ATT
@ AD7779_AVDD4_AVSSX_ATT
Definition: ad7779.h:236
AD7779_REG_GEN_ERR_REG_1_EN
#define AD7779_REG_GEN_ERR_REG_1_EN
Definition: ad7779.h:79
ad7779_set_state
int32_t ad7779_set_state(ad7779_dev *dev, ad7779_ch ch, ad7779_state state)
Definition: ad7779.c:420
ad7779_set_sar_cfg
int32_t ad7779_set_sar_cfg(ad7779_dev *dev, ad7779_state state, ad7779_sar_mux mux)
Definition: ad7779.c:1084
ad7779_gain
ad7779_gain
Definition: ad7779.h:178
ad7779_set_offset_corr
int32_t ad7779_set_offset_corr(ad7779_dev *dev, ad7779_ch ch, uint32_t offset)
Definition: ad7779.c:810
AD7779_REFBUFP_PREQ
#define AD7779_REFBUFP_PREQ
Definition: ad7779.h:132
AD7779_CH7
@ AD7779_CH7
Definition: ad7779.h:170
AD7779_AVDD1B_AVSSX_ATT
@ AD7779_AVDD1B_AVSSX_ATT
Definition: ad7779.h:228
ad7779_get_dclk_div
int32_t ad7779_get_dclk_div(ad7779_dev *dev, ad7779_dclk_div *div)
Definition: ad7779.c:722
AD7779_REF_BUF_POS_EN
#define AD7779_REF_BUF_POS_EN
Definition: ad7779.h:128
ad7779_get_gain_corr
int32_t ad7779_get_gain_corr(ad7779_dev *dev, ad7779_ch ch, uint32_t *gain)
Definition: ad7779.c:935
ad7779_compute_crc8
uint8_t ad7779_compute_crc8(uint8_t *data, uint8_t data_size)
Definition: ad7779.c:80
ad7779_set_offset_corr
int32_t ad7779_set_offset_corr(ad7779_dev *dev, ad7779_ch ch, uint32_t offset)
Definition: ad7779.c:810
no_os_gpio_remove
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:95
ad7779_dev::gpio_dclk1
struct no_os_gpio_desc * gpio_dclk1
Definition: ad7779.h:252
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
ad7771_get_sinc5_filter_state
int32_t ad7771_get_sinc5_filter_state(ad7779_dev *dev, ad7779_state *state)
Definition: ad7779.c:1225
AD7779_CH_GAIN
#define AD7779_CH_GAIN(x)
Definition: ad7779.h:92
ad7779_dev::gpio_mode3
struct no_os_gpio_desc * gpio_mode3
Definition: ad7779.h:250
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
AD7779_INT_REG
@ AD7779_INT_REG
Definition: ad7779.h:157
ad7779_sar_mux
ad7779_sar_mux
Definition: ad7779.h:217
AD7779_AVDD2B_AVSSX_ATT
@ AD7779_AVDD2B_AVSSX_ATT
Definition: ad7779.h:230
AD7779_GAIN_1
@ AD7779_GAIN_1
Definition: ad7779.h:179
AD7779_SPI_CRC_TEST_EN
#define AD7779_SPI_CRC_TEST_EN
Definition: ad7779.h:144
ad7779_do_spi_soft_reset
int32_t ad7779_do_spi_soft_reset(ad7779_dev *dev)
Definition: ad7779.c:1178
ad7779_spi_sar_read_code
int32_t ad7779_spi_sar_read_code(ad7779_dev *dev, ad7779_sar_mux mux_next_conv, uint16_t *sar_code)
Definition: ad7779.c:240
ad7779_get_dec_rate
int32_t ad7779_get_dec_rate(ad7779_dev *dev, uint16_t *int_val, uint16_t *dec_val)
Definition: ad7779.c:597
AD7779_GAIN_4
@ AD7779_GAIN_4
Definition: ad7779.h:181
ad7779_get_reference_type
int32_t ad7779_get_reference_type(ad7779_dev *dev, ad7779_ref_type *ref_type)
Definition: ad7779.c:671
ad7779_set_sar_cfg
int32_t ad7779_set_sar_cfg(ad7779_dev *dev, ad7779_state state, ad7779_sar_mux mux)
Definition: ad7779.c:1084
ad7779_ctrl_mode
ad7779_ctrl_mode
Definition: ad7779.h:151
ad7779_dev::gpio_mode0
struct no_os_gpio_desc * gpio_mode0
Definition: ad7779.h:247
AD7779_DGND_AVSSX_ATT
@ AD7779_DGND_AVSSX_ATT
Definition: ad7779.h:235
no_os_gpio_get
int32_t no_os_gpio_get(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Obtain the GPIO decriptor.
Definition: no_os_gpio.c:55
ad7779_dev
Definition: ad7779.h:242
AD7779_CH1
@ AD7779_CH1
Definition: ad7779.h:164
ad7779_get_reference_type
int32_t ad7779_get_reference_type(ad7779_dev *dev, ad7779_ref_type *ref_type)
Definition: ad7779.c:671
AD7779_DGND_AVSS1B_ATT
@ AD7779_DGND_AVSS1B_ATT
Definition: ad7779.h:234
AD7779_REG_CH_GAIN_LOWER_BYTE
#define AD7779_REG_CH_GAIN_LOWER_BYTE(ch)
Definition: ad7779.h:71
ad7771_set_sinc5_filter_state
int32_t ad7771_set_sinc5_filter_state(ad7779_dev *dev, ad7779_state state)
Definition: ad7779.c:1198
ad7779_do_single_sar_conv
int32_t ad7779_do_single_sar_conv(ad7779_dev *dev, ad7779_sar_mux mux, uint16_t *sar_code)
Definition: ad7779.c:1150
AD7779_REG_SRC_IF_LSB
#define AD7779_REG_SRC_IF_LSB
Definition: ad7779.h:88
AD7779_AVSSX_AVDD4_ATT
@ AD7779_AVSSX_AVDD4_ATT
Definition: ad7779.h:239
ad7779.h
Header file of AD7779 Driver.
AD7779_REF_BUF_NEG_EN
#define AD7779_REF_BUF_NEG_EN
Definition: ad7779.h:129
ad7779_init_param::dclk_div
ad7779_dclk_div dclk_div
Definition: ad7779.h:300
AD7779_EXT_REF
@ AD7779_EXT_REF
Definition: ad7779.h:202
AD7779_PDB_SAR
#define AD7779_PDB_SAR
Definition: ad7779.h:103
ad7779_get_offset_corr
int32_t ad7779_get_offset_corr(ad7779_dev *dev, ad7779_ch ch, uint32_t *offset)
Definition: ad7779.c:857
no_os_gpio_set_value
int32_t no_os_gpio_set_value(struct no_os_gpio_desc *desc, uint8_t value)
Set the value of the specified GPIO.
Definition: no_os_gpio.c:160
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
ad7779_get_power_mode
int32_t ad7779_get_power_mode(ad7779_dev *dev, ad7779_pwr_mode *pwr_mode)
Definition: ad7779.c:635
ad7779_set_gain_corr
int32_t ad7779_set_gain_corr(ad7779_dev *dev, ad7779_ch ch, uint32_t gain)
Definition: ad7779.c:887
AD7779_SPI_SLAVE_MODE_EN
#define AD7779_SPI_SLAVE_MODE_EN
Definition: ad7779.h:116
ad7779_dev::ctrl_mode
ad7779_ctrl_mode ctrl_mode
Definition: ad7779.h:257
AD7779_DISABLE
@ AD7779_DISABLE
Definition: ad7779.h:175
ad7779_dclk_div
ad7779_dclk_div
Definition: ad7779.h:185
AD7779_DCLK_DIV_2
@ AD7779_DCLK_DIV_2
Definition: ad7779.h:187
AD7779_DCLK_DIV_128
@ AD7779_DCLK_DIV_128
Definition: ad7779.h:193
ad7779_set_state
int32_t ad7779_set_state(ad7779_dev *dev, ad7779_ch ch, ad7779_state state)
Definition: ad7779.c:420
AD7779_CH2
@ AD7779_CH2
Definition: ad7779.h:165
ad7779_dev::sar_state
ad7779_state sar_state
Definition: ad7779.h:271
ad7779_spi_int_reg_write_mask
int32_t ad7779_spi_int_reg_write_mask(ad7779_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t data)
Definition: ad7779.c:194
ad7779_dev::gpio_sync_in
struct no_os_gpio_desc * gpio_sync_in
Definition: ad7779.h:254
ad7779_set_dclk_div
int32_t ad7779_set_dclk_div(ad7779_dev *dev, ad7779_dclk_div div)
Definition: ad7779.c:693
AD7779_CH0
@ AD7779_CH0
Definition: ad7779.h:163
ad7779_dev::dec_rate_dec
uint16_t dec_rate_dec
Definition: ad7779.h:263
AD7779_CH3
@ AD7779_CH3
Definition: ad7779.h:166
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
ad7779_do_single_sar_conv
int32_t ad7779_do_single_sar_conv(ad7779_dev *dev, ad7779_sar_mux mux, uint16_t *sar_code)
Definition: ad7779.c:1150
ad7779_init_param::spi_init
no_os_spi_init_param spi_init
Definition: ad7779.h:279
ad7779_set_spi_op_mode
int32_t ad7779_set_spi_op_mode(ad7779_dev *dev, ad7779_spi_op_mode mode)
Definition: ad7779.c:280
ad7779_pwr_mode
ad7779_pwr_mode
Definition: ad7779.h:196
no_os_gpio.h
Header file of GPIO Interface.
AD7779_CH6
@ AD7779_CH6
Definition: ad7779.h:169
ad7779_get_ref_buf_op_mode
int32_t ad7779_get_ref_buf_op_mode(ad7779_dev *dev, ad7779_refx_pin refx_pin, ad7779_ref_buf_op_mode *mode)
Definition: ad7779.c:1038
AD7779_REG_CH_CONFIG
#define AD7779_REG_CH_CONFIG(ch)
Definition: ad7779.h:53
ad7779_dev::spi_op_mode
ad7779_spi_op_mode spi_op_mode
Definition: ad7779.h:259
AD7779_CH_DISABLE
#define AD7779_CH_DISABLE(x)
Definition: ad7779.h:96
AD7779_REF1P_REF1N
@ AD7779_REF1P_REF1N
Definition: ad7779.h:220
ad7779_set_ref_buf_op_mode
int32_t ad7779_set_ref_buf_op_mode(ad7779_dev *dev, ad7779_refx_pin refx_pin, ad7779_ref_buf_op_mode mode)
Definition: ad7779.c:962
AD7779_AREG1CAP_AVSSX_ATT
@ AD7779_AREG1CAP_AVSSX_ATT
Definition: ad7779.h:224
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
ad7779_remove
int32_t ad7779_remove(ad7779_dev *dev)
Free the resources allocated by ad7779_init().
Definition: ad7779.c:1389
ad7779_set_gain
int32_t ad7779_set_gain(ad7779_dev *dev, ad7779_ch ch, ad7779_gain gain)
Definition: ad7779.c:478
AD7779_GAIN_8
@ AD7779_GAIN_8
Definition: ad7779.h:182
ad7779_get_offset_corr
int32_t ad7779_get_offset_corr(ad7779_dev *dev, ad7779_ch ch, uint32_t *offset)
Definition: ad7779.c:857
ad7779_init
int32_t ad7779_init(ad7779_dev **device, ad7779_init_param init_param)
Definition: ad7779.c:1246
ad7779_spi_int_reg_read_mask
int32_t ad7779_spi_int_reg_read_mask(ad7779_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t *data)
Definition: ad7779.c:172
ad7779_ref_buf_op_mode
ad7779_ref_buf_op_mode
Definition: ad7779.h:211
ad7779_dev::gpio_dclk2
struct no_os_gpio_desc * gpio_dclk2
Definition: ad7779.h:253
AD7779_DCLK_CLK_DIV
#define AD7779_DCLK_CLK_DIV(x)
Definition: ad7779.h:122
ad7779_init_param
Definition: ad7779.h:277
ad7779_get_spi_op_mode
int32_t ad7779_get_spi_op_mode(ad7779_dev *dev, ad7779_spi_op_mode *mode)
Definition: ad7779.c:319
AD7779_SAR_CONV
@ AD7779_SAR_CONV
Definition: ad7779.h:159
ad7779_do_spi_soft_reset
int32_t ad7779_do_spi_soft_reset(ad7779_dev *dev)
Definition: ad7779.c:1178
ad7779_get_gain
int32_t ad7779_get_gain(ad7779_dev *dev, ad7779_ch ch, ad7779_gain *gain)
Definition: ad7779.c:523
AD7771_FILTER_MODE
#define AD7771_FILTER_MODE
Definition: ad7779.h:108
no_os_gpio_direction_output
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:124
AD7779_AREG2CAP_AVSSX_ATT
@ AD7779_AREG2CAP_AVSSX_ATT
Definition: ad7779.h:225
AD7779_DCLK_DIV_4
@ AD7779_DCLK_DIV_4
Definition: ad7779.h:188
AD7779_DCLK_DIV_16
@ AD7779_DCLK_DIV_16
Definition: ad7779.h:190
AD7779_REF_OUT_AVSSX
@ AD7779_REF_OUT_AVSSX
Definition: ad7779.h:222
AD7779_HIGH_RES
@ AD7779_HIGH_RES
Definition: ad7779.h:198
AD7779_CH4
@ AD7779_CH4
Definition: ad7779.h:167
AD7779_REG_BUFFER_CONFIG_1
#define AD7779_REG_BUFFER_CONFIG_1
Definition: ad7779.h:64
AD7779_REF_BUF_ENABLED
@ AD7779_REF_BUF_ENABLED
Definition: ad7779.h:212
ad7779_dev::gain_corr
uint32_t gain_corr[8]
Definition: ad7779.h:269
ad7779_get_sar_cfg
int32_t ad7779_get_sar_cfg(ad7779_dev *dev, ad7779_state *state, ad7779_sar_mux *mux)
Definition: ad7779.c:1111
AD7779_SAR_DIAG_MODE_EN
#define AD7779_SAR_DIAG_MODE_EN
Definition: ad7779.h:109
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112