no-OS
parameters.h
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1 /***************************************************************************/
39 #ifndef APP_PARAMETERS_H_
40 #define APP_PARAMETERS_H_
41 
42 #include <xparameters.h>
43 
44 /******************************************************************************/
45 /********************** Macros and Constants Definitions **********************/
46 /******************************************************************************/
47 #define UART_BAUDRATE 115200
48 
49 #ifdef XPS_BOARD_ZCU102
50 #define GPIO_OFFSET 78
51 #else
52 #define GPIO_OFFSET 0
53 #endif
54 
55 #define PHY_CS 0
56 
57 #ifdef QUAD_MXFE
58 #define ADF4371_CS 0
59 #define HMC7043_CS 4
60 
61 #define PHY_RESET (GPIO_OFFSET + 41)
62 
63 #define ADRF5020_CTRL_GPIO (GPIO_OFFSET + 34)
64 #define AD9081_GPIO_0_MUX (GPIO_OFFSET + 44)
65 
66 #define GPIO_2_DEVICE_ID XPAR_AXI_GPIO_2_DEVICE_ID
67 #define SPI_2_DEVICE_ID XPAR_AXI_SPI_2_DEVICE_ID
68 
69 #else
70 #define PHY_RESET (GPIO_OFFSET + 55)
71 #endif
72 
73 #if defined(PLATFORM_MB)
74 #define GPIO_DEVICE_ID XPAR_AXI_GPIO_DEVICE_ID
75 #define PHY_SPI_DEVICE_ID XPAR_AXI_SPI_DEVICE_ID
76 #define CLK_SPI_DEVICE_ID XPAR_AXI_SPI_DEVICE_ID
77 #define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
78 #define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
79 #define DDR_CNTRL_BASEADDR XPAR_AXI_DDR_CNTRL_BASEADDR
80 #define CLK_CS 1
81 #elif defined(PLATFORM_ZYNQMP)
82 #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
83 #define GPIO_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
84 #define PHY_SPI_DEVICE_ID XPAR_PSU_SPI_0_DEVICE_ID
85 #define CLK_SPI_DEVICE_ID XPAR_PSU_SPI_1_DEVICE_ID
86 #define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
87 #define UART_IRQ_ID XPAR_XUARTPS_0_INTR
88 #define DDR_CNTRL_BASEADDR XPAR_PSU_DDRC_0_BASEADDR
89 #define CLK_CS 0
90 #else
91 #error Unsupported platform.
92 #endif
93 
94 #define RX_JESD_BASEADDR XPAR_AXI_MXFE_RX_JESD_RX_AXI_BASEADDR
95 #define TX_JESD_BASEADDR XPAR_AXI_MXFE_TX_JESD_TX_AXI_BASEADDR
96 
97 #ifdef XPAR_AXI_MXFE_RX_XCVR_BASEADDR
98 #define RX_XCVR_BASEADDR XPAR_AXI_MXFE_RX_XCVR_BASEADDR
99 #endif
100 #ifdef XPAR_AXI_MXFE_TX_XCVR_BASEADDR
101 #define TX_XCVR_BASEADDR XPAR_AXI_MXFE_TX_XCVR_BASEADDR
102 #endif
103 
104 #ifdef XPAR_RX_MXFE_TPL_CORE_ADC_TPL_CORE_BASEADDR
105 #define RX_CORE_BASEADDR XPAR_RX_MXFE_TPL_CORE_ADC_TPL_CORE_BASEADDR
106 #else
107 #define RX_CORE_BASEADDR XPAR_RX_MXFE_TPL_CORE_TPL_CORE_BASEADDR
108 #endif
109 #ifdef XPAR_TX_MXFE_TPL_CORE_DAC_TPL_CORE_BASEADDR
110 #define TX_CORE_BASEADDR XPAR_TX_MXFE_TPL_CORE_DAC_TPL_CORE_BASEADDR
111 #else
112 #define TX_CORE_BASEADDR XPAR_TX_MXFE_TPL_CORE_TPL_CORE_BASEADDR
113 #endif
114 
115 #define RX_DMA_BASEADDR XPAR_AXI_MXFE_RX_DMA_BASEADDR
116 #define TX_DMA_BASEADDR XPAR_AXI_MXFE_TX_DMA_BASEADDR
117 
118 #ifdef IIO_SUPPORT
119 
120 #define MAX_DAC_BUF_SAMPLES 10000000 //1MB
121 #define MAX_ADC_BUF_SAMPLES 10000000 //1MB
122 
123 #endif
124 
125 #endif