no-OS
app_clocking.h
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1 /***************************************************************************/
39 #ifndef __APP_CLOCKING_H
40 #define __APP_CLOCKING_H
41 
42 #include <stdint.h>
43 #include "ad9528.h"
44 
50  /* Settings selection */
51  uint8_t uc;
52  /* jesd receive clock */
53  uint32_t lmfc_rate_hz;
54 };
55 
60 struct app_clocking {
61  /* Structure holding a clock device descriptor */
63 };
64 
65 /* @brief Application clocking setup. */
66 int32_t app_clocking_init(struct app_clocking **app,
68 
69 /* @brief Application clocking remove. */
70 int32_t app_clocking_remove(struct app_clocking *app);
71 
72 #endif /* __APP_CLOCKING_H */
axi_clkgen_init::name
const char * name
Definition: clk_axi_clkgen.h:57
SYSREF_SRC_INTERNAL
#define SYSREF_SRC_INTERNAL
Definition: ad9528.h:279
app_clocking_init::uc
uint8_t uc
Definition: app_clocking.h:51
axi_clkgen::name
const char * name
Definition: clk_axi_clkgen.h:51
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
app_talise.h
Talise initialization and control routines.
app_config.h
Config file for ADRV9009 project.
SYSREF_NSHOT_4_PULSES
#define SYSREF_NSHOT_4_PULSES
Definition: ad9528.h:291
NIOS_II_GPIO
@ NIOS_II_GPIO
Definition: gpio_extra.h:59
TX_CLKGEN_BASEADDR
#define TX_CLKGEN_BASEADDR
Definition: parameters.h:127
clocking_init
adiHalErr_t clocking_init(uint32_t rx_div40_rate_hz, uint32_t tx_div40_rate_hz, uint32_t rx_os_div40_rate_hz, uint32_t device_clock_khz, uint32_t lmfc_rate_hz)
Definition: app_clocking.c:99
altera_a10_fpll_enable
int32_t altera_a10_fpll_enable(struct altera_a10_fpll *fpll)
altera_a10_fpll_enable
Definition: clk_altera_a10_fpll.c:453
DRIVER_MODE_HSTL
#define DRIVER_MODE_HSTL
Definition: ad9528.h:259
ad9528_init_param::spi_init
no_os_spi_init_param spi_init
Definition: ad9528.h:492
rx_clkgen
struct axi_clkgen * rx_clkgen
Definition: app_clocking.c:94
no_os_spi.h
Header file of SPI Interface.
app_clocking
Structure holding clocking app descriptor.
Definition: app_clocking.h:60
RPOLE2_900_OHM
@ RPOLE2_900_OHM
Definition: ad9523.h:342
parameters.h
Parameters Definitions.
ad9528_platform_data::pll2_charge_pump_current_nA
uint32_t pll2_charge_pump_current_nA
Definition: ad9528.h:419
ad9528_channel_spec
Output channel configuration.
Definition: ad9528.h:334
hmc7044.h
Header file of HMC7044, HMC7043 Driver.
clk_axi_clkgen.h
Driver for the Analog Devices AXI CLKGEN.
ADC_SYSREF_CLK
#define ADC_SYSREF_CLK
Definition: app_clocking.c:65
ad9528_platform_data::pll2_bypass_en
bool pll2_bypass_en
Definition: ad9528.h:433
pr_err
#define pr_err(fmt, args...)
Definition: no_os_print_log.h:80
GPIO_PL
@ GPIO_PL
Definition: gpio_extra.h:60
ad9528_platform_data::num_channels
uint32_t num_channels
Definition: ad9528.h:447
clocking_deinit
void clocking_deinit(void)
Definition: app_clocking.c:728
no_os_delay.h
Header file of Delay functions.
uc_settings
Definition: uc_settings.h:47
ad9528_clk_set_rate
int32_t ad9528_clk_set_rate(struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
Set channel rate.
Definition: ad9528.c:794
axi_clkgen_init
Definition: clk_axi_clkgen.h:56
ad9528_platform_data::refa_en
uint8_t refa_en
Definition: ad9528.h:365
hmc7044_init
int32_t hmc7044_init(struct hmc7044_dev **device, const struct hmc7044_init_param *init_param)
Definition: hmc7044.c:788
axi_clkgen_set_rate
int32_t axi_clkgen_set_rate(struct axi_clkgen *clkgen, uint32_t rate)
axi_clkgen_set_rate
Definition: clk_axi_clkgen.c:418
ad9528_platform_data::pll2_r1_div
uint8_t pll2_r1_div
Definition: ad9528.h:427
xil_gpio_param
struct xil_gpio_init_param xil_gpio_param
Definition: ad7616_sdz.c:86
app_clocking.h
Clock setup and initialization routines.
ad9528_platform_data::spi3wire
uint8_t spi3wire
Definition: ad9528.h:362
ad9528_init_param
Definition: ad9528.h:490
FPGA_REF_CLK
#define FPGA_REF_CLK
Definition: app_clocking.c:64
no_os_gpio_init_param::number
int32_t number
Definition: no_os_gpio.h:89
no_os_print_log.h
Print messages helpers.
altera_a10_fpll_init::name
const char * name
Definition: clk_altera_a10_fpll.h:58
FMC_SYSREF
#define FMC_SYSREF
Definition: app_clocking.h:67
axi_clkgen_init
int32_t axi_clkgen_init(struct axi_clkgen **clk, const struct axi_clkgen_init *init)
axi_clkgen_init
Definition: clk_axi_clkgen.c:524
ad9528_platform_data::rpole2
uint8_t rpole2
Definition: ad9528.h:437
axi_clkgen
Definition: clk_axi_clkgen.h:50
ad9528_clk_round_rate
uint32_t ad9528_clk_round_rate(struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
Calculate closest possible rate.
Definition: ad9528.c:755
DRIVER_MODE_LVDS
#define DRIVER_MODE_LVDS
Definition: ad9528.h:257
SYSREF_NSHOT_1_PULSE
#define SYSREF_NSHOT_1_PULSE
Definition: ad9528.h:289
CPOLE1_16_PF
@ CPOLE1_16_PF
Definition: ad9523.h:362
uc_settings::clk_hz
uint64_t(* clk_hz)[3]
Definition: uc_settings.h:49
altera_a10_fpll_set_rate
int32_t altera_a10_fpll_set_rate(struct altera_a10_fpll *fpll, uint32_t rate)
altera_a10_fpll_set_rate
Definition: clk_altera_a10_fpll.c:345
ad9528_platform_data::sysref_req_en
bool sysref_req_en
Definition: ad9528.h:415
adi_hal.h
Contains Talise ADI HAL function prototypes type definitions for adi_hal.c.
app_ad9083_check_sysref_rate
bool app_ad9083_check_sysref_rate(uint32_t lmfc, uint32_t sysref)
Check sysref is submultiple of lmfc.
Definition: app_ad9083.c:67
ad9528_platform_data::sysref_req_trigger_mode
uint8_t sysref_req_trigger_mode
Definition: ad9528.h:413
ADC_REF_CLK
#define ADC_REF_CLK
Definition: app_clocking.c:66
xil_gpio_ops
const struct no_os_gpio_platform_ops xil_gpio_ops
Xilinx platform specific gpio platform ops structure.
Definition: xilinx_gpio.c:455
altera_a10_fpll_remove
int32_t altera_a10_fpll_remove(struct altera_a10_fpll *fpll)
altera_a10_fpll_remove
Definition: clk_altera_a10_fpll.c:492
altera_spi_ops
const struct no_os_spi_platform_ops altera_spi_ops
Altera platform specific SPI platform ops structure.
Definition: altera_spi.c:161
no_os_spi_init_param::device_id
uint32_t device_id
Definition: no_os_spi.h:114
RX_OS_CLKGEN_BASEADDR
#define RX_OS_CLKGEN_BASEADDR
Definition: parameters.h:128
app_clocking::clkchip_device
struct ad9528_dev * clkchip_device
Definition: app_clocking.h:62
app_clocking.h
Clock setup and initialization routines.
SYSREF_PATTERN_NSHOT
#define SYSREF_PATTERN_NSHOT
Definition: ad9528.h:282
hmc7044_chan_spec
Definition: hmc7044.h:53
ad9528_platform_data::vcxo_freq
uint32_t vcxo_freq
Definition: ad9528.h:360
get_uc_settings
struct uc_settings * get_uc_settings()
Get use case settings.
Definition: uc_settings.c:196
ad9528_platform_data::pll2_vco_div_m1
uint8_t pll2_vco_div_m1
Definition: ad9528.h:431
ad9528_platform_data::osc_in_cmos_neg_inp_en
uint8_t osc_in_cmos_neg_inp_en
Definition: ad9528.h:385
hmc7044_clk_set_rate
int32_t hmc7044_clk_set_rate(struct hmc7044_dev *dev, uint32_t chan_num, uint64_t rate)
Definition: hmc7044.c:374
no_os_error.h
Error codes definition.
ad9528_platform_data::sysref_nshot_mode
uint8_t sysref_nshot_mode
Definition: ad9528.h:411
uc_settings.h
Use Case Settings of AD9083 project.
DEV_SYSREF
#define DEV_SYSREF
Definition: app_clocking.h:66
hmc7044_remove
int32_t hmc7044_remove(struct hmc7044_dev *device)
Definition: hmc7044.c:889
ad9528_init_param::gpio_resetb
no_os_gpio_init_param * gpio_resetb
Definition: ad9528.h:494
app_clocking_init::lmfc_rate_hz
uint32_t lmfc_rate_hz
Definition: app_clocking.h:53
clk_hz
uint64_t clk_hz[][3]
Definition: uc_settings.c:22
FPGA_SYSREF_CLK
#define FPGA_SYSREF_CLK
Definition: app_clocking.c:62
altera_spi_init_param
Structure holding the initialization parameters for Altera platform specific SPI parameters.
Definition: spi_extra.h:62
clkchip_device
struct ad9528_dev * clkchip_device
Definition: app_clocking.c:86
hmc7044_chan_spec::disable
bool disable
Definition: hmc7044.h:55
ad9528_platform_data::pll1_feedback_src_vcxo
uint8_t pll1_feedback_src_vcxo
Definition: ad9528.h:395
tx_clkgen
struct axi_clkgen * tx_clkgen
Definition: app_clocking.c:95
ad9528_platform_data
platform specific information
Definition: ad9528.h:358
hmc7044_init_param
Definition: hmc7044.h:93
altera_gpio_init_param::type
enum gpio_type type
Definition: gpio_extra.h:69
adrv9009_check_sysref_rate
bool adrv9009_check_sysref_rate(uint32_t lmfc, uint32_t sysref)
Definition: app_talise.c:76
SYSREF_PATTERN_CONTINUOUS
#define SYSREF_PATTERN_CONTINUOUS
Definition: ad9528.h:283
ad9528_platform_data::rzero
uint8_t rzero
Definition: ad9528.h:439
CLK_RESETB_GPIO
#define CLK_RESETB_GPIO
Definition: parameters.h:174
NIOS_II_SPI
@ NIOS_II_SPI
Definition: spi_extra.h:54
ADIHAL_OK
@ ADIHAL_OK
Definition: adi_hal.h:36
ad9528_platform_data::sysref_pattern_mode
uint8_t sysref_pattern_mode
Definition: ad9528.h:407
xil_spi_init_param::type
enum xil_spi_type type
Definition: spi_extra.h:80
clk_altera_a10_fpll.h
Driver for the Altera FPLL.
altera_a10_fpll::name
const char * name
Definition: clk_altera_a10_fpll.h:51
CLK_AD9258_CS
#define CLK_AD9258_CS
Definition: parameters.h:53
app_ad9083.h
RX_CLKGEN_BASEADDR
#define RX_CLKGEN_BASEADDR
Definition: parameters.h:52
FPGA_GLBL_CLK
#define FPGA_GLBL_CLK
Definition: app_clocking.c:63
hmc7044_init_param::pll2_freq
uint32_t pll2_freq
Definition: hmc7044.h:100
xil_spi_init_param
Structure holding the initialization parameters for Xilinx platform specific SPI parameters when usin...
Definition: spi_extra.h:78
ad9528_platform_data::cpole1
uint8_t cpole1
Definition: ad9528.h:441
ad9528_platform_data::pll2_n2_div
uint8_t pll2_n2_div
Definition: ad9528.h:429
hmc7044_init_param::spi_init
no_os_spi_init_param * spi_init
Definition: hmc7044.h:94
hmc7044_dev
Definition: hmc7044.h:69
app_clocking_init
int32_t app_clocking_init(struct app_clocking **app, struct app_clocking_init *init_param)
Initialize the clocking app.
Definition: app_clocking.c:79
SOURCE_VCO
#define SOURCE_VCO
Definition: ad9528.h:262
altera_gpio_init_param
Structure holding the initialization parameters for Altera platform specific GPIO parameters.
Definition: gpio_extra.h:67
app_clocking_init
Structure holding the parameters for clocking app initialization.
Definition: app_clocking.h:49
ad9528_platform_data::refa_r_div
uint16_t refa_r_div
Definition: ad9528.h:389
altera_a10_fpll_init
Definition: clk_altera_a10_fpll.h:57
rx_os_clkgen
struct axi_clkgen * rx_os_clkgen
Definition: app_clocking.c:96
ad9528_dev
Definition: ad9528.h:480
ad9528_remove
int32_t ad9528_remove(struct ad9528_dev *dev)
Free the resources allocated by ad9528_setup().
Definition: ad9528.c:712
ad9528_channel_spec::divider_phase
uint8_t divider_phase
Definition: ad9528.h:347
ad9528_channel_spec::driver_mode
uint8_t driver_mode
Definition: ad9528.h:342
FMC_CLK
#define FMC_CLK
Definition: app_clocking.h:65
NULL
#define NULL
Definition: wrapper.h:64
ad9528_platform_data::sysref_src
uint8_t sysref_src
Definition: ad9528.h:405
SPI_PS
@ SPI_PS
Definition: spi_extra.h:68
xil_spi_ops
const struct no_os_spi_platform_ops xil_spi_ops
Spi engine platform specific SPI platform ops structure.
Definition: xilinx_spi.c:456
app_clocking_remove
int32_t app_clocking_remove(struct app_clocking *app)
Free the resources allocated by app_clocking_init().
Definition: app_clocking.c:260
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
CLK_CS
#define CLK_CS
Definition: parameters.h:163
altera_a10_fpll
Definition: clk_altera_a10_fpll.h:50
SOURCE_SYSREF_VCO
#define SOURCE_SYSREF_VCO
Definition: ad9528.h:264
hmc7044_init_param::channels
struct hmc7044_chan_spec * channels
Definition: hmc7044.h:114
altera_a10_fpll_init
int32_t altera_a10_fpll_init(struct altera_a10_fpll **a10_fpll, const struct altera_a10_fpll_init *init)
altera_a10_fpll_init
Definition: clk_altera_a10_fpll.c:471
ad9528_platform_data::pll1_feedback_div
uint16_t pll1_feedback_div
Definition: ad9528.h:393
ad9528_init_param::pdata
struct ad9528_platform_data * pdata
Definition: ad9528.h:496
GPIO_DEVICE_ID
#define GPIO_DEVICE_ID
Definition: parameters.h:77
hmc7044_clk_round_rate
int32_t hmc7044_clk_round_rate(struct hmc7044_dev *dev, uint32_t rate, uint64_t *rounded_rate)
Definition: hmc7044.c:357
altera_a10_fpll_disable
void altera_a10_fpll_disable(struct altera_a10_fpll *fpll)
altera_a10_fpll_disable
Definition: clk_altera_a10_fpll.c:463
ad9528_init
int32_t ad9528_init(struct ad9528_init_param *init_param)
Initializes the AD9528.
Definition: ad9528.c:295
xil_gpio_init_param
Structure holding the initialization parameters for Xilinx platform specific GPIO parameters.
Definition: gpio_extra.h:70
ad9528_platform_data::stat0_pin_func_sel
uint8_t stat0_pin_func_sel
Definition: ad9528.h:452
ad9528_platform_data::refa_diff_rcv_en
uint8_t refa_diff_rcv_en
Definition: ad9528.h:370
ad9528_platform_data::channels
struct ad9528_channel_spec * channels
Definition: ad9528.h:449
ad9528_platform_data::stat1_pin_func_sel
uint8_t stat1_pin_func_sel
Definition: ad9528.h:454
ADIHAL_ERR
@ ADIHAL_ERR
Definition: adi_hal.h:43
no_os_gpio.h
Header file of GPIO Interface.
ad9528_channel_spec::output_dis
uint8_t output_dis
Definition: ad9528.h:340
axi_clkgen_remove
int32_t axi_clkgen_remove(struct axi_clkgen *clkgen)
axi_clkgen_remove
Definition: clk_axi_clkgen.c:545
app_clocking_init
int32_t app_clocking_init(struct app_clocking **app, struct app_clocking_init *init_param)
Initialize the clocking app.
Definition: app_clocking.c:79
no_os_util.h
Implementation of utility functions.
SYSREF_LEVEL_HIGH
#define SYSREF_LEVEL_HIGH
Definition: ad9528.h:297
ad9528_channel_spec::signal_source
uint8_t signal_source
Definition: ad9528.h:343
ad9528_platform_data::pll1_charge_pump_current_nA
uint16_t pll1_charge_pump_current_nA
Definition: ad9528.h:397
ad9528_platform_data::pll1_bypass_en
uint8_t pll1_bypass_en
Definition: ad9528.h:399
NO_OS_SPI_MODE_0
@ NO_OS_SPI_MODE_0
Definition: no_os_spi.h:66
altera_spi_init_param::type
enum spi_type type
Definition: spi_extra.h:64
DEV_CLK
#define DEV_CLK
Definition: app_clocking.h:64
ad9528_channel_spec::channel_num
uint8_t channel_num
Definition: ad9528.h:336
xil_gpio_init_param::type
enum xil_gpio_type type
Definition: gpio_extra.h:72
ad9528_setup
int32_t ad9528_setup(struct ad9528_dev **device, struct ad9528_init_param init_param)
Initializes the AD9528.
Definition: ad9528.c:355
GPIO_PS
@ GPIO_PS
Definition: gpio_extra.h:62
RZERO_1850_OHM
@ RZERO_1850_OHM
Definition: ad9523.h:356
SPI_CS_DECODE
#define SPI_CS_DECODE
Definition: spi_extra.h:53
SPI_PL
@ SPI_PL
Definition: spi_extra.h:66
app_clocking_remove
int32_t app_clocking_remove(struct app_clocking *app)
Free the resources allocated by app_clocking_init().
Definition: app_clocking.c:260
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
adiHalErr_t
adiHalErr_t
Enum of possible Errors Detected by HAL layer to be communicated to ADI APIs.
Definition: adi_hal.h:35