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54 #define REG_SPI_INTFCONFA 0x000
55 #define REG_SPI_INTFCONFB 0x001
56 #define REG_SPI_DEVCONF 0x002
57 #define REG_SPI_PRODIDL 0x004
58 #define REG_SPI_PRODIDH 0x005
59 #define REG_SPI_CHIPGRADE 0x006
60 #define REG_SPI_PAGEINDX 0x008
61 #define REG_SPI_DEVINDX2 0x009
62 #define REG_SPI_SCRATCHPAD 0x00A
63 #define REG_SPI_MS_UPDATE 0x00F
64 #define REG_PWRCNTRL0 0x011
65 #define REG_TXENMASK1 0x012
66 #define REG_PWRCNTRL3 0x013
67 #define REG_COARSE_GROUP_DLY 0x014
68 #define REG_IRQ_ENABLE0 0x01F
69 #define REG_IRQ_ENABLE1 0x020
70 #define REG_IRQ_ENABLE2 0x021
71 #define REG_IRQ_ENABLE3 0x022
72 #define REG_IRQ_STATUS0 0x023
73 #define REG_IRQ_STATUS1 0x024
74 #define REG_IRQ_STATUS2 0x025
75 #define REG_IRQ_STATUS3 0x026
76 #define REG_JESD_CHECKS 0x030
77 #define REG_SYNC_TESTCTRL 0x031
78 #define REG_SYNC_DACDELAY_L 0x032
79 #define REG_SYNC_DACDELAY_H 0x033
80 #define REG_SYNC_ERRWINDOW 0x034
81 #define REG_SYNC_DLYCOUNT 0x035
82 #define REG_SYNC_REFCOUNT 0x036
83 #define REG_SYNC_LASTERR_L 0x038
84 #define REG_SYNC_LASTERR_H 0x039
85 #define REG_SYNC_CTRL 0x03A
86 #define REG_SYNC_STATUS 0x03B
87 #define REG_SYNC_CURRERR_L 0x03C
88 #define REG_SYNC_CURRERR_H 0x03D
89 #define REG_ERROR_THERM 0x03E
90 #define REG_DACGAIN0_1 0x040
91 #define REG_DACGAIN0_0 0x041
92 #define REG_DACGAIN1_1 0x042
93 #define REG_DACGAIN1_0 0x043
94 #define REG_DACGAIN2_1 0x044
95 #define REG_DACGAIN2_0 0x045
96 #define REG_DACGAIN3_1 0x046
97 #define REG_DACGAIN3_0 0x047
98 #define REG_PD_DACLDO 0x048
99 #define REG_STAT_DACLDO 0x049
100 #define REG_DECODE_CTRL0 0x04B
101 #define REG_DECODE_CTRL1 0x04C
102 #define REG_DECODE_CTRL2 0x04D
103 #define REG_DECODE_CTRL3 0x04E
104 #define REG_NCO_CLRMODE 0x050
105 #define REG_NCOKEY_ILSB 0x051
106 #define REG_NCOKEY_IMSB 0x052
107 #define REG_NCOKEY_QLSB 0x053
108 #define REG_NCOKEY_QMSB 0x054
109 #define REG_PA_THRES0 0x060
110 #define REG_PA_THRES1 0x061
111 #define REG_PA_AVG_TIME 0x062
112 #define REG_PA_POWER0 0x063
113 #define REG_PA_POWER1 0x064
114 #define REG_CLKCFG0 0x080
115 #define REG_SYSREF_ACTRL0 0x081
116 #define REG_SYSREF_ACTRL1 0x082
117 #define REG_DACPLLCNTRL 0x083
118 #define REG_DACPLLSTATUS 0x084
119 #define REG_DACINTEGERWORD0 0x085
120 #define REG_DACLOOPFILT1 0x087
121 #define REG_DACLOOPFILT2 0x088
122 #define REG_DACLOOPFILT3 0x089
123 #define REG_DACCPCNTRL 0x08A
124 #define REG_DACLOGENCNTRL 0x08B
125 #define REG_DACLDOCNTRL1 0x08C
126 #define REG_CAL_DAC_ERR 0x0E0
127 #define REG_CAL_MSB_THRES 0x0E1
128 #define REG_CAL_CTRL_GLOBAL 0x0E2
129 #define REG_CAL_MSBHILVL 0x0E3
130 #define REG_CAL_MSBLOLVL 0x0E4
131 #define REG_CAL_THRESH 0x0E5
132 #define REG_CAL_AVG_CNT 0x0E6
133 #define REG_CAL_CLKDIV 0x0E7
134 #define REG_CAL_INDX 0x0E8
135 #define REG_CAL_CTRL 0x0E9
136 #define REG_CAL_ADDR 0x0EA
137 #define REG_CAL_DATA 0x0EB
138 #define REG_CAL_UPDATE 0x0EC
139 #define REG_CAL_INIT 0x0ED
140 #define REG_DATA_FORMAT 0x110
141 #define REG_DATAPATH_CTRL 0x111
142 #define REG_INTERP_MODE 0x112
143 #define REG_NCO_FTW_UPDATE 0x113
144 #define REG_FTW0 0x114
145 #define REG_FTW1 0x115
146 #define REG_FTW2 0x116
147 #define REG_FTW3 0x117
148 #define REG_FTW4 0x118
149 #define REG_FTW5 0x119
150 #define REG_NCO_PHASE_OFFSET0 0x11A
151 #define REG_NCO_PHASE_OFFSET1 0x11B
152 #define REG_NCO_PHASE_ADJ0 0x11C
153 #define REG_NCO_PHASE_ADJ1 0x11D
154 #define REG_TXEN_FUNC 0x11E
155 #define REG_TXEN_SM_0 0x11F
156 #define REG_TXEN_SM_1 0x120
157 #define REG_TXEN_SM_2 0x121
158 #define REG_TXEN_SM_3 0x122
159 #define REG_TXEN_SM_4 0x123
160 #define REG_TXEN_SM_5 0x124
161 #define REG_DACOUT_ON_DOWN 0x125
162 #define REG_DACOFF 0x12C
163 #define REG_DATA_PATH_FLUSH_COUNT0 0x12D
164 #define REG_DATA_PATH_FLUSH_COUNT1 0x12E
165 #define REG_DIE_TEMP_CTRL0 0x12F
166 #define REG_DIE_TEMP_CTRL1 0x130
167 #define REG_DIE_TEMP_CTRL2 0x131
168 #define REG_DIE_TEMP0 0x132
169 #define REG_DIE_TEMP1 0x133
170 #define REG_DIE_TEMP_UPDATE 0x134
171 #define REG_DC_OFFSET_CTRL 0x135
172 #define REG_IPATH_DC_OFFSET_1PART0 0x136
173 #define REG_IPATH_DC_OFFSET_1PART1 0x137
174 #define REG_QPATH_DC_OFFSET_1PART0 0x138
175 #define REG_QPATH_DC_OFFSET_1PART1 0x139
176 #define REG_IPATH_DC_OFFSET_2PART 0x13A
177 #define REG_QPATH_DC_OFFSET_2PART 0x13B
178 #define REG_IDAC_DIG_GAIN0 0x13C
179 #define REG_IDAC_DIG_GAIN1 0x13D
180 #define REG_QDAC_DIG_GAIN0 0x13E
181 #define REG_QDAC_DIG_GAIN1 0x13F
182 #define REG_GAIN_RAMP_UP_STP0 0x140
183 #define REG_GAIN_RAMP_UP_STP1 0x141
184 #define REG_GAIN_RAMP_DOWN_STP0 0x142
185 #define REG_GAIN_RAMP_DOWN_STP1 0x143
186 #define REG_BLSM_CTRL 0x146
187 #define REG_BLSM_STAT 0x147
188 #define REG_PRBS 0x14B
189 #define REG_PRBS_ERROR_I 0x14C
190 #define REG_PRBS_ERROR_Q 0x14D
191 #define REG_DACPLLT5 0x1B5
192 #define REG_DACPLLTB 0x1BB
193 #define REG_DACPLLTD 0x1BD
194 #define REG_DACPLLT17 0x1C4
195 #define REG_DACPLLT18 0x1C5
196 #define REG_ASPI_SPARE0 0x1C6
197 #define REG_ASPI_SPARE1 0x1C7
198 #define REG_SPISTRENGTH 0x1DF
199 #define REG_CLK_TEST 0x1EB
200 #define REG_ATEST_VOLTS 0x1EC
201 #define REG_ASPI_CLKSRC 0x1ED
202 #define REG_MASTER_PD 0x200
203 #define REG_PHY_PD 0x201
204 #define REG_GENERIC_PD 0x203
205 #define REG_CDR_RESET 0x206
206 #define REG_CDR_OPERATING_MODE_REG_0 0x230
207 #define REG_CONFIG_REG3 0x232
208 #define REG_EQ_CONFIG_PHY_0_1 0x250
209 #define REG_EQ_CONFIG_PHY_2_3 0x251
210 #define REG_EQ_CONFIG_PHY_4_5 0x252
211 #define REG_EQ_CONFIG_PHY_6_7 0x253
212 #define REG_EQ_BIAS_REG 0x268
213 #define REG_SYNTH_ENABLE_CNTRL 0x280
214 #define REG_PLL_STATUS 0x281
215 #define REG_REF_CLK_DIVIDER_LDO 0x289
216 #define REG_SERDES_PLL_CTRL 0x291
217 #define REG_SERDES_PLL_CP3 0x29c
218 #define REG_SERDES_PLL_VAR3 0x29f
219 #define REG_DEV_CONFIG_8 0x2A4
220 #define REG_TERM_BLK1_CTRLREG0 0x2A7
221 #define REG_TERM_BLK1_CTRLREG1 0x2A8
222 #define REG_DEV_CONFIG_9 0x2AA
223 #define REG_DEV_CONFIG_10 0x2AB
224 #define REG_TERM_BLK2_CTRLREG0 0x2AE
225 #define REG_TERM_BLK2_CTRLREG1 0x2AF
226 #define REG_DEV_CONFIG_11 0x2B1
227 #define REG_DEV_CONFIG_12 0x2B2
228 #define REG_GENERAL_JRX_CTRL_0 0x300
229 #define REG_GENERAL_JRX_CTRL_1 0x301
230 #define REG_DYN_LINK_LATENCY_0 0x302
231 #define REG_DYN_LINK_LATENCY_1 0x303
232 #define REG_LMFC_DELAY_0 0x304
233 #define REG_LMFC_DELAY_1 0x305
234 #define REG_LMFC_VAR_0 0x306
235 #define REG_LMFC_VAR_1 0x307
236 #define REG_XBAR(x) (0x308 +(x))
237 #define REG_FIFO_STATUS_REG_0 0x30C
238 #define REG_FIFO_STATUS_REG_1 0x30D
239 #define REG_FIFO_STATUS_REG_2 0x30E
240 #define REG_SYNCB_GEN_0 0x311
241 #define REG_SYNCB_GEN_1 0x312
242 #define REG_SYNCB_GEN_3 0x313
243 #define REG_SERDES_SPI_REG 0x314
244 #define REG_PHY_PRBS_TEST_EN 0x315
245 #define REG_PHY_PRBS_TEST_CTRL 0x316
246 #define REG_PHY_PRBS_TEST_THRESH_LOBITS 0x317
247 #define REG_PHY_PRBS_TEST_THRESH_MIDBITS 0x318
248 #define REG_PHY_PRBS_TEST_THRESH_HIBITS 0x319
249 #define REG_PHY_PRBS_TEST_ERRCNT_LOBITS 0x31A
250 #define REG_PHY_PRBS_TEST_ERRCNT_MIDBITS 0x31B
251 #define REG_PHY_PRBS_TEST_ERRCNT_HIBITS 0x31C
252 #define REG_PHY_PRBS_TEST_STATUS 0x31D
253 #define REG_SHORT_TPL_TEST_0 0x32C
254 #define REG_SHORT_TPL_TEST_1 0x32D
255 #define REG_SHORT_TPL_TEST_2 0x32E
256 #define REG_SHORT_TPL_TEST_3 0x32F
257 #define REG_DEVICE_CONFIG_REG_13 0x333
258 #define REG_JESD_BIT_INVERSE_CTRL 0x334
259 #define REG_DID_REG 0x400
260 #define REG_BID_REG 0x401
261 #define REG_LID0_REG 0x402
262 #define REG_SCR_L_REG 0x403
263 #define REG_F_REG 0x404
264 #define REG_K_REG 0x405
265 #define REG_M_REG 0x406
266 #define REG_CS_N_REG 0x407
267 #define REG_NP_REG 0x408
268 #define REG_S_REG 0x409
269 #define REG_HD_CF_REG 0x40A
270 #define REG_RES1_REG 0x40B
271 #define REG_RES2_REG 0x40C
272 #define REG_CHECKSUM_REG 0x40D
273 #define REG_COMPSUM0_REG 0x40E
274 #define REG_LID1_REG 0x412
275 #define REG_CHECKSUM1_REG 0x415
276 #define REG_COMPSUM1_REG 0x416
277 #define REG_LID2_REG 0x41A
278 #define REG_CHECKSUM2_REG 0x41D
279 #define REG_COMPSUM2_REG 0x41E
280 #define REG_LID3_REG 0x422
281 #define REG_CHECKSUM3_REG 0x425
282 #define REG_COMPSUM3_REG 0x426
283 #define REG_LID4_REG 0x42A
284 #define REG_CHECKSUM4_REG 0x42D
285 #define REG_COMPSUM4_REG 0x42E
286 #define REG_LID5_REG 0x432
287 #define REG_CHECKSUM5_REG 0x435
288 #define REG_COMPSUM5_REG 0x436
289 #define REG_LID6_REG 0x43A
290 #define REG_CHECKSUM6_REG 0x43D
291 #define REG_COMPSUM6_REG 0x43E
292 #define REG_LID7_REG 0x442
293 #define REG_CHECKSUM7_REG 0x445
294 #define REG_COMPSUM7_REG 0x446
295 #define REG_ILS_DID 0x450
296 #define REG_ILS_BID 0x451
297 #define REG_ILS_LID0 0x452
298 #define REG_ILS_SCR_L 0x453
299 #define REG_ILS_F 0x454
300 #define REG_ILS_K 0x455
301 #define REG_ILS_M 0x456
302 #define REG_ILS_CS_N 0x457
303 #define REG_ILS_NP 0x458
304 #define REG_ILS_S 0x459
305 #define REG_ILS_HD_CF 0x45A
306 #define REG_ILS_RES1 0x45B
307 #define REG_ILS_RES2 0x45C
308 #define REG_ILS_CHECKSUM 0x45D
309 #define REG_ERRCNTRMON 0x46B
310 #define REG_LANEDESKEW 0x46C
311 #define REG_BADDISPARITY 0x46D
312 #define REG_NITDISPARITY 0x46E
313 #define REG_UNEXPECTEDKCHAR 0x46F
314 #define REG_CODEGRPSYNCFLG 0x470
315 #define REG_FRAMESYNCFLG 0x471
316 #define REG_GOODCHKSUMFLG 0x472
317 #define REG_INITLANESYNCFLG 0x473
318 #define REG_CTRLREG1 0x476
319 #define REG_CTRLREG2 0x477
320 #define REG_KVAL 0x478
321 #define REG_IRQVECTOR 0x47A
322 #define REG_SYNCASSERTIONMASK 0x47B
323 #define REG_ERRORTHRES 0x47C
324 #define REG_LANEENABLE 0x47D
329 #define SOFTRESET_M (1 << 7)
330 #define LSBFIRST_M (1 << 6)
331 #define ADDRINC_M (1 << 5)
332 #define SDOACTIVE_M (1 << 4)
333 #define SDOACTIVE (1 << 3)
334 #define ADDRINC (1 << 2)
335 #define LSBFIRST (1 << 1)
336 #define SOFTRESET (1 << 0)
341 #define SINGLEINS (1 << 7)
342 #define CSBSTALL (1 << 6)
347 #define DEVSTATUS(x) (((x) & 0xF) << 4)
348 #define CUSTOPMODE(x) (((x) & 0x3) << 2)
349 #define SYSOPMODE(x) (((x) & 0x3) << 0)
354 #define PROD_GRADE(x) (((x) & 0xF) << 4)
355 #define DEV_REVISION(x) (((x) & 0xF) << 0)
360 #define PAGEINDX(x) (((x) & 0x3) << 0)
365 #define SLAVEUPDATE (1 << 0)
370 #define PD_BG (1 << 7)
371 #define PD_DAC_0 (1 << 6)
372 #define PD_DAC_1 (1 << 5)
373 #define PD_DAC_2 (1 << 4)
374 #define PD_DAC_3 (1 << 3)
375 #define PD_DACM (1 << 2)
380 #define SYS_MASK (1 << 2)
381 #define DACB_MASK (1 << 1)
382 #define DACA_MASK (1 << 0)
387 #define ENA_PA_CTRL_FROM_PAPROT_ERR (1 << 6)
388 #define ENA_PA_CTRL_FROM_TXENSM (1 << 5)
389 #define ENA_PA_CTRL_FROM_BLSM (1 << 4)
390 #define ENA_PA_CTRL_FROM_SPI (1 << 3)
391 #define SPI_PA_CTRL (1 << 2)
392 #define ENA_SPI_TXEN (1 << 1)
393 #define SPI_TXEN (1 << 0)
398 #define COARSE_GROUP_DLY(x) (((x) & 0xF) << 0)
403 #define EN_CALPASS (1 << 7)
404 #define EN_CALFAIL (1 << 6)
405 #define EN_DACPLLLOST (1 << 5)
406 #define EN_DACPLLLOCK (1 << 4)
407 #define EN_SERPLLLOST (1 << 3)
408 #define EN_SERPLLLOCK (1 << 2)
409 #define EN_LANEFIFOERR (1 << 1)
410 #define EN_DRDLFIFOERR (1 << 0)
415 #define EN_PARMBAD (1 << 7)
416 #define EN_PRBSQ1 (1 << 3)
417 #define EN_PRBSI1 (1 << 2)
418 #define EN_PRBSQ0 (1 << 1)
419 #define EN_PRBSI0 (1 << 0)
424 #define EN_PAERR0 (1 << 7)
425 #define EN_BIST_DONE0 (1 << 6)
426 #define EN_BLNKDONE0 (1 << 5)
427 #define EN_REFNCOCLR0 (1 << 4)
428 #define EN_REFLOCK0 (1 << 3)
429 #define EN_REFROTA0 (1 << 2)
430 #define EN_REFWLIM0 (1 << 1)
431 #define EN_REFTRIP0 (1 << 0)
436 #define EN_PAERR1 (1 << 7)
437 #define EN_BIST_DONE1 (1 << 6)
438 #define EN_BLNKDONE1 (1 << 5)
439 #define EN_REFNCOCLR1 (1 << 4)
440 #define EN_REFLOCK1 (1 << 3)
441 #define EN_REFROTA1 (1 << 2)
442 #define EN_REFWLIM1 (1 << 1)
443 #define EN_REFTRIP1 (1 << 0)
448 #define IRQ_CALPASS (1 << 7)
449 #define IRQ_CALFAIL (1 << 6)
450 #define IRQ_DACPLLLOST (1 << 5)
451 #define IRQ_DACPLLLOCK (1 << 4)
452 #define IRQ_SERPLLLOST (1 << 3)
453 #define IRQ_SERPLLLOCK (1 << 2)
454 #define IRQ_LANEFIFOERR (1 << 1)
455 #define IRQ_DRDLFIFOERR (1 << 0)
460 #define IRQ_PARMBAD (1 << 7)
461 #define IRQ_PRBSQ1 (1 << 3)
462 #define IRQ_PRBSI1 (1 << 2)
463 #define IRQ_PRBSQ0 (1 << 1)
464 #define IRQ_PRBSI0 (1 << 0)
469 #define IRQ_PAERR0 (1 << 7)
470 #define IRQ_BIST_DONE0 (1 << 6)
471 #define IRQ_BLNKDONE0 (1 << 5)
472 #define IRQ_REFNCOCLR0 (1 << 4)
473 #define IRQ_REFLOCK0 (1 << 3)
474 #define IRQ_REFROTA0 (1 << 2)
475 #define IRQ_REFWLIM0 (1 << 1)
476 #define IRQ_REFTRIP0 (1 << 0)
481 #define IRQ_PAERR1 (1 << 7)
482 #define IRQ_BIST_DONE1 (1 << 6)
483 #define IRQ_BLNKDONE1 (1 << 5)
484 #define IRQ_REFNCOCLR1 (1 << 4)
485 #define IRQ_REFLOCK1 (1 << 3)
486 #define IRQ_REFROTA1 (1 << 2)
487 #define IRQ_REFWLIM1 (1 << 1)
488 #define IRQ_REFTRIP1 (1 << 0)
493 #define ERR_DLYOVER (1 << 5)
494 #define ERR_WINLIMIT (1 << 4)
495 #define ERR_JESDBAD (1 << 3)
496 #define ERR_KUNSUPP (1 << 2)
497 #define ERR_SUBCLASS (1 << 1)
498 #define ERR_INTSUPP (1 << 0)
503 #define TARRFAPHAZ (1 << 0)
504 #define SYNCBYPASS(x) (((x) & 0x3) << 6)
509 #define DAC_DELAY_H (1 << 0)
514 #define ERRWINDOW(x) (((x) & 0x7) << 0)
519 #define LASTUNDER (1 << 7)
520 #define LASTOVER (1 << 6)
521 #define LASTERROR_H (1 << 0)
526 #define SYNCENABLE (1 << 7)
527 #define SYNCARM (1 << 6)
528 #define SYNCCLRSTKY (1 << 5)
529 #define SYNCCLRLAST (1 << 4)
530 #define SYNCMODE(x) (((x) & 0xF) << 0)
535 #define REFBUSY (1 << 7)
536 #define REFLOCK (1 << 3)
537 #define REFROTA (1 << 2)
538 #define REFWLIM (1 << 1)
539 #define REFTRIP (1 << 0)
544 #define CURRUNDER (1 << 7)
545 #define CURROVER (1 << 6)
546 #define CURRERROR_H (1 << 0)
551 #define THRMOLD (1 << 7)
552 #define THRMOVER (1 << 4)
553 #define THRMPOS (1 << 3)
554 #define THRMZERO (1 << 2)
555 #define THRMNEG (1 << 1)
556 #define THRMUNDER (1 << 0)
561 #define DACGAIN_IM0(x) (((x) & 0x3) << 0)
566 #define DACGAIN_IM1(x) (((x) & 0x3) << 0)
571 #define DACGAIN_IM2(x) (((x) & 0x3) << 0)
576 #define DACGAIN_IM3(x) (((x) & 0x3) << 0)
581 #define ENB_DACLDO3 (1 << 7)
582 #define ENB_DACLDO2 (1 << 6)
583 #define ENB_DACLDO1 (1 << 5)
584 #define ENB_DACLDO0 (1 << 4)
589 #define STAT_LDO3 (1 << 3)
590 #define STAT_LDO2 (1 << 2)
591 #define STAT_LDO1 (1 << 1)
592 #define STAT_LDO0 (1 << 0)
597 #define SHUFFLE_MSB0 (1 << 2)
598 #define SHUFFLE_ISB0 (1 << 1)
603 #define SHUFFLE_MSB1 (1 << 2)
604 #define SHUFFLE_ISB1 (1 << 1)
609 #define SHUFFLE_MSB2 (1 << 2)
610 #define SHUFFLE_ISB2 (1 << 1)
615 #define SHUFFLE_MSB3 (1 << 2)
616 #define SHUFFLE_ISB3 (1 << 1)
621 #define NCOCLRARM (1 << 7)
622 #define NCOCLRMTCH (1 << 5)
623 #define NCOCLRPASS (1 << 4)
624 #define NCOCLRFAIL (1 << 3)
625 #define NCOCLRMODE(x) (((x) & 0x3) << 0)
630 #define PA_THRESH_MSB(x) (((x) & 0x1F) << 0)
635 #define PA_ENABLE (1 << 7)
636 #define PA_BUS_SWAP (1 << 6)
637 #define PA_AVG_TIME(x) (((x) & 0xF) << 0)
642 #define PA_POWER_MSB(x) (((x) & 0x1F) << 0)
647 #define PD_CLK01 (1 << 7)
648 #define PD_CLK23 (1 << 6)
649 #define PD_CLK_DIG (1 << 5)
650 #define PD_PCLK (1 << 4)
651 #define PD_CLK_REC (1 << 3)
656 #define PD_SYSREF (1 << 4)
657 #define HYS_ON (1 << 3)
658 #define SYSREF_RISE (1 << 2)
659 #define HYS_CNTRL1(x) (((x) & 0x3) << 0)
664 #define SYNTH_RECAL (1 << 7)
665 #define ENABLE_SYNTH (1 << 4)
670 #define CP_CAL_VALID (1 << 5)
671 #define RFPLL_LOCK (1 << 1)
676 #define LF_C2_WORD(x) (((x) & 0xF) << 4)
677 #define LF_C1_WORD(x) (((x) & 0xF) << 0)
682 #define LF_R1_WORD(x) (((x) & 0xF) << 4)
683 #define LF_C3_WORD(x) (((x) & 0xF) << 0)
688 #define LF_BYPASS_R3 (1 << 7)
689 #define LF_BYPASS_R1 (1 << 6)
690 #define LF_BYPASS_C2 (1 << 5)
691 #define LF_BYPASS_C1 (1 << 4)
692 #define LF_R3_WORD(x) (((x) & 0xF) << 0)
697 #define CP_CURRENT(x) (((x) & 0x3F) << 0)
702 #define LO_DIV_MODE(x) (((x) & 0x3) << 0)
707 #define REF_DIVRATE(x) (((x) & 0x7) << 0)
712 #define INIT_SWEEP_ERR_DAC (1 << 1)
713 #define MSB_SWEEP_ERR_DAC (1 << 0)
718 #define CAL_MSB_TAC(x) (((x) & 0x7) << 0)
723 #define CAL_START_GL (1 << 1)
724 #define CAL_EN_GL (1 << 0)
729 #define CAL_MSBLVLHI(x) (((x) & 0x3F) << 0)
734 #define CAL_MSBLVLLO(x) (((x) & 0x3F) << 0)
739 #define CAL_LTAC_THRES(x) (((x) & 0x7) << 3)
740 #define CAL_TAC_THRES(x) (((x) & 0x7) << 0)
745 #define MSB_GLOBAL_SUBAVG(x) (((x) & 0x3) << 6)
746 #define GLOBAL_AVG_CNT(x) (((x) & 0x7) << 3)
747 #define LOCAL_AVRG_CNT(x) (((x) & 0x7) << 0)
752 #define CAL_CLKDIV(x) (((x) & 0xF) << 0)
757 #define CAL_INDX(x) (((x) & 0xF) << 0)
762 #define CAL_FIN (1 << 7)
763 #define CAL_ACTIVE (1 << 6)
764 #define CAL_ERRHI (1 << 5)
765 #define CAL_ERRLO (1 << 4)
766 #define CAL_TXDACBYDAC (1 << 3)
767 #define CAL_START (1 << 1)
768 #define CAL_EN (1 << 0)
773 #define CAL_ADDR(x) (((x) & 0x3F) << 0)
778 #define CAL_DATA(x) (((x) & 0x3F) << 0)
783 #define CAL_UPDATE (1 << 7)
788 #define BINARY_FORMAT (1 << 7)
793 #define INVSINC_ENABLE (1 << 7)
794 #define DIG_GAIN_ENABLE (1 << 5)
795 #define PHASE_ADJ_ENABLE (1 << 4)
796 #define SEL_SIDEBAND (1 << 1)
797 #define I_TO_Q (1 << 0)
798 #define MODULATION_TYPE(x) (((x) & 0x3) << 2)
799 #define MODULATION_TYPE_MASK (0x03 << 2)
804 #define INTERP_MODE(x) (((x) & 0x7) << 0)
809 #define FTW_UPDATE_ACK (1 << 1)
810 #define FTW_UPDATE_REQ (1 << 0)
815 #define TX_DIG_CLK_PD (1 << 0)
820 #define GP_PA_ON_INVERT (1 << 2)
821 #define GP_PA_CTRL (1 << 1)
822 #define TXEN_SM_EN (1 << 0)
823 #define PA_FALL(x) (((x) & 0x3) << 6)
824 #define PA_RISE(x) (((x) & 0x3) << 4)
829 #define DIG_FALL(x) (((x) & 0x3) << 6)
830 #define DIG_RISE(x) (((x) & 0x3) << 4)
831 #define DAC_FALL(x) (((x) & 0x3) << 2)
832 #define DAC_RISE(x) (((x) & 0x3) << 0)
837 #define DACOUT_SHUTDOWN (1 << 1)
838 #define DACOUT_ON_TRIGGER (1 << 0)
843 #define PROTECT_MODE (1 << 7)
844 #define DACOFF_AVG_PW (1 << 0)
849 #define ADC_TESTMODE (1 << 7)
850 #define AUXADC_ENABLE (1 << 0)
851 #define FS_CURRENT(x) (((x) & 0x7) << 4)
852 #define REF_CURRENT(x) (((x) & 0x7) << 1)
857 #define SELECT_CLKDIG (1 << 3)
858 #define EN_DIV2 (1 << 2)
859 #define INCAP_CTRL(x) (((x) & 0x3) << 0)
864 #define DIE_TEMP_UPDATE (1 << 0)
869 #define DISABLE_NOISE (1 << 1)
870 #define DC_OFFSET_ON (1 << 0)
875 #define IPATH_DC_OFFSET_2PART(x) (((x) & 0x1F) << 0)
880 #define QPATH_DC_OFFSET_2PART(x) (((x) & 0x1F) << 0)
885 #define IDAC_DIG_GAIN1(x) (((x) & 0xF) << 0)
890 #define QDAC_DIG_GAIN1(x) (((x) & 0xF) << 0)
895 #define GAIN_RAMP_UP_STP1(x) (((x) & 0xF) << 0)
900 #define GAIN_RAMP_DOWN_STP1(x) (((x) & 0xF) << 0)
905 #define RESET_BLSM (1 << 7)
906 #define EN_FORCE_GAIN_SOFT_OFF (1 << 4)
907 #define GAIN_SOFT_OFF (1 << 3)
908 #define GAIN_SOFT_ON (1 << 2)
909 #define EN_FORCE_GAIN_SOFT_ON (1 << 1)
914 #define SOFT_OFF_DONE (1 << 5)
915 #define SOFT_ON_DONE (1 << 4)
916 #define GAIN_SOFT_OFF_RB (1 << 3)
917 #define GAIN_SOFT_ON_RB (1 << 2)
918 #define SOFT_OFF_EN_RB (1 << 1)
919 #define SOFT_ON_EN_RB (1 << 0)
920 #define SOFTBLANKRB(x) (((x) & 0x3) << 6)
925 #define PRBS_GOOD_Q (1 << 7)
926 #define PRBS_GOOD_I (1 << 6)
927 #define PRBS_INV_Q (1 << 4)
928 #define PRBS_INV_I (1 << 3)
929 #define PRBS_MODE (1 << 2)
930 #define PRBS_RESET (1 << 1)
931 #define PRBS_EN (1 << 0)
936 #define VCO_VAR(x) (((x) & 0xF) << 0)
941 #define VCO_BIAS_REF(x) (((x) & 0x7) << 0)
946 #define VCO_CAL_REF_MON (1 << 3)
947 #define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0)
952 #define VCO_VAR_REF_TCF(x) (((x) & 0x7) << 4)
953 #define VCO_VAR_OFF(x) (((x) & 0xF) << 0)
958 #define SPIDRV(x) (((x) & 0xF) << 0)
963 #define DUTYCYCLEON (1 << 0)
968 #define ATEST_EN (1 << 0)
969 #define ATEST_TOPVSEL(x) (((x) & 0x3) << 5)
970 #define ATEST_DACSEL(x) (((x) & 0x3) << 3)
971 #define ATEST_VSEL(x) (((x) & 0x3) << 1)
976 #define EN_CLKDIV (1 << 3)
977 #define ASPI_OSC_RATE (1 << 2)
978 #define ASPI_CLK_SRC (1 << 1)
979 #define EN_ASPI_OSC (1 << 0)
984 #define SPI_PD_MASTER (1 << 0)
989 #define SPI_SYNC1_PD (1 << 1)
990 #define SPI_SYNC2_PD (1 << 0)
995 #define SPI_ENHALFRATE (1 << 5)
996 #define SPI_DIVISION_RATE(x) (((x) & 0x3) << 1)
1001 #define SPI_EQ_CONFIG1(x) (((x) & 0xF) << 4)
1002 #define SPI_EQ_CONFIG0(x) (((x) & 0xF) << 0)
1007 #define SPI_EQ_CONFIG3(x) (((x) & 0xF) << 4)
1008 #define SPI_EQ_CONFIG2(x) (((x) & 0xF) << 0)
1013 #define SPI_EQ_CONFIG5(x) (((x) & 0xF) << 4)
1014 #define SPI_EQ_CONFIG4(x) (((x) & 0xF) << 0)
1019 #define SPI_EQ_CONFIG7(x) (((x) & 0xF) << 4)
1020 #define SPI_EQ_CONFIG6(x) (((x) & 0xF) << 0)
1025 #define SPI_EQ_EXTRA_SPI_LSBITS(x) (((x) & 0x3) << 6)
1026 #define SPI_EQ_BIASPTAT(x) (((x) & 0x7) << 3)
1027 #define SPI_EQ_BIASPLY(x) (((x) & 0x7) << 0)
1032 #define SPI_RECAL_SYNTH (1 << 2)
1033 #define SPI_ENABLE_SYNTH (1 << 0)
1038 #define SPI_CP_CAL_VALID_RB (1 << 3)
1039 #define SPI_PLL_LOCK_RB (1 << 0)
1044 #define SPI_CDR_OVERSAMP(x) (((x) & 0x3) << 0)
1049 #define SPI_I_TUNE_R_CAL_TERMBLK1 (1 << 0)
1054 #define SPI_I_TUNE_R_CAL_TERMBLK2 (1 << 0)
1059 #define CHECKSUM_MODE (1 << 6)
1060 #define LINK_MODE (1 << 3)
1061 #define SEL_REG_MAP_1 (1 << 2)
1062 #define LINK_EN(x) (((x) & 0x3) << 0)
1067 #define SUBCLASSV_LOCAL(x) (((x) & 0x7) << 0)
1072 #define DYN_LINK_LATENCY_0(x) (((x) & 0x1F) << 0)
1077 #define DYN_LINK_LATENCY_1(x) (((x) & 0x1F) << 0)
1082 #define LMFC_DELAY_0(x) (((x) & 0x1F) << 0)
1087 #define LMFC_DELAY_1(x) (((x) & 0x1F) << 0)
1092 #define LMFC_VAR_0(x) (((x) & 0x1F) << 0)
1097 #define LMFC_VAR_1(x) (((x) & 0x1F) << 0)
1102 #define SRC_LANE1(x) (((x) & 0x7) << 3)
1103 #define SRC_LANE0(x) (((x) & 0x7) << 0)
1108 #define SRC_LANE3(x) (((x) & 0x7) << 3)
1109 #define SRC_LANE2(x) (((x) & 0x7) << 0)
1114 #define SRC_LANE5(x) (((x) & 0x7) << 3)
1115 #define SRC_LANE4(x) (((x) & 0x7) << 0)
1120 #define SRC_LANE7(x) (((x) & 0x7) << 3)
1121 #define SRC_LANE6(x) (((x) & 0x7) << 0)
1126 #define DRDL_FIFO_EMPTY (1 << 1)
1127 #define DRDL_FIFO_FULL (1 << 0)
1132 #define EOMF_MASK_1 (1 << 3)
1133 #define EOMF_MASK_0 (1 << 2)
1134 #define EOF_MASK_1 (1 << 1)
1135 #define EOF_MASK_0 (1 << 0)
1140 #define SYNCB_ERR_DUR(x) (((x) & 0xF) << 4)
1141 #define SYNCB_SYNCREQ_DUR(x) (((x) & 0xF) << 0)
1146 #define PHY_TEST_START (1 << 1)
1147 #define PHY_TEST_RESET (1 << 0)
1148 #define PHY_SRC_ERR_CNT(x) (((x) & 0x7) << 4)
1149 #define PHY_PRBS_PAT_SEL(x) (((x) & 0x3) << 2)
1154 #define SHORT_TPL_TEST_RESET (1 << 1)
1155 #define SHORT_TPL_TEST_EN (1 << 0)
1156 #define SHORT_TPL_SP_SEL(x) (((x) & 0x3) << 4)
1157 #define SHORT_TPL_M_SEL(x) (((x) & 0x3) << 2)
1162 #define SHORT_TPL_FAIL (1 << 0)
1167 #define ADJCNT_RD(x) (((x) & 0xF) << 4)
1168 #define BID_RD(x) (((x) & 0xF) << 0)
1173 #define ADJDIR_RD (1 << 6)
1174 #define PHADJ_RD (1 << 5)
1175 #define LID0_RD(x) (((x) & 0x1F) << 0)
1180 #define SCR_RD (1 << 7)
1181 #define L_RD(x) (((x) & 0x1F) << 0)
1186 #define K_RD(x) (((x) & 0x1F) << 0)
1191 #define CS_RD(x) (((x) & 0x3) << 6)
1192 #define N_RD(x) (((x) & 0x1F) << 0)
1197 #define SUBCLASSV_RD(x) (((x) & 0x7) << 5)
1198 #define NP_RD(x) (((x) & 0x1F) << 0)
1203 #define JESDV_RD(x) (((x) & 0x7) << 5)
1204 #define S_RD(x) (((x) & 0x1F) << 0)
1209 #define HD_RD (1 << 7)
1210 #define CF_RD(x) (((x) & 0x1F) << 0)
1215 #define LID1_RD(x) (((x) & 0x1F) << 0)
1220 #define LID2_RD(x) (((x) & 0x1F) << 0)
1225 #define LID3_RD(x) (((x) & 0x1F) << 0)
1230 #define LID4_RD(x) (((x) & 0x1F) << 0)
1235 #define LID5_RD(x) (((x) & 0x1F) << 0)
1240 #define LID6_RD(x) (((x) & 0x1F) << 0)
1245 #define LID7_RD(x) (((x) & 0x1F) << 0)
1250 #define ADJCNT(x) (((x) & 0xF) << 4)
1251 #define BID(x) (((x) & 0xF) << 0)
1256 #define ADJDIR (1 << 6)
1257 #define PHADJ (1 << 5)
1258 #define LID0(x) (((x) & 0x1F) << 0)
1263 #define SCR (1 << 7)
1264 #define L(x) (((x) & 0x1F) << 0)
1269 #define K(x) (((x) & 0x1F) << 0)
1274 #define CS(x) (((x) & 0x3) << 6)
1275 #define N(x) (((x) & 0x1F) << 0)
1280 #define SUBCLASSV(x) (((x) & 0x7) << 5)
1281 #define NP(x) (((x) & 0x1F) << 0)
1286 #define JESDV(x) (((x) & 0x7) << 5)
1287 #define S(x) (((x) & 0x1F) << 0)
1293 #define CF(x) (((x) & 0x1F) << 0)
1298 #define LANESEL(x) (((x) & 0x7) << 4)
1299 #define CNTRSEL(x) (((x) & 0x3) << 0)
1304 #define RST_IRQ_DIS (1 << 7)
1305 #define DIS_ERR_CNTR_DIS (1 << 6)
1306 #define RST_ERR_CNTR_DIS (1 << 5)
1307 #define LANE_ADDR_DIS(x) (((x) & 0x7) << 0)
1312 #define RST_IRQ_NIT (1 << 7)
1313 #define DIS_ERR_CNTR_NIT (1 << 6)
1314 #define RST_ERR_CNTR_NIT (1 << 5)
1315 #define LANE_ADDR_NIT(x) (((x) & 0x7) << 0)
1320 #define RST_IRQ_K (1 << 7)
1321 #define DIS_ERR_CNTR_K (1 << 6)
1322 #define RST_ERR_CNTR_K (1 << 5)
1323 #define LANE_ADDR_K(x) (((x) & 0x7) << 0)
1328 #define ILAS_MODE (1 << 7)
1329 #define REPDATATEST (1 << 5)
1330 #define QUETESTERR (1 << 4)
1331 #define AUTO_ECNTR_RST (1 << 3)
1336 #define BADDIS_FLAG_OR_MASK (1 << 7)
1337 #define NITD_FLAG_OR_MASK (1 << 6)
1338 #define UEKC_FLAG_OR_MASK (1 << 5)
1339 #define INITIALLANESYNC_FLAG_OR_MASK (1 << 3)
1340 #define BADCHECKSUM_FLAG_OR_MASK (1 << 2)
1341 #define CODEGRPSYNC_FLAG_OR_MASK (1 << 0)
1346 #define BAD_DIS_S (1 << 7)
1347 #define NIT_DIS_S (1 << 6)
1348 #define UNEX_K_S (1 << 5)
1349 #define CMM_FLAG_OR_MASK (1 << 4)
1350 #define CMM_ENABLE (1 << 3)
1353 #define AD9144_MAX_DAC_RATE 2000000000UL
1354 #define AD9144_CHIP_ID 0x44
1355 #define AD9144_PRBS7 0x0
1356 #define AD9144_PRBS15 0x1
1434 uint8_t exp_reg_data);
uint32_t pll_dac_frequency_khz
Definition: ad9144.h:1408
#define REG_CDR_RESET
Definition: ad9144.h:205
int32_t ad9144_setup_jesd_fsm(struct ad9144_dev **device, const struct ad9144_init_param *init_param)
Definition: ad9144.c:1133
JESD204 link configuration settings.
Definition: jesd204.h:105
uint32_t timeout
Definition: ad413x.c:55
int32_t ad9144_short_pattern_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_short_pattern_test
Definition: ad9144.c:1288
#define FTW_UPDATE_REQ
Definition: ad9144.h:810
#define REG_ILS_SCR_L
Definition: ad9144.h:298
#define SRC_LANE3(x)
Definition: ad9144.h:1108
#define REG_SHORT_TPL_TEST_1
Definition: ad9144.h:254
#define REG_DACINTEGERWORD0
Definition: ad9144.h:119
uint8_t * lane_ids
Definition: jesd204.h:137
#define REG_CAL_CTRL
Definition: ad9144.h:135
unsigned int interpolation
Definition: ad9144.h:1372
int32_t ad9144_datapath_prbs_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_datapath_prbs_test
Definition: ad9144.c:1326
#define NO_OS_GENMASK(h, l)
Definition: no_os_util.h:86
#define REG_MASTER_PD
Definition: ad9144.h:202
struct jesd204_state_op state_ops[__JESD204_MAX_OPS]
Definition: jesd204.h:232
uint16_t reg
Definition: ad9144.c:155
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:95
@ JESD204_STATE_OP_REASON_INIT
Definition: jesd204.h:148
#define REG_PRBS_ERROR_I
Definition: ad9144.h:189
uint8_t samples_per_conv_frame
Definition: jesd204.h:135
uint8_t device_id
Definition: jesd204.h:127
#define REG_LMFC_VAR_0
Definition: ad9144.h:234
uint32_t pll_ref_frequency_khz
Definition: ad9144.h:1380
uint8_t num_converters
Definition: ad9144.h:1390
int32_t ad9144_setup_legacy(struct ad9144_dev **device, const struct ad9144_init_param *init_param)
Definition: ad9144.c:976
#define REG_DACPLLSTATUS
Definition: ad9144.h:118
#define REG_GOODCHKSUMFLG
Definition: ad9144.h:316
#define SOFTRESET_M
Definition: ad9144.h:329
#define REG_LMFC_DELAY_1
Definition: ad9144.h:233
Header file of SPI Interface.
uint32_t sample_rate_khz
Definition: ad9144.h:1368
int32_t ad9144_dac_calibrate(struct ad9144_dev *dev)
Definition: ad9144.c:1197
uint64_t no_os_mul_u64_u32_shr(uint64_t a, uint32_t mul, unsigned int shift)
#define REG_DACLDOCNTRL1
Definition: ad9144.h:125
#define REG_SYSREF_ACTRL0
Definition: ad9144.h:115
#define AD9144_MOD_TYPE_MASK
Definition: ad9144.c:82
void jesd204_copy_link_params(struct jesd204_link *dst, const struct jesd204_link *src)
#define SYNCARM
Definition: ad9144.h:527
#define pr_err(fmt, args...)
Definition: no_os_print_log.h:94
int32_t ad9144_spi_write_seq(struct ad9144_dev *dev, const struct ad9144_reg_seq *seq, uint32_t num)
Definition: ad9144.c:159
struct jesd204_link link_config
Definition: ad9144.h:1366
#define REG_SHORT_TPL_TEST_2
Definition: ad9144.h:255
int32_t ad9144_status(struct ad9144_dev *dev)
ad9144_status - return the status of the JESD interface
Definition: ad9144.c:1249
uint8_t lane_mux[8]
Definition: ad9144.h:1401
Header file of Delay functions.
@ JESD204_ENCODER_8B10B
Definition: jesd204.h:30
uint8_t M
Definition: ad9144.c:53
enum jesd204_sysref_mode mode
Definition: jesd204.h:61
jesd204_state_op_reason
Definition: jesd204.h:147
#define pr_info(fmt, args...)
Definition: no_os_print_log.h:121
uint32_t prbs_type
Definition: ad9144.h:1396
int32_t ad9144_set_nco(struct ad9144_dev *dev, int32_t f_carrier_khz, int16_t phase)
Definition: ad9144.c:381
unsigned int fcenter_shift
Definition: ad9144.h:1373
#define REG_ILS_BID
Definition: ad9144.h:296
#define REG_ILS_DID
Definition: ad9144.h:295
int32_t ad9144_datapath_prbs_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_datapath_prbs_test
Definition: ad9144.c:1326
uint8_t pll_enable
Definition: ad9144.h:1378
uint8_t jesd204_subclass
Definition: ad9144.h:1399
Definition: ad9361_util.h:75
#define SRC_LANE0(x)
Definition: ad9144.h:1103
#define REG_DEV_CONFIG_9
Definition: ad9144.h:222
uint32_t sample_rate_div
Definition: jesd204.h:110
#define REG_FRAMESYNCFLG
Definition: ad9144.h:315
int32_t ad9144_set_nco(struct ad9144_dev *dev, int32_t f_carrier_khz, int16_t phase)
Definition: ad9144.c:381
uint8_t subclass
Definition: jesd204.h:125
int32_t ad9144_spi_read(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9144_spi_read
Definition: ad9144.c:87
#define REG_GENERAL_JRX_CTRL_1
Definition: ad9144.h:229
#define REG_ILS_CS_N
Definition: ad9144.h:302
#define REG_INTERP_MODE
Definition: ad9144.h:142
#define REG_KVAL
Definition: ad9144.h:320
#define REG_ILS_S
Definition: ad9144.h:304
#define MODULATION_TYPE_MASK
Definition: ad9144.h:799
#define REG_ILS_K
Definition: ad9144.h:300
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
#define SRC_LANE1(x)
Definition: ad9144.h:1102
struct jesd204_sysref sysref
Definition: jesd204.h:139
uint8_t scrambling
Definition: jesd204.h:130
struct no_os_spi_desc * spi_desc
Definition: ad9144.h:1363
struct no_os_spi_init_param spi_init
Definition: ad9144.h:1387
#define REG_DEV_CONFIG_12
Definition: ad9144.h:227
#define REG_REF_CLK_DIVIDER_LDO
Definition: ad9144.h:215
void * jesd204_dev_priv(struct jesd204_dev *jdev)
#define REG_DACPLLT5
Definition: ad9144.h:191
uint16_t val
Definition: ad9144.c:156
uint8_t high_density
Definition: jesd204.h:131
uint8_t S
Definition: ad9144.c:55
int32_t ad9144_setup_legacy(struct ad9144_dev **device, const struct ad9144_init_param *init_param)
Definition: ad9144.c:976
#define REG_LANEENABLE
Definition: ad9144.h:324
#define AD9144_MOD_TYPE_COARSE8
Definition: ad9144.c:81
#define REG_SPI_PAGEINDX
Definition: ad9144.h:60
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
uint8_t interpolation
Definition: ad9144.h:1392
#define NO_OS_DIV_ROUND_UP(x, y)
Definition: no_os_util.h:56
#define SEL_SIDEBAND
Definition: ad9144.h:796
#define pr_debug(fmt, args...)
Definition: no_os_print_log.h:135
#define REG_CAL_CLKDIV
Definition: ad9144.h:133
int32_t ad9144_spi_read(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9144_spi_read
Definition: ad9144.c:87
#define REG_EQ_BIAS_REG
Definition: ad9144.h:212
uint8_t jesd204_mode
Definition: ad9144.h:1398
int32_t ad9144_status(struct ad9144_dev *dev)
ad9144_status - return the status of the JESD interface
Definition: ad9144.c:1249
@ JESD204_OP_LINK_INIT
Definition: jesd204.h:198
#define REG_TERM_BLK2_CTRLREG0
Definition: ad9144.h:224
#define REG_NCO_PHASE_OFFSET0
Definition: ad9144.h:150
#define REG_CAL_INIT
Definition: ad9144.h:139
uint8_t num_lanes
Definition: ad9144.h:1391
uint8_t num_lanes
Definition: ad9144.h:1370
@ JESD204_SYSREF_ONESHOT
Definition: jesd204.h:40
#define REG_INITLANESYNCFLG
Definition: ad9144.h:317
#define REG_SHORT_TPL_TEST_0
Definition: ad9144.h:253
#define MODULATION_TYPE(x)
Definition: ad9144.h:798
#define SOFTRESET
Definition: ad9144.h:336
#define REG_XBAR(x)
Definition: ad9144.h:236
#define REG_SHORT_TPL_TEST_3
Definition: ad9144.h:256
uint8_t jesd_version
Definition: jesd204.h:123
bool is_transmit
Definition: jesd204.h:112
@ JESD204_VERSION_B
Definition: jesd204.h:23
#define REG_CDR_OPERATING_MODE_REG_0
Definition: ad9144.h:206
#define AD9144_MOD_TYPE_NONE
Definition: ad9144.c:78
Definition: ad9144.h:1361
#define REG_ILS_LID0
Definition: ad9144.h:297
#define REG_SPI_PRODIDL
Definition: ad9144.h:57
uint32_t pll_ref_frequency_khz
Definition: ad9144.h:1406
@ JESD204_OP_LINK_ENABLE
Definition: jesd204.h:211
Structure holding SPI descriptor.
Definition: no_os_spi.h:143
#define REG_DACLOGENCNTRL
Definition: ad9144.h:124
int32_t ad9144_remove(struct ad9144_dev *dev)
Definition: ad9144.c:1235
#define REG_SYNTH_ENABLE_CNTRL
Definition: ad9144.h:213
#define AD9144_CHIP_ID
Definition: ad9144.h:1354
uint8_t octets_per_frame
Definition: jesd204.h:116
#define REG_ILS_HD_CF
Definition: ad9144.h:305
#define REG_PLL_STATUS
Definition: ad9144.h:214
uint8_t lane_mux[8]
Definition: ad9144.h:1375
#define REG_ILS_NP
Definition: ad9144.h:303
#define REG_PHY_PD
Definition: ad9144.h:203
#define REG_ILS_M
Definition: ad9144.h:301
uint16_t frames_per_multiframe
Definition: jesd204.h:117
#define REG_LANEDESKEW
Definition: ad9144.h:310
uint32_t link_id
Definition: jesd204.h:106
void * no_os_malloc(size_t size)
#define REG_TERM_BLK1_CTRLREG0
Definition: ad9144.h:220
int32_t ad9144_setup_jesd204_link(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
Definition: ad9144.c:206
uint8_t capture_falling_edge
Definition: jesd204.h:62
uint8_t num_lanes
Definition: jesd204.h:114
#define REG_DACPLLT18
Definition: ad9144.h:195
uint64_t sample_rate
Definition: jesd204.h:109
#define NO_OS_BIT(x)
Definition: no_os_util.h:51
void no_os_free(void *ptr)
#define REG_FTW0
Definition: ad9144.h:144
struct ad9144_dev * dev
Definition: ad9144.c:75
int jesd204_dev_register(struct jesd204_dev **jdev, const struct jesd204_dev_data *dev_data)
unsigned int no_os_hweight8(uint8_t word)
int32_t ad9144_dac_calibrate(struct ad9144_dev *dev)
Definition: ad9144.c:1197
#define AD9144_MOD_TYPE_COARSE4
Definition: ad9144.c:80
unsigned int fcenter_shift
Definition: ad9144.h:1393
#define REG_LMFC_DELAY_0
Definition: ad9144.h:232
#define NULL
Definition: wrapper.h:64
#define REG_CAL_INDX
Definition: ad9144.h:134
uint8_t L
Definition: ad9144.c:54
#define REG_DACPLLTB
Definition: ad9144.h:192
uint8_t num_converters
Definition: ad9144.h:1369
#define REG_DEV_CONFIG_11
Definition: ad9144.h:226
int32_t ad9144_spi_check_status(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_mask, uint8_t exp_reg_data)
ad9144_spi_check_status
Definition: ad9144.c:132
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
uint32_t stpl_samples[4][4]
Definition: ad9144.h:1394
Definition: ad9144.h:1385
#define SYNCENABLE
Definition: ad9144.h:526
uint8_t jesd_encoder
Definition: jesd204.h:124
#define REG_ILS_F
Definition: ad9144.h:299
@ JESD204_STATE_CHANGE_DONE
Definition: jesd204.h:46
struct jesd204_dev * jdev
Definition: ad9144.h:1365
#define REG_SPI_SCRATCHPAD
Definition: ad9144.h:62
uint8_t spi3wire
Definition: ad9144.h:1389
#define REG_NCO_FTW_UPDATE
Definition: ad9144.h:143
int32_t ad9144_spi_check_status(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_mask, uint8_t exp_reg_data)
ad9144_spi_check_status
Definition: ad9144.c:132
int32_t ad9144_short_pattern_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_short_pattern_test
Definition: ad9144.c:1288
#define REG_SPI_INTFCONFA
Definition: ad9144.h:54
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:77
#define REG_CTRLREG1
Definition: ad9144.h:318
#define REG_DEV_CONFIG_10
Definition: ad9144.h:223
#define SRC_LANE5(x)
Definition: ad9144.h:1114
#define REG_CODEGRPSYNCFLG
Definition: ad9144.h:314
uint8_t jesd204_scrambling
Definition: ad9144.h:1400
#define REG_SYNCB_GEN_1
Definition: ad9144.h:241
uint8_t pll_enable
Definition: ad9144.h:1404
#define REG_LMFC_VAR_1
Definition: ad9144.h:235
int32_t ad9144_spi_write(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9144_spi_write
Definition: ad9144.c:110
#define REG_SYNC_CTRL
Definition: ad9144.h:85
jesd204_link_cb per_link
Definition: jesd204.h:192
uint8_t id
Definition: ad9144.c:52
#define REG_PWRCNTRL0
Definition: ad9144.h:64
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
#define L(x)
Definition: ad9144.h:1264
#define AD9144_MOD_TYPE_FINE
Definition: ad9144.c:79
int32_t ad9144_setup_jesd_fsm(struct ad9144_dev **device, const struct ad9144_init_param *init_param)
Definition: ad9144.c:1133
Header file of utility functions.
uint32_t pll_dac_frequency_khz
Definition: ad9144.h:1382
#define REG_NCO_PHASE_OFFSET1
Definition: ad9144.h:151
@ JESD204_OP_LINK_RUNNING
Definition: jesd204.h:212
#define REG_DATAPATH_CTRL
Definition: ad9144.h:141
#define SRC_LANE2(x)
Definition: ad9144.h:1109
#define SRC_LANE6(x)
Definition: ad9144.h:1121
uint8_t bank_id
Definition: jesd204.h:128
#define SRC_LANE7(x)
Definition: ad9144.h:1120
uint32_t lane_rate_kbps
Definition: ad9144.h:1395
#define SRC_LANE4(x)
Definition: ad9144.h:1115
#define REG_DACPLLCNTRL
Definition: ad9144.h:117
#define REG_CLKCFG0
Definition: ad9144.h:114
#define REG_SERDES_SPI_REG
Definition: ad9144.h:243
Header file of AD9144 Driver.
#define REG_PRBS_ERROR_Q
Definition: ad9144.h:190
JESD204 device initialization data.
Definition: jesd204.h:227
#define REG_DATA_FORMAT
Definition: ad9144.h:140
int32_t ad9144_remove(struct ad9144_dev *dev)
Definition: ad9144.c:1235
#define REG_GENERAL_JRX_CTRL_0
Definition: ad9144.h:228
uint8_t num_converters
Definition: jesd204.h:115
#define NO_OS_DIV_ROUND_CLOSEST(x, y)
Definition: no_os_util.h:58
int32_t ad9144_spi_write(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9144_spi_write
Definition: ad9144.c:110
@ JESD204_OP_LINK_SETUP
Definition: jesd204.h:204
chip_id
Definition: ad9172.h:57
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:121
uint8_t F
Definition: ad9144.c:56
uint64_t no_os_div_u64(uint64_t dividend, uint32_t divisor)
#define REG_PRBS
Definition: ad9144.h:188