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53 #define REG_SPI_INTFCONFA 0x000
54 #define REG_SPI_INTFCONFB 0x001
55 #define REG_SPI_DEVCONF 0x002
56 #define REG_SPI_PRODIDL 0x004
57 #define REG_SPI_PRODIDH 0x005
58 #define REG_SPI_CHIPGRADE 0x006
59 #define REG_SPI_PAGEINDX 0x008
60 #define REG_SPI_DEVINDX2 0x009
61 #define REG_SPI_SCRATCHPAD 0x00A
62 #define REG_SPI_MS_UPDATE 0x00F
63 #define REG_PWRCNTRL0 0x011
64 #define REG_TXENMASK1 0x012
65 #define REG_PWRCNTRL3 0x013
66 #define REG_COARSE_GROUP_DLY 0x014
67 #define REG_IRQ_ENABLE0 0x01F
68 #define REG_IRQ_ENABLE1 0x020
69 #define REG_IRQ_ENABLE2 0x021
70 #define REG_IRQ_ENABLE3 0x022
71 #define REG_IRQ_STATUS0 0x023
72 #define REG_IRQ_STATUS1 0x024
73 #define REG_IRQ_STATUS2 0x025
74 #define REG_IRQ_STATUS3 0x026
75 #define REG_JESD_CHECKS 0x030
76 #define REG_SYNC_TESTCTRL 0x031
77 #define REG_SYNC_DACDELAY_L 0x032
78 #define REG_SYNC_DACDELAY_H 0x033
79 #define REG_SYNC_ERRWINDOW 0x034
80 #define REG_SYNC_DLYCOUNT 0x035
81 #define REG_SYNC_REFCOUNT 0x036
82 #define REG_SYNC_LASTERR_L 0x038
83 #define REG_SYNC_LASTERR_H 0x039
84 #define REG_SYNC_CTRL 0x03A
85 #define REG_SYNC_STATUS 0x03B
86 #define REG_SYNC_CURRERR_L 0x03C
87 #define REG_SYNC_CURRERR_H 0x03D
88 #define REG_ERROR_THERM 0x03E
89 #define REG_DACGAIN0_1 0x040
90 #define REG_DACGAIN0_0 0x041
91 #define REG_DACGAIN1_1 0x042
92 #define REG_DACGAIN1_0 0x043
93 #define REG_DACGAIN2_1 0x044
94 #define REG_DACGAIN2_0 0x045
95 #define REG_DACGAIN3_1 0x046
96 #define REG_DACGAIN3_0 0x047
97 #define REG_PD_DACLDO 0x048
98 #define REG_STAT_DACLDO 0x049
99 #define REG_DECODE_CTRL0 0x04B
100 #define REG_DECODE_CTRL1 0x04C
101 #define REG_DECODE_CTRL2 0x04D
102 #define REG_DECODE_CTRL3 0x04E
103 #define REG_NCO_CLRMODE 0x050
104 #define REG_NCOKEY_ILSB 0x051
105 #define REG_NCOKEY_IMSB 0x052
106 #define REG_NCOKEY_QLSB 0x053
107 #define REG_NCOKEY_QMSB 0x054
108 #define REG_PA_THRES0 0x060
109 #define REG_PA_THRES1 0x061
110 #define REG_PA_AVG_TIME 0x062
111 #define REG_PA_POWER0 0x063
112 #define REG_PA_POWER1 0x064
113 #define REG_CLKCFG0 0x080
114 #define REG_SYSREF_ACTRL0 0x081
115 #define REG_SYSREF_ACTRL1 0x082
116 #define REG_DACPLLCNTRL 0x083
117 #define REG_DACPLLSTATUS 0x084
118 #define REG_DACINTEGERWORD0 0x085
119 #define REG_DACLOOPFILT1 0x087
120 #define REG_DACLOOPFILT2 0x088
121 #define REG_DACLOOPFILT3 0x089
122 #define REG_DACCPCNTRL 0x08A
123 #define REG_DACLOGENCNTRL 0x08B
124 #define REG_DACLDOCNTRL1 0x08C
125 #define REG_CAL_DAC_ERR 0x0E0
126 #define REG_CAL_MSB_THRES 0x0E1
127 #define REG_CAL_CTRL_GLOBAL 0x0E2
128 #define REG_CAL_MSBHILVL 0x0E3
129 #define REG_CAL_MSBLOLVL 0x0E4
130 #define REG_CAL_THRESH 0x0E5
131 #define REG_CAL_AVG_CNT 0x0E6
132 #define REG_CAL_CLKDIV 0x0E7
133 #define REG_CAL_INDX 0x0E8
134 #define REG_CAL_CTRL 0x0E9
135 #define REG_CAL_ADDR 0x0EA
136 #define REG_CAL_DATA 0x0EB
137 #define REG_CAL_UPDATE 0x0EC
138 #define REG_CAL_INIT 0x0ED
139 #define REG_DATA_FORMAT 0x110
140 #define REG_DATAPATH_CTRL 0x111
141 #define REG_INTERP_MODE 0x112
142 #define REG_NCO_FTW_UPDATE 0x113
143 #define REG_FTW0 0x114
144 #define REG_FTW1 0x115
145 #define REG_FTW2 0x116
146 #define REG_FTW3 0x117
147 #define REG_FTW4 0x118
148 #define REG_FTW5 0x119
149 #define REG_NCO_PHASE_OFFSET0 0x11A
150 #define REG_NCO_PHASE_OFFSET1 0x11B
151 #define REG_NCO_PHASE_ADJ0 0x11C
152 #define REG_NCO_PHASE_ADJ1 0x11D
153 #define REG_TXEN_FUNC 0x11E
154 #define REG_TXEN_SM_0 0x11F
155 #define REG_TXEN_SM_1 0x120
156 #define REG_TXEN_SM_2 0x121
157 #define REG_TXEN_SM_3 0x122
158 #define REG_TXEN_SM_4 0x123
159 #define REG_TXEN_SM_5 0x124
160 #define REG_DACOUT_ON_DOWN 0x125
161 #define REG_DACOFF 0x12C
162 #define REG_DATA_PATH_FLUSH_COUNT0 0x12D
163 #define REG_DATA_PATH_FLUSH_COUNT1 0x12E
164 #define REG_DIE_TEMP_CTRL0 0x12F
165 #define REG_DIE_TEMP_CTRL1 0x130
166 #define REG_DIE_TEMP_CTRL2 0x131
167 #define REG_DIE_TEMP0 0x132
168 #define REG_DIE_TEMP1 0x133
169 #define REG_DIE_TEMP_UPDATE 0x134
170 #define REG_DC_OFFSET_CTRL 0x135
171 #define REG_IPATH_DC_OFFSET_1PART0 0x136
172 #define REG_IPATH_DC_OFFSET_1PART1 0x137
173 #define REG_QPATH_DC_OFFSET_1PART0 0x138
174 #define REG_QPATH_DC_OFFSET_1PART1 0x139
175 #define REG_IPATH_DC_OFFSET_2PART 0x13A
176 #define REG_QPATH_DC_OFFSET_2PART 0x13B
177 #define REG_IDAC_DIG_GAIN0 0x13C
178 #define REG_IDAC_DIG_GAIN1 0x13D
179 #define REG_QDAC_DIG_GAIN0 0x13E
180 #define REG_QDAC_DIG_GAIN1 0x13F
181 #define REG_GAIN_RAMP_UP_STP0 0x140
182 #define REG_GAIN_RAMP_UP_STP1 0x141
183 #define REG_GAIN_RAMP_DOWN_STP0 0x142
184 #define REG_GAIN_RAMP_DOWN_STP1 0x143
185 #define REG_BLSM_CTRL 0x146
186 #define REG_BLSM_STAT 0x147
187 #define REG_PRBS 0x14B
188 #define REG_PRBS_ERROR_I 0x14C
189 #define REG_PRBS_ERROR_Q 0x14D
190 #define REG_DACPLLT5 0x1B5
191 #define REG_DACPLLTB 0x1BB
192 #define REG_DACPLLTD 0x1BD
193 #define REG_DACPLLT17 0x1C4
194 #define REG_DACPLLT18 0x1C5
195 #define REG_ASPI_SPARE0 0x1C6
196 #define REG_ASPI_SPARE1 0x1C7
197 #define REG_SPISTRENGTH 0x1DF
198 #define REG_CLK_TEST 0x1EB
199 #define REG_ATEST_VOLTS 0x1EC
200 #define REG_ASPI_CLKSRC 0x1ED
201 #define REG_MASTER_PD 0x200
202 #define REG_PHY_PD 0x201
203 #define REG_GENERIC_PD 0x203
204 #define REG_CDR_RESET 0x206
205 #define REG_CDR_OPERATING_MODE_REG_0 0x230
206 #define REG_CONFIG_REG3 0x232
207 #define REG_EQ_CONFIG_PHY_0_1 0x250
208 #define REG_EQ_CONFIG_PHY_2_3 0x251
209 #define REG_EQ_CONFIG_PHY_4_5 0x252
210 #define REG_EQ_CONFIG_PHY_6_7 0x253
211 #define REG_EQ_BIAS_REG 0x268
212 #define REG_SYNTH_ENABLE_CNTRL 0x280
213 #define REG_PLL_STATUS 0x281
214 #define REG_REF_CLK_DIVIDER_LDO 0x289
215 #define REG_SERDES_PLL_CTRL 0x291
216 #define REG_SERDES_PLL_CP3 0x29c
217 #define REG_SERDES_PLL_VAR3 0x29f
218 #define REG_DEV_CONFIG_8 0x2A4
219 #define REG_TERM_BLK1_CTRLREG0 0x2A7
220 #define REG_TERM_BLK1_CTRLREG1 0x2A8
221 #define REG_DEV_CONFIG_9 0x2AA
222 #define REG_DEV_CONFIG_10 0x2AB
223 #define REG_TERM_BLK2_CTRLREG0 0x2AE
224 #define REG_TERM_BLK2_CTRLREG1 0x2AF
225 #define REG_DEV_CONFIG_11 0x2B1
226 #define REG_DEV_CONFIG_12 0x2B2
227 #define REG_GENERAL_JRX_CTRL_0 0x300
228 #define REG_GENERAL_JRX_CTRL_1 0x301
229 #define REG_DYN_LINK_LATENCY_0 0x302
230 #define REG_DYN_LINK_LATENCY_1 0x303
231 #define REG_LMFC_DELAY_0 0x304
232 #define REG_LMFC_DELAY_1 0x305
233 #define REG_LMFC_VAR_0 0x306
234 #define REG_LMFC_VAR_1 0x307
235 #define REG_XBAR_LN_0_1 0x308
236 #define REG_XBAR_LN_2_3 0x309
237 #define REG_XBAR_LN_4_5 0x30A
238 #define REG_XBAR_LN_6_7 0x30B
239 #define REG_FIFO_STATUS_REG_0 0x30C
240 #define REG_FIFO_STATUS_REG_1 0x30D
241 #define REG_FIFO_STATUS_REG_2 0x30E
242 #define REG_SYNCB_GEN_0 0x311
243 #define REG_SYNCB_GEN_1 0x312
244 #define REG_SYNCB_GEN_3 0x313
245 #define REG_SERDES_SPI_REG 0x314
246 #define REG_PHY_PRBS_TEST_EN 0x315
247 #define REG_PHY_PRBS_TEST_CTRL 0x316
248 #define REG_PHY_PRBS_TEST_THRESH_LOBITS 0x317
249 #define REG_PHY_PRBS_TEST_THRESH_MIDBITS 0x318
250 #define REG_PHY_PRBS_TEST_THRESH_HIBITS 0x319
251 #define REG_PHY_PRBS_TEST_ERRCNT_LOBITS 0x31A
252 #define REG_PHY_PRBS_TEST_ERRCNT_MIDBITS 0x31B
253 #define REG_PHY_PRBS_TEST_ERRCNT_HIBITS 0x31C
254 #define REG_PHY_PRBS_TEST_STATUS 0x31D
255 #define REG_SHORT_TPL_TEST_0 0x32C
256 #define REG_SHORT_TPL_TEST_1 0x32D
257 #define REG_SHORT_TPL_TEST_2 0x32E
258 #define REG_SHORT_TPL_TEST_3 0x32F
259 #define REG_DEVICE_CONFIG_REG_13 0x333
260 #define REG_JESD_BIT_INVERSE_CTRL 0x334
261 #define REG_DID_REG 0x400
262 #define REG_BID_REG 0x401
263 #define REG_LID0_REG 0x402
264 #define REG_SCR_L_REG 0x403
265 #define REG_F_REG 0x404
266 #define REG_K_REG 0x405
267 #define REG_M_REG 0x406
268 #define REG_CS_N_REG 0x407
269 #define REG_NP_REG 0x408
270 #define REG_S_REG 0x409
271 #define REG_HD_CF_REG 0x40A
272 #define REG_RES1_REG 0x40B
273 #define REG_RES2_REG 0x40C
274 #define REG_CHECKSUM_REG 0x40D
275 #define REG_COMPSUM0_REG 0x40E
276 #define REG_LID1_REG 0x412
277 #define REG_CHECKSUM1_REG 0x415
278 #define REG_COMPSUM1_REG 0x416
279 #define REG_LID2_REG 0x41A
280 #define REG_CHECKSUM2_REG 0x41D
281 #define REG_COMPSUM2_REG 0x41E
282 #define REG_LID3_REG 0x422
283 #define REG_CHECKSUM3_REG 0x425
284 #define REG_COMPSUM3_REG 0x426
285 #define REG_LID4_REG 0x42A
286 #define REG_CHECKSUM4_REG 0x42D
287 #define REG_COMPSUM4_REG 0x42E
288 #define REG_LID5_REG 0x432
289 #define REG_CHECKSUM5_REG 0x435
290 #define REG_COMPSUM5_REG 0x436
291 #define REG_LID6_REG 0x43A
292 #define REG_CHECKSUM6_REG 0x43D
293 #define REG_COMPSUM6_REG 0x43E
294 #define REG_LID7_REG 0x442
295 #define REG_CHECKSUM7_REG 0x445
296 #define REG_COMPSUM7_REG 0x446
297 #define REG_ILS_DID 0x450
298 #define REG_ILS_BID 0x451
299 #define REG_ILS_LID0 0x452
300 #define REG_ILS_SCR_L 0x453
301 #define REG_ILS_F 0x454
302 #define REG_ILS_K 0x455
303 #define REG_ILS_M 0x456
304 #define REG_ILS_CS_N 0x457
305 #define REG_ILS_NP 0x458
306 #define REG_ILS_S 0x459
307 #define REG_ILS_HD_CF 0x45A
308 #define REG_ILS_RES1 0x45B
309 #define REG_ILS_RES2 0x45C
310 #define REG_ILS_CHECKSUM 0x45D
311 #define REG_ERRCNTRMON 0x46B
312 #define REG_LANEDESKEW 0x46C
313 #define REG_BADDISPARITY 0x46D
314 #define REG_NITDISPARITY 0x46E
315 #define REG_UNEXPECTEDKCHAR 0x46F
316 #define REG_CODEGRPSYNCFLG 0x470
317 #define REG_FRAMESYNCFLG 0x471
318 #define REG_GOODCHKSUMFLG 0x472
319 #define REG_INITLANESYNCFLG 0x473
320 #define REG_CTRLREG1 0x476
321 #define REG_CTRLREG2 0x477
322 #define REG_KVAL 0x478
323 #define REG_IRQVECTOR 0x47A
324 #define REG_SYNCASSERTIONMASK 0x47B
325 #define REG_ERRORTHRES 0x47C
326 #define REG_LANEENABLE 0x47D
331 #define SOFTRESET_M (1 << 7)
332 #define LSBFIRST_M (1 << 6)
333 #define ADDRINC_M (1 << 5)
334 #define SDOACTIVE_M (1 << 4)
335 #define SDOACTIVE (1 << 3)
336 #define ADDRINC (1 << 2)
337 #define LSBFIRST (1 << 1)
338 #define SOFTRESET (1 << 0)
343 #define SINGLEINS (1 << 7)
344 #define CSBSTALL (1 << 6)
349 #define DEVSTATUS(x) (((x) & 0xF) << 4)
350 #define CUSTOPMODE(x) (((x) & 0x3) << 2)
351 #define SYSOPMODE(x) (((x) & 0x3) << 0)
356 #define PROD_GRADE(x) (((x) & 0xF) << 4)
357 #define DEV_REVISION(x) (((x) & 0xF) << 0)
362 #define PAGEINDX(x) (((x) & 0x3) << 0)
367 #define SLAVEUPDATE (1 << 0)
372 #define PD_BG (1 << 7)
373 #define PD_DAC_0 (1 << 6)
374 #define PD_DAC_1 (1 << 5)
375 #define PD_DAC_2 (1 << 4)
376 #define PD_DAC_3 (1 << 3)
377 #define PD_DACM (1 << 2)
382 #define SYS_MASK (1 << 2)
383 #define DACB_MASK (1 << 1)
384 #define DACA_MASK (1 << 0)
389 #define ENA_PA_CTRL_FROM_PAPROT_ERR (1 << 6)
390 #define ENA_PA_CTRL_FROM_TXENSM (1 << 5)
391 #define ENA_PA_CTRL_FROM_BLSM (1 << 4)
392 #define ENA_PA_CTRL_FROM_SPI (1 << 3)
393 #define SPI_PA_CTRL (1 << 2)
394 #define ENA_SPI_TXEN (1 << 1)
395 #define SPI_TXEN (1 << 0)
400 #define COARSE_GROUP_DLY(x) (((x) & 0xF) << 0)
405 #define EN_CALPASS (1 << 7)
406 #define EN_CALFAIL (1 << 6)
407 #define EN_DACPLLLOST (1 << 5)
408 #define EN_DACPLLLOCK (1 << 4)
409 #define EN_SERPLLLOST (1 << 3)
410 #define EN_SERPLLLOCK (1 << 2)
411 #define EN_LANEFIFOERR (1 << 1)
412 #define EN_DRDLFIFOERR (1 << 0)
417 #define EN_PARMBAD (1 << 7)
418 #define EN_PRBSQ1 (1 << 3)
419 #define EN_PRBSI1 (1 << 2)
420 #define EN_PRBSQ0 (1 << 1)
421 #define EN_PRBSI0 (1 << 0)
426 #define EN_PAERR0 (1 << 7)
427 #define EN_BIST_DONE0 (1 << 6)
428 #define EN_BLNKDONE0 (1 << 5)
429 #define EN_REFNCOCLR0 (1 << 4)
430 #define EN_REFLOCK0 (1 << 3)
431 #define EN_REFROTA0 (1 << 2)
432 #define EN_REFWLIM0 (1 << 1)
433 #define EN_REFTRIP0 (1 << 0)
438 #define EN_PAERR1 (1 << 7)
439 #define EN_BIST_DONE1 (1 << 6)
440 #define EN_BLNKDONE1 (1 << 5)
441 #define EN_REFNCOCLR1 (1 << 4)
442 #define EN_REFLOCK1 (1 << 3)
443 #define EN_REFROTA1 (1 << 2)
444 #define EN_REFWLIM1 (1 << 1)
445 #define EN_REFTRIP1 (1 << 0)
450 #define IRQ_CALPASS (1 << 7)
451 #define IRQ_CALFAIL (1 << 6)
452 #define IRQ_DACPLLLOST (1 << 5)
453 #define IRQ_DACPLLLOCK (1 << 4)
454 #define IRQ_SERPLLLOST (1 << 3)
455 #define IRQ_SERPLLLOCK (1 << 2)
456 #define IRQ_LANEFIFOERR (1 << 1)
457 #define IRQ_DRDLFIFOERR (1 << 0)
462 #define IRQ_PARMBAD (1 << 7)
463 #define IRQ_PRBSQ1 (1 << 3)
464 #define IRQ_PRBSI1 (1 << 2)
465 #define IRQ_PRBSQ0 (1 << 1)
466 #define IRQ_PRBSI0 (1 << 0)
471 #define IRQ_PAERR0 (1 << 7)
472 #define IRQ_BIST_DONE0 (1 << 6)
473 #define IRQ_BLNKDONE0 (1 << 5)
474 #define IRQ_REFNCOCLR0 (1 << 4)
475 #define IRQ_REFLOCK0 (1 << 3)
476 #define IRQ_REFROTA0 (1 << 2)
477 #define IRQ_REFWLIM0 (1 << 1)
478 #define IRQ_REFTRIP0 (1 << 0)
483 #define IRQ_PAERR1 (1 << 7)
484 #define IRQ_BIST_DONE1 (1 << 6)
485 #define IRQ_BLNKDONE1 (1 << 5)
486 #define IRQ_REFNCOCLR1 (1 << 4)
487 #define IRQ_REFLOCK1 (1 << 3)
488 #define IRQ_REFROTA1 (1 << 2)
489 #define IRQ_REFWLIM1 (1 << 1)
490 #define IRQ_REFTRIP1 (1 << 0)
495 #define ERR_DLYOVER (1 << 5)
496 #define ERR_WINLIMIT (1 << 4)
497 #define ERR_JESDBAD (1 << 3)
498 #define ERR_KUNSUPP (1 << 2)
499 #define ERR_SUBCLASS (1 << 1)
500 #define ERR_INTSUPP (1 << 0)
505 #define TARRFAPHAZ (1 << 0)
506 #define SYNCBYPASS(x) (((x) & 0x3) << 6)
511 #define DAC_DELAY_H (1 << 0)
516 #define ERRWINDOW(x) (((x) & 0x7) << 0)
521 #define LASTUNDER (1 << 7)
522 #define LASTOVER (1 << 6)
523 #define LASTERROR_H (1 << 0)
528 #define SYNCENABLE (1 << 7)
529 #define SYNCARM (1 << 6)
530 #define SYNCCLRSTKY (1 << 5)
531 #define SYNCCLRLAST (1 << 4)
532 #define SYNCMODE(x) (((x) & 0xF) << 0)
537 #define REFBUSY (1 << 7)
538 #define REFLOCK (1 << 3)
539 #define REFROTA (1 << 2)
540 #define REFWLIM (1 << 1)
541 #define REFTRIP (1 << 0)
546 #define CURRUNDER (1 << 7)
547 #define CURROVER (1 << 6)
548 #define CURRERROR_H (1 << 0)
553 #define THRMOLD (1 << 7)
554 #define THRMOVER (1 << 4)
555 #define THRMPOS (1 << 3)
556 #define THRMZERO (1 << 2)
557 #define THRMNEG (1 << 1)
558 #define THRMUNDER (1 << 0)
563 #define DACGAIN_IM0(x) (((x) & 0x3) << 0)
568 #define DACGAIN_IM1(x) (((x) & 0x3) << 0)
573 #define DACGAIN_IM2(x) (((x) & 0x3) << 0)
578 #define DACGAIN_IM3(x) (((x) & 0x3) << 0)
583 #define ENB_DACLDO3 (1 << 7)
584 #define ENB_DACLDO2 (1 << 6)
585 #define ENB_DACLDO1 (1 << 5)
586 #define ENB_DACLDO0 (1 << 4)
591 #define STAT_LDO3 (1 << 3)
592 #define STAT_LDO2 (1 << 2)
593 #define STAT_LDO1 (1 << 1)
594 #define STAT_LDO0 (1 << 0)
599 #define SHUFFLE_MSB0 (1 << 2)
600 #define SHUFFLE_ISB0 (1 << 1)
605 #define SHUFFLE_MSB1 (1 << 2)
606 #define SHUFFLE_ISB1 (1 << 1)
611 #define SHUFFLE_MSB2 (1 << 2)
612 #define SHUFFLE_ISB2 (1 << 1)
617 #define SHUFFLE_MSB3 (1 << 2)
618 #define SHUFFLE_ISB3 (1 << 1)
623 #define NCOCLRARM (1 << 7)
624 #define NCOCLRMTCH (1 << 5)
625 #define NCOCLRPASS (1 << 4)
626 #define NCOCLRFAIL (1 << 3)
627 #define NCOCLRMODE(x) (((x) & 0x3) << 0)
632 #define PA_THRESH_MSB(x) (((x) & 0x1F) << 0)
637 #define PA_ENABLE (1 << 7)
638 #define PA_BUS_SWAP (1 << 6)
639 #define PA_AVG_TIME(x) (((x) & 0xF) << 0)
644 #define PA_POWER_MSB(x) (((x) & 0x1F) << 0)
649 #define PD_CLK01 (1 << 7)
650 #define PD_CLK23 (1 << 6)
651 #define PD_CLK_DIG (1 << 5)
652 #define PD_PCLK (1 << 4)
653 #define PD_CLK_REC (1 << 3)
658 #define PD_SYSREF (1 << 4)
659 #define HYS_ON (1 << 3)
660 #define SYSREF_RISE (1 << 2)
661 #define HYS_CNTRL1(x) (((x) & 0x3) << 0)
666 #define SYNTH_RECAL (1 << 7)
667 #define ENABLE_SYNTH (1 << 4)
672 #define CP_CAL_VALID (1 << 5)
673 #define RFPLL_LOCK (1 << 1)
678 #define LF_C2_WORD(x) (((x) & 0xF) << 4)
679 #define LF_C1_WORD(x) (((x) & 0xF) << 0)
684 #define LF_R1_WORD(x) (((x) & 0xF) << 4)
685 #define LF_C3_WORD(x) (((x) & 0xF) << 0)
690 #define LF_BYPASS_R3 (1 << 7)
691 #define LF_BYPASS_R1 (1 << 6)
692 #define LF_BYPASS_C2 (1 << 5)
693 #define LF_BYPASS_C1 (1 << 4)
694 #define LF_R3_WORD(x) (((x) & 0xF) << 0)
699 #define CP_CURRENT(x) (((x) & 0x3F) << 0)
704 #define LO_DIV_MODE(x) (((x) & 0x3) << 0)
709 #define REF_DIVRATE(x) (((x) & 0x7) << 0)
714 #define INIT_SWEEP_ERR_DAC (1 << 1)
715 #define MSB_SWEEP_ERR_DAC (1 << 0)
720 #define CAL_MSB_TAC(x) (((x) & 0x7) << 0)
725 #define CAL_START_GL (1 << 1)
726 #define CAL_EN_GL (1 << 0)
731 #define CAL_MSBLVLHI(x) (((x) & 0x3F) << 0)
736 #define CAL_MSBLVLLO(x) (((x) & 0x3F) << 0)
741 #define CAL_LTAC_THRES(x) (((x) & 0x7) << 3)
742 #define CAL_TAC_THRES(x) (((x) & 0x7) << 0)
747 #define MSB_GLOBAL_SUBAVG(x) (((x) & 0x3) << 6)
748 #define GLOBAL_AVG_CNT(x) (((x) & 0x7) << 3)
749 #define LOCAL_AVRG_CNT(x) (((x) & 0x7) << 0)
754 #define CAL_CLKDIV(x) (((x) & 0xF) << 0)
759 #define CAL_INDX(x) (((x) & 0xF) << 0)
764 #define CAL_FIN (1 << 7)
765 #define CAL_ACTIVE (1 << 6)
766 #define CAL_ERRHI (1 << 5)
767 #define CAL_ERRLO (1 << 4)
768 #define CAL_TXDACBYDAC (1 << 3)
769 #define CAL_START (1 << 1)
770 #define CAL_EN (1 << 0)
775 #define CAL_ADDR(x) (((x) & 0x3F) << 0)
780 #define CAL_DATA(x) (((x) & 0x3F) << 0)
785 #define CAL_UPDATE (1 << 7)
790 #define BINARY_FORMAT (1 << 7)
795 #define INVSINC_ENABLE (1 << 7)
796 #define DIG_GAIN_ENABLE (1 << 5)
797 #define PHASE_ADJ_ENABLE (1 << 4)
798 #define SEL_SIDEBAND (1 << 1)
799 #define I_TO_Q (1 << 0)
800 #define MODULATION_TYPE(x) (((x) & 0x3) << 2)
801 #define MODULATION_TYPE_MASK (0x03 << 2)
806 #define INTERP_MODE(x) (((x) & 0x7) << 0)
811 #define FTW_UPDATE_ACK (1 << 1)
812 #define FTW_UPDATE_REQ (1 << 0)
817 #define TX_DIG_CLK_PD (1 << 0)
822 #define GP_PA_ON_INVERT (1 << 2)
823 #define GP_PA_CTRL (1 << 1)
824 #define TXEN_SM_EN (1 << 0)
825 #define PA_FALL(x) (((x) & 0x3) << 6)
826 #define PA_RISE(x) (((x) & 0x3) << 4)
831 #define DIG_FALL(x) (((x) & 0x3) << 6)
832 #define DIG_RISE(x) (((x) & 0x3) << 4)
833 #define DAC_FALL(x) (((x) & 0x3) << 2)
834 #define DAC_RISE(x) (((x) & 0x3) << 0)
839 #define DACOUT_SHUTDOWN (1 << 1)
840 #define DACOUT_ON_TRIGGER (1 << 0)
845 #define PROTECT_MODE (1 << 7)
846 #define DACOFF_AVG_PW (1 << 0)
851 #define ADC_TESTMODE (1 << 7)
852 #define AUXADC_ENABLE (1 << 0)
853 #define FS_CURRENT(x) (((x) & 0x7) << 4)
854 #define REF_CURRENT(x) (((x) & 0x7) << 1)
859 #define SELECT_CLKDIG (1 << 3)
860 #define EN_DIV2 (1 << 2)
861 #define INCAP_CTRL(x) (((x) & 0x3) << 0)
866 #define DIE_TEMP_UPDATE (1 << 0)
871 #define DISABLE_NOISE (1 << 1)
872 #define DC_OFFSET_ON (1 << 0)
877 #define IPATH_DC_OFFSET_2PART(x) (((x) & 0x1F) << 0)
882 #define QPATH_DC_OFFSET_2PART(x) (((x) & 0x1F) << 0)
887 #define IDAC_DIG_GAIN1(x) (((x) & 0xF) << 0)
892 #define QDAC_DIG_GAIN1(x) (((x) & 0xF) << 0)
897 #define GAIN_RAMP_UP_STP1(x) (((x) & 0xF) << 0)
902 #define GAIN_RAMP_DOWN_STP1(x) (((x) & 0xF) << 0)
907 #define RESET_BLSM (1 << 7)
908 #define EN_FORCE_GAIN_SOFT_OFF (1 << 4)
909 #define GAIN_SOFT_OFF (1 << 3)
910 #define GAIN_SOFT_ON (1 << 2)
911 #define EN_FORCE_GAIN_SOFT_ON (1 << 1)
916 #define SOFT_OFF_DONE (1 << 5)
917 #define SOFT_ON_DONE (1 << 4)
918 #define GAIN_SOFT_OFF_RB (1 << 3)
919 #define GAIN_SOFT_ON_RB (1 << 2)
920 #define SOFT_OFF_EN_RB (1 << 1)
921 #define SOFT_ON_EN_RB (1 << 0)
922 #define SOFTBLANKRB(x) (((x) & 0x3) << 6)
927 #define PRBS_GOOD_Q (1 << 7)
928 #define PRBS_GOOD_I (1 << 6)
929 #define PRBS_INV_Q (1 << 4)
930 #define PRBS_INV_I (1 << 3)
931 #define PRBS_MODE (1 << 2)
932 #define PRBS_RESET (1 << 1)
933 #define PRBS_EN (1 << 0)
938 #define VCO_VAR(x) (((x) & 0xF) << 0)
943 #define VCO_BIAS_REF(x) (((x) & 0x7) << 0)
948 #define VCO_CAL_REF_MON (1 << 3)
949 #define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0)
954 #define VCO_VAR_REF_TCF(x) (((x) & 0x7) << 4)
955 #define VCO_VAR_OFF(x) (((x) & 0xF) << 0)
960 #define SPIDRV(x) (((x) & 0xF) << 0)
965 #define DUTYCYCLEON (1 << 0)
970 #define ATEST_EN (1 << 0)
971 #define ATEST_TOPVSEL(x) (((x) & 0x3) << 5)
972 #define ATEST_DACSEL(x) (((x) & 0x3) << 3)
973 #define ATEST_VSEL(x) (((x) & 0x3) << 1)
978 #define EN_CLKDIV (1 << 3)
979 #define ASPI_OSC_RATE (1 << 2)
980 #define ASPI_CLK_SRC (1 << 1)
981 #define EN_ASPI_OSC (1 << 0)
986 #define SPI_PD_MASTER (1 << 0)
991 #define SPI_SYNC1_PD (1 << 1)
992 #define SPI_SYNC2_PD (1 << 0)
997 #define SPI_ENHALFRATE (1 << 5)
998 #define SPI_DIVISION_RATE(x) (((x) & 0x3) << 1)
1003 #define SPI_EQ_CONFIG1(x) (((x) & 0xF) << 4)
1004 #define SPI_EQ_CONFIG0(x) (((x) & 0xF) << 0)
1009 #define SPI_EQ_CONFIG3(x) (((x) & 0xF) << 4)
1010 #define SPI_EQ_CONFIG2(x) (((x) & 0xF) << 0)
1015 #define SPI_EQ_CONFIG5(x) (((x) & 0xF) << 4)
1016 #define SPI_EQ_CONFIG4(x) (((x) & 0xF) << 0)
1021 #define SPI_EQ_CONFIG7(x) (((x) & 0xF) << 4)
1022 #define SPI_EQ_CONFIG6(x) (((x) & 0xF) << 0)
1027 #define SPI_EQ_EXTRA_SPI_LSBITS(x) (((x) & 0x3) << 6)
1028 #define SPI_EQ_BIASPTAT(x) (((x) & 0x7) << 3)
1029 #define SPI_EQ_BIASPLY(x) (((x) & 0x7) << 0)
1034 #define SPI_RECAL_SYNTH (1 << 2)
1035 #define SPI_ENABLE_SYNTH (1 << 0)
1040 #define SPI_CP_CAL_VALID_RB (1 << 3)
1041 #define SPI_PLL_LOCK_RB (1 << 0)
1046 #define SPI_CDR_OVERSAMP(x) (((x) & 0x3) << 0)
1051 #define SPI_I_TUNE_R_CAL_TERMBLK1 (1 << 0)
1056 #define SPI_I_TUNE_R_CAL_TERMBLK2 (1 << 0)
1061 #define CHECKSUM_MODE (1 << 6)
1062 #define LINK_MODE (1 << 3)
1063 #define SEL_REG_MAP_1 (1 << 2)
1064 #define LINK_EN(x) (((x) & 0x3) << 0)
1069 #define SUBCLASSV_LOCAL(x) (((x) & 0x7) << 0)
1074 #define DYN_LINK_LATENCY_0(x) (((x) & 0x1F) << 0)
1079 #define DYN_LINK_LATENCY_1(x) (((x) & 0x1F) << 0)
1084 #define LMFC_DELAY_0(x) (((x) & 0x1F) << 0)
1089 #define LMFC_DELAY_1(x) (((x) & 0x1F) << 0)
1094 #define LMFC_VAR_0(x) (((x) & 0x1F) << 0)
1099 #define LMFC_VAR_1(x) (((x) & 0x1F) << 0)
1104 #define SRC_LANE1(x) (((x) & 0x7) << 3)
1105 #define SRC_LANE0(x) (((x) & 0x7) << 0)
1110 #define SRC_LANE3(x) (((x) & 0x7) << 3)
1111 #define SRC_LANE2(x) (((x) & 0x7) << 0)
1116 #define SRC_LANE5(x) (((x) & 0x7) << 3)
1117 #define SRC_LANE4(x) (((x) & 0x7) << 0)
1122 #define SRC_LANE7(x) (((x) & 0x7) << 3)
1123 #define SRC_LANE6(x) (((x) & 0x7) << 0)
1128 #define DRDL_FIFO_EMPTY (1 << 1)
1129 #define DRDL_FIFO_FULL (1 << 0)
1134 #define EOMF_MASK_1 (1 << 3)
1135 #define EOMF_MASK_0 (1 << 2)
1136 #define EOF_MASK_1 (1 << 1)
1137 #define EOF_MASK_0 (1 << 0)
1142 #define SYNCB_ERR_DUR(x) (((x) & 0xF) << 4)
1143 #define SYNCB_SYNCREQ_DUR(x) (((x) & 0xF) << 0)
1148 #define PHY_TEST_START (1 << 1)
1149 #define PHY_TEST_RESET (1 << 0)
1150 #define PHY_SRC_ERR_CNT(x) (((x) & 0x7) << 4)
1151 #define PHY_PRBS_PAT_SEL(x) (((x) & 0x3) << 2)
1156 #define SHORT_TPL_TEST_RESET (1 << 1)
1157 #define SHORT_TPL_TEST_EN (1 << 0)
1158 #define SHORT_TPL_SP_SEL(x) (((x) & 0x3) << 4)
1159 #define SHORT_TPL_M_SEL(x) (((x) & 0x3) << 2)
1164 #define SHORT_TPL_FAIL (1 << 0)
1169 #define ADJCNT_RD(x) (((x) & 0xF) << 4)
1170 #define BID_RD(x) (((x) & 0xF) << 0)
1175 #define ADJDIR_RD (1 << 6)
1176 #define PHADJ_RD (1 << 5)
1177 #define LID0_RD(x) (((x) & 0x1F) << 0)
1182 #define SCR_RD (1 << 7)
1183 #define L_RD(x) (((x) & 0x1F) << 0)
1188 #define K_RD(x) (((x) & 0x1F) << 0)
1193 #define CS_RD(x) (((x) & 0x3) << 6)
1194 #define N_RD(x) (((x) & 0x1F) << 0)
1199 #define SUBCLASSV_RD(x) (((x) & 0x7) << 5)
1200 #define NP_RD(x) (((x) & 0x1F) << 0)
1205 #define JESDV_RD(x) (((x) & 0x7) << 5)
1206 #define S_RD(x) (((x) & 0x1F) << 0)
1211 #define HD_RD (1 << 7)
1212 #define CF_RD(x) (((x) & 0x1F) << 0)
1217 #define LID1_RD(x) (((x) & 0x1F) << 0)
1222 #define LID2_RD(x) (((x) & 0x1F) << 0)
1227 #define LID3_RD(x) (((x) & 0x1F) << 0)
1232 #define LID4_RD(x) (((x) & 0x1F) << 0)
1237 #define LID5_RD(x) (((x) & 0x1F) << 0)
1242 #define LID6_RD(x) (((x) & 0x1F) << 0)
1247 #define LID7_RD(x) (((x) & 0x1F) << 0)
1252 #define ADJCNT(x) (((x) & 0xF) << 4)
1253 #define BID(x) (((x) & 0xF) << 0)
1258 #define ADJDIR (1 << 6)
1259 #define PHADJ (1 << 5)
1260 #define LID0(x) (((x) & 0x1F) << 0)
1265 #define SCR (1 << 7)
1266 #define L(x) (((x) & 0x1F) << 0)
1271 #define K(x) (((x) & 0x1F) << 0)
1276 #define CS(x) (((x) & 0x3) << 6)
1277 #define N(x) (((x) & 0x1F) << 0)
1282 #define SUBCLASSV(x) (((x) & 0x7) << 5)
1283 #define NP(x) (((x) & 0x1F) << 0)
1288 #define JESDV(x) (((x) & 0x7) << 5)
1289 #define S(x) (((x) & 0x1F) << 0)
1295 #define CF(x) (((x) & 0x1F) << 0)
1300 #define LANESEL(x) (((x) & 0x7) << 4)
1301 #define CNTRSEL(x) (((x) & 0x3) << 0)
1306 #define RST_IRQ_DIS (1 << 7)
1307 #define DIS_ERR_CNTR_DIS (1 << 6)
1308 #define RST_ERR_CNTR_DIS (1 << 5)
1309 #define LANE_ADDR_DIS(x) (((x) & 0x7) << 0)
1314 #define RST_IRQ_NIT (1 << 7)
1315 #define DIS_ERR_CNTR_NIT (1 << 6)
1316 #define RST_ERR_CNTR_NIT (1 << 5)
1317 #define LANE_ADDR_NIT(x) (((x) & 0x7) << 0)
1322 #define RST_IRQ_K (1 << 7)
1323 #define DIS_ERR_CNTR_K (1 << 6)
1324 #define RST_ERR_CNTR_K (1 << 5)
1325 #define LANE_ADDR_K(x) (((x) & 0x7) << 0)
1330 #define ILAS_MODE (1 << 7)
1331 #define REPDATATEST (1 << 5)
1332 #define QUETESTERR (1 << 4)
1333 #define AUTO_ECNTR_RST (1 << 3)
1338 #define BADDIS_FLAG_OR_MASK (1 << 7)
1339 #define NITD_FLAG_OR_MASK (1 << 6)
1340 #define UEKC_FLAG_OR_MASK (1 << 5)
1341 #define INITIALLANESYNC_FLAG_OR_MASK (1 << 3)
1342 #define BADCHECKSUM_FLAG_OR_MASK (1 << 2)
1343 #define CODEGRPSYNC_FLAG_OR_MASK (1 << 0)
1348 #define BAD_DIS_S (1 << 7)
1349 #define NIT_DIS_S (1 << 6)
1350 #define UNEX_K_S (1 << 5)
1351 #define CMM_FLAG_OR_MASK (1 << 4)
1352 #define CMM_ENABLE (1 << 3)
1355 #define AD9144_MAX_DAC_RATE 2000000000UL
1356 #define AD9144_CHIP_ID 0x44
1357 #define AD9144_PRBS7 0x0
1358 #define AD9144_PRBS15 0x1
1414 uint8_t exp_reg_data);
uint32_t pll_dac_frequency_khz
Definition: ad9144.h:1392
#define REG_CDR_RESET
Definition: ad9144.h:204
#define REG_XBAR_LN_6_7
Definition: ad9144.h:238
int32_t ad9144_short_pattern_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_short_pattern_test
Definition: ad9144.c:684
#define FTW_UPDATE_REQ
Definition: ad9144.h:812
#define REG_ILS_SCR_L
Definition: ad9144.h:300
#define SRC_LANE3(x)
Definition: ad9144.h:1110
#define REG_SHORT_TPL_TEST_1
Definition: ad9144.h:256
#define REG_DACINTEGERWORD0
Definition: ad9144.h:118
#define REG_CAL_CTRL
Definition: ad9144.h:134
int32_t ad9144_datapath_prbs_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_datapath_prbs_test
Definition: ad9144.c:724
#define REG_MASTER_PD
Definition: ad9144.h:201
uint16_t reg
Definition: ad9144.c:142
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
#define REG_PRBS_ERROR_I
Definition: ad9144.h:188
#define REG_LMFC_VAR_0
Definition: ad9144.h:233
#define REG_DACPLLSTATUS
Definition: ad9144.h:117
#define REG_GOODCHKSUMFLG
Definition: ad9144.h:318
#define SOFTRESET_M
Definition: ad9144.h:331
#define REG_LMFC_DELAY_1
Definition: ad9144.h:232
Header file of SPI Interface.
uint32_t sample_rate_khz
Definition: ad9144.h:1367
int32_t ad9144_dac_calibrate(struct ad9144_dev *dev)
Definition: ad9144.c:593
#define REG_DACLDOCNTRL1
Definition: ad9144.h:124
#define REG_SYSREF_ACTRL0
Definition: ad9144.h:114
int32_t ad9144_spi_write_seq(struct ad9144_dev *dev, const struct ad9144_reg_seq *seq, uint32_t num)
Definition: ad9144.c:146
#define REG_SHORT_TPL_TEST_2
Definition: ad9144.h:257
int32_t ad9144_status(struct ad9144_dev *dev)
ad9144_status - return the status of the JESD interface
Definition: ad9144.c:645
int32_t ad9144_setup(struct ad9144_dev **device, const struct ad9144_init_param *init_param)
ad9144_setup
Definition: ad9144.c:439
#define REG_XBAR_LN_2_3
Definition: ad9144.h:236
Header file of Delay functions.
uint8_t M
Definition: ad9144.c:51
uint32_t prbs_type
Definition: ad9144.h:1380
int32_t ad9144_set_nco(struct ad9144_dev *dev, int32_t f_carrier_khz, int16_t phase)
Definition: ad9144.c:368
#define REG_ILS_BID
Definition: ad9144.h:298
#define REG_ILS_DID
Definition: ad9144.h:297
int32_t ad9144_datapath_prbs_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_datapath_prbs_test
Definition: ad9144.c:724
uint8_t jesd204_subclass
Definition: ad9144.h:1383
Definition: ad9361_util.h:75
#define SRC_LANE0(x)
Definition: ad9144.h:1105
#define REG_DEV_CONFIG_9
Definition: ad9144.h:221
#define REG_FRAMESYNCFLG
Definition: ad9144.h:317
int32_t ad9144_set_nco(struct ad9144_dev *dev, int32_t f_carrier_khz, int16_t phase)
Definition: ad9144.c:368
int32_t ad9144_spi_read(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9144_spi_read
Definition: ad9144.c:74
#define REG_GENERAL_JRX_CTRL_1
Definition: ad9144.h:228
#define REG_ILS_CS_N
Definition: ad9144.h:304
#define REG_INTERP_MODE
Definition: ad9144.h:141
#define REG_ILS_S
Definition: ad9144.h:306
#define MODULATION_TYPE_MASK
Definition: ad9144.h:801
#define REG_ILS_K
Definition: ad9144.h:302
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
#define SRC_LANE1(x)
Definition: ad9144.h:1104
#define REG_DEV_CONFIG_12
Definition: ad9144.h:226
#define REG_REF_CLK_DIVIDER_LDO
Definition: ad9144.h:214
#define REG_DACPLLT5
Definition: ad9144.h:190
uint16_t val
Definition: ad9144.c:143
uint8_t S
Definition: ad9144.c:53
#define REG_LANEENABLE
Definition: ad9144.h:326
#define REG_SPI_PAGEINDX
Definition: ad9144.h:59
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
uint8_t interpolation
Definition: ad9144.h:1377
#define REG_XBAR_LN_0_1
Definition: ad9144.h:235
#define SEL_SIDEBAND
Definition: ad9144.h:798
#define REG_CAL_CLKDIV
Definition: ad9144.h:132
int32_t ad9144_spi_read(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9144_spi_read
Definition: ad9144.c:74
#define REG_EQ_BIAS_REG
Definition: ad9144.h:211
uint8_t jesd204_mode
Definition: ad9144.h:1382
int32_t ad9144_status(struct ad9144_dev *dev)
ad9144_status - return the status of the JESD interface
Definition: ad9144.c:645
#define REG_TERM_BLK2_CTRLREG0
Definition: ad9144.h:223
uint8_t jesd204_lane_xbar[8]
Definition: ad9144.h:1385
#define REG_NCO_PHASE_OFFSET0
Definition: ad9144.h:149
#define REG_CAL_INIT
Definition: ad9144.h:138
uint8_t num_lanes
Definition: ad9144.h:1369
#define REG_INITLANESYNCFLG
Definition: ad9144.h:319
#define REG_SHORT_TPL_TEST_0
Definition: ad9144.h:255
#define MODULATION_TYPE(x)
Definition: ad9144.h:800
#define SOFTRESET
Definition: ad9144.h:338
#define REG_SHORT_TPL_TEST_3
Definition: ad9144.h:258
#define REG_CDR_OPERATING_MODE_REG_0
Definition: ad9144.h:205
Definition: ad9144.h:1363
no_os_spi_init_param spi_init
Definition: ad9144.h:1374
#define REG_ILS_LID0
Definition: ad9144.h:299
#define REG_SPI_PRODIDL
Definition: ad9144.h:56
uint32_t pll_ref_frequency_khz
Definition: ad9144.h:1390
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
#define REG_DACLOGENCNTRL
Definition: ad9144.h:123
int32_t ad9144_remove(struct ad9144_dev *dev)
Free the resources allocated by ad9144_setup().
Definition: ad9144.c:631
#define REG_SYNTH_ENABLE_CNTRL
Definition: ad9144.h:212
#define AD9144_CHIP_ID
Definition: ad9144.h:1356
#define REG_ILS_HD_CF
Definition: ad9144.h:307
no_os_spi_desc * spi_desc
Definition: ad9144.h:1365
#define REG_PLL_STATUS
Definition: ad9144.h:213
#define REG_ILS_NP
Definition: ad9144.h:305
#define REG_PHY_PD
Definition: ad9144.h:202
#define REG_ILS_M
Definition: ad9144.h:303
#define REG_LANEDESKEW
Definition: ad9144.h:312
#define REG_TERM_BLK1_CTRLREG0
Definition: ad9144.h:219
int32_t ad9144_setup_jesd204_link(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
Definition: ad9144.c:193
#define REG_DACPLLT18
Definition: ad9144.h:194
#define NO_OS_BIT(x)
Definition: no_os_util.h:51
#define REG_FTW0
Definition: ad9144.h:143
#define REG_XBAR_LN_4_5
Definition: ad9144.h:237
int32_t ad9144_dac_calibrate(struct ad9144_dev *dev)
Definition: ad9144.c:593
#define REG_LMFC_DELAY_0
Definition: ad9144.h:231
#define NULL
Definition: wrapper.h:64
#define REG_CAL_INDX
Definition: ad9144.h:133
uint8_t L
Definition: ad9144.c:52
#define REG_DACPLLTB
Definition: ad9144.h:191
uint8_t num_converters
Definition: ad9144.h:1368
#define REG_DEV_CONFIG_11
Definition: ad9144.h:225
int32_t ad9144_spi_check_status(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_mask, uint8_t exp_reg_data)
ad9144_spi_check_status
Definition: ad9144.c:119
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
uint32_t stpl_samples[4][4]
Definition: ad9144.h:1378
Definition: ad9144.h:1372
int32_t ad9144_setup(struct ad9144_dev **device, const struct ad9144_init_param *init_param)
ad9144_setup
Definition: ad9144.c:439
#define REG_ILS_F
Definition: ad9144.h:301
#define REG_SPI_SCRATCHPAD
Definition: ad9144.h:61
uint8_t spi3wire
Definition: ad9144.h:1376
#define REG_NCO_FTW_UPDATE
Definition: ad9144.h:142
int32_t ad9144_spi_check_status(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_mask, uint8_t exp_reg_data)
ad9144_spi_check_status
Definition: ad9144.c:119
int32_t ad9144_short_pattern_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_short_pattern_test
Definition: ad9144.c:684
#define REG_SPI_INTFCONFA
Definition: ad9144.h:53
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
#define REG_CTRLREG1
Definition: ad9144.h:320
#define REG_DEV_CONFIG_10
Definition: ad9144.h:222
#define SRC_LANE5(x)
Definition: ad9144.h:1116
#define REG_CODEGRPSYNCFLG
Definition: ad9144.h:316
uint8_t jesd204_scrambling
Definition: ad9144.h:1384
#define REG_SYNCB_GEN_1
Definition: ad9144.h:243
uint8_t pll_enable
Definition: ad9144.h:1388
#define REG_LMFC_VAR_1
Definition: ad9144.h:234
int32_t ad9144_spi_write(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9144_spi_write
Definition: ad9144.c:97
#define REG_SYNC_CTRL
Definition: ad9144.h:84
uint8_t id
Definition: ad9144.c:50
#define REG_PWRCNTRL0
Definition: ad9144.h:63
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
Implementation of utility functions.
#define REG_NCO_PHASE_OFFSET1
Definition: ad9144.h:150
#define REG_DATAPATH_CTRL
Definition: ad9144.h:140
#define SRC_LANE2(x)
Definition: ad9144.h:1111
#define SRC_LANE6(x)
Definition: ad9144.h:1123
#define SRC_LANE7(x)
Definition: ad9144.h:1122
uint32_t lane_rate_kbps
Definition: ad9144.h:1379
#define SRC_LANE4(x)
Definition: ad9144.h:1117
#define REG_DACPLLCNTRL
Definition: ad9144.h:116
#define REG_CLKCFG0
Definition: ad9144.h:113
#define REG_SERDES_SPI_REG
Definition: ad9144.h:245
Header file of AD9144 Driver.
#define REG_PRBS_ERROR_Q
Definition: ad9144.h:189
#define REG_DATA_FORMAT
Definition: ad9144.h:139
int32_t ad9144_remove(struct ad9144_dev *dev)
Free the resources allocated by ad9144_setup().
Definition: ad9144.c:631
#define REG_GENERAL_JRX_CTRL_0
Definition: ad9144.h:227
int32_t ad9144_spi_write(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9144_spi_write
Definition: ad9144.c:97
chip_id
Definition: ad9172.h:57
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
uint8_t F
Definition: ad9144.c:54
#define REG_PRBS
Definition: ad9144.h:187