no-OS
ad9144.h
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1 /***************************************************************************/
39 #ifndef AD9144_H_
40 #define AD9144_H_
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include <stdint.h>
46 #include "no_os_delay.h"
47 #include "no_os_spi.h"
48 #include "no_os_util.h"
49 
50 /******************************************************************************/
51 /********************** Macros and Constants Definitions **********************/
52 /******************************************************************************/
53 #define REG_SPI_INTFCONFA 0x000 /* Interface configuration A */
54 #define REG_SPI_INTFCONFB 0x001 /* Interface configuration B */
55 #define REG_SPI_DEVCONF 0x002 /* Device Configuration */
56 #define REG_SPI_PRODIDL 0x004 /* Product Identification Low Byte */
57 #define REG_SPI_PRODIDH 0x005 /* Product Identification High Byte */
58 #define REG_SPI_CHIPGRADE 0x006 /* Chip Grade */
59 #define REG_SPI_PAGEINDX 0x008 /* Page Pointer or Device Index */
60 #define REG_SPI_DEVINDX2 0x009 /* Secondary Device Index */
61 #define REG_SPI_SCRATCHPAD 0x00A /* Scratch Pad */
62 #define REG_SPI_MS_UPDATE 0x00F /* Master/Slave Update Bit */
63 #define REG_PWRCNTRL0 0x011 /* Power Control Reg 1 */
64 #define REG_TXENMASK1 0x012 /* TXenable masks */
65 #define REG_PWRCNTRL3 0x013 /* Power control register 3 */
66 #define REG_COARSE_GROUP_DLY 0x014 /* Coarse Group Delay Adjustment */
67 #define REG_IRQ_ENABLE0 0x01F /* Interrupt Enable */
68 #define REG_IRQ_ENABLE1 0x020 /* Interrupt Enable */
69 #define REG_IRQ_ENABLE2 0x021 /* Interrupt Enable */
70 #define REG_IRQ_ENABLE3 0x022 /* Interrupt Enable */
71 #define REG_IRQ_STATUS0 0x023 /* Interrupt Status */
72 #define REG_IRQ_STATUS1 0x024 /* Interrupt Status */
73 #define REG_IRQ_STATUS2 0x025 /* Interrupt Status */
74 #define REG_IRQ_STATUS3 0x026 /* Interrupt Status */
75 #define REG_JESD_CHECKS 0x030 /* JESD Parameter Checking */
76 #define REG_SYNC_TESTCTRL 0x031 /* Sync Control Reg0 */
77 #define REG_SYNC_DACDELAY_L 0x032 /* Sync Logic DacDelay [7:0] */
78 #define REG_SYNC_DACDELAY_H 0x033 /* Sync Logic DacDelay [8] */
79 #define REG_SYNC_ERRWINDOW 0x034 /* Sync Error Window */
80 #define REG_SYNC_DLYCOUNT 0x035 /* Sync Control Ref Delay Count */
81 #define REG_SYNC_REFCOUNT 0x036 /* Sync SysRef InActive Interval */
82 #define REG_SYNC_LASTERR_L 0x038 /* SyncLASTerror_L */
83 #define REG_SYNC_LASTERR_H 0x039 /* SyncLASTerror_H */
84 #define REG_SYNC_CTRL 0x03A /* Sync Mode Control */
85 #define REG_SYNC_STATUS 0x03B /* Sync Alignment Flags */
86 #define REG_SYNC_CURRERR_L 0x03C /* Sync Alignment Error[7:0] */
87 #define REG_SYNC_CURRERR_H 0x03D /* Sync Alignment Error[8] */
88 #define REG_ERROR_THERM 0x03E /* Sync Error Thermometer */
89 #define REG_DACGAIN0_1 0x040 /* MSBs of Full Scale Adjust DAC */
90 #define REG_DACGAIN0_0 0x041 /* LSBs of Full Scale Adjust DAC */
91 #define REG_DACGAIN1_1 0x042 /* MSBs of Full Scale Adjust DAC */
92 #define REG_DACGAIN1_0 0x043 /* LSBs of Full Scale Adjust DAC */
93 #define REG_DACGAIN2_1 0x044 /* MSBs of Full Scale Adjust DAC */
94 #define REG_DACGAIN2_0 0x045 /* LSBs of Full Scale Adjust DAC */
95 #define REG_DACGAIN3_1 0x046 /* MSBs of Full Scale Adjust DAC */
96 #define REG_DACGAIN3_0 0x047 /* LSBs of Full Scale Adjust DAC */
97 #define REG_PD_DACLDO 0x048 /* Powerdown DAC LDOs */
98 #define REG_STAT_DACLDO 0x049 /* DAC LDO Status */
99 #define REG_DECODE_CTRL0 0x04B /* Decoder Control */
100 #define REG_DECODE_CTRL1 0x04C /* Decoder Control */
101 #define REG_DECODE_CTRL2 0x04D /* Decoder Control */
102 #define REG_DECODE_CTRL3 0x04E /* Decoder Control */
103 #define REG_NCO_CLRMODE 0x050 /* NCO CLR Mode */
104 #define REG_NCOKEY_ILSB 0x051 /* NCO Clear on Data Key I lsb */
105 #define REG_NCOKEY_IMSB 0x052 /* NCO Clear on Data Key I msb */
106 #define REG_NCOKEY_QLSB 0x053 /* NCO Clear on Data Key Q lsb */
107 #define REG_NCOKEY_QMSB 0x054 /* NCO Clear on Data Key Q msb */
108 #define REG_PA_THRES0 0x060 /* PDP Threshold */
109 #define REG_PA_THRES1 0x061 /* PDP Threshold */
110 #define REG_PA_AVG_TIME 0x062 /* PDP Control */
111 #define REG_PA_POWER0 0x063 /* PDP Power */
112 #define REG_PA_POWER1 0x064 /* PDP Power */
113 #define REG_CLKCFG0 0x080 /* Clock Configuration */
114 #define REG_SYSREF_ACTRL0 0x081 /* SYSREF Analog Control 0 */
115 #define REG_SYSREF_ACTRL1 0x082 /* SYSREF Analog Control 1 */
116 #define REG_DACPLLCNTRL 0x083 /* Top Level Control DAC Clock PLL */
117 #define REG_DACPLLSTATUS 0x084 /* DAC PLL Status Bits */
118 #define REG_DACINTEGERWORD0 0x085 /* Feedback divider tuning word */
119 #define REG_DACLOOPFILT1 0x087 /* C1 and C2 control */
120 #define REG_DACLOOPFILT2 0x088 /* R1 and C3 control */
121 #define REG_DACLOOPFILT3 0x089 /* Bypass and R2 control */
122 #define REG_DACCPCNTRL 0x08A /* Charge Pump/Cntrl Voltage */
123 #define REG_DACLOGENCNTRL 0x08B /* Logen Control */
124 #define REG_DACLDOCNTRL1 0x08C /* LDO Control1 + Reference Divider */
125 #define REG_CAL_DAC_ERR 0x0E0 /* Report DAC Cal errors */
126 #define REG_CAL_MSB_THRES 0x0E1 /* MSB sweep Threshold definition */
127 #define REG_CAL_CTRL_GLOBAL 0x0E2 /* Global Calibration DAC Control */
128 #define REG_CAL_MSBHILVL 0x0E3 /* High Level for MSB level compare */
129 #define REG_CAL_MSBLOLVL 0x0E4 /* Low Level for MSB level compare */
130 #define REG_CAL_THRESH 0x0E5 /* TAC Threshold definition */
131 #define REG_CAL_AVG_CNT 0x0E6 /* CAL DAC Number of averages */
132 #define REG_CAL_CLKDIV 0x0E7 /* Calibration DAC clock divide */
133 #define REG_CAL_INDX 0x0E8 /* Calibration DAC Select */
134 #define REG_CAL_CTRL 0x0E9 /* Calibration DAC Control */
135 #define REG_CAL_ADDR 0x0EA /* Calibration DAC Address */
136 #define REG_CAL_DATA 0x0EB /* Calibration DAC Data */
137 #define REG_CAL_UPDATE 0x0EC /* Calibration DAC Write Update */
138 #define REG_CAL_INIT 0x0ED /* Calibration init */
139 #define REG_DATA_FORMAT 0x110 /* Data format */
140 #define REG_DATAPATH_CTRL 0x111 /* Datapath Control */
141 #define REG_INTERP_MODE 0x112 /* Interpolation Mode */
142 #define REG_NCO_FTW_UPDATE 0x113 /* NCO Frequency Tuning Word Update */
143 #define REG_FTW0 0x114 /* NCO Frequency Tuning Word LSB */
144 #define REG_FTW1 0x115 /* NCO Frequency Tuning Word */
145 #define REG_FTW2 0x116 /* NCO Frequency Tuning Word */
146 #define REG_FTW3 0x117 /* NCO Frequency Tuning Word */
147 #define REG_FTW4 0x118 /* NCO Frequency Tuning Word */
148 #define REG_FTW5 0x119 /* NCO Frequency Tuning Word MSB */
149 #define REG_NCO_PHASE_OFFSET0 0x11A /* NCO Phase Offset LSB */
150 #define REG_NCO_PHASE_OFFSET1 0x11B /* NCO Phase Offset MSB */
151 #define REG_NCO_PHASE_ADJ0 0x11C /* I/Q Phase Adjust LSB */
152 #define REG_NCO_PHASE_ADJ1 0x11D /* I/Q Phase Adjust MSB */
153 #define REG_TXEN_FUNC 0x11E /* Transmit Enable function */
154 #define REG_TXEN_SM_0 0x11F /* Transmit enable power control state machine */
155 #define REG_TXEN_SM_1 0x120 /* Rise and fall */
156 #define REG_TXEN_SM_2 0x121 /* Transmit enable maximum A */
157 #define REG_TXEN_SM_3 0x122 /* Transmit enable maximum B */
158 #define REG_TXEN_SM_4 0x123 /* Transmit enable maximum C */
159 #define REG_TXEN_SM_5 0x124 /* Transmit enable maximum D */
160 #define REG_DACOUT_ON_DOWN 0x125 /* DAC out down control and on trigger */
161 #define REG_DACOFF 0x12C /* DAC Shutdown Source */
162 #define REG_DATA_PATH_FLUSH_COUNT0 0x12D /* Data path flush counter LSB */
163 #define REG_DATA_PATH_FLUSH_COUNT1 0x12E /* Data path flush counter MSB */
164 #define REG_DIE_TEMP_CTRL0 0x12F /* Die Temp Range Control */
165 #define REG_DIE_TEMP_CTRL1 0x130 /* Die temperature control register */
166 #define REG_DIE_TEMP_CTRL2 0x131 /* Die temperature control register */
167 #define REG_DIE_TEMP0 0x132 /* Die temp LSB */
168 #define REG_DIE_TEMP1 0x133 /* Die Temp MSB */
169 #define REG_DIE_TEMP_UPDATE 0x134 /* Die temperature update */
170 #define REG_DC_OFFSET_CTRL 0x135 /* DC Offset Control */
171 #define REG_IPATH_DC_OFFSET_1PART0 0x136 /* LSB of first part of DC Offset value for I path */
172 #define REG_IPATH_DC_OFFSET_1PART1 0x137 /* MSB of first part of DC Offset value for I path */
173 #define REG_QPATH_DC_OFFSET_1PART0 0x138 /* LSB of first part of DC Offset value for Q path */
174 #define REG_QPATH_DC_OFFSET_1PART1 0x139 /* MSB of first part of DC Offset value for Q path */
175 #define REG_IPATH_DC_OFFSET_2PART 0x13A /* Second part of DC Offset value for I path */
176 #define REG_QPATH_DC_OFFSET_2PART 0x13B /* Second part of DC Offset value for Q path */
177 #define REG_IDAC_DIG_GAIN0 0x13C /* I DAC Gain LSB */
178 #define REG_IDAC_DIG_GAIN1 0x13D /* I DAC Gain MSB */
179 #define REG_QDAC_DIG_GAIN0 0x13E /* Q DAC Gain LSB */
180 #define REG_QDAC_DIG_GAIN1 0x13F /* Q DAC Gain MSB */
181 #define REG_GAIN_RAMP_UP_STP0 0x140 /* LSB of digital gain rises */
182 #define REG_GAIN_RAMP_UP_STP1 0x141 /* MSB of digital gain rises */
183 #define REG_GAIN_RAMP_DOWN_STP0 0x142 /* LSB of digital gain drops */
184 #define REG_GAIN_RAMP_DOWN_STP1 0x143 /* MSB of digital gain drops */
185 #define REG_BLSM_CTRL 0x146 /* Blanking SM control and func */
186 #define REG_BLSM_STAT 0x147 /* Blanking SM control and func */
187 #define REG_PRBS 0x14B /* PRBS Input Data Checker */
188 #define REG_PRBS_ERROR_I 0x14C /* PRBS Error Counter Real */
189 #define REG_PRBS_ERROR_Q 0x14D /* PRBS Error Counter Imaginary */
190 #define REG_DACPLLT5 0x1B5 /* ALC/Varactor control */
191 #define REG_DACPLLTB 0x1BB /* VCO Bias Control */
192 #define REG_DACPLLTD 0x1BD /* VCO Cal control */
193 #define REG_DACPLLT17 0x1C4 /* Varactor Control 1 */
194 #define REG_DACPLLT18 0x1C5 /* Varactor Control 2 */
195 #define REG_ASPI_SPARE0 0x1C6 /* Spare Register 0 */
196 #define REG_ASPI_SPARE1 0x1C7 /* Spare Register 1 */
197 #define REG_SPISTRENGTH 0x1DF /* Reg 70 Description */
198 #define REG_CLK_TEST 0x1EB /* Clock related control signaling */
199 #define REG_ATEST_VOLTS 0x1EC /* Analog Test Voltage Extraction */
200 #define REG_ASPI_CLKSRC 0x1ED /* Analog Spi clock source for PD machines */
201 #define REG_MASTER_PD 0x200 /* Master power down for Receiver PHYx */
202 #define REG_PHY_PD 0x201 /* Power down for individual Receiver PHYx */
203 #define REG_GENERIC_PD 0x203 /* Miscellaneous power down controls */
204 #define REG_CDR_RESET 0x206 /* CDR Reset control */
205 #define REG_CDR_OPERATING_MODE_REG_0 0x230 /* Clock and data recovery operating modes */
206 #define REG_CONFIG_REG3 0x232 /* SERDES interface configuration */
207 #define REG_EQ_CONFIG_PHY_0_1 0x250 /* Equalizer configuration for PHY 0 and PHY 1 */
208 #define REG_EQ_CONFIG_PHY_2_3 0x251 /* Equalizer configuration for PHY 2 and PHY 3 */
209 #define REG_EQ_CONFIG_PHY_4_5 0x252 /* Equalizer configuration for PHY 4 and PHY 5 */
210 #define REG_EQ_CONFIG_PHY_6_7 0x253 /* Equalizer configuration for PHY 6 and PHY 7 */
211 #define REG_EQ_BIAS_REG 0x268 /* Equalizer bias control */
212 #define REG_SYNTH_ENABLE_CNTRL 0x280 /* Rx PLL enable controls */
213 #define REG_PLL_STATUS 0x281 /* Rx PLL status readbacks */
214 #define REG_REF_CLK_DIVIDER_LDO 0x289 /* Rx PLL LDO control */
215 #define REG_SERDES_PLL_CTRL 0x291 /* Serdes PLL control */
216 #define REG_SERDES_PLL_CP3 0x29c /* Serdes PLL charge pump */
217 #define REG_SERDES_PLL_VAR3 0x29f /* Serdes PLL VCO varactor */
218 #define REG_DEV_CONFIG_8 0x2A4 /* To control the clock configuration */
219 #define REG_TERM_BLK1_CTRLREG0 0x2A7 /* Termination controls for PHYs 0, 1, 6, and 7 */
220 #define REG_TERM_BLK1_CTRLREG1 0x2A8 /* Termination controls for PHYs 0, 1, 6, and 7 */
221 #define REG_DEV_CONFIG_9 0x2AA /* SERDES interface termination settings */
222 #define REG_DEV_CONFIG_10 0x2AB /* SERDES interface termination settings */
223 #define REG_TERM_BLK2_CTRLREG0 0x2AE /* Termination controls for PHYs 2, 3, 4, and 5 */
224 #define REG_TERM_BLK2_CTRLREG1 0x2AF /* Termination controls for PHYs 2, 3, 4, and 5 */
225 #define REG_DEV_CONFIG_11 0x2B1 /* SERDES interface termination settings */
226 #define REG_DEV_CONFIG_12 0x2B2 /* SERDES interface termination settings */
227 #define REG_GENERAL_JRX_CTRL_0 0x300 /* General JRX Control Register 0 */
228 #define REG_GENERAL_JRX_CTRL_1 0x301 /* General JRX Control Register 1 */
229 #define REG_DYN_LINK_LATENCY_0 0x302 /* Register 1 description */
230 #define REG_DYN_LINK_LATENCY_1 0x303 /* Register 2 description */
231 #define REG_LMFC_DELAY_0 0x304 /* Register 3 description */
232 #define REG_LMFC_DELAY_1 0x305 /* Register 4 description */
233 #define REG_LMFC_VAR_0 0x306 /* Register 5 description */
234 #define REG_LMFC_VAR_1 0x307 /* Register 6 description */
235 #define REG_XBAR_LN_0_1 0x308 /* Register 7 description */
236 #define REG_XBAR_LN_2_3 0x309 /* Register 8 description */
237 #define REG_XBAR_LN_4_5 0x30A /* Register 9 description */
238 #define REG_XBAR_LN_6_7 0x30B /* Register 10 description */
239 #define REG_FIFO_STATUS_REG_0 0x30C /* Register 11 description */
240 #define REG_FIFO_STATUS_REG_1 0x30D /* Register 12 description */
241 #define REG_FIFO_STATUS_REG_2 0x30E /* Register 13 description */
242 #define REG_SYNCB_GEN_0 0x311 /* Register 16 description */
243 #define REG_SYNCB_GEN_1 0x312 /* Register 17 description */
244 #define REG_SYNCB_GEN_3 0x313 /* Register 18 description */
245 #define REG_SERDES_SPI_REG 0x314 /* SERDES SPI configuration */
246 #define REG_PHY_PRBS_TEST_EN 0x315 /* PHY PRBS TEST ENABLE FOR INDIVIDUAL LANES */
247 #define REG_PHY_PRBS_TEST_CTRL 0x316 /* Reg 20 Description */
248 #define REG_PHY_PRBS_TEST_THRESH_LOBITS 0x317 /* Reg 21 Description */
249 #define REG_PHY_PRBS_TEST_THRESH_MIDBITS 0x318 /* Reg 22 Description */
250 #define REG_PHY_PRBS_TEST_THRESH_HIBITS 0x319 /* Reg 23 Description */
251 #define REG_PHY_PRBS_TEST_ERRCNT_LOBITS 0x31A /* Reg 24 Description */
252 #define REG_PHY_PRBS_TEST_ERRCNT_MIDBITS 0x31B /* Reg 25 Description */
253 #define REG_PHY_PRBS_TEST_ERRCNT_HIBITS 0x31C /* Reg 26 Description */
254 #define REG_PHY_PRBS_TEST_STATUS 0x31D /* Reg 27 Description */
255 #define REG_SHORT_TPL_TEST_0 0x32C /* Reg 46 Description */
256 #define REG_SHORT_TPL_TEST_1 0x32D /* Reg 47 Description */
257 #define REG_SHORT_TPL_TEST_2 0x32E /* Reg 48 Description */
258 #define REG_SHORT_TPL_TEST_3 0x32F /* Reg 49 Description */
259 #define REG_DEVICE_CONFIG_REG_13 0x333 /* SERDES interface configuration */
260 #define REG_JESD_BIT_INVERSE_CTRL 0x334 /* Reg 42 Description */
261 #define REG_DID_REG 0x400 /* Reg 0 Description */
262 #define REG_BID_REG 0x401 /* Reg 1 Description */
263 #define REG_LID0_REG 0x402 /* Reg 2 Description */
264 #define REG_SCR_L_REG 0x403 /* Reg 3 Description */
265 #define REG_F_REG 0x404 /* Reg 4 Description */
266 #define REG_K_REG 0x405 /* Reg 5 Description */
267 #define REG_M_REG 0x406 /* Reg 6 Description */
268 #define REG_CS_N_REG 0x407 /* Reg 7 Description */
269 #define REG_NP_REG 0x408 /* Reg 8 Description */
270 #define REG_S_REG 0x409 /* Reg 9 Description */
271 #define REG_HD_CF_REG 0x40A /* Reg 10 Description */
272 #define REG_RES1_REG 0x40B /* Reg 11 Description */
273 #define REG_RES2_REG 0x40C /* Reg 12 Description */
274 #define REG_CHECKSUM_REG 0x40D /* Reg 13 Description */
275 #define REG_COMPSUM0_REG 0x40E /* Reg 14 Description */
276 #define REG_LID1_REG 0x412 /* Reg 18 Description */
277 #define REG_CHECKSUM1_REG 0x415 /* Reg 19 Description */
278 #define REG_COMPSUM1_REG 0x416 /* Reg 22 Description */
279 #define REG_LID2_REG 0x41A /* Reg 26 Description */
280 #define REG_CHECKSUM2_REG 0x41D /* Reg 29 Description */
281 #define REG_COMPSUM2_REG 0x41E /* Reg 30 Description */
282 #define REG_LID3_REG 0x422 /* Reg 34 Description */
283 #define REG_CHECKSUM3_REG 0x425 /* Reg 37 Description */
284 #define REG_COMPSUM3_REG 0x426 /* Reg 38 Description */
285 #define REG_LID4_REG 0x42A /* Reg 34 Description */
286 #define REG_CHECKSUM4_REG 0x42D /* Reg 37 Description */
287 #define REG_COMPSUM4_REG 0x42E /* Reg 38 Description */
288 #define REG_LID5_REG 0x432 /* Reg 34 Description */
289 #define REG_CHECKSUM5_REG 0x435 /* Reg 37 Description */
290 #define REG_COMPSUM5_REG 0x436 /* Reg 38 Description */
291 #define REG_LID6_REG 0x43A /* Reg 34 Description */
292 #define REG_CHECKSUM6_REG 0x43D /* Reg 37 Description */
293 #define REG_COMPSUM6_REG 0x43E /* Reg 38 Description */
294 #define REG_LID7_REG 0x442 /* Reg 34 Description */
295 #define REG_CHECKSUM7_REG 0x445 /* Reg 37 Description */
296 #define REG_COMPSUM7_REG 0x446 /* Reg 38 Description */
297 #define REG_ILS_DID 0x450 /* Reg 80 Description */
298 #define REG_ILS_BID 0x451 /* Reg 81 Description */
299 #define REG_ILS_LID0 0x452 /* Reg 82 Description */
300 #define REG_ILS_SCR_L 0x453 /* Reg 83 Description */
301 #define REG_ILS_F 0x454 /* Reg 84 Description */
302 #define REG_ILS_K 0x455 /* Reg 85 Description */
303 #define REG_ILS_M 0x456 /* Reg 86 Description */
304 #define REG_ILS_CS_N 0x457 /* Reg 87 Description */
305 #define REG_ILS_NP 0x458 /* Reg 88 Description */
306 #define REG_ILS_S 0x459 /* Reg 89 Description */
307 #define REG_ILS_HD_CF 0x45A /* Reg 90 Description */
308 #define REG_ILS_RES1 0x45B /* Reg 91 Description */
309 #define REG_ILS_RES2 0x45C /* Reg 92 Description */
310 #define REG_ILS_CHECKSUM 0x45D /* Reg 93 Description */
311 #define REG_ERRCNTRMON 0x46B /* Reg 107 Description */
312 #define REG_LANEDESKEW 0x46C /* Reg 108 Description */
313 #define REG_BADDISPARITY 0x46D /* Reg 109 Description */
314 #define REG_NITDISPARITY 0x46E /* Reg 110 Description */
315 #define REG_UNEXPECTEDKCHAR 0x46F /* Reg 111 Description */
316 #define REG_CODEGRPSYNCFLG 0x470 /* Reg 112 Description */
317 #define REG_FRAMESYNCFLG 0x471 /* Reg 113 Description */
318 #define REG_GOODCHKSUMFLG 0x472 /* Reg 114 Description */
319 #define REG_INITLANESYNCFLG 0x473 /* Reg 115 Description */
320 #define REG_CTRLREG1 0x476 /* Reg 118 Description */
321 #define REG_CTRLREG2 0x477 /* Reg 119 Description */
322 #define REG_KVAL 0x478 /* Reg 120 Description */
323 #define REG_IRQVECTOR 0x47A /* Reg 122 Description */
324 #define REG_SYNCASSERTIONMASK 0x47B /* Reg 123 Description */
325 #define REG_ERRORTHRES 0x47C /* Reg 124 Description */
326 #define REG_LANEENABLE 0x47D /* Reg 125 Description */
327 
328 /*
329  * REG_SPI_INTFCONFA
330  */
331 #define SOFTRESET_M (1 << 7) /* Soft Reset (Mirror) */
332 #define LSBFIRST_M (1 << 6) /* LSB First (Mirror) */
333 #define ADDRINC_M (1 << 5) /* Address Increment (Mirror) */
334 #define SDOACTIVE_M (1 << 4) /* SDO Active (Mirror) */
335 #define SDOACTIVE (1 << 3) /* SDO Active */
336 #define ADDRINC (1 << 2) /* Address Increment */
337 #define LSBFIRST (1 << 1) /* LSB First */
338 #define SOFTRESET (1 << 0) /* Soft Reset */
339 
340 /*
341  * REG_SPI_INTFCONFB
342  */
343 #define SINGLEINS (1 << 7) /* Single Instruction */
344 #define CSBSTALL (1 << 6) /* CSb Stalling */
345 
346 /*
347  * REG_SPI_DEVCONF
348  */
349 #define DEVSTATUS(x) (((x) & 0xF) << 4) /* Device Status */
350 #define CUSTOPMODE(x) (((x) & 0x3) << 2) /* Customer Operating Mode */
351 #define SYSOPMODE(x) (((x) & 0x3) << 0) /* System Operating Mode */
352 
353 /*
354  * REG_SPI_CHIPGRADE
355  */
356 #define PROD_GRADE(x) (((x) & 0xF) << 4) /* Product Grade */
357 #define DEV_REVISION(x) (((x) & 0xF) << 0) /* Device Revision */
358 
359 /*
360  * REG_SPI_PAGEINDX
361  */
362 #define PAGEINDX(x) (((x) & 0x3) << 0) /* Page or Index Pointer */
363 
364 /*
365  * REG_SPI_MS_UPDATE
366  */
367 #define SLAVEUPDATE (1 << 0) /* M/S Update Bit */
368 
369 /*
370  * REG_PWRCNTRL0
371  */
372 #define PD_BG (1 << 7) /* Reference PowerDown */
373 #define PD_DAC_0 (1 << 6) /* PD Ichannel DAC 0 */
374 #define PD_DAC_1 (1 << 5) /* PD Qchannel DAC 1 */
375 #define PD_DAC_2 (1 << 4) /* PD Ichannel DAC 2 */
376 #define PD_DAC_3 (1 << 3) /* PD Qchannel DAC 3 */
377 #define PD_DACM (1 << 2) /* PD Dac master Bias */
378 
379 /*
380  * REG_TXENMASK1
381  */
382 #define SYS_MASK (1 << 2) /* SYSREF Receiver TXen mask */
383 #define DACB_MASK (1 << 1) /* Dual B Dac TXen1 mask */
384 #define DACA_MASK (1 << 0) /* Dual A Dac TXen0 mask */
385 
386 /*
387  * REG_PWRCNTRL3
388  */
389 #define ENA_PA_CTRL_FROM_PAPROT_ERR (1 << 6) /* Control PDP enable from PAProt block */
390 #define ENA_PA_CTRL_FROM_TXENSM (1 << 5) /* Control PDP enable from Txen State machine */
391 #define ENA_PA_CTRL_FROM_BLSM (1 << 4) /* Control PDP enable from Blanking state machine */
392 #define ENA_PA_CTRL_FROM_SPI (1 << 3) /* Control PDP enable via SPI */
393 #define SPI_PA_CTRL (1 << 2) /* PDP on/off via SPI */
394 #define ENA_SPI_TXEN (1 << 1) /* TXEN from SPI control */
395 #define SPI_TXEN (1 << 0) /* Spi TXEN */
396 
397 /*
398  * REG_COARSE_GROUP_DLY
399  */
400 #define COARSE_GROUP_DLY(x) (((x) & 0xF) << 0) /* Coarse group delay */
401 
402 /*
403  * REG_IRQ_ENABLE0
404  */
405 #define EN_CALPASS (1 << 7) /* Enable Calib PASS detection */
406 #define EN_CALFAIL (1 << 6) /* Enable Calib FAIL detection */
407 #define EN_DACPLLLOST (1 << 5) /* Enable DAC Pll Lost detection */
408 #define EN_DACPLLLOCK (1 << 4) /* Enable DAC Pll Lock detection */
409 #define EN_SERPLLLOST (1 << 3) /* Enable Serdes PLL Lost detection */
410 #define EN_SERPLLLOCK (1 << 2) /* Enable Serdes PLL Lock detection */
411 #define EN_LANEFIFOERR (1 << 1) /* Enable Lane FIFO Error detection */
412 #define EN_DRDLFIFOERR (1 << 0) /* Enable DRDL FIFO Error detection */
413 
414 /*
415  * REG_IRQ_ENABLE1
416  */
417 #define EN_PARMBAD (1 << 7) /* enable BAD Parameter interrupt */
418 #define EN_PRBSQ1 (1 << 3) /* enable PRBS imag DAC B interrupt */
419 #define EN_PRBSI1 (1 << 2) /* enable PRBS real DAC B interrupt */
420 #define EN_PRBSQ0 (1 << 1) /* enable PRBS imag DAC A interrupt */
421 #define EN_PRBSI0 (1 << 0) /* enable PRBS real DAC A interrupt */
422 
423 /*
424  * REG_IRQ_ENABLE2
425  */
426 #define EN_PAERR0 (1 << 7) /* Link A PA Error */
427 #define EN_BIST_DONE0 (1 << 6) /* Link A BIST done */
428 #define EN_BLNKDONE0 (1 << 5) /* Link A Blanking done */
429 #define EN_REFNCOCLR0 (1 << 4) /* Link A Nco Clear Tripped */
430 #define EN_REFLOCK0 (1 << 3) /* Link A Alignment Locked */
431 #define EN_REFROTA0 (1 << 2) /* Link A Alignment Rotate */
432 #define EN_REFWLIM0 (1 << 1) /* Link A Over/Under Threshold */
433 #define EN_REFTRIP0 (1 << 0) /* Link A Alignment Trip */
434 
435 /*
436  * REG_IRQ_ENABLE3
437  */
438 #define EN_PAERR1 (1 << 7) /* Link B PA Error */
439 #define EN_BIST_DONE1 (1 << 6) /* Link B BIST done */
440 #define EN_BLNKDONE1 (1 << 5) /* Link B Blanking done */
441 #define EN_REFNCOCLR1 (1 << 4) /* Link B Nco Clear Tripped */
442 #define EN_REFLOCK1 (1 << 3) /* Link B Alignment Locked */
443 #define EN_REFROTA1 (1 << 2) /* Link B Alignment Rotate */
444 #define EN_REFWLIM1 (1 << 1) /* Link B Over/Under Threshold */
445 #define EN_REFTRIP1 (1 << 0) /* Link B Alignment Trip */
446 
447 /*
448  * REG_IRQ_STATUS0
449  */
450 #define IRQ_CALPASS (1 << 7) /* Calib PASS detection */
451 #define IRQ_CALFAIL (1 << 6) /* Calib FAIL detection */
452 #define IRQ_DACPLLLOST (1 << 5) /* DAC PLL Lost */
453 #define IRQ_DACPLLLOCK (1 << 4) /* DAC PLL Lock */
454 #define IRQ_SERPLLLOST (1 << 3) /* Serdes PLL Lost */
455 #define IRQ_SERPLLLOCK (1 << 2) /* Serdes PLL Lock */
456 #define IRQ_LANEFIFOERR (1 << 1) /* Lane Fifo Error */
457 #define IRQ_DRDLFIFOERR (1 << 0) /* DRDL Fifo Error */
458 
459 /*
460  * REG_IRQ_STATUS1
461  */
462 #define IRQ_PARMBAD (1 << 7) /* BAD Parameter interrupt */
463 #define IRQ_PRBSQ1 (1 << 3) /* PRBS data check error DAC 1 imag */
464 #define IRQ_PRBSI1 (1 << 2) /* PRBS data check error DAC 1 real */
465 #define IRQ_PRBSQ0 (1 << 1) /* PRBS data check error DAC 0 imag */
466 #define IRQ_PRBSI0 (1 << 0) /* PRBS data check error DAC 0 real */
467 
468 /*
469  * REG_IRQ_STATUS2
470  */
471 #define IRQ_PAERR0 (1 << 7) /* Link A PA Error */
472 #define IRQ_BIST_DONE0 (1 << 6) /* Link A BIST done */
473 #define IRQ_BLNKDONE0 (1 << 5) /* Link A Blanking Done */
474 #define IRQ_REFNCOCLR0 (1 << 4) /* Link A Alignment UnderRange */
475 #define IRQ_REFLOCK0 (1 << 3) /* Link A BIST done */
476 #define IRQ_REFROTA0 (1 << 2) /* Link A Alignment Trip */
477 #define IRQ_REFWLIM0 (1 << 1) /* Link A Alignment Lock */
478 #define IRQ_REFTRIP0 (1 << 0) /* Link A Alignment Rotate */
479 
480 /*
481  * REG_IRQ_STATUS3
482  */
483 #define IRQ_PAERR1 (1 << 7) /* Link B PA Error */
484 #define IRQ_BIST_DONE1 (1 << 6) /* Link B BIST done */
485 #define IRQ_BLNKDONE1 (1 << 5) /* Link A Blanking Done */
486 #define IRQ_REFNCOCLR1 (1 << 4) /* Link B Alignment UnderRange */
487 #define IRQ_REFLOCK1 (1 << 3) /* Link B BIST done */
488 #define IRQ_REFROTA1 (1 << 2) /* Link B Alignment Trip */
489 #define IRQ_REFWLIM1 (1 << 1) /* Link B Alignment Lock */
490 #define IRQ_REFTRIP1 (1 << 0) /* Link B Alignment Rotate */
491 
492 /*
493  * REG_JESD_CHECKS
494  */
495 #define ERR_DLYOVER (1 << 5) /* LMFC_Delay > JESD_K parameter */
496 #define ERR_WINLIMIT (1 << 4) /* Unsupported Window Limit */
497 #define ERR_JESDBAD (1 << 3) /* Unsupported M/L/S/F selection */
498 #define ERR_KUNSUPP (1 << 2) /* Unsupported K values */
499 #define ERR_SUBCLASS (1 << 1) /* Unsupported SubClassv value */
500 #define ERR_INTSUPP (1 << 0) /* Unsupported Interpolation rate factor */
501 
502 /*
503  * REG_SYNC_TESTCTRL
504  */
505 #define TARRFAPHAZ (1 << 0) /* Target Polarity of Rf Divider */
506 #define SYNCBYPASS(x) (((x) & 0x3) << 6) /* Sync Bypass handshaking */
507 
508 /*
509  * REG_SYNC_DACDELAY_H
510  */
511 #define DAC_DELAY_H (1 << 0) /* Dac Delay[8] */
512 
513 /*
514  * REG_SYNC_ERRWINDOW
515  */
516 #define ERRWINDOW(x) (((x) & 0x7) << 0) /* Sync Error Window */
517 
518 /*
519  * REG_SYNC_LASTERR_H
520  */
521 #define LASTUNDER (1 << 7) /* Sync Last Error Under Flag */
522 #define LASTOVER (1 << 6) /* Sync Last Error Over Flag */
523 #define LASTERROR_H (1 << 0) /* Sync Last Error[8] and Flags */
524 
525 /*
526  * REG_SYNC_CTRL
527  */
528 #define SYNCENABLE (1 << 7) /* SyncLogic Enable */
529 #define SYNCARM (1 << 6) /* Sync Arming Strobe */
530 #define SYNCCLRSTKY (1 << 5) /* Sync Sticky Bit Clear */
531 #define SYNCCLRLAST (1 << 4) /* Sync Clear LAST_ */
532 #define SYNCMODE(x) (((x) & 0xF) << 0) /* Sync Mode */
533 
534 /*
535  * REG_SYNC_STATUS
536  */
537 #define REFBUSY (1 << 7) /* Sync Machine Busy */
538 #define REFLOCK (1 << 3) /* Sync Alignment Locked */
539 #define REFROTA (1 << 2) /* Sync Rotated */
540 #define REFWLIM (1 << 1) /* Sync Alignment Limit Range */
541 #define REFTRIP (1 << 0) /* Sync Tripped after Arming */
542 
543 /*
544  * REG_SYNC_CURRERR_H
545  */
546 #define CURRUNDER (1 << 7) /* Sync Current Error Under Flag */
547 #define CURROVER (1 << 6) /* Sync Current Error Over Flag */
548 #define CURRERROR_H (1 << 0) /* SyncCurrent Error[8] */
549 
550 /*
551  * REG_ERROR_THERM
552  */
553 #define THRMOLD (1 << 7) /* Error is from a prior sample */
554 #define THRMOVER (1 << 4) /* Error > +WinLimit */
555 #define THRMPOS (1 << 3) /* Sync Current Error Under Flag */
556 #define THRMZERO (1 << 2) /* Error = 0 */
557 #define THRMNEG (1 << 1) /* Error < 0 */
558 #define THRMUNDER (1 << 0) /* Error < -WinLimit */
559 
560 /*
561  * REG_DACGAIN0_1
562  */
563 #define DACGAIN_IM0(x) (((x) & 0x3) << 0) /* I Channel DAC gain <9:8> Dual A */
564 
565 /*
566  * REG_DACGAIN1_1
567  */
568 #define DACGAIN_IM1(x) (((x) & 0x3) << 0) /* Q Channel DAC gain <9:8> Dual A */
569 
570 /*
571  * REG_DACGAIN2_1
572  */
573 #define DACGAIN_IM2(x) (((x) & 0x3) << 0) /* I Channel DAC gain <9:8> Dual B */
574 
575 /*
576  * REG_DACGAIN3_1
577  */
578 #define DACGAIN_IM3(x) (((x) & 0x3) << 0) /* Q Channel DAC gain <9:8> Dual B */
579 
580 /*
581  * REG_PD_DACLDO
582  */
583 #define ENB_DACLDO3 (1 << 7) /* Disable DAC3 ldo */
584 #define ENB_DACLDO2 (1 << 6) /* Disable DAC2 ldo */
585 #define ENB_DACLDO1 (1 << 5) /* Disable DAC1 ldo */
586 #define ENB_DACLDO0 (1 << 4) /* Disable DAC0 ldo */
587 
588 /*
589  * REG_STAT_DACLDO
590  */
591 #define STAT_LDO3 (1 << 3) /* DAC3 LDO status */
592 #define STAT_LDO2 (1 << 2) /* DAC2 LDO status */
593 #define STAT_LDO1 (1 << 1) /* DAC1 LDO status */
594 #define STAT_LDO0 (1 << 0) /* DAC0 LDO status */
595 
596 /*
597  * REG_DECODE_CTRL0
598  */
599 #define SHUFFLE_MSB0 (1 << 2) /* MSB shuffling mode */
600 #define SHUFFLE_ISB0 (1 << 1) /* ISB shuffling mode */
601 
602 /*
603  * REG_DECODE_CTRL1
604  */
605 #define SHUFFLE_MSB1 (1 << 2) /* MSB shuffling mode */
606 #define SHUFFLE_ISB1 (1 << 1) /* ISB shuffling mode */
607 
608 /*
609  * REG_DECODE_CTRL2
610  */
611 #define SHUFFLE_MSB2 (1 << 2) /* MSB shuffling mod */
612 #define SHUFFLE_ISB2 (1 << 1) /* ISB shuffling mode */
613 
614 /*
615  * REG_DECODE_CTRL3
616  */
617 #define SHUFFLE_MSB3 (1 << 2) /* MSB shuffling mode */
618 #define SHUFFLE_ISB3 (1 << 1) /* ISB shuffling mode */
619 
620 /*
621  * REG_NCO_CLRMODE
622  */
623 #define NCOCLRARM (1 << 7) /* Arm NCO Clear */
624 #define NCOCLRMTCH (1 << 5) /* NCO Clear Data Match */
625 #define NCOCLRPASS (1 << 4) /* NCO Clear PASSed */
626 #define NCOCLRFAIL (1 << 3) /* NCO Clear FAILed */
627 #define NCOCLRMODE(x) (((x) & 0x3) << 0) /* NCO Clear Mode */
628 
629 /*
630  * REG_PA_THRES1
631  */
632 #define PA_THRESH_MSB(x) (((x) & 0x1F) << 0) /* Average power threshold for comparison. */
633 
634 /*
635  * REG_PA_AVG_TIME
636  */
637 #define PA_ENABLE (1 << 7) /* 1 = Enable average power calculation and error detection */
638 #define PA_BUS_SWAP (1 << 6) /* Swap channelA or channelB databus for power calculation */
639 #define PA_AVG_TIME(x) (((x) & 0xF) << 0) /* Set power average time */
640 
641 /*
642  * REG_PA_POWER1
643  */
644 #define PA_POWER_MSB(x) (((x) & 0x1F) << 0) /* average power bus = I^2+Q^2 (I/Q use 6MSB of databus) */
645 
646 /*
647  * REG_CLKCFG0
648  */
649 #define PD_CLK01 (1 << 7) /* Powerdown clock for Dual A */
650 #define PD_CLK23 (1 << 6) /* Powerdown clock for Dual B */
651 #define PD_CLK_DIG (1 << 5) /* Powerdown clocks to all DACs */
652 #define PD_PCLK (1 << 4) /* Cal reference/Serdes PLL clock powerdown */
653 #define PD_CLK_REC (1 << 3) /* Clock reciever powerdown */
654 
655 /*
656  * REG_SYSREF_ACTRL0
657  */
658 #define PD_SYSREF (1 << 4) /* Powerdown SYSREF buffer */
659 #define HYS_ON (1 << 3) /* Hysteresis enabled */
660 #define SYSREF_RISE (1 << 2) /* Use SYSREF rising edge */
661 #define HYS_CNTRL1(x) (((x) & 0x3) << 0) /* Hysteresis control bits <9:8> */
662 
663 /*
664  * REG_DACPLLCNTRL
665  */
666 #define SYNTH_RECAL (1 << 7) /* Recalibrate VCO Band */
667 #define ENABLE_SYNTH (1 << 4) /* Synthesizer Enable */
668 
669 /*
670  * REG_DACPLLSTATUS
671  */
672 #define CP_CAL_VALID (1 << 5) /* Charge Pump Cal Valid */
673 #define RFPLL_LOCK (1 << 1) /* PLL Lock bit */
674 
675 /*
676  * REG_DACLOOPFILT1
677  */
678 #define LF_C2_WORD(x) (((x) & 0xF) << 4) /* C2 control word */
679 #define LF_C1_WORD(x) (((x) & 0xF) << 0) /* C1 control word */
680 
681 /*
682  * REG_DACLOOPFILT2
683  */
684 #define LF_R1_WORD(x) (((x) & 0xF) << 4) /* R1 control word */
685 #define LF_C3_WORD(x) (((x) & 0xF) << 0) /* C3 control word */
686 
687 /*
688  * REG_DACLOOPFILT3
689  */
690 #define LF_BYPASS_R3 (1 << 7) /* Bypass R3 res */
691 #define LF_BYPASS_R1 (1 << 6) /* Bypass R1 res */
692 #define LF_BYPASS_C2 (1 << 5) /* Bypass C2 cap */
693 #define LF_BYPASS_C1 (1 << 4) /* Bypass C1 cap */
694 #define LF_R3_WORD(x) (((x) & 0xF) << 0) /* R3 Control Word */
695 
696 /*
697  * REG_DACCPCNTRL
698  */
699 #define CP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current Control */
700 
701 /*
702  * REG_DACLOGENCNTRL
703  */
704 #define LO_DIV_MODE(x) (((x) & 0x3) << 0) /* Logen_Division */
705 
706 /*
707  * REG_DACLDOCNTRL1
708  */
709 #define REF_DIVRATE(x) (((x) & 0x7) << 0) /* Reference Clock Division Ratio */
710 
711 /*
712  * REG_CAL_DAC_ERR
713  */
714 #define INIT_SWEEP_ERR_DAC (1 << 1) /* Initial setup sweep failed */
715 #define MSB_SWEEP_ERR_DAC (1 << 0) /* MSB sweep failed */
716 
717 /*
718  * REG_CAL_MSB_THRES
719  */
720 #define CAL_MSB_TAC(x) (((x) & 0x7) << 0) /* MSB sweep TAC */
721 
722 /*
723  * REG_CAL_CTRL_GLOBAL
724  */
725 #define CAL_START_GL (1 << 1) /* Global Calibration start */
726 #define CAL_EN_GL (1 << 0) /* Global Calibration enable */
727 
728 /*
729  * REG_CAL_MSBHILVL
730  */
731 #define CAL_MSBLVLHI(x) (((x) & 0x3F) << 0) /* High level limit for msb sweep average */
732 
733 /*
734  * REG_CAL_MSBLOLVL
735  */
736 #define CAL_MSBLVLLO(x) (((x) & 0x3F) << 0) /* Low level limit for msb sweep average */
737 
738 /*
739  * REG_CAL_THRESH
740  */
741 #define CAL_LTAC_THRES(x) (((x) & 0x7) << 3) /* Long TAC threshold */
742 #define CAL_TAC_THRES(x) (((x) & 0x7) << 0) /* TAC threshold */
743 
744 /*
745  * REG_CAL_AVG_CNT
746  */
747 #define MSB_GLOBAL_SUBAVG(x) (((x) & 0x3) << 6) /* Local Averages for MSB in Global Calibration */
748 #define GLOBAL_AVG_CNT(x) (((x) & 0x7) << 3) /* Global avg Terminal count */
749 #define LOCAL_AVRG_CNT(x) (((x) & 0x7) << 0) /* Local avg terminal count */
750 
751 /*
752  * REG_CAL_CLKDIV
753  */
754 #define CAL_CLKDIV(x) (((x) & 0xF) << 0) /* Calibration clock divider */
755 
756 /*
757  * REG_CAL_INDX
758  */
759 #define CAL_INDX(x) (((x) & 0xF) << 0) /* DAC Calibration Index paging bits */
760 
761 /*
762  * REG_CAL_CTRL
763  */
764 #define CAL_FIN (1 << 7) /* Calibration finished */
765 #define CAL_ACTIVE (1 << 6) /* Calibration active */
766 #define CAL_ERRHI (1 << 5) /* SAR data error: too hi */
767 #define CAL_ERRLO (1 << 4) /* SAR data error: too lo */
768 #define CAL_TXDACBYDAC (1 << 3) /* Calibration of TXDAC by TXDAC */
769 #define CAL_START (1 << 1) /* Calibration start */
770 #define CAL_EN (1 << 0) /* Calibration enable */
771 
772 /*
773  * REG_CAL_ADDR
774  */
775 #define CAL_ADDR(x) (((x) & 0x3F) << 0) /* Calibration DAC address */
776 
777 /*
778  * REG_CAL_DATA
779  */
780 #define CAL_DATA(x) (((x) & 0x3F) << 0) /* Calibration DAC Coefficient Data */
781 
782 /*
783  * REG_CAL_UPDATE
784  */
785 #define CAL_UPDATE (1 << 7) /* Calibration DAC Coefficient Update */
786 
787 /*
788  * REG_DATA_FORMAT
789  */
790 #define BINARY_FORMAT (1 << 7) /* Binary or 2's complementary format on DATA bus */
791 
792 /*
793  * REG_DATAPATH_CTRL
794  */
795 #define INVSINC_ENABLE (1 << 7) /* 1 = Enable inver sinc filter */
796 #define DIG_GAIN_ENABLE (1 << 5) /* 1 = Enable digital gain */
797 #define PHASE_ADJ_ENABLE (1 << 4) /* 1 = Enable phase compensation */
798 #define SEL_SIDEBAND (1 << 1) /* 1 = Select upper or lower sideband from modulation result */
799 #define I_TO_Q (1 << 0) /* 1 = send I datapath into Q DAC */
800 #define MODULATION_TYPE(x) (((x) & 0x3) << 2) /* selects type of modulation operation */
801 #define MODULATION_TYPE_MASK (0x03 << 2)
802 
803 /*
804  * REG_INTERP_MODE
805  */
806 #define INTERP_MODE(x) (((x) & 0x7) << 0) /* Interpolation Mode */
807 
808 /*
809  * REG_NCO_FTW_UPDATE
810  */
811 #define FTW_UPDATE_ACK (1 << 1) /* Frequency Tuning Word Update Acknowledge */
812 #define FTW_UPDATE_REQ (1 << 0) /* Frequency Tuning Word Update Request from SPI */
813 
814 /*
815  * REG_TXEN_FUNC
816  */
817 #define TX_DIG_CLK_PD (1 << 0) /* 1 = Digital clocks will be shut down when Tx_enable pin is low. */
818 
819 /*
820  * REG_TXEN_SM_0
821  */
822 #define GP_PA_ON_INVERT (1 << 2) /* External Modulator polarity invert */
823 #define GP_PA_CTRL (1 << 1) /* External PA control */
824 #define TXEN_SM_EN (1 << 0) /* Enable TXEN state machine */
825 #define PA_FALL(x) (((x) & 0x3) << 6) /* PA fall control */
826 #define PA_RISE(x) (((x) & 0x3) << 4) /* PA rises control */
827 
828 /*
829  * REG_TXEN_SM_1
830  */
831 #define DIG_FALL(x) (((x) & 0x3) << 6) /* DIG_FALL */
832 #define DIG_RISE(x) (((x) & 0x3) << 4) /* DIG_RISE */
833 #define DAC_FALL(x) (((x) & 0x3) << 2) /* DAC_FALL */
834 #define DAC_RISE(x) (((x) & 0x3) << 0) /* DAC_RISE */
835 
836 /*
837  * REG_DACOUT_ON_DOWN
838  */
839 #define DACOUT_SHUTDOWN (1 << 1) /* Shut down DAC output. 1 means DAC get shut down manually. */
840 #define DACOUT_ON_TRIGGER (1 << 0) /* Turn on DAC output manually. Self clear signal. */
841 
842 /*
843  * REG_DACOFF
844  */
845 #define PROTECT_MODE (1 << 7) /* PROTECT_MODE */
846 #define DACOFF_AVG_PW (1 << 0) /* DACOFF_AVG_PW */
847 
848 /*
849  * REG_DIE_TEMP_CTRL0
850  */
851 #define ADC_TESTMODE (1 << 7) /* ADC_TESTMODE */
852 #define AUXADC_ENABLE (1 << 0) /* AUXADC_ENABLE */
853 #define FS_CURRENT(x) (((x) & 0x7) << 4) /* FS_CURRENT */
854 #define REF_CURRENT(x) (((x) & 0x7) << 1) /* REF_CURRENT */
855 
856 /*
857  * REG_DIE_TEMP_CTRL1
858  */
859 #define SELECT_CLKDIG (1 << 3) /* SELECT_CLKDIG */
860 #define EN_DIV2 (1 << 2) /* EN_DIV2 */
861 #define INCAP_CTRL(x) (((x) & 0x3) << 0) /* INCAP_CTRL */
862 
863 /*
864  * REG_DIE_TEMP_UPDATE
865  */
866 #define DIE_TEMP_UPDATE (1 << 0) /* Die temperature update */
867 
868 /*
869  * REG_DC_OFFSET_CTRL
870  */
871 #define DISABLE_NOISE (1 << 1) /* DISABLE_NOISE */
872 #define DC_OFFSET_ON (1 << 0) /* DC_OFFSET_ON */
873 
874 /*
875  * REG_IPATH_DC_OFFSET_2PART
876  */
877 #define IPATH_DC_OFFSET_2PART(x) (((x) & 0x1F) << 0) /* second part of DC Offset value for I path */
878 
879 /*
880  * REG_QPATH_DC_OFFSET_2PART
881  */
882 #define QPATH_DC_OFFSET_2PART(x) (((x) & 0x1F) << 0) /* second part of DC Offset value for Q path */
883 
884 /*
885  * REG_IDAC_DIG_GAIN1
886  */
887 #define IDAC_DIG_GAIN1(x) (((x) & 0xF) << 0) /* MSB of I DAC digital gain */
888 
889 /*
890  * REG_QDAC_DIG_GAIN1
891  */
892 #define QDAC_DIG_GAIN1(x) (((x) & 0xF) << 0) /* MSB of Q DAC digital gain */
893 
894 /*
895  * REG_GAIN_RAMP_UP_STP1
896  */
897 #define GAIN_RAMP_UP_STP1(x) (((x) & 0xF) << 0) /* MSB of digital gain rises */
898 
899 /*
900  * REG_GAIN_RAMP_DOWN_STP1
901  */
902 #define GAIN_RAMP_DOWN_STP1(x) (((x) & 0xF) << 0) /* MSB of digital gain drops */
903 
904 /*
905  * REG_BLSM_CTRL
906  */
907 #define RESET_BLSM (1 << 7) /* Soft rest to the new Blanking SM */
908 #define EN_FORCE_GAIN_SOFT_OFF (1 << 4) /* Enable forcing gan_soft_off from SPI */
909 #define GAIN_SOFT_OFF (1 << 3) /* gain_soft_off forced value */
910 #define GAIN_SOFT_ON (1 << 2) /* gain_soft_on forced value */
911 #define EN_FORCE_GAIN_SOFT_ON (1 << 1) /* Force the gain_soft_on from SPI */
912 
913 /*
914  * REG_BLSM_STAT
915  */
916 #define SOFT_OFF_DONE (1 << 5) /* Blanking SoftOff Enable */
917 #define SOFT_ON_DONE (1 << 4) /* Blanking SoftOn Done */
918 #define GAIN_SOFT_OFF_RB (1 << 3) /* gain soft off readback */
919 #define GAIN_SOFT_ON_RB (1 << 2) /* gain soft on readback */
920 #define SOFT_OFF_EN_RB (1 << 1) /* Blanking SM soft Off read back */
921 #define SOFT_ON_EN_RB (1 << 0) /* Blanking SM soft On read back */
922 #define SOFTBLANKRB(x) (((x) & 0x3) << 6) /* Blanking State */
923 
924 /*
925  * REG_PRBS
926  */
927 #define PRBS_GOOD_Q (1 << 7) /* Good data indicator imaginary channel */
928 #define PRBS_GOOD_I (1 << 6) /* Good data indicator real channel */
929 #define PRBS_INV_Q (1 << 4) /* Data Inversion imaginary channel */
930 #define PRBS_INV_I (1 << 3) /* Data Inversion real channel */
931 #define PRBS_MODE (1 << 2) /* Polynomial Select */
932 #define PRBS_RESET (1 << 1) /* Reset Error Counters */
933 #define PRBS_EN (1 << 0) /* Enable PRBS Checker */
934 
935 /*
936  * REG_DACPLLT5
937  */
938 #define VCO_VAR(x) (((x) & 0xF) << 0) /* Varactor KVO setting */
939 
940 /*
941  * REG_DACPLLTB
942  */
943 #define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias control */
944 
945 /*
946  * REG_DACPLLTD
947  */
948 #define VCO_CAL_REF_MON (1 << 3) /* Sent control voltage to outside world */
949 #define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* TempCo for cal ref */
950 
951 /*
952  * REG_DACPLLT17
953  */
954 #define VCO_VAR_REF_TCF(x) (((x) & 0x7) << 4) /* Varactor Reference TempCo */
955 #define VCO_VAR_OFF(x) (((x) & 0xF) << 0) /* Varactor Offset */
956 
957 /*
958  * REG_SPISTRENGTH
959  */
960 #define SPIDRV(x) (((x) & 0xF) << 0) /* Slew and drive strength for cmos interface */
961 
962 /*
963  * REG_CLK_TEST
964  */
965 #define DUTYCYCLEON (1 << 0) /* Clock Duty Cycle Control On */
966 
967 /*
968  * REG_ATEST_VOLTS
969  */
970 #define ATEST_EN (1 << 0) /* Enable Analog Test Mode */
971 #define ATEST_TOPVSEL(x) (((x) & 0x3) << 5) /* Which source at analog top to use */
972 #define ATEST_DACSEL(x) (((x) & 0x3) << 3) /* DAC from which to get voltage */
973 #define ATEST_VSEL(x) (((x) & 0x3) << 1) /* DAC Voltage to Select */
974 
975 /*
976  * REG_ASPI_CLKSRC
977  */
978 #define EN_CLKDIV (1 << 3) /* Enable the fdac/8 clock path to generate PD timing clock */
979 #define ASPI_OSC_RATE (1 << 2) /* Aspi Oscillator Rate */
980 #define ASPI_CLK_SRC (1 << 1) /* Choose Aspi Clock Source */
981 #define EN_ASPI_OSC (1 << 0) /* Enable Aspi Oscillator clock */
982 
983 /*
984  * REG_MASTER_PD
985  */
986 #define SPI_PD_MASTER (1 << 0)
987 
988 /*
989  * REG_GENERIC_PD
990  */
991 #define SPI_SYNC1_PD (1 << 1)
992 #define SPI_SYNC2_PD (1 << 0)
993 
994 /*
995  * REG_CDR_OPERATING_MODE_REG_0
996  */
997 #define SPI_ENHALFRATE (1 << 5)
998 #define SPI_DIVISION_RATE(x) (((x) & 0x3) << 1)
999 
1000 /*
1001  * REG_EQ_CONFIG_PHY_0_1
1002  */
1003 #define SPI_EQ_CONFIG1(x) (((x) & 0xF) << 4)
1004 #define SPI_EQ_CONFIG0(x) (((x) & 0xF) << 0)
1005 
1006 /*
1007  * REG_EQ_CONFIG_PHY_2_3
1008  */
1009 #define SPI_EQ_CONFIG3(x) (((x) & 0xF) << 4)
1010 #define SPI_EQ_CONFIG2(x) (((x) & 0xF) << 0)
1011 
1012 /*
1013  * REG_EQ_CONFIG_PHY_4_5
1014  */
1015 #define SPI_EQ_CONFIG5(x) (((x) & 0xF) << 4)
1016 #define SPI_EQ_CONFIG4(x) (((x) & 0xF) << 0)
1017 
1018 /*
1019  * REG_EQ_CONFIG_PHY_6_7
1020  */
1021 #define SPI_EQ_CONFIG7(x) (((x) & 0xF) << 4)
1022 #define SPI_EQ_CONFIG6(x) (((x) & 0xF) << 0)
1023 
1024 /*
1025  * REG_EQ_BIAS_REG
1026  */
1027 #define SPI_EQ_EXTRA_SPI_LSBITS(x) (((x) & 0x3) << 6)
1028 #define SPI_EQ_BIASPTAT(x) (((x) & 0x7) << 3)
1029 #define SPI_EQ_BIASPLY(x) (((x) & 0x7) << 0)
1030 
1031 /*
1032  * REG_SYNTH_ENABLE_CNTRL
1033  */
1034 #define SPI_RECAL_SYNTH (1 << 2)
1035 #define SPI_ENABLE_SYNTH (1 << 0)
1036 
1037 /*
1038  * REG_PLL_STATUS
1039  */
1040 #define SPI_CP_CAL_VALID_RB (1 << 3)
1041 #define SPI_PLL_LOCK_RB (1 << 0)
1042 
1043 /*
1044  * REG_REF_CLK_DIVIDER_LDO
1045  */
1046 #define SPI_CDR_OVERSAMP(x) (((x) & 0x3) << 0)
1047 
1048 /*
1049  * REG_TERM_BLK1_CTRLREG0
1050  */
1051 #define SPI_I_TUNE_R_CAL_TERMBLK1 (1 << 0)
1052 
1053 /*
1054  * REG_TERM_BLK2_CTRLREG0
1055  */
1056 #define SPI_I_TUNE_R_CAL_TERMBLK2 (1 << 0)
1057 
1058 /*
1059  * REG_GENERAL_JRX_CTRL_0
1060  */
1061 #define CHECKSUM_MODE (1 << 6) /* Checksum mode */
1062 #define LINK_MODE (1 << 3) /* Link mode */
1063 #define SEL_REG_MAP_1 (1 << 2) /* Link register map selection */
1064 #define LINK_EN(x) (((x) & 0x3) << 0) /* Link enable */
1065 
1066 /*
1067  * REG_GENERAL_JRX_CTRL_1
1068  */
1069 #define SUBCLASSV_LOCAL(x) (((x) & 0x7) << 0) /* JESD204B subclass */
1070 
1071 /*
1072  * REG_DYN_LINK_LATENCY_0
1073  */
1074 #define DYN_LINK_LATENCY_0(x) (((x) & 0x1F) << 0) /* Dynamic link latency: Link 0 */
1075 
1076 /*
1077  * REG_DYN_LINK_LATENCY_1
1078  */
1079 #define DYN_LINK_LATENCY_1(x) (((x) & 0x1F) << 0) /* Dynamic link latency: Link 1 */
1080 
1081 /*
1082  * REG_LMFC_DELAY_0
1083  */
1084 #define LMFC_DELAY_0(x) (((x) & 0x1F) << 0) /* LMFC delay: Link 0 */
1085 
1086 /*
1087  * REG_LMFC_DELAY_1
1088  */
1089 #define LMFC_DELAY_1(x) (((x) & 0x1F) << 0) /* LMFC delay: Link 1 */
1090 
1091 /*
1092  * REG_LMFC_VAR_0
1093  */
1094 #define LMFC_VAR_0(x) (((x) & 0x1F) << 0) /* Location in RX LMFC where JESD words are read out from buffer */
1095 
1096 /*
1097  * REG_LMFC_VAR_1
1098  */
1099 #define LMFC_VAR_1(x) (((x) & 0x1F) << 0) /* Location in RX LMFC where JESD words are read out from buffer */
1100 
1101 /*
1102  * REG_XBAR_LN_0_1
1103  */
1104 #define SRC_LANE1(x) (((x) & 0x7) << 3) /* Logic Lane 1 source */
1105 #define SRC_LANE0(x) (((x) & 0x7) << 0) /* Logic Lane 0 source */
1106 
1107 /*
1108  * REG_XBAR_LN_2_3
1109  */
1110 #define SRC_LANE3(x) (((x) & 0x7) << 3) /* Logic Lane 3 source */
1111 #define SRC_LANE2(x) (((x) & 0x7) << 0) /* Logic Lane 2 source */
1112 
1113 /*
1114  * REG_XBAR_LN_4_5
1115  */
1116 #define SRC_LANE5(x) (((x) & 0x7) << 3) /* Logic Lane 5 source */
1117 #define SRC_LANE4(x) (((x) & 0x7) << 0) /* Logic Lane 4 source */
1118 
1119 /*
1120  * REG_XBAR_LN_6_7
1121  */
1122 #define SRC_LANE7(x) (((x) & 0x7) << 3) /* Logic Lane 7 source */
1123 #define SRC_LANE6(x) (((x) & 0x7) << 0) /* Logic Lane 6 source */
1124 
1125 /*
1126  * REG_FIFO_STATUS_REG_2
1127  */
1128 #define DRDL_FIFO_EMPTY (1 << 1) /* Deterministic latency (DRDL) FIFO is between JESD204B receiver and DAC2 and DAC3 */
1129 #define DRDL_FIFO_FULL (1 << 0) /* DRDL FIFO is between JESD204B receiver and DAC2 and DAC3 */
1130 
1131 /*
1132  * REG_SYNCB_GEN_0
1133  */
1134 #define EOMF_MASK_1 (1 << 3) /* EOMF_MASK_1 */
1135 #define EOMF_MASK_0 (1 << 2) /* EOMF_MASK_0 */
1136 #define EOF_MASK_1 (1 << 1) /* Mask EOF from QBD_1 */
1137 #define EOF_MASK_0 (1 << 0) /* Mask EOF from QBD_0 */
1138 
1139 /*
1140  * REG_SYNCB_GEN_1
1141  */
1142 #define SYNCB_ERR_DUR(x) (((x) & 0xF) << 4) /* Duration of SYNCOUT low for the purpose of error reporting */
1143 #define SYNCB_SYNCREQ_DUR(x) (((x) & 0xF) << 0) /* Duration of SYNCOUT low for purpose of synchronization request */
1144 
1145 /*
1146  * REG_PHY_PRBS_TEST_CTRL
1147  */
1148 #define PHY_TEST_START (1 << 1) /* PHY PRBS test start */
1149 #define PHY_TEST_RESET (1 << 0) /* PHY PRBS test reset */
1150 #define PHY_SRC_ERR_CNT(x) (((x) & 0x7) << 4) /* PHY error count source */
1151 #define PHY_PRBS_PAT_SEL(x) (((x) & 0x3) << 2) /* PHY PRBS pattern select */
1152 
1153 /*
1154  * REG_SHORT_TPL_TEST_0
1155  */
1156 #define SHORT_TPL_TEST_RESET (1 << 1) /* Short transport layer test reset */
1157 #define SHORT_TPL_TEST_EN (1 << 0) /* Short transport layer test enable */
1158 #define SHORT_TPL_SP_SEL(x) (((x) & 0x3) << 4) /* Short transport layer sample select */
1159 #define SHORT_TPL_M_SEL(x) (((x) & 0x3) << 2) /* Short transport layer test DAC select */
1160 
1161 /*
1162  * REG_SHORT_TPL_TEST_3
1163  */
1164 #define SHORT_TPL_FAIL (1 << 0) /* Short transport layer test fail */
1165 
1166 /*
1167  * REG_BID_REG
1168  */
1169 #define ADJCNT_RD(x) (((x) & 0xF) << 4)
1170 #define BID_RD(x) (((x) & 0xF) << 0)
1171 
1172 /*
1173  * REG_LID0_REG
1174  */
1175 #define ADJDIR_RD (1 << 6)
1176 #define PHADJ_RD (1 << 5)
1177 #define LID0_RD(x) (((x) & 0x1F) << 0)
1178 
1179 /*
1180  * REG_SCR_L_REG
1181  */
1182 #define SCR_RD (1 << 7)
1183 #define L_RD(x) (((x) & 0x1F) << 0)
1184 
1185 /*
1186  * REG_K_REG
1187  */
1188 #define K_RD(x) (((x) & 0x1F) << 0)
1189 
1190 /*
1191  * REG_CS_N_REG
1192  */
1193 #define CS_RD(x) (((x) & 0x3) << 6)
1194 #define N_RD(x) (((x) & 0x1F) << 0)
1195 
1196 /*
1197  * REG_NP_REG
1198  */
1199 #define SUBCLASSV_RD(x) (((x) & 0x7) << 5)
1200 #define NP_RD(x) (((x) & 0x1F) << 0)
1201 
1202 /*
1203  * REG_S_REG
1204  */
1205 #define JESDV_RD(x) (((x) & 0x7) << 5)
1206 #define S_RD(x) (((x) & 0x1F) << 0)
1207 
1208 /*
1209  * REG_HD_CF_REG
1210  */
1211 #define HD_RD (1 << 7)
1212 #define CF_RD(x) (((x) & 0x1F) << 0)
1213 
1214 /*
1215  * REG_LID1_REG
1216  */
1217 #define LID1_RD(x) (((x) & 0x1F) << 0)
1218 
1219 /*
1220  * REG_LID2_REG
1221  */
1222 #define LID2_RD(x) (((x) & 0x1F) << 0)
1223 
1224 /*
1225  * REG_LID3_REG
1226  */
1227 #define LID3_RD(x) (((x) & 0x1F) << 0)
1228 
1229 /*
1230  * REG_LID4_REG
1231  */
1232 #define LID4_RD(x) (((x) & 0x1F) << 0)
1233 
1234 /*
1235  * REG_LID5_REG
1236  */
1237 #define LID5_RD(x) (((x) & 0x1F) << 0)
1238 
1239 /*
1240  * REG_LID6_REG
1241  */
1242 #define LID6_RD(x) (((x) & 0x1F) << 0)
1243 
1244 /*
1245  * REG_LID7_REG
1246  */
1247 #define LID7_RD(x) (((x) & 0x1F) << 0)
1248 
1249 /*
1250  * REG_ILS_BID
1251  */
1252 #define ADJCNT(x) (((x) & 0xF) << 4)
1253 #define BID(x) (((x) & 0xF) << 0)
1254 
1255 /*
1256  * REG_ILS_LID0
1257  */
1258 #define ADJDIR (1 << 6)
1259 #define PHADJ (1 << 5)
1260 #define LID0(x) (((x) & 0x1F) << 0)
1261 
1262 /*
1263  * REG_ILS_SCR_L
1264  */
1265 #define SCR (1 << 7)
1266 #define L(x) (((x) & 0x1F) << 0)
1267 
1268 /*
1269  * REG_ILS_K
1270  */
1271 #define K(x) (((x) & 0x1F) << 0)
1272 
1273 /*
1274  * REG_ILS_CS_N
1275  */
1276 #define CS(x) (((x) & 0x3) << 6)
1277 #define N(x) (((x) & 0x1F) << 0)
1278 
1279 /*
1280  * REG_ILS_NP
1281  */
1282 #define SUBCLASSV(x) (((x) & 0x7) << 5)
1283 #define NP(x) (((x) & 0x1F) << 0)
1284 
1285 /*
1286  * REG_ILS_S
1287  */
1288 #define JESDV(x) (((x) & 0x7) << 5)
1289 #define S(x) (((x) & 0x1F) << 0)
1290 
1291 /*
1292  * REG_ILS_HD_CF
1293  */
1294 #define HD (1 << 7)
1295 #define CF(x) (((x) & 0x1F) << 0)
1296 
1297 /*
1298  * REG_ERRCNTRMON
1299  */
1300 #define LANESEL(x) (((x) & 0x7) << 4)
1301 #define CNTRSEL(x) (((x) & 0x3) << 0)
1302 
1303 /*
1304  * REG_BADDISPARITY
1305  */
1306 #define RST_IRQ_DIS (1 << 7)
1307 #define DIS_ERR_CNTR_DIS (1 << 6)
1308 #define RST_ERR_CNTR_DIS (1 << 5)
1309 #define LANE_ADDR_DIS(x) (((x) & 0x7) << 0)
1310 
1311 /*
1312  * REG_NITDISPARITY
1313  */
1314 #define RST_IRQ_NIT (1 << 7)
1315 #define DIS_ERR_CNTR_NIT (1 << 6)
1316 #define RST_ERR_CNTR_NIT (1 << 5)
1317 #define LANE_ADDR_NIT(x) (((x) & 0x7) << 0)
1318 
1319 /*
1320  * REG_UNEXPECTEDKCHAR
1321  */
1322 #define RST_IRQ_K (1 << 7)
1323 #define DIS_ERR_CNTR_K (1 << 6)
1324 #define RST_ERR_CNTR_K (1 << 5)
1325 #define LANE_ADDR_K(x) (((x) & 0x7) << 0)
1326 
1327 /*
1328  * REG_CTRLREG2
1329  */
1330 #define ILAS_MODE (1 << 7)
1331 #define REPDATATEST (1 << 5)
1332 #define QUETESTERR (1 << 4)
1333 #define AUTO_ECNTR_RST (1 << 3)
1334 
1335 /*
1336  * REG_IRQVECTOR
1337  */
1338 #define BADDIS_FLAG_OR_MASK (1 << 7)
1339 #define NITD_FLAG_OR_MASK (1 << 6)
1340 #define UEKC_FLAG_OR_MASK (1 << 5)
1341 #define INITIALLANESYNC_FLAG_OR_MASK (1 << 3)
1342 #define BADCHECKSUM_FLAG_OR_MASK (1 << 2)
1343 #define CODEGRPSYNC_FLAG_OR_MASK (1 << 0)
1344 
1345 /*
1346  * REG_SYNCASSERTIONMASK
1347  */
1348 #define BAD_DIS_S (1 << 7)
1349 #define NIT_DIS_S (1 << 6)
1350 #define UNEX_K_S (1 << 5)
1351 #define CMM_FLAG_OR_MASK (1 << 4)
1352 #define CMM_ENABLE (1 << 3)
1353 
1354 
1355 #define AD9144_MAX_DAC_RATE 2000000000UL
1356 #define AD9144_CHIP_ID 0x44
1357 #define AD9144_PRBS7 0x0
1358 #define AD9144_PRBS15 0x1
1359 
1360 /******************************************************************************/
1361 /*************************** Types Declarations *******************************/
1362 /******************************************************************************/
1363 struct ad9144_dev {
1364  /* SPI */
1366 
1369  uint8_t num_lanes;
1370 };
1371 
1373  /* SPI */
1375  /* Device Settings */
1376  uint8_t spi3wire; // set device spi intereface 3/4 wires
1377  uint8_t interpolation; // interpolation factor
1378  uint32_t stpl_samples[4][4];
1379  uint32_t lane_rate_kbps;
1380  uint32_t prbs_type;
1381 
1382  uint8_t jesd204_mode;
1385  uint8_t jesd204_lane_xbar[8];
1386 
1387  /* Whether to enable the internal DAC PLL (0=disable, 1=enable) */
1388  uint8_t pll_enable;
1389  /* When using the DAC PLL this specifies the external reference clock frequency in kHz. */
1391  /* When using the DAC PLL this specifies the target PLL output frequency in kHz. */
1393 };
1394 
1395 /******************************************************************************/
1396 /************************ Functions Declarations ******************************/
1397 /******************************************************************************/
1398 int32_t ad9144_setup(struct ad9144_dev **device,
1399  const struct ad9144_init_param *init_param);
1400 
1401 int32_t ad9144_remove(struct ad9144_dev *dev);
1402 
1403 int32_t ad9144_spi_read(struct ad9144_dev *dev,
1404  uint16_t reg_addr,
1405  uint8_t *reg_data);
1406 
1407 int32_t ad9144_spi_write(struct ad9144_dev *dev,
1408  uint16_t reg_addr,
1409  uint8_t reg_data);
1410 
1411 int32_t ad9144_spi_check_status(struct ad9144_dev *dev,
1412  uint16_t reg_addr,
1413  uint8_t reg_mask,
1414  uint8_t exp_reg_data);
1415 
1416 int32_t ad9144_status(struct ad9144_dev *dev);
1417 
1418 int32_t ad9144_short_pattern_test(struct ad9144_dev *dev,
1419  const struct ad9144_init_param *init_param);
1420 
1421 int32_t ad9144_datapath_prbs_test(struct ad9144_dev *dev,
1422  const struct ad9144_init_param *init_param);
1423 
1424 int32_t ad9144_dac_calibrate(struct ad9144_dev *dev);
1425 
1426 int32_t ad9144_set_nco(struct ad9144_dev *dev, int32_t f_carrier_khz,
1427  int16_t phase);
1428 
1429 #endif
ad9144_init_param::pll_dac_frequency_khz
uint32_t pll_dac_frequency_khz
Definition: ad9144.h:1392
REG_CDR_RESET
#define REG_CDR_RESET
Definition: ad9144.h:204
REG_XBAR_LN_6_7
#define REG_XBAR_LN_6_7
Definition: ad9144.h:238
ad9144_short_pattern_test
int32_t ad9144_short_pattern_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_short_pattern_test
Definition: ad9144.c:684
FTW_UPDATE_REQ
#define FTW_UPDATE_REQ
Definition: ad9144.h:812
REG_ILS_SCR_L
#define REG_ILS_SCR_L
Definition: ad9144.h:300
SRC_LANE3
#define SRC_LANE3(x)
Definition: ad9144.h:1110
REG_SHORT_TPL_TEST_1
#define REG_SHORT_TPL_TEST_1
Definition: ad9144.h:256
REG_DACINTEGERWORD0
#define REG_DACINTEGERWORD0
Definition: ad9144.h:118
REG_CAL_CTRL
#define REG_CAL_CTRL
Definition: ad9144.h:134
ad9144_datapath_prbs_test
int32_t ad9144_datapath_prbs_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_datapath_prbs_test
Definition: ad9144.c:724
REG_MASTER_PD
#define REG_MASTER_PD
Definition: ad9144.h:201
ad9144_reg_seq::reg
uint16_t reg
Definition: ad9144.c:142
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
REG_PRBS_ERROR_I
#define REG_PRBS_ERROR_I
Definition: ad9144.h:188
REG_LMFC_VAR_0
#define REG_LMFC_VAR_0
Definition: ad9144.h:233
REG_DACPLLSTATUS
#define REG_DACPLLSTATUS
Definition: ad9144.h:117
REG_GOODCHKSUMFLG
#define REG_GOODCHKSUMFLG
Definition: ad9144.h:318
SOFTRESET_M
#define SOFTRESET_M
Definition: ad9144.h:331
REG_LMFC_DELAY_1
#define REG_LMFC_DELAY_1
Definition: ad9144.h:232
no_os_spi.h
Header file of SPI Interface.
ad9144_dev::sample_rate_khz
uint32_t sample_rate_khz
Definition: ad9144.h:1367
ad9144_dac_calibrate
int32_t ad9144_dac_calibrate(struct ad9144_dev *dev)
Definition: ad9144.c:593
REG_DACLDOCNTRL1
#define REG_DACLDOCNTRL1
Definition: ad9144.h:124
REG_SYSREF_ACTRL0
#define REG_SYSREF_ACTRL0
Definition: ad9144.h:114
ad9144_spi_write_seq
int32_t ad9144_spi_write_seq(struct ad9144_dev *dev, const struct ad9144_reg_seq *seq, uint32_t num)
Definition: ad9144.c:146
REG_SHORT_TPL_TEST_2
#define REG_SHORT_TPL_TEST_2
Definition: ad9144.h:257
ad9144_status
int32_t ad9144_status(struct ad9144_dev *dev)
ad9144_status - return the status of the JESD interface
Definition: ad9144.c:645
ad9144_setup
int32_t ad9144_setup(struct ad9144_dev **device, const struct ad9144_init_param *init_param)
ad9144_setup
Definition: ad9144.c:439
REG_XBAR_LN_2_3
#define REG_XBAR_LN_2_3
Definition: ad9144.h:236
no_os_delay.h
Header file of Delay functions.
ad9144_init_param::prbs_type
uint32_t prbs_type
Definition: ad9144.h:1380
ad9144_set_nco
int32_t ad9144_set_nco(struct ad9144_dev *dev, int32_t f_carrier_khz, int16_t phase)
Definition: ad9144.c:368
REG_ILS_BID
#define REG_ILS_BID
Definition: ad9144.h:298
REG_ILS_DID
#define REG_ILS_DID
Definition: ad9144.h:297
ad9144_datapath_prbs_test
int32_t ad9144_datapath_prbs_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_datapath_prbs_test
Definition: ad9144.c:724
ad9144_init_param::jesd204_subclass
uint8_t jesd204_subclass
Definition: ad9144.h:1383
device
Definition: ad9361_util.h:75
SRC_LANE0
#define SRC_LANE0(x)
Definition: ad9144.h:1105
REG_DEV_CONFIG_9
#define REG_DEV_CONFIG_9
Definition: ad9144.h:221
REG_FRAMESYNCFLG
#define REG_FRAMESYNCFLG
Definition: ad9144.h:317
ad9144_set_nco
int32_t ad9144_set_nco(struct ad9144_dev *dev, int32_t f_carrier_khz, int16_t phase)
Definition: ad9144.c:368
ad9144_spi_read
int32_t ad9144_spi_read(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9144_spi_read
Definition: ad9144.c:74
REG_GENERAL_JRX_CTRL_1
#define REG_GENERAL_JRX_CTRL_1
Definition: ad9144.h:228
REG_ILS_CS_N
#define REG_ILS_CS_N
Definition: ad9144.h:304
REG_INTERP_MODE
#define REG_INTERP_MODE
Definition: ad9144.h:141
REG_ILS_S
#define REG_ILS_S
Definition: ad9144.h:306
MODULATION_TYPE_MASK
#define MODULATION_TYPE_MASK
Definition: ad9144.h:801
REG_ILS_K
#define REG_ILS_K
Definition: ad9144.h:302
NO_OS_ARRAY_SIZE
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
SRC_LANE1
#define SRC_LANE1(x)
Definition: ad9144.h:1104
REG_DEV_CONFIG_12
#define REG_DEV_CONFIG_12
Definition: ad9144.h:226
REG_REF_CLK_DIVIDER_LDO
#define REG_REF_CLK_DIVIDER_LDO
Definition: ad9144.h:214
REG_DACPLLT5
#define REG_DACPLLT5
Definition: ad9144.h:190
ad9144_reg_seq::val
uint16_t val
Definition: ad9144.c:143
REG_LANEENABLE
#define REG_LANEENABLE
Definition: ad9144.h:326
REG_SPI_PAGEINDX
#define REG_SPI_PAGEINDX
Definition: ad9144.h:59
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
ad9144_init_param::interpolation
uint8_t interpolation
Definition: ad9144.h:1377
REG_XBAR_LN_0_1
#define REG_XBAR_LN_0_1
Definition: ad9144.h:235
no_os_error.h
Error codes definition.
SEL_SIDEBAND
#define SEL_SIDEBAND
Definition: ad9144.h:798
REG_CAL_CLKDIV
#define REG_CAL_CLKDIV
Definition: ad9144.h:132
ad9144_spi_read
int32_t ad9144_spi_read(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9144_spi_read
Definition: ad9144.c:74
REG_EQ_BIAS_REG
#define REG_EQ_BIAS_REG
Definition: ad9144.h:211
ad9144_init_param::jesd204_mode
uint8_t jesd204_mode
Definition: ad9144.h:1382
ad9144_status
int32_t ad9144_status(struct ad9144_dev *dev)
ad9144_status - return the status of the JESD interface
Definition: ad9144.c:645
REG_TERM_BLK2_CTRLREG0
#define REG_TERM_BLK2_CTRLREG0
Definition: ad9144.h:223
ad9144_init_param::jesd204_lane_xbar
uint8_t jesd204_lane_xbar[8]
Definition: ad9144.h:1385
REG_NCO_PHASE_OFFSET0
#define REG_NCO_PHASE_OFFSET0
Definition: ad9144.h:149
REG_CAL_INIT
#define REG_CAL_INIT
Definition: ad9144.h:138
ad9144_dev::num_lanes
uint8_t num_lanes
Definition: ad9144.h:1369
REG_INITLANESYNCFLG
#define REG_INITLANESYNCFLG
Definition: ad9144.h:319
REG_SHORT_TPL_TEST_0
#define REG_SHORT_TPL_TEST_0
Definition: ad9144.h:255
MODULATION_TYPE
#define MODULATION_TYPE(x)
Definition: ad9144.h:800
SOFTRESET
#define SOFTRESET
Definition: ad9144.h:338
REG_SHORT_TPL_TEST_3
#define REG_SHORT_TPL_TEST_3
Definition: ad9144.h:258
REG_CDR_OPERATING_MODE_REG_0
#define REG_CDR_OPERATING_MODE_REG_0
Definition: ad9144.h:205
ad9144_dev
Definition: ad9144.h:1363
ad9144_init_param::spi_init
no_os_spi_init_param spi_init
Definition: ad9144.h:1374
REG_ILS_LID0
#define REG_ILS_LID0
Definition: ad9144.h:299
REG_SPI_PRODIDL
#define REG_SPI_PRODIDL
Definition: ad9144.h:56
ad9144_init_param::pll_ref_frequency_khz
uint32_t pll_ref_frequency_khz
Definition: ad9144.h:1390
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
REG_DACLOGENCNTRL
#define REG_DACLOGENCNTRL
Definition: ad9144.h:123
ad9144_remove
int32_t ad9144_remove(struct ad9144_dev *dev)
Free the resources allocated by ad9144_setup().
Definition: ad9144.c:631
REG_SYNTH_ENABLE_CNTRL
#define REG_SYNTH_ENABLE_CNTRL
Definition: ad9144.h:212
AD9144_CHIP_ID
#define AD9144_CHIP_ID
Definition: ad9144.h:1356
REG_ILS_HD_CF
#define REG_ILS_HD_CF
Definition: ad9144.h:307
ad9144_dev::spi_desc
no_os_spi_desc * spi_desc
Definition: ad9144.h:1365
REG_PLL_STATUS
#define REG_PLL_STATUS
Definition: ad9144.h:213
REG_ILS_NP
#define REG_ILS_NP
Definition: ad9144.h:305
REG_PHY_PD
#define REG_PHY_PD
Definition: ad9144.h:202
REG_ILS_M
#define REG_ILS_M
Definition: ad9144.h:303
REG_LANEDESKEW
#define REG_LANEDESKEW
Definition: ad9144.h:312
REG_TERM_BLK1_CTRLREG0
#define REG_TERM_BLK1_CTRLREG0
Definition: ad9144.h:219
ad9144_setup_jesd204_link
int32_t ad9144_setup_jesd204_link(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
Definition: ad9144.c:193
ad9144_reg_seq
Definition: ad9144.c:141
REG_DACPLLT18
#define REG_DACPLLT18
Definition: ad9144.h:194
NO_OS_BIT
#define NO_OS_BIT(x)
Definition: no_os_util.h:51
REG_FTW0
#define REG_FTW0
Definition: ad9144.h:143
REG_XBAR_LN_4_5
#define REG_XBAR_LN_4_5
Definition: ad9144.h:237
ad9144_dac_calibrate
int32_t ad9144_dac_calibrate(struct ad9144_dev *dev)
Definition: ad9144.c:593
REG_LMFC_DELAY_0
#define REG_LMFC_DELAY_0
Definition: ad9144.h:231
NULL
#define NULL
Definition: wrapper.h:64
REG_CAL_INDX
#define REG_CAL_INDX
Definition: ad9144.h:133
REG_DACPLLTB
#define REG_DACPLLTB
Definition: ad9144.h:191
ad9144_dev::num_converters
uint8_t num_converters
Definition: ad9144.h:1368
REG_DEV_CONFIG_11
#define REG_DEV_CONFIG_11
Definition: ad9144.h:225
ad9144_spi_check_status
int32_t ad9144_spi_check_status(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_mask, uint8_t exp_reg_data)
ad9144_spi_check_status
Definition: ad9144.c:119
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
ad9144_init_param::stpl_samples
uint32_t stpl_samples[4][4]
Definition: ad9144.h:1378
ad9144_init_param
Definition: ad9144.h:1372
ad9144_setup
int32_t ad9144_setup(struct ad9144_dev **device, const struct ad9144_init_param *init_param)
ad9144_setup
Definition: ad9144.c:439
REG_ILS_F
#define REG_ILS_F
Definition: ad9144.h:301
REG_SPI_SCRATCHPAD
#define REG_SPI_SCRATCHPAD
Definition: ad9144.h:61
ad9144_init_param::spi3wire
uint8_t spi3wire
Definition: ad9144.h:1376
REG_NCO_FTW_UPDATE
#define REG_NCO_FTW_UPDATE
Definition: ad9144.h:142
ad9144_spi_check_status
int32_t ad9144_spi_check_status(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_mask, uint8_t exp_reg_data)
ad9144_spi_check_status
Definition: ad9144.c:119
ad9144_short_pattern_test
int32_t ad9144_short_pattern_test(struct ad9144_dev *dev, const struct ad9144_init_param *init_param)
ad9144_short_pattern_test
Definition: ad9144.c:684
REG_SPI_INTFCONFA
#define REG_SPI_INTFCONFA
Definition: ad9144.h:53
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
REG_CTRLREG1
#define REG_CTRLREG1
Definition: ad9144.h:320
REG_DEV_CONFIG_10
#define REG_DEV_CONFIG_10
Definition: ad9144.h:222
SRC_LANE5
#define SRC_LANE5(x)
Definition: ad9144.h:1116
REG_CODEGRPSYNCFLG
#define REG_CODEGRPSYNCFLG
Definition: ad9144.h:316
ad9144_init_param::jesd204_scrambling
uint8_t jesd204_scrambling
Definition: ad9144.h:1384
REG_SYNCB_GEN_1
#define REG_SYNCB_GEN_1
Definition: ad9144.h:243
ad9144_init_param::pll_enable
uint8_t pll_enable
Definition: ad9144.h:1388
REG_LMFC_VAR_1
#define REG_LMFC_VAR_1
Definition: ad9144.h:234
ad9144_spi_write
int32_t ad9144_spi_write(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9144_spi_write
Definition: ad9144.c:97
REG_SYNC_CTRL
#define REG_SYNC_CTRL
Definition: ad9144.h:84
REG_PWRCNTRL0
#define REG_PWRCNTRL0
Definition: ad9144.h:63
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
no_os_util.h
Implementation of utility functions.
REG_NCO_PHASE_OFFSET1
#define REG_NCO_PHASE_OFFSET1
Definition: ad9144.h:150
REG_DATAPATH_CTRL
#define REG_DATAPATH_CTRL
Definition: ad9144.h:140
SRC_LANE2
#define SRC_LANE2(x)
Definition: ad9144.h:1111
SRC_LANE6
#define SRC_LANE6(x)
Definition: ad9144.h:1123
SRC_LANE7
#define SRC_LANE7(x)
Definition: ad9144.h:1122
ad9144_init_param::lane_rate_kbps
uint32_t lane_rate_kbps
Definition: ad9144.h:1379
SRC_LANE4
#define SRC_LANE4(x)
Definition: ad9144.h:1117
REG_DACPLLCNTRL
#define REG_DACPLLCNTRL
Definition: ad9144.h:116
REG_CLKCFG0
#define REG_CLKCFG0
Definition: ad9144.h:113
REG_SERDES_SPI_REG
#define REG_SERDES_SPI_REG
Definition: ad9144.h:245
ad9144.h
Header file of AD9144 Driver.
REG_PRBS_ERROR_Q
#define REG_PRBS_ERROR_Q
Definition: ad9144.h:189
REG_DATA_FORMAT
#define REG_DATA_FORMAT
Definition: ad9144.h:139
ad9144_remove
int32_t ad9144_remove(struct ad9144_dev *dev)
Free the resources allocated by ad9144_setup().
Definition: ad9144.c:631
REG_GENERAL_JRX_CTRL_0
#define REG_GENERAL_JRX_CTRL_0
Definition: ad9144.h:227
ad9144_spi_write
int32_t ad9144_spi_write(struct ad9144_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9144_spi_write
Definition: ad9144.c:97
chip_id
chip_id
Definition: ad9172.h:57
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
REG_PRBS
#define REG_PRBS
Definition: ad9144.h:187