no-OS
ad9152.h
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1 /***************************************************************************/
39 #ifndef AD9152_H_
40 #define AD9152_H_
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include <stdint.h>
46 #include "no_os_delay.h"
47 #include "no_os_spi.h"
48 
49 /******************************************************************************/
50 /********************** Macros and Constants Definitions **********************/
51 /******************************************************************************/
52 #define REG_SPI_INTFCONFA 0x000 /* Interface configuration A */
53 #define REG_SPI_INTFCONFB 0x001 /* Interface configuration B */
54 #define REG_SPI_DEVCONF 0x002 /* Device Configuration */
55 #define REG_SPI_PRODIDL 0x004 /* Product Identification Low Byte */
56 #define REG_SPI_PRODIDH 0x005 /* Product Identification High Byte */
57 #define REG_SPI_CHIPGRADE 0x006 /* Chip Grade */
58 #define REG_SPI_PAGEINDX 0x008 /* Page Pointer or Device Index */
59 #define REG_SPI_DEVINDX2 0x009 /* Secondary Device Index */
60 #define REG_SPI_SCRATCHPAD 0x00A /* Scratch Pad */
61 #define REG_SPI_MS_UPDATE 0x00F /* Master/Slave Update Bit */
62 #define REG_PWRCNTRL0 0x011 /* Power Control Reg 1 */
63 #define REG_TXENMASK1 0x012 /* TXenable masks */
64 #define REG_PWRCNTRL3 0x013 /* Power control register 3 */
65 #define REG_COARSE_GROUP_DLY 0x014 /* Coarse Group Delay Adjustment */
66 #define REG_IRQ_ENABLE0 0x01F /* Interrupt Enable */
67 #define REG_IRQ_ENABLE1 0x020 /* Interrupt Enable */
68 #define REG_IRQ_ENABLE2 0x021 /* Interrupt Enable */
69 #define REG_IRQ_ENABLE3 0x022 /* Interrupt Enable */
70 #define REG_IRQ_STATUS0 0x023 /* Interrupt Status */
71 #define REG_IRQ_STATUS1 0x024 /* Interrupt Status */
72 #define REG_IRQ_STATUS2 0x025 /* Interrupt Status */
73 #define REG_IRQ_STATUS3 0x026 /* Interrupt Status */
74 #define REG_JESD_CHECKS 0x030 /* JESD Parameter Checking */
75 #define REG_SYNC_TESTCTRL 0x031 /* Sync Control Reg0 */
76 #define REG_SYNC_DACDELAY_L 0x032 /* Sync Logic DacDelay [7:0] */
77 #define REG_SYNC_DACDELAY_H 0x033 /* Sync Logic DacDelay [8] */
78 #define REG_SYNC_ERRWINDOW 0x034 /* Sync Error Window */
79 #define REG_SYNC_DLYCOUNT 0x035 /* Sync Control Ref Delay Count */
80 #define REG_SYNC_REFCOUNT 0x036 /* Sync SysRef InActive Interval */
81 #define REG_SYNC_LASTERR_L 0x038 /* SyncLASTerror_L */
82 #define REG_SYNC_LASTERR_H 0x039 /* SyncLASTerror_H */
83 #define REG_SYNC_CTRL 0x03A /* Sync Mode Control */
84 #define REG_SYNC_STATUS 0x03B /* Sync Alignment Flags */
85 #define REG_SYNC_CURRERR_L 0x03C /* Sync Alignment Error[7:0] */
86 #define REG_SYNC_CURRERR_H 0x03D /* Sync Alignment Error[8] */
87 #define REG_ERROR_THERM 0x03E /* Sync Error Thermometer */
88 #define REG_DACGAIN0_1 0x040 /* MSBs of Full Scale Adjust DAC */
89 #define REG_DACGAIN0_0 0x041 /* LSBs of Full Scale Adjust DAC */
90 #define REG_DACGAIN1_1 0x042 /* MSBs of Full Scale Adjust DAC */
91 #define REG_DACGAIN1_0 0x043 /* LSBs of Full Scale Adjust DAC */
92 #define REG_DACGAIN2_1 0x044 /* MSBs of Full Scale Adjust DAC */
93 #define REG_DACGAIN2_0 0x045 /* LSBs of Full Scale Adjust DAC */
94 #define REG_DACGAIN3_1 0x046 /* MSBs of Full Scale Adjust DAC */
95 #define REG_DACGAIN3_0 0x047 /* LSBs of Full Scale Adjust DAC */
96 #define REG_PD_DACLDO 0x048 /* Powerdown DAC LDOs */
97 #define REG_STAT_DACLDO 0x049 /* DAC LDO Status */
98 #define REG_DECODE_CTRL0 0x04B /* Decoder Control */
99 #define REG_DECODE_CTRL1 0x04C /* Decoder Control */
100 #define REG_DECODE_CTRL2 0x04D /* Decoder Control */
101 #define REG_DECODE_CTRL3 0x04E /* Decoder Control */
102 #define REG_NCO_CLRMODE 0x050 /* NCO CLR Mode */
103 #define REG_NCOKEY_ILSB 0x051 /* NCO Clear on Data Key I lsb */
104 #define REG_NCOKEY_IMSB 0x052 /* NCO Clear on Data Key I msb */
105 #define REG_NCOKEY_QLSB 0x053 /* NCO Clear on Data Key Q lsb */
106 #define REG_NCOKEY_QMSB 0x054 /* NCO Clear on Data Key Q msb */
107 #define REG_PA_THRES0 0x060 /* PDP Threshold */
108 #define REG_PA_THRES1 0x061 /* PDP Threshold */
109 #define REG_PA_AVG_TIME 0x062 /* PDP Control */
110 #define REG_PA_POWER0 0x063 /* PDP Power */
111 #define REG_PA_POWER1 0x064 /* PDP Power */
112 #define REG_CLKCFG0 0x080 /* Clock Configuration */
113 #define REG_SYSREF_ACTRL0 0x081 /* SYSREF Analog Control 0 */
114 #define REG_SYSREF_ACTRL1 0x082 /* SYSREF Analog Control 1 */
115 #define REG_DACPLLCNTRL 0x083 /* Top Level Control DAC Clock PLL */
116 #define REG_DACPLLSTATUS 0x084 /* DAC PLL Status Bits */
117 #define REG_DACINTEGERWORD0 0x085 /* Feedback divider tuning word */
118 #define REG_DACLOOPFILT1 0x087 /* C1 and C2 control */
119 #define REG_DACLOOPFILT2 0x088 /* R1 and C3 control */
120 #define REG_DACLOOPFILT3 0x089 /* Bypass and R2 control */
121 #define REG_DACCPCNTRL 0x08A /* Charge Pump/Cntrl Voltage */
122 #define REG_DACLOGENCNTRL 0x08B /* Logen Control */
123 #define REG_DACLDOCNTRL1 0x08C /* LDO Control1 + Reference Divider */
124 #define REG_CAL_DAC_ERR 0x0E0 /* Report DAC Cal errors */
125 #define REG_CAL_MSB_THRES 0x0E1 /* MSB sweep Threshold definition */
126 #define REG_CAL_CTRL_GLOBAL 0x0E2 /* Global Calibration DAC Control */
127 #define REG_CAL_MSBHILVL 0x0E3 /* High Level for MSB level compare */
128 #define REG_CAL_MSBLOLVL 0x0E4 /* Low Level for MSB level compare */
129 #define REG_CAL_THRESH 0x0E5 /* TAC Threshold definition */
130 #define REG_CAL_AVG_CNT 0x0E6 /* CAL DAC Number of averages */
131 #define REG_CAL_CLKDIV 0x0E7 /* Calibration DAC clock divide */
132 #define REG_CAL_INDX 0x0E8 /* Calibration DAC Select */
133 #define REG_CAL_CTRL 0x0E9 /* Calibration DAC Control */
134 #define REG_CAL_ADDR 0x0EA /* Calibration DAC Address */
135 #define REG_CAL_DATA 0x0EB /* Calibration DAC Data */
136 #define REG_CAL_UPDATE 0x0EC /* Calibration DAC Write Update */
137 #define REG_DATA_FORMAT 0x110 /* Data format */
138 #define REG_DATAPATH_CTRL 0x111 /* Datapath Control */
139 #define REG_INTERP_MODE 0x112 /* Interpolation Mode */
140 #define REG_NCO_FTW_UPDATE 0x113 /* NCO Frequency Tuning Word Update */
141 #define REG_FTW0 0x114 /* NCO Frequency Tuning Word LSB */
142 #define REG_FTW1 0x115 /* NCO Frequency Tuning Word */
143 #define REG_FTW2 0x116 /* NCO Frequency Tuning Word */
144 #define REG_FTW3 0x117 /* NCO Frequency Tuning Word */
145 #define REG_FTW4 0x118 /* NCO Frequency Tuning Word */
146 #define REG_FTW5 0x119 /* NCO Frequency Tuning Word MSB */
147 #define REG_NCO_PHASE_OFFSET0 0x11A /* NCO Phase Offset LSB */
148 #define REG_NCO_PHASE_OFFSET1 0x11B /* NCO Phase Offset MSB */
149 #define REG_NCO_PHASE_ADJ0 0x11C /* I/Q Phase Adjust LSB */
150 #define REG_NCO_PHASE_ADJ1 0x11D /* I/Q Phase Adjust MSB */
151 #define REG_TXEN_FUNC 0x11E /* Transmit Enable function */
152 #define REG_TXEN_SM_0 0x11F /* Transmit enable power control state machine */
153 #define REG_TXEN_SM_1 0x120 /* Rise and fall */
154 #define REG_TXEN_SM_2 0x121 /* Transmit enable maximum A */
155 #define REG_TXEN_SM_3 0x122 /* Transmit enable maximum B */
156 #define REG_TXEN_SM_4 0x123 /* Transmit enable maximum C */
157 #define REG_TXEN_SM_5 0x124 /* Transmit enable maximum D */
158 #define REG_DACOUT_ON_DOWN 0x125 /* DAC out down control and on trigger */
159 #define REG_DACOFF 0x12C /* DAC Shutdown Source */
160 #define REG_DATA_PATH_FLUSH_COUNT0 0x12D /* Data path flush counter LSB */
161 #define REG_DATA_PATH_FLUSH_COUNT1 0x12E /* Data path flush counter MSB */
162 #define REG_DIE_TEMP_CTRL0 0x12F /* Die Temp Range Control */
163 #define REG_DIE_TEMP_CTRL1 0x130 /* Die temperature control register */
164 #define REG_DIE_TEMP_CTRL2 0x131 /* Die temperature control register */
165 #define REG_DIE_TEMP0 0x132 /* Die temp LSB */
166 #define REG_DIE_TEMP1 0x133 /* Die Temp MSB */
167 #define REG_DIE_TEMP_UPDATE 0x134 /* Die temperature update */
168 #define REG_DC_OFFSET_CTRL 0x135 /* DC Offset Control */
169 #define REG_IPATH_DC_OFFSET_1PART0 0x136 /* LSB of first part of DC Offset value for I path */
170 #define REG_IPATH_DC_OFFSET_1PART1 0x137 /* MSB of first part of DC Offset value for I path */
171 #define REG_QPATH_DC_OFFSET_1PART0 0x138 /* LSB of first part of DC Offset value for Q path */
172 #define REG_QPATH_DC_OFFSET_1PART1 0x139 /* MSB of first part of DC Offset value for Q path */
173 #define REG_IPATH_DC_OFFSET_2PART 0x13A /* Second part of DC Offset value for I path */
174 #define REG_QPATH_DC_OFFSET_2PART 0x13B /* Second part of DC Offset value for Q path */
175 #define REG_IDAC_DIG_GAIN0 0x13C /* I DAC Gain LSB */
176 #define REG_IDAC_DIG_GAIN1 0x13D /* I DAC Gain MSB */
177 #define REG_QDAC_DIG_GAIN0 0x13E /* Q DAC Gain LSB */
178 #define REG_QDAC_DIG_GAIN1 0x13F /* Q DAC Gain MSB */
179 #define REG_GAIN_RAMP_UP_STP0 0x140 /* LSB of digital gain rises */
180 #define REG_GAIN_RAMP_UP_STP1 0x141 /* MSB of digital gain rises */
181 #define REG_GAIN_RAMP_DOWN_STP0 0x142 /* LSB of digital gain drops */
182 #define REG_GAIN_RAMP_DOWN_STP1 0x143 /* MSB of digital gain drops */
183 #define REG_BLSM_CTRL 0x146 /* Blanking SM control and func */
184 #define REG_BLSM_STAT 0x147 /* Blanking SM control and func */
185 #define REG_PRBS 0x14B /* PRBS Input Data Checker */
186 #define REG_PRBS_ERROR_I 0x14C /* PRBS Error Counter Real */
187 #define REG_PRBS_ERROR_Q 0x14D /* PRBS Error Counter Imaginary */
188 #define REG_DACPLLT5 0x1B5 /* ALC/Varactor control */
189 #define REG_DACPLLTB 0x1BB /* VCO Bias Control */
190 #define REG_DACPLLTD 0x1BD /* VCO Cal control */
191 #define REG_DACPLLT17 0x1C4 /* Varactor ControlV */
192 #define REG_ASPI_SPARE0 0x1C6 /* Spare Register 0 */
193 #define REG_ASPI_SPARE1 0x1C7 /* Spare Register 1 */
194 #define REG_SPISTRENGTH 0x1DF /* Reg 70 Description */
195 #define REG_CLK_TEST 0x1EB /* Clock related control signaling */
196 #define REG_ATEST_VOLTS 0x1EC /* Analog Test Voltage Extraction */
197 #define REG_ASPI_CLKSRC 0x1ED /* Analog Spi clock source for PD machines */
198 #define REG_MASTER_PD 0x200 /* Master power down for Receiver PHYx */
199 #define REG_PHY_PD 0x201 /* Power down for individual Receiver PHYx */
200 #define REG_GENERIC_PD 0x203 /* Miscellaneous power down controls */
201 #define REG_CDR_OPERATING_MODE_REG_0 0x230 /* Clock and data recovery operating modes */
202 #define REG_EQ_CONFIG_PHY_0_1 0x250 /* Equalizer configuration for PHY 0 and PHY 1 */
203 #define REG_EQ_CONFIG_PHY_2_3 0x251 /* Equalizer configuration for PHY 2 and PHY 3 */
204 #define REG_EQ_CONFIG_PHY_4_5 0x252 /* Equalizer configuration for PHY 4 and PHY 5 */
205 #define REG_EQ_CONFIG_PHY_6_7 0x253 /* Equalizer configuration for PHY 6 and PHY 7 */
206 #define REG_EQ_BIAS_REG 0x268 /* Equalizer bias control */
207 #define REG_SYNTH_ENABLE_CNTRL 0x280 /* Rx PLL enable controls */
208 #define REG_PLL_STATUS 0x281 /* Rx PLL status readbacks */
209 #define REG_REF_CLK_DIVIDER_LDO 0x289 /* Rx PLL LDO control */
210 #define REG_TERM_BLK1_CTRLREG0 0x2A7 /* Termination controls for PHYs 0, 1, 6, and 7 */
211 #define REG_TERM_BLK1_CTRLREG1 0x2A8 /* Termination controls for PHYs 0, 1, 6, and 7 */
212 #define REG_TERM_BLK2_CTRLREG0 0x2AE /* Termination controls for PHYs 2, 3, 4, and 5 */
213 #define REG_TERM_BLK2_CTRLREG1 0x2AF /* Termination controls for PHYs 2, 3, 4, and 5 */
214 #define REG_GENERAL_JRX_CTRL_0 0x300 /* General JRX Control Register 0 */
215 #define REG_GENERAL_JRX_CTRL_1 0x301 /* General JRX Control Register 1 */
216 #define REG_DYN_LINK_LATENCY_0 0x302 /* Register 1 description */
217 #define REG_DYN_LINK_LATENCY_1 0x303 /* Register 2 description */
218 #define REG_LMFC_DELAY_0 0x304 /* Register 3 description */
219 #define REG_LMFC_DELAY_1 0x305 /* Register 4 description */
220 #define REG_LMFC_VAR_0 0x306 /* Register 5 description */
221 #define REG_LMFC_VAR_1 0x307 /* Register 6 description */
222 #define REG_XBAR_LN_0_1 0x308 /* Register 7 description */
223 #define REG_XBAR_LN_2_3 0x309 /* Register 8 description */
224 #define REG_XBAR_LN_4_5 0x30A /* Register 9 description */
225 #define REG_XBAR_LN_6_7 0x30B /* Register 10 description */
226 #define REG_FIFO_STATUS_REG_0 0x30C /* Register 11 description */
227 #define REG_FIFO_STATUS_REG_1 0x30D /* Register 12 description */
228 #define REG_FIFO_STATUS_REG_2 0x30E /* Register 13 description */
229 #define REG_SYNCB_GEN_0 0x311 /* Register 16 description */
230 #define REG_SYNCB_GEN_1 0x312 /* Register 17 description */
231 #define REG_SYNCB_GEN_3 0x313 /* Register 18 description */
232 #define REG_PHY_PRBS_TEST_EN 0x315 /* PHY PRBS TEST ENABLE FOR INDIVIDUAL LANES */
233 #define REG_PHY_PRBS_TEST_CTRL 0x316 /* Reg 20 Description */
234 #define REG_PHY_PRBS_TEST_THRESH_LOBITS 0x317 /* Reg 21 Description */
235 #define REG_PHY_PRBS_TEST_THRESH_MIDBITS 0x318 /* Reg 22 Description */
236 #define REG_PHY_PRBS_TEST_THRESH_HIBITS 0x319 /* Reg 23 Description */
237 #define REG_PHY_PRBS_TEST_ERRCNT_LOBITS 0x31A /* Reg 24 Description */
238 #define REG_PHY_PRBS_TEST_ERRCNT_MIDBITS 0x31B /* Reg 25 Description */
239 #define REG_PHY_PRBS_TEST_ERRCNT_HIBITS 0x31C /* Reg 26 Description */
240 #define REG_PHY_PRBS_TEST_STATUS 0x31D /* Reg 27 Description */
241 #define REG_SHORT_TPL_TEST_0 0x32C /* Reg 46 Description */
242 #define REG_SHORT_TPL_TEST_1 0x32D /* Reg 47 Description */
243 #define REG_SHORT_TPL_TEST_2 0x32E /* Reg 48 Description */
244 #define REG_SHORT_TPL_TEST_3 0x32F /* Reg 49 Description */
245 #define REG_JESD_BIT_INVERSE_CTRL 0x334 /* Reg 42 Description */
246 #define REG_DID_REG 0x400 /* Reg 0 Description */
247 #define REG_BID_REG 0x401 /* Reg 1 Description */
248 #define REG_LID0_REG 0x402 /* Reg 2 Description */
249 #define REG_SCR_L_REG 0x403 /* Reg 3 Description */
250 #define REG_F_REG 0x404 /* Reg 4 Description */
251 #define REG_K_REG 0x405 /* Reg 5 Description */
252 #define REG_M_REG 0x406 /* Reg 6 Description */
253 #define REG_CS_N_REG 0x407 /* Reg 7 Description */
254 #define REG_NP_REG 0x408 /* Reg 8 Description */
255 #define REG_S_REG 0x409 /* Reg 9 Description */
256 #define REG_HD_CF_REG 0x40A /* Reg 10 Description */
257 #define REG_RES1_REG 0x40B /* Reg 11 Description */
258 #define REG_RES2_REG 0x40C /* Reg 12 Description */
259 #define REG_CHECKSUM_REG 0x40D /* Reg 13 Description */
260 #define REG_COMPSUM0_REG 0x40E /* Reg 14 Description */
261 #define REG_LID1_REG 0x412 /* Reg 18 Description */
262 #define REG_CHECKSUM1_REG 0x415 /* Reg 19 Description */
263 #define REG_COMPSUM1_REG 0x416 /* Reg 22 Description */
264 #define REG_LID2_REG 0x41A /* Reg 26 Description */
265 #define REG_CHECKSUM2_REG 0x41D /* Reg 29 Description */
266 #define REG_COMPSUM2_REG 0x41E /* Reg 30 Description */
267 #define REG_LID3_REG 0x422 /* Reg 34 Description */
268 #define REG_CHECKSUM3_REG 0x425 /* Reg 37 Description */
269 #define REG_COMPSUM3_REG 0x426 /* Reg 38 Description */
270 #define REG_LID4_REG 0x42A /* Reg 34 Description */
271 #define REG_CHECKSUM4_REG 0x42D /* Reg 37 Description */
272 #define REG_COMPSUM4_REG 0x42E /* Reg 38 Description */
273 #define REG_LID5_REG 0x432 /* Reg 34 Description */
274 #define REG_CHECKSUM5_REG 0x435 /* Reg 37 Description */
275 #define REG_COMPSUM5_REG 0x436 /* Reg 38 Description */
276 #define REG_LID6_REG 0x43A /* Reg 34 Description */
277 #define REG_CHECKSUM6_REG 0x43D /* Reg 37 Description */
278 #define REG_COMPSUM6_REG 0x43E /* Reg 38 Description */
279 #define REG_LID7_REG 0x442 /* Reg 34 Description */
280 #define REG_CHECKSUM7_REG 0x445 /* Reg 37 Description */
281 #define REG_COMPSUM7_REG 0x446 /* Reg 38 Description */
282 #define REG_ILS_DID 0x450 /* Reg 80 Description */
283 #define REG_ILS_BID 0x451 /* Reg 81 Description */
284 #define REG_ILS_LID0 0x452 /* Reg 82 Description */
285 #define REG_ILS_SCR_L 0x453 /* Reg 83 Description */
286 #define REG_ILS_K 0x455 /* Reg 85 Description */
287 #define REG_ILS_M 0x456 /* Reg 86 Description */
288 #define REG_ILS_CS_N 0x457 /* Reg 87 Description */
289 #define REG_ILS_NP 0x458 /* Reg 88 Description */
290 #define REG_ILS_S 0x459 /* Reg 89 Description */
291 #define REG_ILS_HD_CF 0x45A /* Reg 90 Description */
292 #define REG_ILS_RES1 0x45B /* Reg 91 Description */
293 #define REG_ILS_RES2 0x45C /* Reg 92 Description */
294 #define REG_ILS_CHECKSUM 0x45D /* Reg 93 Description */
295 #define REG_ERRCNTRMON 0x46B /* Reg 107 Description */
296 #define REG_LANEDESKEW 0x46C /* Reg 108 Description */
297 #define REG_BADDISPARITY 0x46D /* Reg 109 Description */
298 #define REG_NITDISPARITY 0x46E /* Reg 110 Description */
299 #define REG_UNEXPECTEDKCHAR 0x46F /* Reg 111 Description */
300 #define REG_CODEGRPSYNCFLG 0x470 /* Reg 112 Description */
301 #define REG_FRAMESYNCFLG 0x471 /* Reg 113 Description */
302 #define REG_GOODCHKSUMFLG 0x472 /* Reg 114 Description */
303 #define REG_INITLANESYNCFLG 0x473 /* Reg 115 Description */
304 #define REG_CTRLREG1 0x476 /* Reg 118 Description */
305 #define REG_CTRLREG2 0x477 /* Reg 119 Description */
306 #define REG_KVAL 0x478 /* Reg 120 Description */
307 #define REG_IRQVECTOR 0x47A /* Reg 122 Description */
308 #define REG_SYNCASSERTIONMASK 0x47B /* Reg 123 Description */
309 #define REG_ERRORTHRES 0x47C /* Reg 124 Description */
310 #define REG_LANEENABLE 0x47D /* Reg 125 Description */
311 
312 /*
313  * REG_SPI_INTFCONFA
314  */
315 #define SOFTRESET_M (1 << 7) /* Soft Reset (Mirror) */
316 #define LSBFIRST_M (1 << 6) /* LSB First (Mirror) */
317 #define ADDRINC_M (1 << 5) /* Address Increment (Mirror) */
318 #define SDOACTIVE_M (1 << 4) /* SDO Active (Mirror) */
319 #define SDOACTIVE (1 << 3) /* SDO Active */
320 #define ADDRINC (1 << 2) /* Address Increment */
321 #define LSBFIRST (1 << 1) /* LSB First */
322 #define SOFTRESET (1 << 0) /* Soft Reset */
323 
324 /*
325  * REG_SPI_INTFCONFB
326  */
327 #define SINGLEINS (1 << 7) /* Single Instruction */
328 #define CSBSTALL (1 << 6) /* CSb Stalling */
329 
330 /*
331  * REG_SPI_DEVCONF
332  */
333 #define DEVSTATUS(x) (((x) & 0xF) << 4) /* Device Status */
334 #define CUSTOPMODE(x) (((x) & 0x3) << 2) /* Customer Operating Mode */
335 #define SYSOPMODE(x) (((x) & 0x3) << 0) /* System Operating Mode */
336 
337 /*
338  * REG_SPI_CHIPGRADE
339  */
340 #define PROD_GRADE(x) (((x) & 0xF) << 4) /* Product Grade */
341 #define DEV_REVISION(x) (((x) & 0xF) << 0) /* Device Revision */
342 
343 /*
344  * REG_SPI_PAGEINDX
345  */
346 #define PAGEINDX(x) (((x) & 0x3) << 0) /* Page or Index Pointer */
347 
348 /*
349  * REG_SPI_MS_UPDATE
350  */
351 #define SLAVEUPDATE (1 << 0) /* M/S Update Bit */
352 
353 /*
354  * REG_PWRCNTRL0
355  */
356 #define PD_BG (1 << 7) /* Reference PowerDown */
357 #define PD_DAC_0 (1 << 6) /* PD Ichannel DAC 0 */
358 #define PD_DAC_1 (1 << 5) /* PD Qchannel DAC 1 */
359 #define PD_DAC_2 (1 << 4) /* PD Ichannel DAC 2 */
360 #define PD_DAC_3 (1 << 3) /* PD Qchannel DAC 3 */
361 #define PD_DACM (1 << 2) /* PD Dac master Bias */
362 
363 /*
364  * REG_TXENMASK1
365  */
366 #define SYS_MASK (1 << 2) /* SYSREF Receiver TXen mask */
367 #define DACB_MASK (1 << 1) /* Dual B Dac TXen1 mask */
368 #define DACA_MASK (1 << 0) /* Dual A Dac TXen0 mask */
369 
370 /*
371  * REG_PWRCNTRL3
372  */
373 #define ENA_PA_CTRL_FROM_PAPROT_ERR (1 << 6) /* Control PDP enable from PAProt block */
374 #define ENA_PA_CTRL_FROM_TXENSM (1 << 5) /* Control PDP enable from Txen State machine */
375 #define ENA_PA_CTRL_FROM_BLSM (1 << 4) /* Control PDP enable from Blanking state machine */
376 #define ENA_PA_CTRL_FROM_SPI (1 << 3) /* Control PDP enable via SPI */
377 #define SPI_PA_CTRL (1 << 2) /* PDP on/off via SPI */
378 #define ENA_SPI_TXEN (1 << 1) /* TXEN from SPI control */
379 #define SPI_TXEN (1 << 0) /* Spi TXEN */
380 
381 /*
382  * REG_COARSE_GROUP_DLY
383  */
384 #define COARSE_GROUP_DLY(x) (((x) & 0xF) << 0) /* Coarse group delay */
385 
386 /*
387  * REG_IRQ_ENABLE0
388  */
389 #define EN_CALPASS (1 << 7) /* Enable Calib PASS detection */
390 #define EN_CALFAIL (1 << 6) /* Enable Calib FAIL detection */
391 #define EN_DACPLLLOST (1 << 5) /* Enable DAC Pll Lost detection */
392 #define EN_DACPLLLOCK (1 << 4) /* Enable DAC Pll Lock detection */
393 #define EN_SERPLLLOST (1 << 3) /* Enable Serdes PLL Lost detection */
394 #define EN_SERPLLLOCK (1 << 2) /* Enable Serdes PLL Lock detection */
395 #define EN_LANEFIFOERR (1 << 1) /* Enable Lane FIFO Error detection */
396 #define EN_DRDLFIFOERR (1 << 0) /* Enable DRDL FIFO Error detection */
397 
398 /*
399  * REG_IRQ_ENABLE1
400  */
401 #define EN_PARMBAD (1 << 7) /* enable BAD Parameter interrupt */
402 #define EN_PRBSQ1 (1 << 3) /* enable PRBS imag DAC B interrupt */
403 #define EN_PRBSI1 (1 << 2) /* enable PRBS real DAC B interrupt */
404 #define EN_PRBSQ0 (1 << 1) /* enable PRBS imag DAC A interrupt */
405 #define EN_PRBSI0 (1 << 0) /* enable PRBS real DAC A interrupt */
406 
407 /*
408  * REG_IRQ_ENABLE2
409  */
410 #define EN_PAERR0 (1 << 7) /* Link A PA Error */
411 #define EN_BIST_DONE0 (1 << 6) /* Link A BIST done */
412 #define EN_BLNKDONE0 (1 << 5) /* Link A Blanking done */
413 #define EN_REFNCOCLR0 (1 << 4) /* Link A Nco Clear Tripped */
414 #define EN_REFLOCK0 (1 << 3) /* Link A Alignment Locked */
415 #define EN_REFROTA0 (1 << 2) /* Link A Alignment Rotate */
416 #define EN_REFWLIM0 (1 << 1) /* Link A Over/Under Threshold */
417 #define EN_REFTRIP0 (1 << 0) /* Link A Alignment Trip */
418 
419 /*
420  * REG_IRQ_ENABLE3
421  */
422 #define EN_PAERR1 (1 << 7) /* Link B PA Error */
423 #define EN_BIST_DONE1 (1 << 6) /* Link B BIST done */
424 #define EN_BLNKDONE1 (1 << 5) /* Link B Blanking done */
425 #define EN_REFNCOCLR1 (1 << 4) /* Link B Nco Clear Tripped */
426 #define EN_REFLOCK1 (1 << 3) /* Link B Alignment Locked */
427 #define EN_REFROTA1 (1 << 2) /* Link B Alignment Rotate */
428 #define EN_REFWLIM1 (1 << 1) /* Link B Over/Under Threshold */
429 #define EN_REFTRIP1 (1 << 0) /* Link B Alignment Trip */
430 
431 /*
432  * REG_IRQ_STATUS0
433  */
434 #define IRQ_CALPASS (1 << 7) /* Calib PASS detection */
435 #define IRQ_CALFAIL (1 << 6) /* Calib FAIL detection */
436 #define IRQ_DACPLLLOST (1 << 5) /* DAC PLL Lost */
437 #define IRQ_DACPLLLOCK (1 << 4) /* DAC PLL Lock */
438 #define IRQ_SERPLLLOST (1 << 3) /* Serdes PLL Lost */
439 #define IRQ_SERPLLLOCK (1 << 2) /* Serdes PLL Lock */
440 #define IRQ_LANEFIFOERR (1 << 1) /* Lane Fifo Error */
441 #define IRQ_DRDLFIFOERR (1 << 0) /* DRDL Fifo Error */
442 
443 /*
444  * REG_IRQ_STATUS1
445  */
446 #define IRQ_PARMBAD (1 << 7) /* BAD Parameter interrupt */
447 #define IRQ_PRBSQ1 (1 << 3) /* PRBS data check error DAC 1 imag */
448 #define IRQ_PRBSI1 (1 << 2) /* PRBS data check error DAC 1 real */
449 #define IRQ_PRBSQ0 (1 << 1) /* PRBS data check error DAC 0 imag */
450 #define IRQ_PRBSI0 (1 << 0) /* PRBS data check error DAC 0 real */
451 
452 /*
453  * REG_IRQ_STATUS2
454  */
455 #define IRQ_PAERR0 (1 << 7) /* Link A PA Error */
456 #define IRQ_BIST_DONE0 (1 << 6) /* Link A BIST done */
457 #define IRQ_BLNKDONE0 (1 << 5) /* Link A Blanking Done */
458 #define IRQ_REFNCOCLR0 (1 << 4) /* Link A Alignment UnderRange */
459 #define IRQ_REFLOCK0 (1 << 3) /* Link A BIST done */
460 #define IRQ_REFROTA0 (1 << 2) /* Link A Alignment Trip */
461 #define IRQ_REFWLIM0 (1 << 1) /* Link A Alignment Lock */
462 #define IRQ_REFTRIP0 (1 << 0) /* Link A Alignment Rotate */
463 
464 /*
465  * REG_IRQ_STATUS3
466  */
467 #define IRQ_PAERR1 (1 << 7) /* Link B PA Error */
468 #define IRQ_BIST_DONE1 (1 << 6) /* Link B BIST done */
469 #define IRQ_BLNKDONE1 (1 << 5) /* Link A Blanking Done */
470 #define IRQ_REFNCOCLR1 (1 << 4) /* Link B Alignment UnderRange */
471 #define IRQ_REFLOCK1 (1 << 3) /* Link B BIST done */
472 #define IRQ_REFROTA1 (1 << 2) /* Link B Alignment Trip */
473 #define IRQ_REFWLIM1 (1 << 1) /* Link B Alignment Lock */
474 #define IRQ_REFTRIP1 (1 << 0) /* Link B Alignment Rotate */
475 
476 /*
477  * REG_JESD_CHECKS
478  */
479 #define ERR_DLYOVER (1 << 5) /* LMFC_Delay > JESD_K parameter */
480 #define ERR_WINLIMIT (1 << 4) /* Unsupported Window Limit */
481 #define ERR_JESDBAD (1 << 3) /* Unsupported M/L/S/F selection */
482 #define ERR_KUNSUPP (1 << 2) /* Unsupported K values */
483 #define ERR_SUBCLASS (1 << 1) /* Unsupported SubClassv value */
484 #define ERR_INTSUPP (1 << 0) /* Unsupported Interpolation rate factor */
485 
486 /*
487  * REG_SYNC_TESTCTRL
488  */
489 #define TARRFAPHAZ (1 << 0) /* Target Polarity of Rf Divider */
490 #define SYNCBYPASS(x) (((x) & 0x3) << 6) /* Sync Bypass handshaking */
491 
492 /*
493  * REG_SYNC_DACDELAY_H
494  */
495 #define DAC_DELAY_H (1 << 0) /* Dac Delay[8] */
496 
497 /*
498  * REG_SYNC_ERRWINDOW
499  */
500 #define ERRWINDOW(x) (((x) & 0x7) << 0) /* Sync Error Window */
501 
502 /*
503  * REG_SYNC_LASTERR_H
504  */
505 #define LASTUNDER (1 << 7) /* Sync Last Error Under Flag */
506 #define LASTOVER (1 << 6) /* Sync Last Error Over Flag */
507 #define LASTERROR_H (1 << 0) /* Sync Last Error[8] and Flags */
508 
509 /*
510  * REG_SYNC_CTRL
511  */
512 #define SYNCENABLE (1 << 7) /* SyncLogic Enable */
513 #define SYNCARM (1 << 6) /* Sync Arming Strobe */
514 #define SYNCCLRSTKY (1 << 5) /* Sync Sticky Bit Clear */
515 #define SYNCCLRLAST (1 << 4) /* Sync Clear LAST_ */
516 #define SYNCMODE(x) (((x) & 0xF) << 0) /* Sync Mode */
517 
518 /*
519  * REG_SYNC_STATUS
520  */
521 #define REFBUSY (1 << 7) /* Sync Machine Busy */
522 #define REFLOCK (1 << 3) /* Sync Alignment Locked */
523 #define REFROTA (1 << 2) /* Sync Rotated */
524 #define REFWLIM (1 << 1) /* Sync Alignment Limit Range */
525 #define REFTRIP (1 << 0) /* Sync Tripped after Arming */
526 
527 /*
528  * REG_SYNC_CURRERR_H
529  */
530 #define CURRUNDER (1 << 7) /* Sync Current Error Under Flag */
531 #define CURROVER (1 << 6) /* Sync Current Error Over Flag */
532 #define CURRERROR_H (1 << 0) /* SyncCurrent Error[8] */
533 
534 /*
535  * REG_ERROR_THERM
536  */
537 #define THRMOLD (1 << 7) /* Error is from a prior sample */
538 #define THRMOVER (1 << 4) /* Error > +WinLimit */
539 #define THRMPOS (1 << 3) /* Sync Current Error Under Flag */
540 #define THRMZERO (1 << 2) /* Error = 0 */
541 #define THRMNEG (1 << 1) /* Error < 0 */
542 #define THRMUNDER (1 << 0) /* Error < -WinLimit */
543 
544 /*
545  * REG_DACGAIN0_1
546  */
547 #define DACGAIN_IM0(x) (((x) & 0x3) << 0) /* I Channel DAC gain <9:8> Dual A */
548 
549 /*
550  * REG_DACGAIN1_1
551  */
552 #define DACGAIN_IM1(x) (((x) & 0x3) << 0) /* Q Channel DAC gain <9:8> Dual A */
553 
554 /*
555  * REG_DACGAIN2_1
556  */
557 #define DACGAIN_IM2(x) (((x) & 0x3) << 0) /* I Channel DAC gain <9:8> Dual B */
558 
559 /*
560  * REG_DACGAIN3_1
561  */
562 #define DACGAIN_IM3(x) (((x) & 0x3) << 0) /* Q Channel DAC gain <9:8> Dual B */
563 
564 /*
565  * REG_PD_DACLDO
566  */
567 #define ENB_DACLDO3 (1 << 7) /* Disable DAC3 ldo */
568 #define ENB_DACLDO2 (1 << 6) /* Disable DAC2 ldo */
569 #define ENB_DACLDO1 (1 << 5) /* Disable DAC1 ldo */
570 #define ENB_DACLDO0 (1 << 4) /* Disable DAC0 ldo */
571 
572 /*
573  * REG_STAT_DACLDO
574  */
575 #define STAT_LDO3 (1 << 3) /* DAC3 LDO status */
576 #define STAT_LDO2 (1 << 2) /* DAC2 LDO status */
577 #define STAT_LDO1 (1 << 1) /* DAC1 LDO status */
578 #define STAT_LDO0 (1 << 0) /* DAC0 LDO status */
579 
580 /*
581  * REG_DECODE_CTRL0
582  */
583 #define SHUFFLE_MSB0 (1 << 2) /* MSB shuffling mode */
584 #define SHUFFLE_ISB0 (1 << 1) /* ISB shuffling mode */
585 
586 /*
587  * REG_DECODE_CTRL1
588  */
589 #define SHUFFLE_MSB1 (1 << 2) /* MSB shuffling mode */
590 #define SHUFFLE_ISB1 (1 << 1) /* ISB shuffling mode */
591 
592 /*
593  * REG_DECODE_CTRL2
594  */
595 #define SHUFFLE_MSB2 (1 << 2) /* MSB shuffling mod */
596 #define SHUFFLE_ISB2 (1 << 1) /* ISB shuffling mode */
597 
598 /*
599  * REG_DECODE_CTRL3
600  */
601 #define SHUFFLE_MSB3 (1 << 2) /* MSB shuffling mode */
602 #define SHUFFLE_ISB3 (1 << 1) /* ISB shuffling mode */
603 
604 /*
605  * REG_NCO_CLRMODE
606  */
607 #define NCOCLRARM (1 << 7) /* Arm NCO Clear */
608 #define NCOCLRMTCH (1 << 5) /* NCO Clear Data Match */
609 #define NCOCLRPASS (1 << 4) /* NCO Clear PASSed */
610 #define NCOCLRFAIL (1 << 3) /* NCO Clear FAILed */
611 #define NCOCLRMODE(x) (((x) & 0x3) << 0) /* NCO Clear Mode */
612 
613 /*
614  * REG_PA_THRES1
615  */
616 #define PA_THRESH_MSB(x) (((x) & 0x1F) << 0) /* Average power threshold for comparison. */
617 
618 /*
619  * REG_PA_AVG_TIME
620  */
621 #define PA_ENABLE (1 << 7) /* 1 = Enable average power calculation and error detection */
622 #define PA_BUS_SWAP (1 << 6) /* Swap channelA or channelB databus for power calculation */
623 #define PA_AVG_TIME(x) (((x) & 0xF) << 0) /* Set power average time */
624 
625 /*
626  * REG_PA_POWER1
627  */
628 #define PA_POWER_MSB(x) (((x) & 0x1F) << 0) /* average power bus = I^2+Q^2 (I/Q use 6MSB of databus) */
629 
630 /*
631  * REG_CLKCFG0
632  */
633 #define PD_CLK01 (1 << 7) /* Powerdown clock for Dual A */
634 #define PD_CLK23 (1 << 6) /* Powerdown clock for Dual B */
635 #define PD_CLK_DIG (1 << 5) /* Powerdown clocks to all DACs */
636 #define PD_PCLK (1 << 4) /* Cal reference/Serdes PLL clock powerdown */
637 #define PD_CLK_REC (1 << 3) /* Clock reciever powerdown */
638 
639 /*
640  * REG_SYSREF_ACTRL0
641  */
642 #define PD_SYSREF (1 << 4) /* Powerdown SYSREF buffer */
643 #define HYS_ON (1 << 3) /* Hysteresis enabled */
644 #define SYSREF_RISE (1 << 2) /* Use SYSREF rising edge */
645 #define HYS_CNTRL1(x) (((x) & 0x3) << 0) /* Hysteresis control bits <9:8> */
646 
647 /*
648  * REG_DACPLLCNTRL
649  */
650 #define SYNTH_RECAL (1 << 7) /* Recalibrate VCO Band */
651 #define ENABLE_SYNTH (1 << 4) /* Synthesizer Enable */
652 
653 /*
654  * REG_DACPLLSTATUS
655  */
656 #define CP_CAL_VALID (1 << 5) /* Charge Pump Cal Valid */
657 #define RFPLL_LOCK (1 << 1) /* PLL Lock bit */
658 
659 /*
660  * REG_DACLOOPFILT1
661  */
662 #define LF_C2_WORD(x) (((x) & 0xF) << 4) /* C2 control word */
663 #define LF_C1_WORD(x) (((x) & 0xF) << 0) /* C1 control word */
664 
665 /*
666  * REG_DACLOOPFILT2
667  */
668 #define LF_R1_WORD(x) (((x) & 0xF) << 4) /* R1 control word */
669 #define LF_C3_WORD(x) (((x) & 0xF) << 0) /* C3 control word */
670 
671 /*
672  * REG_DACLOOPFILT3
673  */
674 #define LF_BYPASS_R3 (1 << 7) /* Bypass R3 res */
675 #define LF_BYPASS_R1 (1 << 6) /* Bypass R1 res */
676 #define LF_BYPASS_C2 (1 << 5) /* Bypass C2 cap */
677 #define LF_BYPASS_C1 (1 << 4) /* Bypass C1 cap */
678 #define LF_R3_WORD(x) (((x) & 0xF) << 0) /* R3 Control Word */
679 
680 /*
681  * REG_DACCPCNTRL
682  */
683 #define CP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current Control */
684 
685 /*
686  * REG_DACLOGENCNTRL
687  */
688 #define LO_DIV_MODE(x) (((x) & 0x3) << 0) /* Logen_Division */
689 
690 /*
691  * REG_DACLDOCNTRL1
692  */
693 #define REF_DIVRATE(x) (((x) & 0x7) << 0) /* Reference Clock Division Ratio */
694 
695 /*
696  * REG_CAL_DAC_ERR
697  */
698 #define INIT_SWEEP_ERR_DAC (1 << 1) /* Initial setup sweep failed */
699 #define MSB_SWEEP_ERR_DAC (1 << 0) /* MSB sweep failed */
700 
701 /*
702  * REG_CAL_MSB_THRES
703  */
704 #define CAL_MSB_TAC(x) (((x) & 0x7) << 0) /* MSB sweep TAC */
705 
706 /*
707  * REG_CAL_CTRL_GLOBAL
708  */
709 #define CAL_START_GL (1 << 1) /* Global Calibration start */
710 #define CAL_EN_GL (1 << 0) /* Global Calibration enable */
711 
712 /*
713  * REG_CAL_MSBHILVL
714  */
715 #define CAL_MSBLVLHI(x) (((x) & 0x3F) << 0) /* High level limit for msb sweep average */
716 
717 /*
718  * REG_CAL_MSBLOLVL
719  */
720 #define CAL_MSBLVLLO(x) (((x) & 0x3F) << 0) /* Low level limit for msb sweep average */
721 
722 /*
723  * REG_CAL_THRESH
724  */
725 #define CAL_LTAC_THRES(x) (((x) & 0x7) << 3) /* Long TAC threshold */
726 #define CAL_TAC_THRES(x) (((x) & 0x7) << 0) /* TAC threshold */
727 
728 /*
729  * REG_CAL_AVG_CNT
730  */
731 #define MSB_GLOBAL_SUBAVG(x) (((x) & 0x3) << 6) /* Local Averages for MSB in Global Calibration */
732 #define GLOBAL_AVG_CNT(x) (((x) & 0x7) << 3) /* Global avg Terminal count */
733 #define LOCAL_AVRG_CNT(x) (((x) & 0x7) << 0) /* Local avg terminal count */
734 
735 /*
736  * REG_CAL_CLKDIV
737  */
738 #define CAL_CLKDIV(x) (((x) & 0xF) << 0) /* Calibration clock divider */
739 
740 /*
741  * REG_CAL_INDX
742  */
743 #define CAL_INDX(x) (((x) & 0xF) << 0) /* DAC Calibration Index paging bits */
744 
745 /*
746  * REG_CAL_CTRL
747  */
748 #define CAL_FIN (1 << 7) /* Calibration finished */
749 #define CAL_ACTIVE (1 << 6) /* Calibration active */
750 #define CAL_ERRHI (1 << 5) /* SAR data error: too hi */
751 #define CAL_ERRLO (1 << 4) /* SAR data error: too lo */
752 #define CAL_TXDACBYDAC (1 << 3) /* Calibration of TXDAC by TXDAC */
753 #define CAL_START (1 << 1) /* Calibration start */
754 #define CAL_EN (1 << 0) /* Calibration enable */
755 
756 /*
757  * REG_CAL_ADDR
758  */
759 #define CAL_ADDR(x) (((x) & 0x3F) << 0) /* Calibration DAC address */
760 
761 /*
762  * REG_CAL_DATA
763  */
764 #define CAL_DATA(x) (((x) & 0x3F) << 0) /* Calibration DAC Coefficient Data */
765 
766 /*
767  * REG_CAL_UPDATE
768  */
769 #define CAL_UPDATE (1 << 7) /* Calibration DAC Coefficient Update */
770 
771 /*
772  * REG_DATA_FORMAT
773  */
774 #define BINARY_FORMAT (1 << 7) /* Binary or 2's complementary format on DATA bus */
775 
776 /*
777  * REG_DATAPATH_CTRL
778  */
779 #define INVSINC_ENABLE (1 << 7) /* 1 = Enable inver sinc filter */
780 #define DIG_GAIN_ENABLE (1 << 5) /* 1 = Enable digital gain */
781 #define PHASE_ADJ_ENABLE (1 << 4) /* 1 = Enable phase compensation */
782 #define SEL_SIDEBAND (1 << 1) /* 1 = Select upper or lower sideband from modulation result */
783 #define I_TO_Q (1 << 0) /* 1 = send I datapath into Q DAC */
784 #define MODULATION_TYPE(x) (((x) & 0x3) << 2) /* selects type of modulation operation */
785 
786 /*
787  * REG_INTERP_MODE
788  */
789 #define INTERP_MODE(x) (((x) & 0x7) << 0) /* Interpolation Mode */
790 
791 /*
792  * REG_NCO_FTW_UPDATE
793  */
794 #define FTW_UPDATE_ACK (1 << 1) /* Frequency Tuning Word Update Acknowledge */
795 #define FTW_UPDATE_REQ (1 << 0) /* Frequency Tuning Word Update Request from SPI */
796 
797 /*
798  * REG_TXEN_FUNC
799  */
800 #define TX_DIG_CLK_PD (1 << 0) /* 1 = Digital clocks will be shut down when Tx_enable pin is low. */
801 
802 /*
803  * REG_TXEN_SM_0
804  */
805 #define GP_PA_ON_INVERT (1 << 2) /* External Modulator polarity invert */
806 #define GP_PA_CTRL (1 << 1) /* External PA control */
807 #define TXEN_SM_EN (1 << 0) /* Enable TXEN state machine */
808 #define PA_FALL(x) (((x) & 0x3) << 6) /* PA fall control */
809 #define PA_RISE(x) (((x) & 0x3) << 4) /* PA rises control */
810 
811 /*
812  * REG_TXEN_SM_1
813  */
814 #define DIG_FALL(x) (((x) & 0x3) << 6) /* DIG_FALL */
815 #define DIG_RISE(x) (((x) & 0x3) << 4) /* DIG_RISE */
816 #define DAC_FALL(x) (((x) & 0x3) << 2) /* DAC_FALL */
817 #define DAC_RISE(x) (((x) & 0x3) << 0) /* DAC_RISE */
818 
819 /*
820  * REG_DACOUT_ON_DOWN
821  */
822 #define DACOUT_SHUTDOWN (1 << 1) /* Shut down DAC output. 1 means DAC get shut down manually. */
823 #define DACOUT_ON_TRIGGER (1 << 0) /* Turn on DAC output manually. Self clear signal. */
824 
825 /*
826  * REG_DACOFF
827  */
828 #define PROTECT_MODE (1 << 7) /* PROTECT_MODE */
829 #define DACOFF_AVG_PW (1 << 0) /* DACOFF_AVG_PW */
830 
831 /*
832  * REG_DIE_TEMP_CTRL0
833  */
834 #define ADC_TESTMODE (1 << 7) /* ADC_TESTMODE */
835 #define AUXADC_ENABLE (1 << 0) /* AUXADC_ENABLE */
836 #define FS_CURRENT(x) (((x) & 0x7) << 4) /* FS_CURRENT */
837 #define REF_CURRENT(x) (((x) & 0x7) << 1) /* REF_CURRENT */
838 
839 /*
840  * REG_DIE_TEMP_CTRL1
841  */
842 #define SELECT_CLKDIG (1 << 3) /* SELECT_CLKDIG */
843 #define EN_DIV2 (1 << 2) /* EN_DIV2 */
844 #define INCAP_CTRL(x) (((x) & 0x3) << 0) /* INCAP_CTRL */
845 
846 /*
847  * REG_DIE_TEMP_UPDATE
848  */
849 #define DIE_TEMP_UPDATE (1 << 0) /* Die temperature update */
850 
851 /*
852  * REG_DC_OFFSET_CTRL
853  */
854 #define DISABLE_NOISE (1 << 1) /* DISABLE_NOISE */
855 #define DC_OFFSET_ON (1 << 0) /* DC_OFFSET_ON */
856 
857 /*
858  * REG_IPATH_DC_OFFSET_2PART
859  */
860 #define IPATH_DC_OFFSET_2PART(x) (((x) & 0x1F) << 0) /* second part of DC Offset value for I path */
861 
862 /*
863  * REG_QPATH_DC_OFFSET_2PART
864  */
865 #define QPATH_DC_OFFSET_2PART(x) (((x) & 0x1F) << 0) /* second part of DC Offset value for Q path */
866 
867 /*
868  * REG_IDAC_DIG_GAIN1
869  */
870 #define IDAC_DIG_GAIN1(x) (((x) & 0xF) << 0) /* MSB of I DAC digital gain */
871 
872 /*
873  * REG_QDAC_DIG_GAIN1
874  */
875 #define QDAC_DIG_GAIN1(x) (((x) & 0xF) << 0) /* MSB of Q DAC digital gain */
876 
877 /*
878  * REG_GAIN_RAMP_UP_STP1
879  */
880 #define GAIN_RAMP_UP_STP1(x) (((x) & 0xF) << 0) /* MSB of digital gain rises */
881 
882 /*
883  * REG_GAIN_RAMP_DOWN_STP1
884  */
885 #define GAIN_RAMP_DOWN_STP1(x) (((x) & 0xF) << 0) /* MSB of digital gain drops */
886 
887 /*
888  * REG_BLSM_CTRL
889  */
890 #define RESET_BLSM (1 << 7) /* Soft rest to the new Blanking SM */
891 #define EN_FORCE_GAIN_SOFT_OFF (1 << 4) /* Enable forcing gan_soft_off from SPI */
892 #define GAIN_SOFT_OFF (1 << 3) /* gain_soft_off forced value */
893 #define GAIN_SOFT_ON (1 << 2) /* gain_soft_on forced value */
894 #define EN_FORCE_GAIN_SOFT_ON (1 << 1) /* Force the gain_soft_on from SPI */
895 
896 /*
897  * REG_BLSM_STAT
898  */
899 #define SOFT_OFF_DONE (1 << 5) /* Blanking SoftOff Enable */
900 #define SOFT_ON_DONE (1 << 4) /* Blanking SoftOn Done */
901 #define GAIN_SOFT_OFF_RB (1 << 3) /* gain soft off readback */
902 #define GAIN_SOFT_ON_RB (1 << 2) /* gain soft on readback */
903 #define SOFT_OFF_EN_RB (1 << 1) /* Blanking SM soft Off read back */
904 #define SOFT_ON_EN_RB (1 << 0) /* Blanking SM soft On read back */
905 #define SOFTBLANKRB(x) (((x) & 0x3) << 6) /* Blanking State */
906 
907 /*
908  * REG_PRBS
909  */
910 #define PRBS_GOOD_Q (1 << 7) /* Good data indicator imaginary channel */
911 #define PRBS_GOOD_I (1 << 6) /* Good data indicator real channel */
912 #define PRBS_INV_Q (1 << 4) /* Data Inversion imaginary channel */
913 #define PRBS_INV_I (1 << 3) /* Data Inversion real channel */
914 #define PRBS_MODE (1 << 2) /* Polynomial Select */
915 #define PRBS_RESET (1 << 1) /* Reset Error Counters */
916 #define PRBS_EN (1 << 0) /* Enable PRBS Checker */
917 
918 /*
919  * REG_DACPLLT5
920  */
921 #define VCO_VAR(x) (((x) & 0xF) << 0) /* Varactor KVO setting */
922 
923 /*
924  * REG_DACPLLTB
925  */
926 #define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias control */
927 
928 /*
929  * REG_DACPLLTD
930  */
931 #define VCO_CAL_REF_MON (1 << 3) /* Sent control voltage to outside world */
932 #define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* TempCo for cal ref */
933 
934 /*
935  * REG_DACPLLT17
936  */
937 #define VCO_VAR_REF_TCF(x) (((x) & 0x7) << 4) /* Varactor Reference TempCo */
938 #define VCO_VAR_OFF(x) (((x) & 0xF) << 0) /* Varactor Offset */
939 
940 /*
941  * REG_SPISTRENGTH
942  */
943 #define SPIDRV(x) (((x) & 0xF) << 0) /* Slew and drive strength for cmos interface */
944 
945 /*
946  * REG_CLK_TEST
947  */
948 #define DUTYCYCLEON (1 << 0) /* Clock Duty Cycle Control On */
949 
950 /*
951  * REG_ATEST_VOLTS
952  */
953 #define ATEST_EN (1 << 0) /* Enable Analog Test Mode */
954 #define ATEST_TOPVSEL(x) (((x) & 0x3) << 5) /* Which source at analog top to use */
955 #define ATEST_DACSEL(x) (((x) & 0x3) << 3) /* DAC from which to get voltage */
956 #define ATEST_VSEL(x) (((x) & 0x3) << 1) /* DAC Voltage to Select */
957 
958 /*
959  * REG_ASPI_CLKSRC
960  */
961 #define EN_CLKDIV (1 << 3) /* Enable the fdac/8 clock path to generate PD timing clock */
962 #define ASPI_OSC_RATE (1 << 2) /* Aspi Oscillator Rate */
963 #define ASPI_CLK_SRC (1 << 1) /* Choose Aspi Clock Source */
964 #define EN_ASPI_OSC (1 << 0) /* Enable Aspi Oscillator clock */
965 
966 /*
967  * REG_MASTER_PD
968  */
969 #define SPI_PD_MASTER (1 << 0)
970 
971 /*
972  * REG_GENERIC_PD
973  */
974 #define SPI_SYNC1_PD (1 << 1)
975 #define SPI_SYNC2_PD (1 << 0)
976 
977 /*
978  * REG_CDR_OPERATING_MODE_REG_0
979  */
980 #define SPI_ENHALFRATE (1 << 5)
981 #define SPI_DIVISION_RATE(x) (((x) & 0x3) << 1)
982 
983 /*
984  * REG_EQ_CONFIG_PHY_0_1
985  */
986 #define SPI_EQ_CONFIG1(x) (((x) & 0xF) << 4)
987 #define SPI_EQ_CONFIG0(x) (((x) & 0xF) << 0)
988 
989 /*
990  * REG_EQ_CONFIG_PHY_2_3
991  */
992 #define SPI_EQ_CONFIG3(x) (((x) & 0xF) << 4)
993 #define SPI_EQ_CONFIG2(x) (((x) & 0xF) << 0)
994 
995 /*
996  * REG_EQ_CONFIG_PHY_4_5
997  */
998 #define SPI_EQ_CONFIG5(x) (((x) & 0xF) << 4)
999 #define SPI_EQ_CONFIG4(x) (((x) & 0xF) << 0)
1000 
1001 /*
1002  * REG_EQ_CONFIG_PHY_6_7
1003  */
1004 #define SPI_EQ_CONFIG7(x) (((x) & 0xF) << 4)
1005 #define SPI_EQ_CONFIG6(x) (((x) & 0xF) << 0)
1006 
1007 /*
1008  * REG_EQ_BIAS_REG
1009  */
1010 #define SPI_EQ_EXTRA_SPI_LSBITS(x) (((x) & 0x3) << 6)
1011 #define SPI_EQ_BIASPTAT(x) (((x) & 0x7) << 3)
1012 #define SPI_EQ_BIASPLY(x) (((x) & 0x7) << 0)
1013 
1014 /*
1015  * REG_SYNTH_ENABLE_CNTRL
1016  */
1017 #define SPI_RECAL_SYNTH (1 << 2)
1018 #define SPI_ENABLE_SYNTH (1 << 0)
1019 
1020 /*
1021  * REG_PLL_STATUS
1022  */
1023 #define SPI_CP_CAL_VALID_RB (1 << 3)
1024 #define SPI_PLL_LOCK_RB (1 << 0)
1025 
1026 /*
1027  * REG_REF_CLK_DIVIDER_LDO
1028  */
1029 #define SPI_CDR_OVERSAMP(x) (((x) & 0x3) << 0)
1030 
1031 /*
1032  * REG_TERM_BLK1_CTRLREG0
1033  */
1034 #define SPI_I_TUNE_R_CAL_TERMBLK1 (1 << 0)
1035 
1036 /*
1037  * REG_TERM_BLK2_CTRLREG0
1038  */
1039 #define SPI_I_TUNE_R_CAL_TERMBLK2 (1 << 0)
1040 
1041 /*
1042  * REG_GENERAL_JRX_CTRL_0
1043  */
1044 #define CHECKSUM_MODE (1 << 6) /* Checksum mode */
1045 #define LINK_MODE (1 << 3) /* Link mode */
1046 #define SEL_REG_MAP_1 (1 << 2) /* Link register map selection */
1047 #define LINK_EN(x) (((x) & 0x3) << 0) /* Link enable */
1048 
1049 /*
1050  * REG_GENERAL_JRX_CTRL_1
1051  */
1052 #define SUBCLASSV_LOCAL(x) (((x) & 0x7) << 0) /* JESD204B subclass */
1053 
1054 /*
1055  * REG_DYN_LINK_LATENCY_0
1056  */
1057 #define DYN_LINK_LATENCY_0(x) (((x) & 0x1F) << 0) /* Dynamic link latency: Link 0 */
1058 
1059 /*
1060  * REG_DYN_LINK_LATENCY_1
1061  */
1062 #define DYN_LINK_LATENCY_1(x) (((x) & 0x1F) << 0) /* Dynamic link latency: Link 1 */
1063 
1064 /*
1065  * REG_LMFC_DELAY_0
1066  */
1067 #define LMFC_DELAY_0(x) (((x) & 0x1F) << 0) /* LMFC delay: Link 0 */
1068 
1069 /*
1070  * REG_LMFC_DELAY_1
1071  */
1072 #define LMFC_DELAY_1(x) (((x) & 0x1F) << 0) /* LMFC delay: Link 1 */
1073 
1074 /*
1075  * REG_LMFC_VAR_0
1076  */
1077 #define LMFC_VAR_0(x) (((x) & 0x1F) << 0) /* Location in RX LMFC where JESD words are read out from buffer */
1078 
1079 /*
1080  * REG_LMFC_VAR_1
1081  */
1082 #define LMFC_VAR_1(x) (((x) & 0x1F) << 0) /* Location in RX LMFC where JESD words are read out from buffer */
1083 
1084 /*
1085  * REG_XBAR_LN_0_1
1086  */
1087 #define SRC_LANE1(x) (((x) & 0x7) << 3) /* Logic Lane 1 source */
1088 #define SRC_LANE0(x) (((x) & 0x7) << 0) /* Logic Lane 0 source */
1089 
1090 /*
1091  * REG_XBAR_LN_2_3
1092  */
1093 #define SRC_LANE3(x) (((x) & 0x7) << 3) /* Logic Lane 3 source */
1094 #define SRC_LANE2(x) (((x) & 0x7) << 0) /* Logic Lane 2 source */
1095 
1096 /*
1097  * REG_XBAR_LN_4_5
1098  */
1099 #define SRC_LANE5(x) (((x) & 0x7) << 3) /* Logic Lane 5 source */
1100 #define SRC_LANE4(x) (((x) & 0x7) << 0) /* Logic Lane 4 source */
1101 
1102 /*
1103  * REG_XBAR_LN_6_7
1104  */
1105 #define SRC_LANE7(x) (((x) & 0x7) << 3) /* Logic Lane 7 source */
1106 #define SRC_LANE6(x) (((x) & 0x7) << 0) /* Logic Lane 6 source */
1107 
1108 /*
1109  * REG_FIFO_STATUS_REG_2
1110  */
1111 #define DRDL_FIFO_EMPTY (1 << 1) /* Deterministic latency (DRDL) FIFO is between JESD204B receiver and DAC2 and DAC3 */
1112 #define DRDL_FIFO_FULL (1 << 0) /* DRDL FIFO is between JESD204B receiver and DAC2 and DAC3 */
1113 
1114 /*
1115  * REG_SYNCB_GEN_0
1116  */
1117 #define EOMF_MASK_1 (1 << 3) /* EOMF_MASK_1 */
1118 #define EOMF_MASK_0 (1 << 2) /* EOMF_MASK_0 */
1119 #define EOF_MASK_1 (1 << 1) /* Mask EOF from QBD_1 */
1120 #define EOF_MASK_0 (1 << 0) /* Mask EOF from QBD_0 */
1121 
1122 /*
1123  * REG_SYNCB_GEN_1
1124  */
1125 #define SYNCB_ERR_DUR(x) (((x) & 0xF) << 4) /* Duration of SYNCOUT low for the purpose of error reporting */
1126 #define SYNCB_SYNCREQ_DUR(x) (((x) & 0xF) << 0) /* Duration of SYNCOUT low for purpose of synchronization request */
1127 
1128 /*
1129  * REG_PHY_PRBS_TEST_CTRL
1130  */
1131 #define PHY_TEST_START (1 << 1) /* PHY PRBS test start */
1132 #define PHY_TEST_RESET (1 << 0) /* PHY PRBS test reset */
1133 #define PHY_SRC_ERR_CNT(x) (((x) & 0x7) << 4) /* PHY error count source */
1134 #define PHY_PRBS_PAT_SEL(x) (((x) & 0x3) << 2) /* PHY PRBS pattern select */
1135 
1136 /*
1137  * REG_SHORT_TPL_TEST_0
1138  */
1139 #define SHORT_TPL_TEST_RESET (1 << 1) /* Short transport layer test reset */
1140 #define SHORT_TPL_TEST_EN (1 << 0) /* Short transport layer test enable */
1141 #define SHORT_TPL_SP_SEL(x) (((x) & 0x3) << 4) /* Short transport layer sample select */
1142 #define SHORT_TPL_M_SEL(x) (((x) & 0x3) << 2) /* Short transport layer test DAC select */
1143 
1144 /*
1145  * REG_SHORT_TPL_TEST_3
1146  */
1147 #define SHORT_TPL_FAIL (1 << 0) /* Short transport layer test fail */
1148 
1149 /*
1150  * REG_BID_REG
1151  */
1152 #define ADJCNT_RD(x) (((x) & 0xF) << 4)
1153 #define BID_RD(x) (((x) & 0xF) << 0)
1154 
1155 /*
1156  * REG_LID0_REG
1157  */
1158 #define ADJDIR_RD (1 << 6)
1159 #define PHADJ_RD (1 << 5)
1160 #define LID0_RD(x) (((x) & 0x1F) << 0)
1161 
1162 /*
1163  * REG_SCR_L_REG
1164  */
1165 #define SCR_RD (1 << 7)
1166 #define L_RD(x) (((x) & 0x1F) << 0)
1167 
1168 /*
1169  * REG_K_REG
1170  */
1171 #define K_RD(x) (((x) & 0x1F) << 0)
1172 
1173 /*
1174  * REG_CS_N_REG
1175  */
1176 #define CS_RD(x) (((x) & 0x3) << 6)
1177 #define N_RD(x) (((x) & 0x1F) << 0)
1178 
1179 /*
1180  * REG_NP_REG
1181  */
1182 #define SUBCLASSV_RD(x) (((x) & 0x7) << 5)
1183 #define NP_RD(x) (((x) & 0x1F) << 0)
1184 
1185 /*
1186  * REG_S_REG
1187  */
1188 #define JESDV_RD(x) (((x) & 0x7) << 5)
1189 #define S_RD(x) (((x) & 0x1F) << 0)
1190 
1191 /*
1192  * REG_HD_CF_REG
1193  */
1194 #define HD_RD (1 << 7)
1195 #define CF_RD(x) (((x) & 0x1F) << 0)
1196 
1197 /*
1198  * REG_LID1_REG
1199  */
1200 #define LID1_RD(x) (((x) & 0x1F) << 0)
1201 
1202 /*
1203  * REG_LID2_REG
1204  */
1205 #define LID2_RD(x) (((x) & 0x1F) << 0)
1206 
1207 /*
1208  * REG_LID3_REG
1209  */
1210 #define LID3_RD(x) (((x) & 0x1F) << 0)
1211 
1212 /*
1213  * REG_LID4_REG
1214  */
1215 #define LID4_RD(x) (((x) & 0x1F) << 0)
1216 
1217 /*
1218  * REG_LID5_REG
1219  */
1220 #define LID5_RD(x) (((x) & 0x1F) << 0)
1221 
1222 /*
1223  * REG_LID6_REG
1224  */
1225 #define LID6_RD(x) (((x) & 0x1F) << 0)
1226 
1227 /*
1228  * REG_LID7_REG
1229  */
1230 #define LID7_RD(x) (((x) & 0x1F) << 0)
1231 
1232 /*
1233  * REG_ILS_BID
1234  */
1235 #define ADJCNT(x) (((x) & 0xF) << 4)
1236 #define BID(x) (((x) & 0xF) << 0)
1237 
1238 /*
1239  * REG_ILS_LID0
1240  */
1241 #define ADJDIR (1 << 6)
1242 #define PHADJ (1 << 5)
1243 #define LID0(x) (((x) & 0x1F) << 0)
1244 
1245 /*
1246  * REG_ILS_SCR_L
1247  */
1248 #define SCR (1 << 7)
1249 #define L(x) (((x) & 0x1F) << 0)
1250 
1251 /*
1252  * REG_ILS_K
1253  */
1254 #define K(x) (((x) & 0x1F) << 0)
1255 
1256 /*
1257  * REG_ILS_CS_N
1258  */
1259 #define CS(x) (((x) & 0x3) << 6)
1260 #define N(x) (((x) & 0x1F) << 0)
1261 
1262 /*
1263  * REG_ILS_NP
1264  */
1265 #define SUBCLASSV(x) (((x) & 0x7) << 5)
1266 #define NP(x) (((x) & 0x1F) << 0)
1267 
1268 /*
1269  * REG_ILS_S
1270  */
1271 #define JESDV(x) (((x) & 0x7) << 5)
1272 #define S(x) (((x) & 0x1F) << 0)
1273 
1274 /*
1275  * REG_ILS_HD_CF
1276  */
1277 #define HD (1 << 7)
1278 #define CF(x) (((x) & 0x1F) << 0)
1279 
1280 /*
1281  * REG_ERRCNTRMON
1282  */
1283 #define LANESEL(x) (((x) & 0x7) << 4)
1284 #define CNTRSEL(x) (((x) & 0x3) << 0)
1285 
1286 /*
1287  * REG_BADDISPARITY
1288  */
1289 #define RST_IRQ_DIS (1 << 7)
1290 #define DIS_ERR_CNTR_DIS (1 << 6)
1291 #define RST_ERR_CNTR_DIS (1 << 5)
1292 #define LANE_ADDR_DIS(x) (((x) & 0x7) << 0)
1293 
1294 /*
1295  * REG_NITDISPARITY
1296  */
1297 #define RST_IRQ_NIT (1 << 7)
1298 #define DIS_ERR_CNTR_NIT (1 << 6)
1299 #define RST_ERR_CNTR_NIT (1 << 5)
1300 #define LANE_ADDR_NIT(x) (((x) & 0x7) << 0)
1301 
1302 /*
1303  * REG_UNEXPECTEDKCHAR
1304  */
1305 #define RST_IRQ_K (1 << 7)
1306 #define DIS_ERR_CNTR_K (1 << 6)
1307 #define RST_ERR_CNTR_K (1 << 5)
1308 #define LANE_ADDR_K(x) (((x) & 0x7) << 0)
1309 
1310 /*
1311  * REG_CTRLREG2
1312  */
1313 #define ILAS_MODE (1 << 7)
1314 #define REPDATATEST (1 << 5)
1315 #define QUETESTERR (1 << 4)
1316 #define AUTO_ECNTR_RST (1 << 3)
1317 
1318 /*
1319  * REG_IRQVECTOR
1320  */
1321 #define BADDIS_FLAG_OR_MASK (1 << 7)
1322 #define NITD_FLAG_OR_MASK (1 << 6)
1323 #define UEKC_FLAG_OR_MASK (1 << 5)
1324 #define INITIALLANESYNC_FLAG_OR_MASK (1 << 3)
1325 #define BADCHECKSUM_FLAG_OR_MASK (1 << 2)
1326 #define CODEGRPSYNC_FLAG_OR_MASK (1 << 0)
1327 
1328 /*
1329  * REG_SYNCASSERTIONMASK
1330  */
1331 #define BAD_DIS_S (1 << 7)
1332 #define NIT_DIS_S (1 << 6)
1333 #define UNEX_K_S (1 << 5)
1334 #define CMM_FLAG_OR_MASK (1 << 4)
1335 #define CMM_ENABLE (1 << 3)
1336 
1337 
1338 #define AD9152_MAX_DAC_RATE 2000000000UL
1339 #define AD9152_CHIP_ID 0x52
1340 #define AD9152_TEST_PN15 0x01
1341 #define AD9152_TEST_PN7 0x00
1342 
1343 /******************************************************************************/
1344 /*************************** Types Declarations *******************************/
1345 /******************************************************************************/
1346 
1348  /* SPI */
1350  /* Device Settings */
1351  uint32_t stpl_samples[2][4];
1352  uint32_t interpolation;
1353  uint32_t prbs_type;
1354  uint32_t lane_rate_kbps;
1355 };
1356 
1357 struct ad9152_dev {
1358  /* SPI */
1360 };
1361 
1362 /******************************************************************************/
1363 /************************ Functions Declarations ******************************/
1364 /******************************************************************************/
1365 
1366 int32_t ad9152_spi_read(struct ad9152_dev *dev,
1367  uint16_t reg_addr,
1368  uint8_t *reg_data);
1369 int32_t ad9152_spi_write(struct ad9152_dev *dev,
1370  uint16_t reg_addr,
1371  uint8_t reg_data);
1372 int32_t ad9152_setup(struct ad9152_dev **device,
1373  struct ad9152_init_param init_param);
1374 int32_t ad9152_datapath_prbs_test(struct ad9152_dev *dev,
1375  struct ad9152_init_param init_param);
1376 int32_t ad9152_short_pattern_test(struct ad9152_dev *dev,
1377  struct ad9152_init_param init_param);
1378 int32_t ad9152_status(struct ad9152_dev *dev);
1379 int32_t ad9152_remove(struct ad9152_dev *dev);
1380 
1381 #endif
ad9152_dev
Definition: ad9152.h:1357
ad9152_datapath_prbs_test
int32_t ad9152_datapath_prbs_test(struct ad9152_dev *dev, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:261
ad9152_init_param
Definition: ad9152.h:1347
ad9152_init_param::lane_rate_kbps
uint32_t lane_rate_kbps
Definition: ad9152.h:1354
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
REG_PRBS_ERROR_I
#define REG_PRBS_ERROR_I
Definition: ad9144.h:188
REG_GOODCHKSUMFLG
#define REG_GOODCHKSUMFLG
Definition: ad9144.h:318
SOFTRESET_M
#define SOFTRESET_M
Definition: ad9144.h:331
no_os_spi.h
Header file of SPI Interface.
ad9152_spi_read
int32_t ad9152_spi_read(struct ad9152_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9152_spi_read
Definition: ad9152.c:50
no_os_delay.h
Header file of Delay functions.
device
Definition: ad9361_util.h:75
REG_FRAMESYNCFLG
#define REG_FRAMESYNCFLG
Definition: ad9144.h:317
ad9152_setup
int32_t ad9152_setup(struct ad9152_dev **device, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:95
ad9152_setup
int32_t ad9152_setup(struct ad9152_dev **device, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:95
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
ad9152_init_param::prbs_type
uint32_t prbs_type
Definition: ad9152.h:1353
ad9152_short_pattern_test
int32_t ad9152_short_pattern_test(struct ad9152_dev *dev, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:221
AD9152_CHIP_ID
#define AD9152_CHIP_ID
Definition: ad9152.h:1339
REG_INITLANESYNCFLG
#define REG_INITLANESYNCFLG
Definition: ad9144.h:319
SOFTRESET
#define SOFTRESET
Definition: ad9144.h:338
ad9152_spi_write
int32_t ad9152_spi_write(struct ad9152_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9152_spi_write
Definition: ad9152.c:73
ad9152_dev::spi_desc
no_os_spi_desc * spi_desc
Definition: ad9152.h:1359
ad9152_spi_write
int32_t ad9152_spi_write(struct ad9152_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9152_spi_write
Definition: ad9152.c:73
ad9152_init_param::spi_init
no_os_spi_init_param spi_init
Definition: ad9152.h:1349
REG_SPI_PRODIDL
#define REG_SPI_PRODIDL
Definition: ad9144.h:56
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
ad9152_status
int32_t ad9152_status(struct ad9152_dev *dev)
ad9152_setup
Definition: ad9152.c:301
ad9152_init_param::stpl_samples
uint32_t stpl_samples[2][4]
Definition: ad9152.h:1351
ad9152_datapath_prbs_test
int32_t ad9152_datapath_prbs_test(struct ad9152_dev *dev, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:261
ad9152_remove
int32_t ad9152_remove(struct ad9152_dev *dev)
Free the resources allocated by ad9152_setup().
Definition: ad9152.c:206
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
ad9152.h
Header file of AD9152 Driver.
ad9152_short_pattern_test
int32_t ad9152_short_pattern_test(struct ad9152_dev *dev, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:221
REG_SPI_INTFCONFA
#define REG_SPI_INTFCONFA
Definition: ad9144.h:53
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
REG_CODEGRPSYNCFLG
#define REG_CODEGRPSYNCFLG
Definition: ad9144.h:316
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
ad9152_remove
int32_t ad9152_remove(struct ad9152_dev *dev)
Free the resources allocated by ad9152_setup().
Definition: ad9152.c:206
ad9152_spi_read
int32_t ad9152_spi_read(struct ad9152_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9152_spi_read
Definition: ad9152.c:50
ad9152_init_param::interpolation
uint32_t interpolation
Definition: ad9152.h:1352
REG_PRBS_ERROR_Q
#define REG_PRBS_ERROR_Q
Definition: ad9144.h:189
ad9152_status
int32_t ad9152_status(struct ad9152_dev *dev)
ad9152_setup
Definition: ad9152.c:301
chip_id
chip_id
Definition: ad9172.h:57
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
REG_PRBS
#define REG_PRBS
Definition: ad9144.h:187