no-OS
ad917x_reg.h
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1 // SPDX-License-Identifier: GPL-2.0
13 #ifndef __AD917X_REGISTERS_H__
14 #define __AD917X_REGISTERS_H__
15 
16 #include "api_def.h"
17 
19  struct adi_reg_data *tbl, uint32_t count);
20 
22  const uint16_t address, uint8_t *data, uint32_t count);
23 
24 /*Device DEFINITION */
25 #define AD917X_JESD_NOF_LANES 8
26 #define AD917X_JESD_NOF_LINKS 2
27 #define AD917X_JESD_NOF_SYNCOUTB 2
28 #define AD9171_ID 9171
29 #define AD9172_ID 9172
30 #define AD9173_ID 9173
31 
32 /*REGISTER SUMMARY : (AD917X_REGMAP_V4)*/
33 #define AD917X_IF_CFG_A_REG 0x000
34 #define AD917X_IF_CFG_B_REG 0x001
35 #define AD917X_DEV_CFG_REG 0x002
36 #define AD917X_CHIP_TYPE_REG 0x003
37 #define AD917X_PROD_ID_LSB_REG 0x004
38 #define AD917X_PROD_ID_MSB_REG 0x005
39 #define AD917X_CHIP_GRADE_REG 0x006
40 #define AD917X_SPI_PAGEINDX_REG 0x008
41 #define AD917X_CHANNEL_PAGE_0 NO_OS_BIT(0)
42 #define AD917X_CHANNEL_PAGE_1 NO_OS_BIT(1)
43 #define AD917X_CHANNEL_PAGE_2 NO_OS_BIT(2)
44 #define AD917X_CHANNEL_PAGE_3 NO_OS_BIT(3)
45 #define AD917X_CHANNEL_PAGE_4 NO_OS_BIT(4)
46 #define AD917X_CHANNEL_PAGE_5 NO_OS_BIT(5)
47 #define AD917X_MAINDAC_PAGE_0 NO_OS_BIT(6)
48 #define AD917X_MAINDAC_PAGE_1 NO_OS_BIT(7)
49 
50 #define AD917X_SYSREF_ROTATION_REG 0x03B
51 #define AD917X_SYNC_LOGIC_EN NO_OS_BIT(7)
52 #define AD917X_SYNC_RSV_EN NO_OS_BIT(6)
53 #define AD917X_PERIODIC_RST_EN NO_OS_BIT(5)
54 #define AD917X_NCORST_AFTER_ROTATION NO_OS_BIT(4)
55 #define AD917X_ROTATION_MODE(x) (((x) & 0x3) << 0)
56 
57 
58 
59 #define AD917X_SYSREF_CTRL_REG 0x084
60 #define AD917X_SYSREF_PD NO_OS_BIT(0)
61 #define AD917X_SYSREF_DC_COUPLED NO_OS_BIT(6)
62 
63 #define AD917X_PLL_VCO_CTRL_REG 0x094
64 #define AD917X_PLL_VCO_DIV_EN(x) (((x) & 0x3) << 0)
65 
66 #define AD917X_PLL_BYPASS_REG 0x095
67 #define AD917X_PLL_BYPASS(x) ((x) ? NO_OS_BIT(0) : 0)
68 
69 #define AD917X_DLL_CTRL0_REG 0x0C1
70 #define AD917X_DLL_CFG NO_OS_BIT(6) | NO_OS_BIT(3)
71 #define AD917X_DLL_HF NO_OS_BIT(5)
72 #define AD917X_DLL_RST NO_OS_BIT(0)
73 #define AD917X_DLL_STATUS_REG 0x0C3
74 #define AD917X_DLL_LOCK NO_OS_BIT(0)
75 
76 #define AD917X_DIG_RESET_REG 0x100
77 #define AD917X_DIG_PATH_PDN(x) ((x) ? NO_OS_BIT(0) : 0)
78 
79 #define AD917X_JESD_MODE_REG 0x110
80 #define AD917X_JESD_MODE_INVALID NO_OS_BIT(7)
81 #define AD917X_LINK_MODE NO_OS_BIT(5)
82 #define AD917X_JESD_MODE(x) (((x) & 0x1F) << 0)
83 
84 #define AD917X_INTERP_MODE_REG 0x111
85 #define AD917X_CH_INTERP_MODE(x) (((x) & 0xF) << 0)
86 #define AD917X_DP_INTERP_MODE(x) (((x) & 0xF) << 4)
87 
88 #define AD917X_DDSM_DATAPATH_CFG_REG 0x112
89 #define AD917X_DDSM_MODE(x) (((x) & 0x3) << 4)
90 #define AD917X_DDSM_NCO_EN NO_OS_BIT(3)
91 #define AD917X_DDSM_MODULUS_EN NO_OS_BIT(2)
92 #define AD917X_DDSM_SEL_SIDEBAND NO_OS_BIT(1)
93 #define AD917X_DDSM_EN_SYNC_ALL_CHNL_NCO_RESETS NO_OS_BIT(0)
94 
95 #define AD917X_DDSM_FTW_UPDATE_REG 0x113
96 #define AD917X_DDSM_FTW_LOAD_SYSREF NO_OS_BIT(2)
97 #define AD917X_DDSM_FTW_LOAD_ACK NO_OS_BIT(1)
98 #define AD917X_DDSM_FTW_LOAD_REQ NO_OS_BIT(0)
99 
100 #define AD917X_DDSM_FTW0_REG 0x114
101 #define AD917X_DDSM_FTW1_REG 0x115
102 #define AD917X_DDSM_FTW2_REG 0x116
103 #define AD917X_DDSM_FTW3_REG 0x117
104 #define AD917X_DDSM_FTW4_REG 0x118
105 #define AD917X_DDSM_FTW5_REG 0x119
106 
107 #define AD917X_DDSM_PHASE_OFFSET0_REG 0x11C
108 #define AD917X_DDSM_PHASE_OFFSET1_REG 0x11D
109 
110 #define AD917X_DDSM_ACC_MODULUS0_REG 0x124
111 #define AD917X_DDSM_ACC_MODULUS1_REG 0x125
112 #define AD917X_DDSM_ACC_MODULUS2_REG 0x126
113 #define AD917X_DDSM_ACC_MODULUS3_REG 0x127
114 #define AD917X_DDSM_ACC_MODULUS4_REG 0x128
115 #define AD917X_DDSM_ACC_MODULUS5_REG 0x129
116 
117 #define AD917X_DDSM_ACC_DELTA0_REG 0x12A
118 #define AD917X_DDSM_ACC_DELTA1_REG 0x12B
119 #define AD917X_DDSM_ACC_DELTA2_REG 0x12C
120 #define AD917X_DDSM_ACC_DELTA3_REG 0x12D
121 #define AD917X_DDSM_ACC_DELTA4_REG 0x12E
122 #define AD917X_DDSM_ACC_DELTA5_REG 0x12F
123 
124 #define AD917X_DDSC_DATAPATH_CFG_REG 0x130
125 #define AD917X_DDSC_NCO_EN NO_OS_BIT(6)
126 #define AD917X_DDSC_MODULUS_EN NO_OS_BIT(2)
127 #define AD917X_DDSC_SEL_SIDEBAND NO_OS_BIT(1)
128 #define AD917X_DDSC_TEST_TONE_EN NO_OS_BIT(0)
129 
130 #define AD917X_DDSC_FTW_UPDATE_REG 0x131
131 #define AD917X_DDSC_FTW_LOAD_SYSREF NO_OS_BIT(2)
132 #define AD917X_DDSC_FTW_LOAD_ACK NO_OS_BIT(1)
133 #define AD917X_DDSC_FTW_LOAD_REQ NO_OS_BIT(0)
134 
135 #define AD917X_DDSC_FTW0_REG 0x132
136 #define AD917X_DDSC_FTW1_REG 0x133
137 #define AD917X_DDSC_FTW2_REG 0x134
138 #define AD917X_DDSC_FTW3_REG 0x135
139 #define AD917X_DDSC_FTW4_REG 0x136
140 #define AD917X_DDSC_FTW5_REG 0x137
141 
142 #define AD917X_DDSC_PHASE_OFFSET0_REG 0x138
143 #define AD917X_DDSC_PHASE_OFFSET1_REG 0x139
144 
145 #define AD917X_DDSC_ACC_MODULUS0_REG 0x13A
146 #define AD917X_DDSC_ACC_MODULUS1_REG 0x13B
147 #define AD917X_DDSC_ACC_MODULUS2_REG 0x13C
148 #define AD917X_DDSC_ACC_MODULUS3_REG 0x13D
149 #define AD917X_DDSC_ACC_MODULUS4_REG 0x13E
150 #define AD917X_DDSC_ACC_MODULUS5_REG 0x13F
151 
152 #define AD917X_DDSC_ACC_DELTA0_REG 0x140
153 #define AD917X_DDSC_ACC_DELTA1_REG 0x141
154 #define AD917X_DDSC_ACC_DELTA2_REG 0x142
155 #define AD917X_DDSC_ACC_DELTA3_REG 0x143
156 #define AD917X_DDSC_ACC_DELTA4_REG 0x144
157 #define AD917X_DDSC_ACC_DELTA5_REG 0x145
158 
159 #define AD917X_X_FTW_UPDATE_REG(x) ((x)==AD917X_DDSM?0x113:0x131)
160 
161 #define AD917X_X_FTW0_REG(x) ((x)==AD917X_DDSM?0x114:0x132)
162 #define AD917X_X_FTW1_REG(x) ((x)==AD917X_DDSM?0x115:0x133)
163 #define AD917X_X_FTW2_REG(x) ((x)==AD917X_DDSM?0x116:0x134)
164 #define AD917X_X_FTW3_REG(x) ((x)==AD917X_DDSM?0x117:0x135)
165 #define AD917X_X_FTW4_REG(x) ((x)==AD917X_DDSM?0x118:0x136)
166 #define AD917X_X_FTW5_REG(x) ((x)==AD917X_DDSM?0x119:0x137)
167 
168 #define AD917X_X_PHASE_OFFSET0_REG(x) ((x)==AD917X_DDSM?0x11C:0x138)
169 #define AD917X_X_PHASE_OFFSET1_REG(x) ((x)==AD917X_DDSM?0x11D:0x139)
170 
171 #define AD917X_X_ACC_MODULUS0_REG(x) ((x)==AD917X_DDSM?0x124:0x13A)
172 #define AD917X_X_ACC_MODULUS1_REG(x) ((x)==AD917X_DDSM?0x125:0x13B)
173 #define AD917X_X_ACC_MODULUS2_REG(x) ((x)==AD917X_DDSM?0x126:0x13C)
174 #define AD917X_X_ACC_MODULUS3_REG(x) ((x)==AD917X_DDSM?0x127:0x13D)
175 #define AD917X_X_ACC_MODULUS4_REG(x) ((x)==AD917X_DDSM?0x128:0x13E)
176 #define AD917X_X_ACC_MODULUS5_REG(x) ((x)==AD917X_DDSM?0x129:0x13F)
177 
178 #define AD917X_X_ACC_DELTA0_REG(x) ((x)==AD917X_DDSM?0x12A:0x140)
179 #define AD917X_X_ACC_DELTA1_REG(x) ((x)==AD917X_DDSM?0x12B:0x141)
180 #define AD917X_X_ACC_DELTA2_REG(x) ((x)==AD917X_DDSM?0x12C:0x142)
181 #define AD917X_X_ACC_DELTA3_REG(x) ((x)==AD917X_DDSM?0x12D:0x143)
182 #define AD917X_X_ACC_DELTA4_REG(x) ((x)==AD917X_DDSM?0x12E:0x144)
183 #define AD917X_X_ACC_DELTA5_REG(x) ((x)==AD917X_DDSM?0x12F:0x145)
184 
185 #define AD917X_CHNL_GAIN0_REG 0x146
186 #define AD917X_CHNL_GAIN1_REG 0x147
187 #define CHANNEL_GAIN0(x) (uint8_t)((x) & 0xFF)
188 #define CHANNEL_GAIN1(x) (uint8_t)(((x) >> 8) & 0x0F)
189 #define CHANNEL_GAIN(g0, g1) (uint16_t)(((uint16_t)((g1) << 8) | (g0)) & 0xFFF)
190 
191 #define AD917X_DC_CAL_TONE0_REG 0x148
192 #define AD917X_DC_CAL_TONE1_REG 0x149
193 
194 #define AD917X_DDSM_CAL_MODE_DEF_REG 0x1E6
195 #define AD917X_DDSM_EN_CAL_ACC NO_OS_BIT(2)
196 #define AD917X_DDSM_EN_CAL_DC_INPUT NO_OS_BIT(1)
197 #define AD917X_DDSM_EN_CAL_FREQ_TUNE NO_OS_BIT(0)
198 
199 
200 #define AD917X_MASTER_PD_REG 0x200
201 #define AD917X_SERDES_PDN(x) ((x) ? NO_OS_BIT(0) : 0)
202 #define AD917X_PHY_PD_REG 0x201
203 #define AD917X_PLL_EN_CTRL_REG 0x280
204 #define AD917X_SERDES_PLL_STARTUP NO_OS_BIT(0)
205 
206 #define AD917X_GEN_PD_REG 0x203
207 #define AD917X_SYNCOUTB_0_PD NO_OS_BIT(1)
208 #define AD917X_SYNCOUTB_1_PD NO_OS_BIT(0)
209 #define AD917X_SYNCOUTB_PD(x) (((x) & 0x3) << 0)
210 
211 #define AD917X_SYNCOUTB_CTRL_0_REG 0x253
212 #define AD917X_SYNCOUTB_CTRL_1_REG 0x254
213 #define AD917X_SYNCOUTB_MODE(x) ((x) ? NO_OS_BIT(0) : 0)
214 
215 #define AD917X_PLL_STATUS_REG 0x281
216 
217 #define AD917X_JESD_RX_CTL_REG 0x300
218 #define AD917X_DUAL_MODE NO_OS_BIT(3)
219 #define AD917X_LINK_PAGE(x) ((x) ? NO_OS_BIT(2) : 0)
220 #define AD917X_LINK_EN(x) (((x) & 0x3) << 0)
221 #define AD917X_LINK_0_EN NO_OS_BIT(0)
222 #define AD917X_LINK_1_EN NO_OS_BIT(1)
223 
224 #define AD917X_JESD_LMFC_DELAY0_REG 0x304
225 #define AD917X_JESD_LMFC_DELAY1_REG 0x305
226 #define AD917X_JESD_LMFC_DELAY(x) (((x) & 0x3F) << 0)
227 #define AD917X_JESD_LMFC_VAR0_REG 0x306
228 #define AD917X_JESD_LMFC_VAR1_REG 0x307
229 #define AD917X_JESD_LMFC_VAR(x) (((x) & 0x3F) << 0)
230 
231 #define AD917X_JESD_XBAR_LANE_REG 0x308
232 #define AD917X_JESD_XBAR_LANE_REG 0x308
233 #define AD917X_JESD_XBAR_LANE_REG 0x308
234 
235 #define AD917X_JESD_XBAR_LANE_REG 0x308
236 #define AD917X_XBAR_LANE_EVEN(x) (((x) & 0x7) << 0)
237 #define AD917X_XBAR_LANE_ODD(x) (((x) & 0x7) << 3)
238 
239 #define AD917X_JESD_INVERT_LANE_REG 0x334
240 #define AD917X_JESD_INVERT_LANE(x) NO_OS_BIT(x)
241 
242 #define AD917X_JESD_PARAM_REG_BASE 0x450
243 #define AD917X_JESD_PARAM_REG_LEN 0xB
244 #define AD917X_JESD_L_GET(x) ((x[3] & 0xF) + 1)
245 #define AD917X_JESD_F_GET(x) ((x[4]) + 1)
246 #define AD917X_JESD_K_GET(x) ((x[5] & 0x1F) + 1)
247 #define AD917X_JESD_M_GET(x) ((x[6]) + 1)
248 #define AD917X_JESD_N_GET(x) ((x[7] & 0xF) + 1)
249 #define AD917X_JESD_NP_GET(x) ((x[8] & 0xF) + 1)
250 #define AD917X_JESD_S_GET(x) ((x[9] & 0xF) + 1)
251 #define AD917X_JESD_HD_GET(x) ((x[10] & 0x80) >> 7)
252 #define AD917X_JESD_DID_GET(x) (x[0])
253 #define AD917X_JESD_BID_GET(x) (x[1])
254 #define AD917X_JESD_LID0_GET(x) (x[2] & 0xF)
255 #define AD917X_JESD_V_GET(x) ((x[9] & 0xF8) >> 5)
256 #define AD917X_JESD_L(x) (((x) & 0xF) << 0)
257 #define AD917X_JESD_NP(x) (((x) & 0xF) << 0)
258 
259 #define AD917X_JESD_ILS_SCR_L_REG 0x453
260 #define AD917X_JESD_SCR NO_OS_BIT(7)
261 #define AD917X_JESD_ILS_NP_REG 0x458
262 #define AD917X_JESD_JESDV NO_OS_BIT(5)
263 
264 #define AD917X_JESD_CODE_GRP_SYNC_REG 0x470
265 #define AD917X_JESD_FRAME_SYNC_REG 0x471
266 #define AD917X_JESD_GOOD_CHECKSUM_REG 0x472
267 #define AD917X_JESD_INIT_LANE_SYNC_REG 0x473
268 
269 #define AD917X_JESD_CTRL0_REG 0x475
270 #define AD917X_JESD_QBD_SOFT_RST NO_OS_BIT(3)
271 
272 
273 
274 #define AD917X_NVM_LOADER_REG 0x705
275 #define AD917X_NVM_BLR_DONE NO_OS_BIT(1)
276 
277 
278 #define AD917X_DACPLL_CTRLX_REG 0x790
279 #define AD917X_DACPLL_CTRLY_REG 0x791
280 #define AD917X_DACPLL_CTRL0_REG 0x792
281 #define AD917X_RESET_VCO_DIV NO_OS_BIT(1)
282 
283 #define AD917X_DACPLL_CTRL1_REG 0x793
284 #define AD917X_M_DIV(x) (((x) & 0x3) << 0)
285 
286 #define AD917X_DACPLL_CTRL7_REG 0x799
287 #define AD917X_L_DIV(x) (((x) & 0x3) << 6)
288 #define AD917X_N_DIV(x) (((x) & 0x3F) << 0)
289 
290 
291 #define AD917X_DACPLL_STATUS_REG 0x7B5
292 #define AD917X_DACPLL_LOCK NO_OS_BIT(0)
293 
294 #endif /*__AD917X_REG_H__*/
SYNCOUTB_0
@ SYNCOUTB_0
Definition: api_def.h:216
AD917X_X_ACC_DELTA2_REG
#define AD917X_X_ACC_DELTA2_REG(x)
Definition: ad917x_reg.h:180
SPI_SDO
@ SPI_SDO
Definition: api_def.h:183
AD917X_JESD_BID_GET
#define AD917X_JESD_BID_GET(x)
Definition: ad917x_reg.h:253
AD917X_JESD_PARAM_REG_BASE
#define AD917X_JESD_PARAM_REG_BASE
Definition: ad917x_reg.h:242
ad917x_deinit
int32_t ad917x_deinit(ad917x_handle_t *h)
De-initialize the AD917X Device.
Definition: ad917x_api.c:200
AD917X_JESD_L_GET
#define AD917X_JESD_L_GET(x)
Definition: ad917x_reg.h:244
AD917X_DDSM_DATAPATH_CFG_REG
#define AD917X_DDSM_DATAPATH_CFG_REG
Definition: ad917x_reg.h:88
AD917X_X_FTW_UPDATE_REG
#define AD917X_X_FTW_UPDATE_REG(x)
Definition: ad917x_reg.h:159
API_ERROR_INVALID_HANDLE_PTR
#define API_ERROR_INVALID_HANDLE_PTR
Definition: api_errors.h:29
AD917X_DDSM_FTW_LOAD_ACK
#define AD917X_DDSM_FTW_LOAD_ACK
Definition: ad917x_reg.h:97
ad917x_handle_t::hw_open
hw_open_t hw_open
Definition: AD917x.h:97
adi_reg_data
Definition: api_def.h:156
ad917x_jesd_set_sysref_enable
int32_t ad917x_jesd_set_sysref_enable(ad917x_handle_t *h, uint8_t en)
Enable SysRef Input.
Definition: ad917x_jesd_api.c:246
jesd_param_t::jesd_CS
uint8_t jesd_CS
Definition: api_def.h:242
AD917X_X_ACC_MODULUS1_REG
#define AD917X_X_ACC_MODULUS1_REG(x)
Definition: ad917x_reg.h:172
API_ERROR_INVALID_XFER_PTR
#define API_ERROR_INVALID_XFER_PTR
Definition: api_errors.h:31
AD917X_LINK_1_EN
#define AD917X_LINK_1_EN
Definition: ad917x_reg.h:222
AD917X_CHNL_GAIN0_REG
#define AD917X_CHNL_GAIN0_REG
Definition: ad917x_reg.h:185
AD917X_DDSM_NCO_EN
#define AD917X_DDSM_NCO_EN
Definition: ad917x_reg.h:90
AD917X_CH_0
@ AD917X_CH_0
Definition: AD917x.h:51
ad917x_init
int32_t ad917x_init(ad917x_handle_t *h)
Initialize AD917X Device This API must be called first before any other API calls....
Definition: ad917x_api.c:168
AD917X_DACPLL_CTRLY_REG
#define AD917X_DACPLL_CTRLY_REG
Definition: ad917x_reg.h:279
AD917X_JESD_INIT_LANE_SYNC_REG
#define AD917X_JESD_INIT_LANE_SYNC_REG
Definition: ad917x_reg.h:267
ad917x_jesd_set_lane_xbar
int32_t ad917x_jesd_set_lane_xbar(ad917x_handle_t *h, uint8_t logical_lane, uint8_t physical_lane)
Configure the Lane Cross Bar in the JESD datalink layer.
Definition: ad917x_jesd_api.c:487
API_ERROR_INIT_SEQ_FAIL
#define API_ERROR_INIT_SEQ_FAIL
Definition: api_errors.h:45
AD917X_JESD_V_GET
#define AD917X_JESD_V_GET(x)
Definition: ad917x_reg.h:255
AD917X_PLL_STATUS_REG
#define AD917X_PLL_STATUS_REG
Definition: ad917x_reg.h:215
ad917x_jesd_invert_lane
int32_t ad917x_jesd_invert_lane(ad917x_handle_t *h, uint8_t logical_lane, uint8_t invert)
Invert or un-invert logical lanes.
Definition: ad917x_jesd_api.c:521
IN_OUT_BUFF_SZ
#define IN_OUT_BUFF_SZ
Definition: ad917x_reg.c:21
AD917X_DIG_PATH_PDN
#define AD917X_DIG_PATH_PDN(x)
Definition: ad917x_reg.h:77
AD917X_SERDES_PLL_STARTUP
#define AD917X_SERDES_PLL_STARTUP
Definition: ad917x_reg.h:204
AD917X_NVM_BLR_DONE
#define AD917X_NVM_BLR_DONE
Definition: ad917x_reg.h:275
AD917X_DACPLL_CTRL7_REG
#define AD917X_DACPLL_CTRL7_REG
Definition: ad917x_reg.h:286
CS_DEFAULT
#define CS_DEFAULT
Definition: ad917x_jesd_api.c:35
AD917X_X_ACC_DELTA4_REG
#define AD917X_X_ACC_DELTA4_REG(x)
Definition: ad917x_reg.h:182
AD917X_PLL_BYPASS_REG
#define AD917X_PLL_BYPASS_REG
Definition: ad917x_reg.h:66
AD917X_CH_5
@ AD917X_CH_5
Definition: AD917x.h:61
SYNCOUTB_INDEX
#define SYNCOUTB_INDEX(x)
Definition: ad917x_jesd_api.c:27
AD917X_DDSM_CAL_MODE_DEF_REG
#define AD917X_DDSM_CAL_MODE_DEF_REG
Definition: ad917x_reg.h:194
ad917x_reset
int32_t ad917x_reset(ad917x_handle_t *h, uint8_t hw_reset)
Reset the AD917X.
Definition: ad917x_api.c:246
jesd_param_t::jesd_L
uint8_t jesd_L
Definition: api_def.h:232
AD917X_X_ACC_MODULUS4_REG
#define AD917X_X_ACC_MODULUS4_REG(x)
Definition: ad917x_reg.h:175
AD917X_N_DIV
#define AD917X_N_DIV(x)
Definition: ad917x_reg.h:288
AD917X_DLL_RST
#define AD917X_DLL_RST
Definition: ad917x_reg.h:72
ad917x_jesd_get_cfg_status
int32_t ad917x_jesd_get_cfg_status(ad917x_handle_t *h, uint8_t *cfg_valid)
Get JESD Configuration Status.
Definition: ad917x_jesd_api.c:192
AD917X_CH_4
@ AD917X_CH_4
Definition: AD917x.h:59
AD917X_PROD_ID_MSB_REG
#define AD917X_PROD_ID_MSB_REG
Definition: ad917x_reg.h:38
COUPLING_DC
@ COUPLING_DC
Definition: api_def.h:203
jesd_param_t::jesd_N
uint8_t jesd_N
Definition: api_def.h:239
ad917x_set_dac_clk_freq
int32_t ad917x_set_dac_clk_freq(ad917x_handle_t *h, uint64_t dac_clk_freq_hz)
Set the DAC CLK Frequency.
Definition: ad917x_api.c:422
ad917x_jesd_get_cfg_param
int32_t ad917x_jesd_get_cfg_param(ad917x_handle_t *h, jesd_param_t *jesd_param)
Read back all current JESD parameter settings.
Definition: ad917x_jesd_api.c:211
AD917X_SYSREF_PD
#define AD917X_SYSREF_PD
Definition: ad917x_reg.h:60
API_ERROR_INVALID_DELAYUS_PTR
#define API_ERROR_INVALID_DELAYUS_PTR
Definition: api_errors.h:33
AD917X_X_ACC_DELTA0_REG
#define AD917X_X_ACC_DELTA0_REG(x)
Definition: ad917x_reg.h:178
LINK_INDEX
#define LINK_INDEX(x)
Definition: ad917x_jesd_api.c:25
AD917x.h
AD917X API interface header file.
AD917X_X_FTW2_REG
#define AD917X_X_FTW2_REG(x)
Definition: ad917x_reg.h:163
adi_reg_data::val
uint8_t val
Definition: api_def.h:160
AD917X_JESD_MODE_REG
#define AD917X_JESD_MODE_REG
Definition: ad917x_reg.h:79
ad917x_jesd_set_lmfc_delay
int32_t ad917x_jesd_set_lmfc_delay(ad917x_handle_t *h, jesd_link_t link, uint8_t delay, uint8_t var)
Set the LMFC Delay and Variance for the JESD Links.
Definition: ad917x_jesd_api.c:637
AD917X_IF_CFG_A_REG
#define AD917X_IF_CFG_A_REG
Definition: ad917x_reg.h:33
NO_OS_S16_MAX
#define NO_OS_S16_MAX
Definition: no_os_util.h:111
api_errors.h
API error codes header file.
SYNCOUTB_1
@ SYNCOUTB_1
Definition: api_def.h:217
AD917X_PLL_EN_CTRL_REG
#define AD917X_PLL_EN_CTRL_REG
Definition: ad917x_reg.h:203
AD917X_JESD_S_GET
#define AD917X_JESD_S_GET(x)
Definition: ad917x_reg.h:250
ad917x_dac_select_t
ad917x_dac_select_t
Definition: AD917x.h:37
ad917x_dds_select_t
ad917x_dds_select_t
Definition: AD917x.h:29
AD917X_DDSC_DATAPATH_CFG_REG
#define AD917X_DDSC_DATAPATH_CFG_REG
Definition: ad917x_reg.h:124
ad917x_handle_t::hw_close
hw_close_t hw_close
Definition: AD917x.h:99
AD917X_GEN_PD_REG
#define AD917X_GEN_PD_REG
Definition: ad917x_reg.h:206
API_ERROR_US_DELAY
#define API_ERROR_US_DELAY
Definition: api_errors.h:51
AD917X_JESD_MODE_INVALID
#define AD917X_JESD_MODE_INVALID
Definition: ad917x_reg.h:80
JESD_LINK_0
@ JESD_LINK_0
Definition: api_def.h:209
AD917X_XBAR_LANE_EVEN
#define AD917X_XBAR_LANE_EVEN(x)
Definition: ad917x_reg.h:236
SIGNAL_LVDS
@ SIGNAL_LVDS
Definition: api_def.h:196
ad917x_get_dac_clk_status
int32_t ad917x_get_dac_clk_status(ad917x_handle_t *h, uint8_t *pll_lock_stat, uint8_t *dll_lock_stat)
Get DAC CLK Status.
Definition: ad917x_api.c:473
AD917X_JESD_LMFC_VAR0_REG
#define AD917X_JESD_LMFC_VAR0_REG
Definition: ad917x_reg.h:227
AD917X_DDSM_EN_CAL_DC_INPUT
#define AD917X_DDSM_EN_CAL_DC_INPUT
Definition: ad917x_reg.h:196
AD917X_ROTATION_MODE
#define AD917X_ROTATION_MODE(x)
Definition: ad917x_reg.h:55
NO_OS_ARRAY_SIZE
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
AD917X_JESD_RX_CTL_REG
#define AD917X_JESD_RX_CTL_REG
Definition: ad917x_reg.h:217
NVRAM_RESET_PERIOD_US
#define NVRAM_RESET_PERIOD_US
Definition: ad917x_api.c:23
AD917X_CHNL_GAIN1_REG
#define AD917X_CHNL_GAIN1_REG
Definition: ad917x_reg.h:186
AD917X_RESET_VCO_DIV
#define AD917X_RESET_VCO_DIV
Definition: ad917x_reg.h:281
AD917X_PHY_PD_REG
#define AD917X_PHY_PD_REG
Definition: ad917x_reg.h:202
AD917X_DACPLL_CTRL1_REG
#define AD917X_DACPLL_CTRL1_REG
Definition: ad917x_reg.h:283
ad917x_jesd_set_scrambler_enable
int32_t ad917x_jesd_set_scrambler_enable(ad917x_handle_t *h, uint8_t en)
Enable the de-scrambler for the JESD Interface.
Definition: ad917x_jesd_api.c:307
ad917x_handle_t::delay_us
delay_us_t delay_us
Definition: AD917x.h:92
API_ERROR_SPI_XFER
#define API_ERROR_SPI_XFER
Definition: api_errors.h:49
AD917X_X_ACC_DELTA3_REG
#define AD917X_X_ACC_DELTA3_REG(x)
Definition: ad917x_reg.h:181
CHANNEL_GAIN0
#define CHANNEL_GAIN0(x)
Definition: ad917x_reg.h:187
AD917X_DACPLL_LOCK
#define AD917X_DACPLL_LOCK
Definition: ad917x_reg.h:292
DP_INTERPOLATION_MAX
#define DP_INTERPOLATION_MAX
Definition: ad917x_jesd_api.c:40
AD917X_DDSM_PHASE_OFFSET1_REG
#define AD917X_DDSM_PHASE_OFFSET1_REG
Definition: ad917x_reg.h:108
AD917X_DDSM_MODE
#define AD917X_DDSM_MODE(x)
Definition: ad917x_reg.h:89
jesd_param_t::jesd_S
uint8_t jesd_S
Definition: api_def.h:235
ADI_POW2_48
#define ADI_POW2_48
Definition: api_def.h:20
AD917X_SYNCOUTB_1_PD
#define AD917X_SYNCOUTB_1_PD
Definition: ad917x_reg.h:208
AD917X_JESD_MODE
#define AD917X_JESD_MODE(x)
Definition: ad917x_reg.h:82
AD917X_CH_1
@ AD917X_CH_1
Definition: AD917x.h:53
AD917X_X_FTW3_REG
#define AD917X_X_FTW3_REG(x)
Definition: ad917x_reg.h:164
ad917x_handle_t::sysref
signal_coupling_t sysref
Definition: AD917x.h:89
AD917X_JESD_ILS_NP_REG
#define AD917X_JESD_ILS_NP_REG
Definition: ad917x_reg.h:261
SYNCOUTB_INDEX_MAX
#define SYNCOUTB_INDEX_MAX
Definition: ad917x_jesd_api.c:26
AD917X_X_FTW0_REG
#define AD917X_X_FTW0_REG(x)
Definition: ad917x_reg.h:161
jesd_param_t::jesd_NP
uint8_t jesd_NP
Definition: api_def.h:240
AD917X_DDSC_PHASE_OFFSET1_REG
#define AD917X_DDSC_PHASE_OFFSET1_REG
Definition: ad917x_reg.h:143
AD917X_JESD_CODE_GRP_SYNC_REG
#define AD917X_JESD_CODE_GRP_SYNC_REG
Definition: ad917x_reg.h:264
jesd_param_t
Definition: api_def.h:231
AD917X_DDSM
@ AD917X_DDSM
Definition: AD917x.h:31
ad917x_get_page_idx
int32_t ad917x_get_page_idx(ad917x_handle_t *h, int32_t *dac, int32_t *channel)
Get select page index.
Definition: ad917x_api.c:621
DAC_CLK_FREQ_MAX_HZ
#define DAC_CLK_FREQ_MAX_HZ
Definition: ad917x_api.c:33
AD917X_DAC1
@ AD917X_DAC1
Definition: AD917x.h:43
AD917X_X_FTW4_REG
#define AD917X_X_FTW4_REG(x)
Definition: ad917x_reg.h:165
ad917x_jesd_get_lane_xbar
int32_t ad917x_jesd_get_lane_xbar(ad917x_handle_t *h, uint8_t *phy_log_map)
Get current Lane Cross Bar configuration for the JESD datalink layer.
Definition: ad917x_jesd_api.c:549
AD917X_DACPLL_CTRLX_REG
#define AD917X_DACPLL_CTRLX_REG
Definition: ad917x_reg.h:278
LANE_INDEX_MAX
#define LANE_INDEX_MAX
Definition: ad917x_jesd_api.c:23
API_ERROR_HW_OPEN
#define API_ERROR_HW_OPEN
Definition: api_errors.h:59
ad917x_handle_t::dac_freq_hz
uint64_t dac_freq_hz
Definition: AD917x.h:90
AD917X_JESD_N_GET
#define AD917X_JESD_N_GET(x)
Definition: ad917x_reg.h:248
DAC_9171_CLK_FREQ_MAX_HZ
#define DAC_9171_CLK_FREQ_MAX_HZ
Definition: ad917x_api.c:32
AD917X_JESD_INVERT_LANE_REG
#define AD917X_JESD_INVERT_LANE_REG
Definition: ad917x_reg.h:239
AD917X_PLL_BYPASS
#define AD917X_PLL_BYPASS(x)
Definition: ad917x_reg.h:67
SPI_CONFIG_MAX
@ SPI_CONFIG_MAX
Definition: api_def.h:190
N
#define N(x)
Definition: ad9144.h:1277
jesd_param_t::jesd_F
uint8_t jesd_F
Definition: api_def.h:233
AD917X_NVM_LOADER_REG
#define AD917X_NVM_LOADER_REG
Definition: ad917x_reg.h:274
SPI_RESET_PERIOD_US
#define SPI_RESET_PERIOD_US
Definition: ad917x_api.c:22
AD917X_SYNC_RSV_EN
#define AD917X_SYNC_RSV_EN
Definition: ad917x_reg.h:52
AD917X_DIG_RESET_REG
#define AD917X_DIG_RESET_REG
Definition: ad917x_reg.h:76
ad917x_register_write_tbl
int32_t ad917x_register_write_tbl(ad917x_handle_t *h, struct adi_reg_data *tbl, uint32_t count)
Definition: ad917x_reg.c:80
JESD_LINK_1
@ JESD_LINK_1
Definition: api_def.h:210
PFD_CLK_FREQ_MHZ_MIN
#define PFD_CLK_FREQ_MHZ_MIN
Definition: ad917x_api.c:29
ad917x_jesd_set_syncoutb_enable
int32_t ad917x_jesd_set_syncoutb_enable(ad917x_handle_t *h, jesd_syncoutb_t syncoutb, uint8_t en)
Enable the SYNCOUTB Output Signal.
Definition: ad917x_jesd_api.c:436
REF_CLK_FREQ_MHZ_MIN
#define REF_CLK_FREQ_MHZ_MIN
Definition: ad917x_api.c:27
NO_OS_DIV_U64
#define NO_OS_DIV_U64(x, y)
Definition: no_os_util.h:113
ad917x_set_page_idx
int32_t ad917x_set_page_idx(ad917x_handle_t *h, const uint32_t dac, const uint32_t channel)
Select Page.
Definition: ad917x_api.c:611
AD917X_LMFC_VAR_MAX
#define AD917X_LMFC_VAR_MAX
Definition: ad917x_jesd_api.c:47
AD917X_DACPLL_STATUS_REG
#define AD917X_DACPLL_STATUS_REG
Definition: ad917x_reg.h:291
ad917x_register_read_block
int32_t ad917x_register_read_block(ad917x_handle_t *h, const uint16_t address, uint8_t *data, uint32_t count)
Definition: ad917x_reg.c:65
ad917x_set_clkout_config
int32_t ad917x_set_clkout_config(ad917x_handle_t *h, uint8_t l_div)
Set CLKOUT configuration.
Definition: ad917x_api.c:498
ad917x_nco_set_phase_offset
int32_t ad917x_nco_set_phase_offset(ad917x_handle_t *h, const ad917x_dac_select_t dacs, const uint16_t dacs_po, const ad917x_channel_select_t channels, const uint16_t ch_po)
Set NCO phase offset.
Definition: ad917x_nco_api.c:263
AD917X_DC_CAL_TONE0_REG
#define AD917X_DC_CAL_TONE0_REG
Definition: ad917x_reg.h:191
AD917X_DDSC
@ AD917X_DDSC
Definition: AD917x.h:33
ad917x_register_write_tbl
int32_t ad917x_register_write_tbl(ad917x_handle_t *h, struct adi_reg_data *tbl, uint32_t count)
Definition: ad917x_reg.c:80
AD917X_JESD_JESDV
#define AD917X_JESD_JESDV
Definition: ad917x_reg.h:262
ALL
#define ALL
Definition: api_def.h:27
CHANNEL_GAIN
#define CHANNEL_GAIN(g0, g1)
Definition: ad917x_reg.h:189
CHANNEL_GAIN1
#define CHANNEL_GAIN1(x)
Definition: ad917x_reg.h:188
ad917x_register_read
int32_t ad917x_register_read(ad917x_handle_t *h, const uint16_t address, uint8_t *data)
Perform SPI register read access to AD917X Device.
Definition: ad917x_reg.c:43
AD917X_MASTER_PD_REG
#define AD917X_MASTER_PD_REG
Definition: ad917x_reg.h:200
jesd_param_t::jesd_HD
uint8_t jesd_HD
Definition: api_def.h:237
AD917X_MAINDAC_PAGE_1
#define AD917X_MAINDAC_PAGE_1
Definition: ad917x_reg.h:48
ad917x_dc_test_tone_set
int32_t ad917x_dc_test_tone_set(ad917x_handle_t *h, int32_t dc_test_tone_en)
Set DC Test Tone enable status.
Definition: ad917x_nco_api.c:690
ad917x_set_dac_clk
int32_t ad917x_set_dac_clk(ad917x_handle_t *h, uint64_t dac_clk_freq_hz, uint8_t dac_pll_en, uint64_t ref_clk_freq_hz)
Configure the DAC Clock Input path based on a the desired dac clock frequency, the applied reference ...
Definition: ad917x_api.c:519
jesd_param_t::jesd_BID
uint8_t jesd_BID
Definition: api_def.h:245
DAC_CLK_FREQ_MIN_HZ
#define DAC_CLK_FREQ_MIN_HZ
Definition: ad917x_api.c:34
ad917x_get_revision
int32_t ad917x_get_revision(ad917x_handle_t *h, uint8_t *rev_major, uint8_t *rev_minor, uint8_t *rev_rc)
Get API Revision Data.
Definition: ad917x_api.c:304
AD917X_JESD_LMFC_VAR
#define AD917X_JESD_LMFC_VAR(x)
Definition: ad917x_reg.h:229
API_ERROR_HW_CLOSE
#define API_ERROR_HW_CLOSE
Definition: api_errors.h:61
AD917X_CHIP_TYPE_REG
#define AD917X_CHIP_TYPE_REG
Definition: ad917x_reg.h:36
AD917X_JESD_HD_GET
#define AD917X_JESD_HD_GET(x)
Definition: ad917x_reg.h:251
jesd_param_t::jesd_JESDV
uint8_t jesd_JESDV
Definition: api_def.h:247
ad917x_get_channel_gain
int32_t ad917x_get_channel_gain(ad917x_handle_t *h, uint16_t *gain)
Get Channel gain.
Definition: ad917x_nco_api.c:607
AD917X_JESD_F_GET
#define AD917X_JESD_F_GET(x)
Definition: ad917x_reg.h:245
ad917x_jesd_get_pll_status
int32_t ad917x_jesd_get_pll_status(ad917x_handle_t *h, uint8_t *pll_status)
Get SERDES PLL Status.
Definition: ad917x_jesd_api.c:472
AD917X_JESD_FRAME_SYNC_REG
#define AD917X_JESD_FRAME_SYNC_REG
Definition: ad917x_reg.h:265
API_ERROR_FTW_LOAD_ACK
#define API_ERROR_FTW_LOAD_ACK
Definition: api_errors.h:41
AD917X_X_ACC_DELTA1_REG
#define AD917X_X_ACC_DELTA1_REG(x)
Definition: ad917x_reg.h:179
ad917x_register_read_block
int32_t ad917x_register_read_block(ad917x_handle_t *h, const uint16_t address, uint8_t *data, uint32_t count)
Definition: ad917x_reg.c:65
AD917X_X_ACC_MODULUS3_REG
#define AD917X_X_ACC_MODULUS3_REG(x)
Definition: ad917x_reg.h:174
AD917X_SYNCOUTB_0_PD
#define AD917X_SYNCOUTB_0_PD
Definition: ad917x_reg.h:207
ad917x_jesd_enable_datapath
int32_t ad917x_jesd_enable_datapath(ad917x_handle_t *h, uint8_t lanes_msk, uint8_t run_cal, uint8_t en)
Enable the JESD Interface.
Definition: ad917x_jesd_api.c:341
AD917X_M_DIV
#define AD917X_M_DIV(x)
Definition: ad917x_reg.h:284
AD917X_LINK_MODE
#define AD917X_LINK_MODE
Definition: ad917x_reg.h:81
API_ERROR_SPI_SDO
#define API_ERROR_SPI_SDO
Definition: api_errors.h:27
AD917X_DLL_CTRL0_REG
#define AD917X_DLL_CTRL0_REG
Definition: ad917x_reg.h:69
ADI_GET_BYTE
#define ADI_GET_BYTE(w, p)
Definition: api_def.h:26
ad917x_nco_get_ftw
int32_t ad917x_nco_get_ftw(ad917x_handle_t *h, const ad917x_dds_select_t dds, uint64_t *ftw, uint64_t *acc_modulus, uint64_t *acc_delta)
Get FTW, ACC and MOD values.
Definition: ad917x_nco_api.c:467
ad917x_jesd_get_link_status
int32_t ad917x_jesd_get_link_status(ad917x_handle_t *h, jesd_link_t link, ad917x_jesd_link_stat_t *link_status)
Get JESD Link Status.
Definition: ad917x_jesd_api.c:598
ad917x_reg.h
AD917x SPI Register Definition Header File.
AD917X_JESD_LMFC_DELAY
#define AD917X_JESD_LMFC_DELAY(x)
Definition: ad917x_reg.h:226
AD917X_INTERP_MODE_REG
#define AD917X_INTERP_MODE_REG
Definition: ad917x_reg.h:84
AD917X_DACPLL_CTRL0_REG
#define AD917X_DACPLL_CTRL0_REG
Definition: ad917x_reg.h:280
AD917X_DDSC_PHASE_OFFSET0_REG
#define AD917X_DDSC_PHASE_OFFSET0_REG
Definition: ad917x_reg.h:142
AD917X_SYNCOUTB_MODE
#define AD917X_SYNCOUTB_MODE(x)
Definition: ad917x_reg.h:213
AD917X_DDSC_MODULUS_EN
#define AD917X_DDSC_MODULUS_EN
Definition: ad917x_reg.h:126
ad917x_nco_set_ftw
int32_t ad917x_nco_set_ftw(ad917x_handle_t *h, const ad917x_dds_select_t dds, const uint64_t ftw, const uint64_t acc_modulus, const uint64_t acc_delta)
Set FTW, ACC and MOD values.
Definition: ad917x_nco_api.c:364
SYNCOUTB_ALL
@ SYNCOUTB_ALL
Definition: api_def.h:218
api_def.h
API definitions header file.
AD917X_DDSM_PHASE_OFFSET0_REG
#define AD917X_DDSM_PHASE_OFFSET0_REG
Definition: ad917x_reg.h:107
AD917X_JESD_NOF_LANES
#define AD917X_JESD_NOF_LANES
Definition: ad917x_reg.h:25
ad917x_ddsm_cal_dc_input_set
int32_t ad917x_ddsm_cal_dc_input_set(ad917x_handle_t *h, int32_t ddsm_cal_dc_input_en)
Set Main DAC Cal DC Input.
Definition: ad917x_nco_api.c:729
ad917x_handle_t::sdo
spi_sdo_config_t sdo
Definition: AD917x.h:87
ad917x_set_channel_gain
int32_t ad917x_set_channel_gain(ad917x_handle_t *h, const uint16_t gain)
Set Channel gain.
Definition: ad917x_nco_api.c:577
API_ERROR_INVALID_PARAM
#define API_ERROR_INVALID_PARAM
Definition: api_errors.h:35
PFD_CLK_FREQ_MHZ_MAX
#define PFD_CLK_FREQ_MHZ_MAX
Definition: ad917x_api.c:30
AD917X_SPI_PAGEINDX_REG
#define AD917X_SPI_PAGEINDX_REG
Definition: ad917x_reg.h:40
CF_DEFAULT
#define CF_DEFAULT
Definition: ad917x_jesd_api.c:34
AD917X_PLL_VCO_CTRL_REG
#define AD917X_PLL_VCO_CTRL_REG
Definition: ad917x_reg.h:63
AD917X_CH_INTERP_MODE
#define AD917X_CH_INTERP_MODE(x)
Definition: ad917x_reg.h:85
AD917X_CHANNEL_PAGE_0
#define AD917X_CHANNEL_PAGE_0
Definition: ad917x_reg.h:41
HW_RESET_PERIOD_US
#define HW_RESET_PERIOD_US
Definition: ad917x_api.c:21
ad917x_jesd_get_sysref_enable
int32_t ad917x_jesd_get_sysref_enable(ad917x_handle_t *h, uint8_t *en)
Get the current SYSREF Input.
Definition: ad917x_jesd_api.c:288
jesd_param_t::jesd_K
uint8_t jesd_K
Definition: api_def.h:238
AD917X_CHIP_GRADE_REG
#define AD917X_CHIP_GRADE_REG
Definition: ad917x_reg.h:39
AD917X_CH_2
@ AD917X_CH_2
Definition: AD917x.h:55
ad917x_nco_channel_freq_get
int32_t ad917x_nco_channel_freq_get(ad917x_handle_t *h, ad917x_channel_select_t channel, int64_t *carrier_freq_hz)
Get Channel NCO frequency.
Definition: ad917x_nco_api.c:968
AD917X_SYSREF_CTRL_REG
#define AD917X_SYSREF_CTRL_REG
Definition: ad917x_reg.h:59
AD917X_JESD_K_GET
#define AD917X_JESD_K_GET(x)
Definition: ad917x_reg.h:246
gcd
uint32_t gcd(uint32_t x, uint32_t y)
Computes the greatest common divider of two numbers.
Definition: adf4156.c:214
AD9171_ID
#define AD9171_ID
Definition: ad917x_reg.h:28
AD917X_JESD_PARAM_REG_LEN
#define AD917X_JESD_PARAM_REG_LEN
Definition: ad917x_reg.h:243
ad917x_get_chip_id
int32_t ad917x_get_chip_id(ad917x_handle_t *h, adi_chip_id_t *chip_id)
Get Chip Identification Data.
Definition: ad917x_api.c:213
NULL
#define NULL
Definition: wrapper.h:64
REF_CLK_FREQ_MHZ_MAX
#define REF_CLK_FREQ_MHZ_MAX
Definition: ad917x_api.c:28
JESD_LINK_ALL
@ JESD_LINK_ALL
Definition: api_def.h:211
ad917x_nco_set
int32_t ad917x_nco_set(ad917x_handle_t *h, const ad917x_dac_select_t dacs, const ad917x_channel_select_t channels, const int64_t carrier_freq_hz, const uint16_t amplitude, int32_t dc_test_tone_en, int32_t ddsm_cal_dc_input_en)
Set NCO.
Definition: ad917x_nco_api.c:773
LINK_INDEX_MAX
#define LINK_INDEX_MAX
Definition: ad917x_jesd_api.c:24
AD917X_JESD_XBAR_LANE_REG
#define AD917X_JESD_XBAR_LANE_REG
Definition: ad917x_reg.h:235
INTERPOLATION_MIN
#define INTERPOLATION_MIN
Definition: ad917x_jesd_api.c:39
AD917X_JESD_GOOD_CHECKSUM_REG
#define AD917X_JESD_GOOD_CHECKSUM_REG
Definition: ad917x_reg.h:266
ad917x_handle_t::dev_xfer
spi_xfer_t dev_xfer
Definition: AD917x.h:91
AD917X_PLL_VCO_DIV_EN
#define AD917X_PLL_VCO_DIV_EN(x)
Definition: ad917x_reg.h:64
AD917X_X_FTW5_REG
#define AD917X_X_FTW5_REG(x)
Definition: ad917x_reg.h:166
AD917X_DAC0
@ AD917X_DAC0
Definition: AD917x.h:41
AD917X_JESD_LMFC_DELAY1_REG
#define AD917X_JESD_LMFC_DELAY1_REG
Definition: ad917x_reg.h:225
AD917X_JESD_M_GET
#define AD917X_JESD_M_GET(x)
Definition: ad917x_reg.h:247
AD917X_DDSC_NCO_EN
#define AD917X_DDSC_NCO_EN
Definition: ad917x_reg.h:125
AD917X_JESD_INVERT_LANE
#define AD917X_JESD_INVERT_LANE(x)
Definition: ad917x_reg.h:240
adi_chip_id_t
Definition: api_def.h:164
ad917x_get_dac_clk_freq
int32_t ad917x_get_dac_clk_freq(ad917x_handle_t *h, uint64_t *dac_clk_freq_hz)
Get the DAC CLK Frequency.
Definition: ad917x_api.c:462
ad917x_set_dc_cal_tone_amp
int32_t ad917x_set_dc_cal_tone_amp(ad917x_handle_t *h, const uint16_t amp)
Set DC Calibration tone.
Definition: ad917x_nco_api.c:592
ADI_MAXUINT48
#define ADI_MAXUINT48
Definition: api_def.h:21
ad917x_nco_get_phase_offset
int32_t ad917x_nco_get_phase_offset(ad917x_handle_t *h, const ad917x_dac_select_t dacs, uint16_t *dacs_po, const ad917x_channel_select_t channels, uint16_t *ch_po)
Get NCO phase offset.
Definition: ad917x_nco_api.c:312
AD917X_CH_3
@ AD917X_CH_3
Definition: AD917x.h:57
AD917X_SYNCOUTB_CTRL_0_REG
#define AD917X_SYNCOUTB_CTRL_0_REG
Definition: ad917x_reg.h:211
AD917X_JESD_DID_GET
#define AD917X_JESD_DID_GET(x)
Definition: ad917x_reg.h:252
AD917X_X_ACC_MODULUS2_REG
#define AD917X_X_ACC_MODULUS2_REG(x)
Definition: ad917x_reg.h:173
jesd_param_t::jesd_M
uint8_t jesd_M
Definition: api_def.h:234
AD917X_PERIODIC_RST_EN
#define AD917X_PERIODIC_RST_EN
Definition: ad917x_reg.h:53
AD917X_JESD_NP_GET
#define AD917X_JESD_NP_GET(x)
Definition: ad917x_reg.h:249
ad917x_nco_main_freq_get
int32_t ad917x_nco_main_freq_get(ad917x_handle_t *h, ad917x_dac_select_t dac, int64_t *carrier_freq_hz)
Get Main DAC NCO frequency.
Definition: ad917x_nco_api.c:950
ad917x_dc_test_tone_get
int32_t ad917x_dc_test_tone_get(ad917x_handle_t *h, int32_t *dc_test_tone_en)
Get DC Test Tone enable status.
Definition: ad917x_nco_api.c:710
AD917X_DP_INTERP_MODE
#define AD917X_DP_INTERP_MODE(x)
Definition: ad917x_reg.h:86
AD917X_X_ACC_MODULUS0_REG
#define AD917X_X_ACC_MODULUS0_REG(x)
Definition: ad917x_reg.h:171
AD917X_L_DIV
#define AD917X_L_DIV(x)
Definition: ad917x_reg.h:287
API_ERROR_OK
#define API_ERROR_OK
Definition: api_errors.h:25
DLL_CLK_FREQ_THRES_HZ
#define DLL_CLK_FREQ_THRES_HZ
Definition: ad917x_api.c:31
ad917x_handle_t::reset_pin_ctrl
reset_pin_ctrl_t reset_pin_ctrl
Definition: AD917x.h:96
jesd_param_t::jesd_CF
uint8_t jesd_CF
Definition: api_def.h:241
ad917x_handle_t::user_data
void * user_data
Definition: AD917x.h:86
AD917X_JESD_ILS_SCR_L_REG
#define AD917X_JESD_ILS_SCR_L_REG
Definition: ad917x_reg.h:259
JESD_MODE_INVALID
#define JESD_MODE_INVALID
Definition: ad917x_jesd_api.c:46
ad917x_handle_t::syncoutb
signal_type_t syncoutb
Definition: AD917x.h:88
AD917X_XBAR_LANE_ODD
#define AD917X_XBAR_LANE_ODD(x)
Definition: ad917x_reg.h:237
API_ERROR_RESET_PIN_CTRL
#define API_ERROR_RESET_PIN_CTRL
Definition: api_errors.h:55
ad917x_nco_enable
int32_t ad917x_nco_enable(ad917x_handle_t *h, const ad917x_dac_select_t dacs, const ad917x_channel_select_t channels)
NCO Enable.
Definition: ad917x_nco_api.c:625
CH_INTERPOLATION_MAX
#define CH_INTERPOLATION_MAX
Definition: ad917x_jesd_api.c:41
AD917X_SYSREF_ROTATION_REG
#define AD917X_SYSREF_ROTATION_REG
Definition: ad917x_reg.h:50
jesd_link_t
jesd_link_t
Definition: api_def.h:208
AD917X_X_FTW1_REG
#define AD917X_X_FTW1_REG(x)
Definition: ad917x_reg.h:162
AD917X_DDSM_MODULUS_EN
#define AD917X_DDSM_MODULUS_EN
Definition: ad917x_reg.h:91
ad917x_set_dac_pll_config
int32_t ad917x_set_dac_pll_config(ad917x_handle_t *h, uint8_t dac_pll_en, uint8_t m_div, uint8_t n_div, uint8_t vco_div)
Configure the On Chip DAC PLL.
Definition: ad917x_api.c:326
AD917X_DDSM_FTW_LOAD_REQ
#define AD917X_DDSM_FTW_LOAD_REQ
Definition: ad917x_reg.h:98
AD917X_JESD_SCR
#define AD917X_JESD_SCR
Definition: ad917x_reg.h:260
jesd_param_t::jesd_DID
uint8_t jesd_DID
Definition: api_def.h:244
ad917x_register_write
int32_t ad917x_register_write(ad917x_handle_t *h, const uint16_t address, const uint8_t data)
Perform SPI register write access to AD917X Device.
Definition: ad917x_reg.c:23
AD917X_JESD_LMFC_VAR1_REG
#define AD917X_JESD_LMFC_VAR1_REG
Definition: ad917x_reg.h:228
adi_reg_data::reg
uint16_t reg
Definition: api_def.h:158
AD917X_LINK_PAGE
#define AD917X_LINK_PAGE(x)
Definition: ad917x_reg.h:219
adi_chip_id_t::prod_id
uint16_t prod_id
Definition: api_def.h:168
AD917X_JESD_LMFC_DELAY0_REG
#define AD917X_JESD_LMFC_DELAY0_REG
Definition: ad917x_reg.h:224
AD917X_LINK_0_EN
#define AD917X_LINK_0_EN
Definition: ad917x_reg.h:221
ad917x_ddsm_cal_dc_input_get
int32_t ad917x_ddsm_cal_dc_input_get(ad917x_handle_t *h, int32_t *ddsm_cal_dc_input_en)
Get Main DAC Cal DC Input.
Definition: ad917x_nco_api.c:750
ad917x_handle_t
Definition: AD917x.h:85
AD917X_DC_CAL_TONE1_REG
#define AD917X_DC_CAL_TONE1_REG
Definition: ad917x_reg.h:192
AD917X_PROD_ID_LSB_REG
#define AD917X_PROD_ID_LSB_REG
Definition: ad917x_reg.h:37
AD917X_X_ACC_MODULUS5_REG
#define AD917X_X_ACC_MODULUS5_REG(x)
Definition: ad917x_reg.h:176
AD917X_DLL_STATUS_REG
#define AD917X_DLL_STATUS_REG
Definition: ad917x_reg.h:73
ad917x_jesd_enable_link
int32_t ad917x_jesd_enable_link(ad917x_handle_t *h, jesd_link_t link, uint8_t en)
Enable JESD Link.
Definition: ad917x_jesd_api.c:572
AD917X_DDSC_TEST_TONE_EN
#define AD917X_DDSC_TEST_TONE_EN
Definition: ad917x_reg.h:128
SERDES_PWRUP_DELAY
#define SERDES_PWRUP_DELAY
Definition: ad917x_jesd_api.c:21
AD917X_SERDES_PDN
#define AD917X_SERDES_PDN(x)
Definition: ad917x_reg.h:201
AD917X_DLL_LOCK
#define AD917X_DLL_LOCK
Definition: ad917x_reg.h:74
NO_OS_DIV_ROUND_CLOSEST
#define NO_OS_DIV_ROUND_CLOSEST(x, y)
Definition: no_os_util.h:58
ad917x_jesd_config_datapath
int32_t ad917x_jesd_config_datapath(ad917x_handle_t *h, uint8_t dual_en, uint8_t jesd_mode, uint8_t ch_intpl, uint8_t dp_intpl)
Configure the JESD Datapath for AD917X.
Definition: ad917x_jesd_api.c:135
U64MSB
#define U64MSB
Definition: ad9208_adc_api.c:54
AD917X_MAINDAC_PAGE_0
#define AD917X_MAINDAC_PAGE_0
Definition: ad917x_reg.h:47
chip_id
chip_id
Definition: ad9172.h:57
AD917X_LINK_EN
#define AD917X_LINK_EN(x)
Definition: ad917x_reg.h:220
SPI_SDIO
@ SPI_SDIO
Definition: api_def.h:188
jesd_syncoutb_t
jesd_syncoutb_t
Definition: api_def.h:215
ad917x_channel_select_t
ad917x_channel_select_t
Definition: AD917x.h:47
AD917X_X_ACC_DELTA5_REG
#define AD917X_X_ACC_DELTA5_REG(x)
Definition: ad917x_reg.h:183