no-OS
Classes | Macros | Enumerations | Functions
ad9250.h File Reference

Header file of AD9250 Driver. More...

#include <stdint.h>
#include "no_os_spi.h"
Include dependency graph for ad9250.h:
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Classes

struct  ad9250_platform_data
 Platform specific information. More...
 
struct  ad9250_jesd204b_cfg
 JESD204B interface configuration. More...
 
struct  ad9250_fast_detect_cfg
 Fast Detect module configuration. More...
 
struct  ad9250_state
 
struct  ad9250_dev
 
struct  ad9250_init_param
 

Macros

#define AD9250_READ   (1 << 15)
 
#define AD9250_WRITE   (0 << 15)
 
#define AD9250_CNT(x)   ((((x) & 0x3) - 1) << 13)
 
#define AD9250_ADDR(x)   ((x) & 0xFF)
 
#define AD9250_R1B   (1 << 8)
 
#define AD9250_R2B   (2 << 8)
 
#define AD9250_R3B   (3 << 8)
 
#define AD9250_TRANSF_LEN(x)   (((x) >> 8) & 0xFF)
 
#define SHADOW(x)   ((x) << 16)
 
#define AD9250_REG_SPI_CFG   (AD9250_R1B | 0x00)
 
#define AD9250_REG_CHIP_ID   (AD9250_R1B | 0x01)
 
#define AD9250_REG_CHIP_INFO   (AD9250_R1B | 0x02)
 
#define AD9250_REG_CH_INDEX   (AD9250_R1B | 0x05)
 
#define AD9250_REG_DEVICE_UPDATE   (AD9250_R1B | 0xFF)
 
#define AD9250_REG_PDWN   (AD9250_R1B | 0x08)
 
#define AD9250_REG_CLOCK   (AD9250_R1B | 0x09 | SHADOW(1))
 
#define AD9250_REG_PLL_STAT   (AD9250_R1B | 0x0A)
 
#define AD9250_REG_CLOCK_DIV   (AD9250_R1B | 0x0B | SHADOW(2))
 
#define AD9250_REG_TEST   (AD9250_R1B | 0x0D | SHADOW(3))
 
#define AD9250_REG_BIST   (AD9250_R1B | 0x0E | SHADOW(4))
 
#define AD9250_REG_OFFSET   (AD9250_R1B | 0x10 | SHADOW(5))
 
#define AD9250_REG_OUT_MODE   (AD9250_R1B | 0x14 | SHADOW(6))
 
#define AD9250_REG_CML   (AD9250_R1B | 0x15)
 
#define AD9250_REG_VREF   (AD9250_R1B | 0x18 | SHADOW(7))
 
#define AD9250_REG_USER_TEST1   (AD9250_R2B | 0x1A)
 
#define AD9250_REG_USER_TEST2   (AD9250_R2B | 0x1C)
 
#define AD9250_REG_USER_TEST3   (AD9250_R2B | 0x1E)
 
#define AD9250_REG_USER_TEST4   (AD9250_R2B | 0x20)
 
#define AD9250_REG_PLL_ENCODE   (AD9250_R1B | 0x21)
 
#define AD9250_REG_BIST_MISR   (AD9250_R2B | 0x25)
 
#define AD9250_REG_SYS_CTRL   (AD9250_R1B | 0x3A | SHADOW(8))
 
#define AD9250_REG_DCC_CTRL   (AD9250_R1B | 0x40 | SHADOW(9))
 
#define AD9250_REG_DCC_VAL   (AD9250_R2B | 0x42 | SHADOW(10))
 
#define AD9250_REG_FAST_DETECT   (AD9250_R1B | 0x45 | SHADOW(11))
 
#define AD9250_REG_FD_UPPER_THD   (AD9250_R2B | 0x48 | SHADOW(12))
 
#define AD9250_REG_FD_LOWER_THD   (AD9250_R2B | 0x4A | SHADOW(13))
 
#define AD9250_REG_FD_DWELL_TIME   (AD9250_R2B | 0x4C | SHADOW(14))
 
#define AD9250_REG_204B_QUICK_CFG   (AD9250_R1B | 0x5E)
 
#define AD9250_REG_204B_CTRL1   (AD9250_R1B | 0x5F)
 
#define AD9250_REG_204B_CTRL2   (AD9250_R1B | 0x60)
 
#define AD9250_REG_204B_CTRL3   (AD9250_R1B | 0x61)
 
#define AD9250_REG_204B_DID_CFG   (AD9250_R1B | 0x64)
 
#define AD9250_REG_204B_BID_CFG   (AD9250_R1B | 0x65)
 
#define AD9250_REG_204B_LID_CFG0   (AD9250_R1B | 0x66)
 
#define AD9250_REG_204B_LID_CFG1   (AD9250_R1B | 0x67)
 
#define AD9250_REG_204B_PARAM_SCR_L   (AD9250_R1B | 0x6E)
 
#define AD9250_REG_204B_PARAM_F   (AD9250_R1B | 0x6F)
 
#define AD9250_REG_204B_PARAM_K   (AD9250_R1B | 0x70)
 
#define AD9250_REG_204B_PARAM_M   (AD9250_R1B | 0x71)
 
#define AD9250_REG_204B_PARAM_CS_N   (AD9250_R1B | 0x72)
 
#define AD9250_REG_204B_PARAM_NP   (AD9250_R1B | 0x73)
 
#define AD9250_REG_204B_PARAM_S   (AD9250_R1B | 0x74)
 
#define AD9250_REG_204B_PARAM_HD_CF   (AD9250_R1B | 0x75)
 
#define AD9250_REG_204B_RESV1   (AD9250_R1B | 0x76)
 
#define AD9250_REG_204B_RESV2   (AD9250_R1B | 0x77)
 
#define AD9250_REG_204B_CHKSUM0   (AD9250_R1B | 0x79)
 
#define AD9250_REG_204B_CHKSUM1   (AD9250_R1B | 0x7A)
 
#define AD9250_REG_204B_LANE_ASSGN1   (AD9250_R1B | 0x82)
 
#define AD9250_REG_204B_LANE_ASSGN2   (AD9250_R1B | 0x83)
 
#define AD9250_REG_204B_LMFC_OFFSET   (AD9250_R1B | 0x8B)
 
#define AD9250_REG_204B_PRE_EMPHASIS   (AD9250_R1B | 0xA8)
 
#define AD9250_SPI_CFG_LSB_FIRST   ((1 << 6) | (1 << 1))
 
#define AD9250_SPI_CFG_SOFT_RST   ((1 << 5) | (1 << 2))
 
#define AD9250_CH_INDEX_ADC_A   (1 << 0)
 
#define AD9250_CH_INDEX_ADC_B   (1 << 1)
 
#define AD9250_DEVICE_UPDATE_SW   (1 << 0)
 
#define AD9250_PDWN_EXTERN   (1 << 5)
 
#define AD9250_PDWN_JTX   (1 << 4)
 
#define AD9250_PDWN_JESD204B(x)   (((x) & 0x3) << 2)
 
#define AD9250_PDWN_CHIP(x)   (((x) & 0x3) << 0)
 
#define AD9250_CLOCK_SELECTION(x)   (((x) & 0x3) << 4)
 
#define AD9250_CLOCK_DUTY_CYCLE   (1 << 0)
 
#define AD9250_PLL_STAT_LOCKED   (1 << 7)
 
#define AD9250_PLL_STAT_204B_LINK_RDY   (1 << 0)
 
#define AD9250_CLOCK_DIV_PHASE(x)   (((x) & 0x7) << 3)
 
#define AD9250_CLOCK_DIV_RATIO(x)   (((x) & 0x7) << 0)
 
#define AD9250_TEST_USER_TEST_MODE(x)   (((x) & 0x3) << 6)
 
#define AD9250_TEST_RST_PN_LONG   (1 << 5)
 
#define AD9250_TEST_RST_PN_SHOR   (1 << 4)
 
#define AD9250_TEST_OUTPUT_TEST(x)   (((x) & 0xF) << 0)
 
#define AD9250_TEST_OFF   0x00
 
#define AD9250_TEST_MID_SCALE   0x01
 
#define AD9250_TEST_POS_FSCALE   0x02
 
#define AD9250_TEST_NEG_FSCALE   0x03
 
#define AD9250_TEST_CHECKBOARD   0x04
 
#define AD9250_TEST_PNLONG   0x05
 
#define AD9250_TEST_ONE2ZERO   0x07
 
#define AD9250_TEST_PATTERN   0x08
 
#define AD9250_TEST_RAMP   0x0F
 
#define AD9250_BIST_RESET   (1 << 2)
 
#define AD9250_BIST_ENABLE   (1 << 0)
 
#define AD9250_REG_OFFSET_ADJUST(x)   (((x) & 0x3F) << 0)
 
#define AD9250_OUT_MODE_JTX_BIT_ASSIGN(x)   (((x) & 0x7) << 5)
 
#define AD9250_OUT_MODE_DISABLE   (1 << 4)
 
#define AD9250_OUT_MODE_INVERT_DATA   (1 << 3)
 
#define AD9250_OUT_MODE_DATA_FORMAT(x)   (((x) & 0x1) << 0)
 
#define AD9250_OUT_OFFSET_BINARY   0x00
 
#define AD9250_OUT_2S_COMPLEMENT   0x01
 
#define AD9250_CML_DIFF_OUT_LEVEL(x)   (((x) & 0x7) << 0)
 
#define AD9250_VREF_FS_ADJUST(x)   (((x) & 0x1F) << 0)
 
#define AD9250_PLL_ENCODE(x)   (((x) & 0x3) << 3)
 
#define AD9250_SYS_CTRL_REALIGN_ON_SYNCINB   (1 << 4)
 
#define AD9250_SYS_CTRL_REALIGN_ON_SYSREF   (1 << 3)
 
#define AD9250_SYS_CTRL_SYSREF_MODE   (1 << 2)
 
#define AD9250_SYS_CTRL_SYSREF_EN   (1 << 1)
 
#define AD9250_SYS_CTRL_SYNCINB_EN   (1 << 0)
 
#define AD9250_DCC_CTRL_FREEZE_DCC   (1 << 6)
 
#define AD9250_DCC_CTRL_DCC_BW(x)   (((x) & 0xF) << 2)
 
#define AD9250_DCC_CTRL_DCC_EN   (1 << 1)
 
#define AD9250_FAST_DETECT_PIN_FCT   (1 << 4)
 
#define AD9250_FAST_DETECT_FORCE_FDA_FDB_PIN   (1 << 3)
 
#define AD9250_FAST_DETECT_FORCE_FDA_FDB_VAL   (1 << 2)
 
#define AD9250_FAST_DETECT_OUTPUT_ENABLE   (1 << 0)
 
#define AD9250_204B_QUICK_CFG(x)   (((x) & 0xFF) << 0)
 
#define AD9250_204B_CTRL1_TAIL_BITS   (1 << 6)
 
#define AD9250_204B_CTRL1_TEST_SAMPLE_EN   (1 << 5)
 
#define AD9250_204B_CTRL1_ILAS_MODE(x)   (((x) & 0x3) << 2)
 
#define AD9250_204B_CTRL1_POWER_DOWN   (1 << 0)
 
#define AD9250_204B_CTRL2_INVERT_JESD_BITS   (1 << 1)
 
#define AD9250_204B_CTRL3_TEST_DATA_INJ_PT(x)   (((x) & 0x3) << 4)
 
#define AD9250_204B_CTRL3_JESD_TEST_MODE(x)   (((x) & 0xF) << 0)
 
#define AD9250_204B_PARAM_SCR_L_SCRAMBLING   (1 << 7)
 
#define AD9250_204B_PARAM_SCR_L_LANES   (1 << 0)
 
#define AD9250_204B_PARAM_CS_N_NR_CTRL_BITS(x)   (((x) & 0x3) << 6)
 
#define AD9250_204B_PARAM_CS_N_ADC_RESOLUTION(x)   (((x) & 0xF) << 0)
 
#define AD9250_204B_PARAM_NP_JESD_SUBCLASS(x)   (((x) & 0x3) << 5)
 
#define AD9250_204B_PARAM_NP_JESD_N_VAL(x)   (((x) & 0xF) << 0)
 
#define AD9250_204B_PARAM_S(x)   (((x) << 0x1F) << 0)
 
#define AD9250_204B_PARAM_HD_CF_HD_VAL   (1 << 7)
 
#define AD9250_204B_PARAM_HD_CF_CF_VAL(x)   (((x) & 0x1F) << 0)
 
#define AD9250_204B_LANE_ASSGN1(x)   (((x) & 0x3) << 4)
 
#define AD9250_204B_LANE_ASSGN2(x)   (((x) &0x3) << 0)
 
#define AD9250_204B_LMFC_OFFSET(x)   (((x) & 0x1F) << 0)
 

Enumerations

enum  shadow_registers {
  AD6673_SHD_REG_CLOCK = 1,
  AD6673_SHD_REG_CLOCK_DIV,
  AD6673_SHD_REG_TEST,
  AD6673_SHD_REG_BIST,
  AD6673_SHD_REG_OFFSET,
  AD6673_SHD_REG_OUT_MODE,
  AD6673_SHD_REG_VREF,
  AD6673_SHD_REG_SYS_CTRL,
  AD6673_REG_SHD_NSR_CTRL,
  AD6673_REG_SHD_NSR_TUNING,
  AD6673_SHD_REG_DCC_CTRL,
  AD6673_SHD_REG_DCC_VAL,
  AD6673_SHD_REG_FAST_DETECT,
  AD6673_SHD_REG_FD_UPPER_THD,
  AD6673_SHD_REG_FD_LOWER_THD,
  AD6673_SHD_REG_FD_DWELL_TIME,
  SHADOW_REGISTER_COUNT,
  AD9250_SHD_REG_CLOCK = 1,
  AD9250_SHD_REG_CLOCK_DIV,
  AD9250_SHD_REG_TEST,
  AD9250_SHD_REG_BIST,
  AD9250_SHD_REG_OFFSET,
  AD9250_SHD_REG_OUT_MODE,
  AD9250_SHD_REG_VREF,
  AD9250_SHD_REG_SYS_CTRL,
  AD9250_SHD_REG_DCC_CTRL,
  AD9250_SHD_REG_DCC_VAL,
  AD9250_SHD_REG_FAST_DETECT,
  AD9250_SHD_REG_FD_UPPER_THD,
  AD9250_SHD_REG_FD_LOWER_THD,
  AD9250_SHD_REG_FD_DWELL_TIME,
  SHADOW_REGISTER_COUNT
}
 

Functions

int32_t ad9250_setup (struct ad9250_dev **device, struct ad9250_init_param init_param)
 Configures the device. More...
 
int32_t ad9250_remove (struct ad9250_dev *dev)
 Free the resources allocated by ad9250_setup(). More...
 
int32_t ad9250_read (struct ad9250_dev *dev, int32_t register_address)
 Reads the value of the selected register. More...
 
int32_t ad9250_write (struct ad9250_dev *dev, int32_t register_address, int32_t register_value)
 Writes a value to the selected register. More...
 
int32_t ad9250_transfer (struct ad9250_dev *dev)
 Initiates a transfer and waits for the operation to end. Note: This function may be called after a shadowed register was written, so that the internal update can actually take place. More...
 
int32_t ad9250_soft_reset (struct ad9250_dev *dev)
 Resets all registers to their default values. More...
 
int32_t ad9250_chip_pwr_mode (struct ad9250_dev *dev, int32_t mode)
 Configures the power mode of the chip. More...
 
int32_t ad9250_select_channel_for_config (struct ad9250_dev *dev, int32_t channel)
 Selects a channel as the current channel for further configurations. More...
 
int32_t ad9250_test_mode (struct ad9250_dev *dev, int32_t mode)
 Sets the ADC's test mode. More...
 
int32_t ad9250_offset_adj (struct ad9250_dev *dev, int32_t adj)
 Sets the offset adjustment. More...
 
int32_t ad9250_output_disable (struct ad9250_dev *dev, int32_t en)
 Disables (1) or enables (0) the data output. Note: This function modifies a shadowed register, therefore a call of ad9250_transfer() is required for the internal update to take place. More...
 
int32_t ad9250_output_invert (struct ad9250_dev *dev, int32_t invert)
 Activates the inverted (1) or normal (0) output mode. Note: This function modifies a shadowed register, therefore a call of ad9250_transfer() is required for the internal update to take place. More...
 
int32_t ad9250_output_format (struct ad9250_dev *dev, int32_t format)
 Specifies the output format. Note: This function modifies a shadowed register, therefore a call of ad9250_transfer() is required for the internal update to take place. More...
 
int32_t ad9250_reset_PN29 (struct ad9250_dev *dev, int32_t rst)
 
int32_t ad9250_reset_pn23 (struct ad9250_dev *dev, int32_t rst)
 Sets (1) or clears (0) the reset long PN sequence bit(PN23). More...
 
int32_t ad9250_set_user_pattern (struct ad9250_dev *dev, int32_t pattern_no, int32_t user_pattern)
 Configures a User Test Pattern. More...
 
int32_t ad9250_bist_enable (struct ad9250_dev *dev, int32_t enable)
 Enables the Build-In-Self-Test. More...
 
int32_t ad9250_bist_reset (struct ad9250_dev *dev, int32_t reset)
 Resets the Build-In-Self-Test. More...
 
int32_t ad9250_jesd204b_setup (struct ad9250_dev *dev)
 Configures the JESD204B interface. More...
 
int32_t ad9250_jesd204b_pwr_mode (struct ad9250_dev *dev, int32_t mode)
 Configures the power mode of the JESD204B data transmit block. More...
 
int32_t ad9250_jesd204b_select_test_injection_point (struct ad9250_dev *dev, int32_t inj_point)
 Selects the point in the processing path of a lane, where the test data will be inserted. More...
 
int32_t ad9250_jesd204b_test_mode (struct ad9250_dev *dev, int32_t test_mode)
 Selects a JESD204B test mode. More...
 
int32_t ad9250_jesd204b_invert_logic (struct ad9250_dev *dev, int32_t invert)
 Inverts the logic of JESD204B bits. More...
 
int32_t ad9250_fast_detect_setup (struct ad9250_dev *dev)
 Configures the Fast-Detect module. More...
 
int32_t ad9250_dcc_enable (struct ad9250_dev *dev, int32_t enable)
 Enables DC correction for use in the output data signal path. More...
 
int32_t ad9250_dcc_bandwidth (struct ad9250_dev *dev, int32_t bw)
 Selects the bandwidth value for the DC correction circuit. More...
 
int32_t ad9250_dcc_freeze (struct ad9250_dev *dev, int32_t freeze)
 Freezes DC correction value. More...
 

Detailed Description

Header file of AD9250 Driver.

Author
DNechita (Dan.N.nosp@m.echi.nosp@m.ta@an.nosp@m.alog.nosp@m..com)

Copyright 2013(c) Analog Devices, Inc.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ AD9250_204B_CTRL1_ILAS_MODE

#define AD9250_204B_CTRL1_ILAS_MODE (   x)    (((x) & 0x3) << 2)

◆ AD9250_204B_CTRL1_POWER_DOWN

#define AD9250_204B_CTRL1_POWER_DOWN   (1 << 0)

◆ AD9250_204B_CTRL1_TAIL_BITS

#define AD9250_204B_CTRL1_TAIL_BITS   (1 << 6)

◆ AD9250_204B_CTRL1_TEST_SAMPLE_EN

#define AD9250_204B_CTRL1_TEST_SAMPLE_EN   (1 << 5)

◆ AD9250_204B_CTRL2_INVERT_JESD_BITS

#define AD9250_204B_CTRL2_INVERT_JESD_BITS   (1 << 1)

◆ AD9250_204B_CTRL3_JESD_TEST_MODE

#define AD9250_204B_CTRL3_JESD_TEST_MODE (   x)    (((x) & 0xF) << 0)

◆ AD9250_204B_CTRL3_TEST_DATA_INJ_PT

#define AD9250_204B_CTRL3_TEST_DATA_INJ_PT (   x)    (((x) & 0x3) << 4)

◆ AD9250_204B_LANE_ASSGN1

#define AD9250_204B_LANE_ASSGN1 (   x)    (((x) & 0x3) << 4)

◆ AD9250_204B_LANE_ASSGN2

#define AD9250_204B_LANE_ASSGN2 (   x)    (((x) &0x3) << 0)

◆ AD9250_204B_LMFC_OFFSET

#define AD9250_204B_LMFC_OFFSET (   x)    (((x) & 0x1F) << 0)

◆ AD9250_204B_PARAM_CS_N_ADC_RESOLUTION

#define AD9250_204B_PARAM_CS_N_ADC_RESOLUTION (   x)    (((x) & 0xF) << 0)

◆ AD9250_204B_PARAM_CS_N_NR_CTRL_BITS

#define AD9250_204B_PARAM_CS_N_NR_CTRL_BITS (   x)    (((x) & 0x3) << 6)

◆ AD9250_204B_PARAM_HD_CF_CF_VAL

#define AD9250_204B_PARAM_HD_CF_CF_VAL (   x)    (((x) & 0x1F) << 0)

◆ AD9250_204B_PARAM_HD_CF_HD_VAL

#define AD9250_204B_PARAM_HD_CF_HD_VAL   (1 << 7)

◆ AD9250_204B_PARAM_NP_JESD_N_VAL

#define AD9250_204B_PARAM_NP_JESD_N_VAL (   x)    (((x) & 0xF) << 0)

◆ AD9250_204B_PARAM_NP_JESD_SUBCLASS

#define AD9250_204B_PARAM_NP_JESD_SUBCLASS (   x)    (((x) & 0x3) << 5)

◆ AD9250_204B_PARAM_S

#define AD9250_204B_PARAM_S (   x)    (((x) << 0x1F) << 0)

◆ AD9250_204B_PARAM_SCR_L_LANES

#define AD9250_204B_PARAM_SCR_L_LANES   (1 << 0)

◆ AD9250_204B_PARAM_SCR_L_SCRAMBLING

#define AD9250_204B_PARAM_SCR_L_SCRAMBLING   (1 << 7)

◆ AD9250_204B_QUICK_CFG

#define AD9250_204B_QUICK_CFG (   x)    (((x) & 0xFF) << 0)

◆ AD9250_ADDR

#define AD9250_ADDR (   x)    ((x) & 0xFF)

◆ AD9250_BIST_ENABLE

#define AD9250_BIST_ENABLE   (1 << 0)

◆ AD9250_BIST_RESET

#define AD9250_BIST_RESET   (1 << 2)

◆ AD9250_CH_INDEX_ADC_A

#define AD9250_CH_INDEX_ADC_A   (1 << 0)

◆ AD9250_CH_INDEX_ADC_B

#define AD9250_CH_INDEX_ADC_B   (1 << 1)

◆ AD9250_CLOCK_DIV_PHASE

#define AD9250_CLOCK_DIV_PHASE (   x)    (((x) & 0x7) << 3)

◆ AD9250_CLOCK_DIV_RATIO

#define AD9250_CLOCK_DIV_RATIO (   x)    (((x) & 0x7) << 0)

◆ AD9250_CLOCK_DUTY_CYCLE

#define AD9250_CLOCK_DUTY_CYCLE   (1 << 0)

◆ AD9250_CLOCK_SELECTION

#define AD9250_CLOCK_SELECTION (   x)    (((x) & 0x3) << 4)

◆ AD9250_CML_DIFF_OUT_LEVEL

#define AD9250_CML_DIFF_OUT_LEVEL (   x)    (((x) & 0x7) << 0)

◆ AD9250_CNT

#define AD9250_CNT (   x)    ((((x) & 0x3) - 1) << 13)

◆ AD9250_DCC_CTRL_DCC_BW

#define AD9250_DCC_CTRL_DCC_BW (   x)    (((x) & 0xF) << 2)

◆ AD9250_DCC_CTRL_DCC_EN

#define AD9250_DCC_CTRL_DCC_EN   (1 << 1)

◆ AD9250_DCC_CTRL_FREEZE_DCC

#define AD9250_DCC_CTRL_FREEZE_DCC   (1 << 6)

◆ AD9250_DEVICE_UPDATE_SW

#define AD9250_DEVICE_UPDATE_SW   (1 << 0)

◆ AD9250_FAST_DETECT_FORCE_FDA_FDB_PIN

#define AD9250_FAST_DETECT_FORCE_FDA_FDB_PIN   (1 << 3)

◆ AD9250_FAST_DETECT_FORCE_FDA_FDB_VAL

#define AD9250_FAST_DETECT_FORCE_FDA_FDB_VAL   (1 << 2)

◆ AD9250_FAST_DETECT_OUTPUT_ENABLE

#define AD9250_FAST_DETECT_OUTPUT_ENABLE   (1 << 0)

◆ AD9250_FAST_DETECT_PIN_FCT

#define AD9250_FAST_DETECT_PIN_FCT   (1 << 4)

◆ AD9250_OUT_2S_COMPLEMENT

#define AD9250_OUT_2S_COMPLEMENT   0x01

◆ AD9250_OUT_MODE_DATA_FORMAT

#define AD9250_OUT_MODE_DATA_FORMAT (   x)    (((x) & 0x1) << 0)

◆ AD9250_OUT_MODE_DISABLE

#define AD9250_OUT_MODE_DISABLE   (1 << 4)

◆ AD9250_OUT_MODE_INVERT_DATA

#define AD9250_OUT_MODE_INVERT_DATA   (1 << 3)

◆ AD9250_OUT_MODE_JTX_BIT_ASSIGN

#define AD9250_OUT_MODE_JTX_BIT_ASSIGN (   x)    (((x) & 0x7) << 5)

◆ AD9250_OUT_OFFSET_BINARY

#define AD9250_OUT_OFFSET_BINARY   0x00

◆ AD9250_PDWN_CHIP

#define AD9250_PDWN_CHIP (   x)    (((x) & 0x3) << 0)

◆ AD9250_PDWN_EXTERN

#define AD9250_PDWN_EXTERN   (1 << 5)

◆ AD9250_PDWN_JESD204B

#define AD9250_PDWN_JESD204B (   x)    (((x) & 0x3) << 2)

◆ AD9250_PDWN_JTX

#define AD9250_PDWN_JTX   (1 << 4)

◆ AD9250_PLL_ENCODE

#define AD9250_PLL_ENCODE (   x)    (((x) & 0x3) << 3)

◆ AD9250_PLL_STAT_204B_LINK_RDY

#define AD9250_PLL_STAT_204B_LINK_RDY   (1 << 0)

◆ AD9250_PLL_STAT_LOCKED

#define AD9250_PLL_STAT_LOCKED   (1 << 7)

◆ AD9250_R1B

#define AD9250_R1B   (1 << 8)

◆ AD9250_R2B

#define AD9250_R2B   (2 << 8)

◆ AD9250_R3B

#define AD9250_R3B   (3 << 8)

◆ AD9250_READ

#define AD9250_READ   (1 << 15)

◆ AD9250_REG_204B_BID_CFG

#define AD9250_REG_204B_BID_CFG   (AD9250_R1B | 0x65)

◆ AD9250_REG_204B_CHKSUM0

#define AD9250_REG_204B_CHKSUM0   (AD9250_R1B | 0x79)

◆ AD9250_REG_204B_CHKSUM1

#define AD9250_REG_204B_CHKSUM1   (AD9250_R1B | 0x7A)

◆ AD9250_REG_204B_CTRL1

#define AD9250_REG_204B_CTRL1   (AD9250_R1B | 0x5F)

◆ AD9250_REG_204B_CTRL2

#define AD9250_REG_204B_CTRL2   (AD9250_R1B | 0x60)

◆ AD9250_REG_204B_CTRL3

#define AD9250_REG_204B_CTRL3   (AD9250_R1B | 0x61)

◆ AD9250_REG_204B_DID_CFG

#define AD9250_REG_204B_DID_CFG   (AD9250_R1B | 0x64)

◆ AD9250_REG_204B_LANE_ASSGN1

#define AD9250_REG_204B_LANE_ASSGN1   (AD9250_R1B | 0x82)

◆ AD9250_REG_204B_LANE_ASSGN2

#define AD9250_REG_204B_LANE_ASSGN2   (AD9250_R1B | 0x83)

◆ AD9250_REG_204B_LID_CFG0

#define AD9250_REG_204B_LID_CFG0   (AD9250_R1B | 0x66)

◆ AD9250_REG_204B_LID_CFG1

#define AD9250_REG_204B_LID_CFG1   (AD9250_R1B | 0x67)

◆ AD9250_REG_204B_LMFC_OFFSET

#define AD9250_REG_204B_LMFC_OFFSET   (AD9250_R1B | 0x8B)

◆ AD9250_REG_204B_PARAM_CS_N

#define AD9250_REG_204B_PARAM_CS_N   (AD9250_R1B | 0x72)

◆ AD9250_REG_204B_PARAM_F

#define AD9250_REG_204B_PARAM_F   (AD9250_R1B | 0x6F)

◆ AD9250_REG_204B_PARAM_HD_CF

#define AD9250_REG_204B_PARAM_HD_CF   (AD9250_R1B | 0x75)

◆ AD9250_REG_204B_PARAM_K

#define AD9250_REG_204B_PARAM_K   (AD9250_R1B | 0x70)

◆ AD9250_REG_204B_PARAM_M

#define AD9250_REG_204B_PARAM_M   (AD9250_R1B | 0x71)

◆ AD9250_REG_204B_PARAM_NP

#define AD9250_REG_204B_PARAM_NP   (AD9250_R1B | 0x73)

◆ AD9250_REG_204B_PARAM_S

#define AD9250_REG_204B_PARAM_S   (AD9250_R1B | 0x74)

◆ AD9250_REG_204B_PARAM_SCR_L

#define AD9250_REG_204B_PARAM_SCR_L   (AD9250_R1B | 0x6E)

◆ AD9250_REG_204B_PRE_EMPHASIS

#define AD9250_REG_204B_PRE_EMPHASIS   (AD9250_R1B | 0xA8)

◆ AD9250_REG_204B_QUICK_CFG

#define AD9250_REG_204B_QUICK_CFG   (AD9250_R1B | 0x5E)

◆ AD9250_REG_204B_RESV1

#define AD9250_REG_204B_RESV1   (AD9250_R1B | 0x76)

◆ AD9250_REG_204B_RESV2

#define AD9250_REG_204B_RESV2   (AD9250_R1B | 0x77)

◆ AD9250_REG_BIST

#define AD9250_REG_BIST   (AD9250_R1B | 0x0E | SHADOW(4))

◆ AD9250_REG_BIST_MISR

#define AD9250_REG_BIST_MISR   (AD9250_R2B | 0x25)

◆ AD9250_REG_CH_INDEX

#define AD9250_REG_CH_INDEX   (AD9250_R1B | 0x05)

◆ AD9250_REG_CHIP_ID

#define AD9250_REG_CHIP_ID   (AD9250_R1B | 0x01)

◆ AD9250_REG_CHIP_INFO

#define AD9250_REG_CHIP_INFO   (AD9250_R1B | 0x02)

◆ AD9250_REG_CLOCK

#define AD9250_REG_CLOCK   (AD9250_R1B | 0x09 | SHADOW(1))

◆ AD9250_REG_CLOCK_DIV

#define AD9250_REG_CLOCK_DIV   (AD9250_R1B | 0x0B | SHADOW(2))

◆ AD9250_REG_CML

#define AD9250_REG_CML   (AD9250_R1B | 0x15)

◆ AD9250_REG_DCC_CTRL

#define AD9250_REG_DCC_CTRL   (AD9250_R1B | 0x40 | SHADOW(9))

◆ AD9250_REG_DCC_VAL

#define AD9250_REG_DCC_VAL   (AD9250_R2B | 0x42 | SHADOW(10))

◆ AD9250_REG_DEVICE_UPDATE

#define AD9250_REG_DEVICE_UPDATE   (AD9250_R1B | 0xFF)

◆ AD9250_REG_FAST_DETECT

#define AD9250_REG_FAST_DETECT   (AD9250_R1B | 0x45 | SHADOW(11))

◆ AD9250_REG_FD_DWELL_TIME

#define AD9250_REG_FD_DWELL_TIME   (AD9250_R2B | 0x4C | SHADOW(14))

◆ AD9250_REG_FD_LOWER_THD

#define AD9250_REG_FD_LOWER_THD   (AD9250_R2B | 0x4A | SHADOW(13))

◆ AD9250_REG_FD_UPPER_THD

#define AD9250_REG_FD_UPPER_THD   (AD9250_R2B | 0x48 | SHADOW(12))

◆ AD9250_REG_OFFSET

#define AD9250_REG_OFFSET   (AD9250_R1B | 0x10 | SHADOW(5))

◆ AD9250_REG_OFFSET_ADJUST

#define AD9250_REG_OFFSET_ADJUST (   x)    (((x) & 0x3F) << 0)

◆ AD9250_REG_OUT_MODE

#define AD9250_REG_OUT_MODE   (AD9250_R1B | 0x14 | SHADOW(6))

◆ AD9250_REG_PDWN

#define AD9250_REG_PDWN   (AD9250_R1B | 0x08)

◆ AD9250_REG_PLL_ENCODE

#define AD9250_REG_PLL_ENCODE   (AD9250_R1B | 0x21)

◆ AD9250_REG_PLL_STAT

#define AD9250_REG_PLL_STAT   (AD9250_R1B | 0x0A)

◆ AD9250_REG_SPI_CFG

#define AD9250_REG_SPI_CFG   (AD9250_R1B | 0x00)

◆ AD9250_REG_SYS_CTRL

#define AD9250_REG_SYS_CTRL   (AD9250_R1B | 0x3A | SHADOW(8))

◆ AD9250_REG_TEST

#define AD9250_REG_TEST   (AD9250_R1B | 0x0D | SHADOW(3))

◆ AD9250_REG_USER_TEST1

#define AD9250_REG_USER_TEST1   (AD9250_R2B | 0x1A)

◆ AD9250_REG_USER_TEST2

#define AD9250_REG_USER_TEST2   (AD9250_R2B | 0x1C)

◆ AD9250_REG_USER_TEST3

#define AD9250_REG_USER_TEST3   (AD9250_R2B | 0x1E)

◆ AD9250_REG_USER_TEST4

#define AD9250_REG_USER_TEST4   (AD9250_R2B | 0x20)

◆ AD9250_REG_VREF

#define AD9250_REG_VREF   (AD9250_R1B | 0x18 | SHADOW(7))

◆ AD9250_SPI_CFG_LSB_FIRST

#define AD9250_SPI_CFG_LSB_FIRST   ((1 << 6) | (1 << 1))

◆ AD9250_SPI_CFG_SOFT_RST

#define AD9250_SPI_CFG_SOFT_RST   ((1 << 5) | (1 << 2))

◆ AD9250_SYS_CTRL_REALIGN_ON_SYNCINB

#define AD9250_SYS_CTRL_REALIGN_ON_SYNCINB   (1 << 4)

◆ AD9250_SYS_CTRL_REALIGN_ON_SYSREF

#define AD9250_SYS_CTRL_REALIGN_ON_SYSREF   (1 << 3)

◆ AD9250_SYS_CTRL_SYNCINB_EN

#define AD9250_SYS_CTRL_SYNCINB_EN   (1 << 0)

◆ AD9250_SYS_CTRL_SYSREF_EN

#define AD9250_SYS_CTRL_SYSREF_EN   (1 << 1)

◆ AD9250_SYS_CTRL_SYSREF_MODE

#define AD9250_SYS_CTRL_SYSREF_MODE   (1 << 2)

◆ AD9250_TEST_CHECKBOARD

#define AD9250_TEST_CHECKBOARD   0x04

◆ AD9250_TEST_MID_SCALE

#define AD9250_TEST_MID_SCALE   0x01

◆ AD9250_TEST_NEG_FSCALE

#define AD9250_TEST_NEG_FSCALE   0x03

◆ AD9250_TEST_OFF

#define AD9250_TEST_OFF   0x00

◆ AD9250_TEST_ONE2ZERO

#define AD9250_TEST_ONE2ZERO   0x07

◆ AD9250_TEST_OUTPUT_TEST

#define AD9250_TEST_OUTPUT_TEST (   x)    (((x) & 0xF) << 0)

◆ AD9250_TEST_PATTERN

#define AD9250_TEST_PATTERN   0x08

◆ AD9250_TEST_PNLONG

#define AD9250_TEST_PNLONG   0x05

◆ AD9250_TEST_POS_FSCALE

#define AD9250_TEST_POS_FSCALE   0x02

◆ AD9250_TEST_RAMP

#define AD9250_TEST_RAMP   0x0F

◆ AD9250_TEST_RST_PN_LONG

#define AD9250_TEST_RST_PN_LONG   (1 << 5)

◆ AD9250_TEST_RST_PN_SHOR

#define AD9250_TEST_RST_PN_SHOR   (1 << 4)

◆ AD9250_TEST_USER_TEST_MODE

#define AD9250_TEST_USER_TEST_MODE (   x)    (((x) & 0x3) << 6)

◆ AD9250_TRANSF_LEN

#define AD9250_TRANSF_LEN (   x)    (((x) >> 8) & 0xFF)

◆ AD9250_VREF_FS_ADJUST

#define AD9250_VREF_FS_ADJUST (   x)    (((x) & 0x1F) << 0)

◆ AD9250_WRITE

#define AD9250_WRITE   (0 << 15)

◆ SHADOW

#define SHADOW (   x)    ((x) << 16)

Enumeration Type Documentation

◆ shadow_registers

Enumerator
AD6673_SHD_REG_CLOCK 
AD6673_SHD_REG_CLOCK_DIV 
AD6673_SHD_REG_TEST 
AD6673_SHD_REG_BIST 
AD6673_SHD_REG_OFFSET 
AD6673_SHD_REG_OUT_MODE 
AD6673_SHD_REG_VREF 
AD6673_SHD_REG_SYS_CTRL 
AD6673_REG_SHD_NSR_CTRL 
AD6673_REG_SHD_NSR_TUNING 
AD6673_SHD_REG_DCC_CTRL 
AD6673_SHD_REG_DCC_VAL 
AD6673_SHD_REG_FAST_DETECT 
AD6673_SHD_REG_FD_UPPER_THD 
AD6673_SHD_REG_FD_LOWER_THD 
AD6673_SHD_REG_FD_DWELL_TIME 
SHADOW_REGISTER_COUNT 
AD9250_SHD_REG_CLOCK 
AD9250_SHD_REG_CLOCK_DIV 
AD9250_SHD_REG_TEST 
AD9250_SHD_REG_BIST 
AD9250_SHD_REG_OFFSET 
AD9250_SHD_REG_OUT_MODE 
AD9250_SHD_REG_VREF 
AD9250_SHD_REG_SYS_CTRL 
AD9250_SHD_REG_DCC_CTRL 
AD9250_SHD_REG_DCC_VAL 
AD9250_SHD_REG_FAST_DETECT 
AD9250_SHD_REG_FD_UPPER_THD 
AD9250_SHD_REG_FD_LOWER_THD 
AD9250_SHD_REG_FD_DWELL_TIME 
SHADOW_REGISTER_COUNT 

Function Documentation

◆ ad9250_bist_enable()

int32_t ad9250_bist_enable ( struct ad9250_dev dev,
int32_t  enable 
)

Enables the Build-In-Self-Test.

Enables the Build-In-Self-Test.

Parameters
dev- The device structure.
enable- enable option.
Returns
Returns negative error code or the state of the enable bit.

◆ ad9250_bist_reset()

int32_t ad9250_bist_reset ( struct ad9250_dev dev,
int32_t  reset 
)

Resets the Build-In-Self-Test.

Resets the Build-In-Self-Test.

Parameters
dev- The device structure.
reset- reset option.
Returns
Returns negative error code or the state of the reset bit.

◆ ad9250_chip_pwr_mode()

int32_t ad9250_chip_pwr_mode ( struct ad9250_dev dev,
int32_t  mode 
)

Configures the power mode of the chip.

Configures the power mode of the chip.

Parameters
dev- The device structure.
mode- The power mode. Example: 00 � normal operation(default); 01 � power-down; 10 - standby.
Returns
Returns negative error code or the set power mode.

◆ ad9250_dcc_bandwidth()

int32_t ad9250_dcc_bandwidth ( struct ad9250_dev dev,
int32_t  bw 
)

Selects the bandwidth value for the DC correction circuit.

Selects the bandwidth value for the DC correction circuit.

Parameters
dev- The device structure.
bw- DC correction bandwidth. Example: 0 - 2387.32 Hz at Sample Rate of 245.76 MSPS 1 - 1193.66 Hz at Sample Rate of 245.76 MSPS ... 13 - 0.29 Hz at Sample Rate of 245.76 MSPS
Returns
Returns negative error code or the state of the bandwidth bits.

◆ ad9250_dcc_enable()

int32_t ad9250_dcc_enable ( struct ad9250_dev dev,
int32_t  enable 
)

Enables DC correction for use in the output data signal path.

Enables DC correction for use in the output data signal path.

Parameters
dev- The device structure.
enable- enable option. Example: 0 - correction off 1 - correction on
Returns
Returns negative error code or the status of the enable bit.

◆ ad9250_dcc_freeze()

int32_t ad9250_dcc_freeze ( struct ad9250_dev dev,
int32_t  freeze 
)

Freezes DC correction value.

Freezes DC correction value.

Parameters
dev- The device structure.
freeze- freeze option. Example: 0 - calculates the correction value 1 - freezes the DC correction at its current state
Returns
Returns negative error code or the status of the freeze bit.

◆ ad9250_fast_detect_setup()

int32_t ad9250_fast_detect_setup ( struct ad9250_dev dev)

Configures the Fast-Detect module.

Configures the Fast-Detect module.

Parameters
dev- The device structure.
Returns
Returns negative error code or 0 in case of success.
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◆ ad9250_jesd204b_invert_logic()

int32_t ad9250_jesd204b_invert_logic ( struct ad9250_dev dev,
int32_t  invert 
)

Inverts the logic of JESD204B bits.

Inverts the logic of JESD204B bits.

Parameters
dev- The device structure.
invert- Invert option. Example: 1 - Activates the inverted mode 0 - Activates the normal mode
Returns
Returns negative error code or the set mode.
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◆ ad9250_jesd204b_pwr_mode()

int32_t ad9250_jesd204b_pwr_mode ( struct ad9250_dev dev,
int32_t  mode 
)

Configures the power mode of the JESD204B data transmit block.

Configures the power mode of the JESD204B data transmit block.

Parameters
dev- The device structure.
mode- The power mode. Example: 00 � normal operation(default); 01 � power-down; 10 - standby.
Returns
Returns negative error code or the set power mode.

◆ ad9250_jesd204b_select_test_injection_point()

int32_t ad9250_jesd204b_select_test_injection_point ( struct ad9250_dev dev,
int32_t  inj_point 
)

Selects the point in the processing path of a lane, where the test data will be inserted.

Selects the point in the processing path of a lane, where the test data will be inserted.

Parameters
dev- The device structure.
inj_point- The point in the processing path of a lane. Example: 1 - a 10-bit data is inserted at 8B/10B ENCODER output 2 - a 8-bit at scrambler input
Returns
Returns negative error code or the status of the data injection point bit.

◆ ad9250_jesd204b_setup()

int32_t ad9250_jesd204b_setup ( struct ad9250_dev dev)

Configures the JESD204B interface.

Configures the JESD204B interface.

Parameters
dev- The device structure.
Returns
Returns negative error code or 0 in case of success.
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◆ ad9250_jesd204b_test_mode()

int32_t ad9250_jesd204b_test_mode ( struct ad9250_dev dev,
int32_t  test_mode 
)

Selects a JESD204B test mode.

Selects a JESD204B test mode.

Parameters
dev- The device structure.
test_mode- mode option. Example: 0 - test mode disabled 1 - alternating checker board 2 - 1/0 word toggle 3 - PN23 sequence 4 - PN9 sequence 5 - continuous/repeat user test mode 6 - single user test mode 7 - reserved 8 - modified RPAT test sequence 12 - PN7 sequence 13 - PN15 sequence
Returns
Returns the set test mode or negative error code.

◆ ad9250_offset_adj()

int32_t ad9250_offset_adj ( struct ad9250_dev dev,
int32_t  adj 
)

Sets the offset adjustment.

Sets the offset adjustment.

Parameters
dev- The device structure.
adj- The offset adjust value in LSBs from +31 to -32.
Returns
Returns negative error code or the set offset adjustment.

◆ ad9250_output_disable()

int32_t ad9250_output_disable ( struct ad9250_dev dev,
int32_t  en 
)

Disables (1) or enables (0) the data output. Note: This function modifies a shadowed register, therefore a call of ad9250_transfer() is required for the internal update to take place.

Disables (1) or enables (0) the data output.

Parameters
dev- The device structure.
en- Enable option. Example: 1 - Disables the data output; 0 - Enables the data output(default).
Returns
Returns negative error code or the output disable state.

◆ ad9250_output_format()

int32_t ad9250_output_format ( struct ad9250_dev dev,
int32_t  format 
)

Specifies the output format. Note: This function modifies a shadowed register, therefore a call of ad9250_transfer() is required for the internal update to take place.

Specifies the output format.

Parameters
dev- The device structure.
format- The output format. Example: 0 � offset binary(default); 1 � two's complement;
Returns
Returns negative error code or the set output format.
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◆ ad9250_output_invert()

int32_t ad9250_output_invert ( struct ad9250_dev dev,
int32_t  invert 
)

Activates the inverted (1) or normal (0) output mode. Note: This function modifies a shadowed register, therefore a call of ad9250_transfer() is required for the internal update to take place.

Activates the inverted (1) or normal (0) output mode.

Parameters
dev- The device structure.
invert- Invert option. Example: 1 - Activates the inverted output mode; 0 - Activates the normal output mode(default).
Returns
Returns negative error code or the set output mode.

◆ ad9250_read()

int32_t ad9250_read ( struct ad9250_dev dev,
int32_t  register_address 
)

Reads the value of the selected register.

Reads the value of the selected register.

Parameters
dev- The device structure.
register_address- The address of the register to read.
Returns
reg_value - The register's value or negative error code.
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◆ ad9250_remove()

int32_t ad9250_remove ( struct ad9250_dev dev)

Free the resources allocated by ad9250_setup().

Free the resources allocated by ad9250_setup().

Parameters
dev- The device structure.
Returns
0 in case of success, negative error code otherwise.

◆ ad9250_reset_pn23()

int32_t ad9250_reset_pn23 ( struct ad9250_dev dev,
int32_t  rst 
)

Sets (1) or clears (0) the reset long PN sequence bit(PN23).

Sets (1) or clears (0) the reset long PN sequence bit(PN23).

Parameters
dev- The device structure.
rst- Enable option. Example: 1 - The PN sequence is held in reset; 0 - The PN sequence resumes from the seed value(0x3AFF).
Returns
Returns negative error code or the set PN23 status.

◆ ad9250_reset_PN29()

int32_t ad9250_reset_PN29 ( struct ad9250_dev dev,
int32_t  rst 
)

Sets (1) or clears (0) the reset short PN sequence bit(PN9).

◆ ad9250_select_channel_for_config()

int32_t ad9250_select_channel_for_config ( struct ad9250_dev dev,
int32_t  channel 
)

Selects a channel as the current channel for further configurations.

Selects a channel as the current channel for further configurations.

Parameters
dev- The device structure.
channel- Channel option. Example 1 - channel A 2 - channel B 3 - channel A and channel B
Returns
Returns negative error code or the selected channel.

◆ ad9250_set_user_pattern()

int32_t ad9250_set_user_pattern ( struct ad9250_dev dev,
int32_t  pattern_no,
int32_t  user_pattern 
)

Configures a User Test Pattern.

Configures a User Test Pattern.

Parameters
dev- The device structure.
pattern_no- Selects the patterns to be configured. Range 1..4.
user_pattern- Users's pattern.
Returns
Returns negative error code or the selected user pattern.

◆ ad9250_setup()

int32_t ad9250_setup ( struct ad9250_dev **  device,
struct ad9250_init_param  init_param 
)

Configures the device.

Configures the device.

Parameters
device- The device structure.
init_param- The structure that contains the device initial parameters.
Returns
Returns negative error code or 0 in case of success.
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◆ ad9250_soft_reset()

int32_t ad9250_soft_reset ( struct ad9250_dev dev)

Resets all registers to their default values.

Resets all registers to their default values.

Parameters
dev- The device structure.
Returns
Returns negative error code or 0 in case of success.
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◆ ad9250_test_mode()

int32_t ad9250_test_mode ( struct ad9250_dev dev,
int32_t  mode 
)

Sets the ADC's test mode.

Sets the ADC's test mode.

Parameters
dev- The device structure.
mode- ADC test mode. Example: 0 -> off(default) 1 -> midscale short 2 -> +FS short 3 -> -FS short 4 -> checkerboard output 5 -> PN sequence long 6 -> PN 9 short 7 -> one/zero word toggle 8 -> user test mode 9 to 14 -> unused 15 -> ramp output
Returns
Returns the set test mode or negative error code.
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◆ ad9250_transfer()

int32_t ad9250_transfer ( struct ad9250_dev dev)

Initiates a transfer and waits for the operation to end. Note: This function may be called after a shadowed register was written, so that the internal update can actually take place.

Initiates a transfer and waits for the operation to end.

Parameters
dev- The device structure.
Returns
Negative error code or 0 in case of success.
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◆ ad9250_write()

int32_t ad9250_write ( struct ad9250_dev dev,
int32_t  register_address,
int32_t  register_value 
)

Writes a value to the selected register.

Writes a value to the selected register.

Parameters
dev- The device structure.
register_address- The address of the register to write to.
register_value- The value to write to the register.
Returns
Returns 0 in case of success or negative error code.
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