no-OS
ad9250.h
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1 /***************************************************************************/
39 #ifndef __AD9250_H__
40 #define __AD9250_H__
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include <stdint.h>
46 #include "no_os_spi.h"
47 
48 /******************************************************************************/
49 /*********************************** AD9250 ***********************************/
50 /******************************************************************************/
51 
52 /* Registers */
53 
54 #define AD9250_READ (1 << 15)
55 #define AD9250_WRITE (0 << 15)
56 #define AD9250_CNT(x) ((((x) & 0x3) - 1) << 13)
57 #define AD9250_ADDR(x) ((x) & 0xFF)
58 
59 #define AD9250_R1B (1 << 8)
60 #define AD9250_R2B (2 << 8)
61 #define AD9250_R3B (3 << 8)
62 #define AD9250_TRANSF_LEN(x) (((x) >> 8) & 0xFF)
63 #define SHADOW(x) ((x) << 16)
64 
65 /* Chip configuration registers */
66 #define AD9250_REG_SPI_CFG (AD9250_R1B | 0x00)
67 #define AD9250_REG_CHIP_ID (AD9250_R1B | 0x01)
68 #define AD9250_REG_CHIP_INFO (AD9250_R1B | 0x02)
69 
70 /* Channel index and transfer registers */
71 #define AD9250_REG_CH_INDEX (AD9250_R1B | 0x05)
72 #define AD9250_REG_DEVICE_UPDATE (AD9250_R1B | 0xFF)
73 
74 /* Program register map */
75 #define AD9250_REG_PDWN (AD9250_R1B | 0x08)
76 #define AD9250_REG_CLOCK (AD9250_R1B | 0x09 | SHADOW(1))
77 #define AD9250_REG_PLL_STAT (AD9250_R1B | 0x0A)
78 #define AD9250_REG_CLOCK_DIV (AD9250_R1B | 0x0B | SHADOW(2))
79 #define AD9250_REG_TEST (AD9250_R1B | 0x0D | SHADOW(3))
80 #define AD9250_REG_BIST (AD9250_R1B | 0x0E | SHADOW(4))
81 #define AD9250_REG_OFFSET (AD9250_R1B | 0x10 | SHADOW(5))
82 #define AD9250_REG_OUT_MODE (AD9250_R1B | 0x14 | SHADOW(6))
83 #define AD9250_REG_CML (AD9250_R1B | 0x15)
84 #define AD9250_REG_VREF (AD9250_R1B | 0x18 | SHADOW(7))
85 #define AD9250_REG_USER_TEST1 (AD9250_R2B | 0x1A)
86 #define AD9250_REG_USER_TEST2 (AD9250_R2B | 0x1C)
87 #define AD9250_REG_USER_TEST3 (AD9250_R2B | 0x1E)
88 #define AD9250_REG_USER_TEST4 (AD9250_R2B | 0x20)
89 #define AD9250_REG_PLL_ENCODE (AD9250_R1B | 0x21)
90 #define AD9250_REG_BIST_MISR (AD9250_R2B | 0x25)
91 #define AD9250_REG_SYS_CTRL (AD9250_R1B | 0x3A | SHADOW(8))
92 #define AD9250_REG_DCC_CTRL (AD9250_R1B | 0x40 | SHADOW(9))
93 #define AD9250_REG_DCC_VAL (AD9250_R2B | 0x42 | SHADOW(10))
94 #define AD9250_REG_FAST_DETECT (AD9250_R1B | 0x45 | SHADOW(11))
95 #define AD9250_REG_FD_UPPER_THD (AD9250_R2B | 0x48 | SHADOW(12))
96 #define AD9250_REG_FD_LOWER_THD (AD9250_R2B | 0x4A | SHADOW(13))
97 #define AD9250_REG_FD_DWELL_TIME (AD9250_R2B | 0x4C | SHADOW(14))
98 #define AD9250_REG_204B_QUICK_CFG (AD9250_R1B | 0x5E)
99 #define AD9250_REG_204B_CTRL1 (AD9250_R1B | 0x5F)
100 #define AD9250_REG_204B_CTRL2 (AD9250_R1B | 0x60)
101 #define AD9250_REG_204B_CTRL3 (AD9250_R1B | 0x61)
102 #define AD9250_REG_204B_DID_CFG (AD9250_R1B | 0x64)
103 #define AD9250_REG_204B_BID_CFG (AD9250_R1B | 0x65)
104 #define AD9250_REG_204B_LID_CFG0 (AD9250_R1B | 0x66)
105 #define AD9250_REG_204B_LID_CFG1 (AD9250_R1B | 0x67)
106 #define AD9250_REG_204B_PARAM_SCR_L (AD9250_R1B | 0x6E)
107 #define AD9250_REG_204B_PARAM_F (AD9250_R1B | 0x6F)
108 #define AD9250_REG_204B_PARAM_K (AD9250_R1B | 0x70)
109 #define AD9250_REG_204B_PARAM_M (AD9250_R1B | 0x71)
110 #define AD9250_REG_204B_PARAM_CS_N (AD9250_R1B | 0x72)
111 #define AD9250_REG_204B_PARAM_NP (AD9250_R1B | 0x73)
112 #define AD9250_REG_204B_PARAM_S (AD9250_R1B | 0x74)
113 #define AD9250_REG_204B_PARAM_HD_CF (AD9250_R1B | 0x75)
114 #define AD9250_REG_204B_RESV1 (AD9250_R1B | 0x76)
115 #define AD9250_REG_204B_RESV2 (AD9250_R1B | 0x77)
116 #define AD9250_REG_204B_CHKSUM0 (AD9250_R1B | 0x79)
117 #define AD9250_REG_204B_CHKSUM1 (AD9250_R1B | 0x7A)
118 #define AD9250_REG_204B_LANE_ASSGN1 (AD9250_R1B | 0x82)
119 #define AD9250_REG_204B_LANE_ASSGN2 (AD9250_R1B | 0x83)
120 #define AD9250_REG_204B_LMFC_OFFSET (AD9250_R1B | 0x8B)
121 #define AD9250_REG_204B_PRE_EMPHASIS (AD9250_R1B | 0xA8)
122 
123 /* AD9250_REG_SPI_CFG */
124 #define AD9250_SPI_CFG_LSB_FIRST ((1 << 6) | (1 << 1))
125 #define AD9250_SPI_CFG_SOFT_RST ((1 << 5) | (1 << 2))
126 
127 /* AD9250_REG_CH_INDEX */
128 #define AD9250_CH_INDEX_ADC_A (1 << 0)
129 #define AD9250_CH_INDEX_ADC_B (1 << 1)
130 
131 /* AD9250_REG_DEVICE_UPDATE */
132 #define AD9250_DEVICE_UPDATE_SW (1 << 0)
133 
134 /* AD9250_REG_PDWN */
135 #define AD9250_PDWN_EXTERN (1 << 5)
136 #define AD9250_PDWN_JTX (1 << 4)
137 #define AD9250_PDWN_JESD204B(x) (((x) & 0x3) << 2)
138 #define AD9250_PDWN_CHIP(x) (((x) & 0x3) << 0)
139 
140 /* AD9250_REG_CLOCK */
141 #define AD9250_CLOCK_SELECTION(x) (((x) & 0x3) << 4)
142 #define AD9250_CLOCK_DUTY_CYCLE (1 << 0)
143 
144 /* AD9250_REG_PLL_STAT */
145 #define AD9250_PLL_STAT_LOCKED (1 << 7)
146 #define AD9250_PLL_STAT_204B_LINK_RDY (1 << 0)
147 
148 /* AD9250_REG_CLOCK_DIV */
149 #define AD9250_CLOCK_DIV_PHASE(x) (((x) & 0x7) << 3)
150 #define AD9250_CLOCK_DIV_RATIO(x) (((x) & 0x7) << 0)
151 
152 /* AD9250_REG_TEST */
153 #define AD9250_TEST_USER_TEST_MODE(x) (((x) & 0x3) << 6)
154 #define AD9250_TEST_RST_PN_LONG (1 << 5)
155 #define AD9250_TEST_RST_PN_SHOR (1 << 4)
156 #define AD9250_TEST_OUTPUT_TEST(x) (((x) & 0xF) << 0)
157 
158 /* AD9250_TEST */
159 #define AD9250_TEST_OFF 0x00
160 #define AD9250_TEST_MID_SCALE 0x01
161 #define AD9250_TEST_POS_FSCALE 0x02
162 #define AD9250_TEST_NEG_FSCALE 0x03
163 #define AD9250_TEST_CHECKBOARD 0x04
164 #define AD9250_TEST_PNLONG 0x05
165 #define AD9250_TEST_ONE2ZERO 0x07
166 #define AD9250_TEST_PATTERN 0x08
167 #define AD9250_TEST_RAMP 0x0F
168 
169 /* AD9250_REG_BIST */
170 #define AD9250_BIST_RESET (1 << 2)
171 #define AD9250_BIST_ENABLE (1 << 0)
172 
173 /* AD9250_REG_OFFSET */
174 #define AD9250_REG_OFFSET_ADJUST(x) (((x) & 0x3F) << 0)
175 
176 /* AD9250_REG_OUT_MODE */
177 #define AD9250_OUT_MODE_JTX_BIT_ASSIGN(x) (((x) & 0x7) << 5)
178 #define AD9250_OUT_MODE_DISABLE (1 << 4)
179 #define AD9250_OUT_MODE_INVERT_DATA (1 << 3)
180 #define AD9250_OUT_MODE_DATA_FORMAT(x) (((x) & 0x1) << 0)
181 
182 /* AD9250_OUT */
183 #define AD9250_OUT_OFFSET_BINARY 0x00
184 #define AD9250_OUT_2S_COMPLEMENT 0x01
185 
186 /* AD9250_REG_CML */
187 #define AD9250_CML_DIFF_OUT_LEVEL(x) (((x) & 0x7) << 0)
188 
189 /* AD9250_REG_VREF */
190 #define AD9250_VREF_FS_ADJUST(x) (((x) & 0x1F) << 0)
191 
192 /* AD9250_REG_PLL_ENCODE */
193 #define AD9250_PLL_ENCODE(x) (((x) & 0x3) << 3)
194 
195 /* AD9250_REG_SYS_CTRL */
196 #define AD9250_SYS_CTRL_REALIGN_ON_SYNCINB (1 << 4)
197 #define AD9250_SYS_CTRL_REALIGN_ON_SYSREF (1 << 3)
198 #define AD9250_SYS_CTRL_SYSREF_MODE (1 << 2)
199 #define AD9250_SYS_CTRL_SYSREF_EN (1 << 1)
200 #define AD9250_SYS_CTRL_SYNCINB_EN (1 << 0)
201 
202 /* AD9250_REG_DCC_CTRL */
203 #define AD9250_DCC_CTRL_FREEZE_DCC (1 << 6)
204 #define AD9250_DCC_CTRL_DCC_BW(x) (((x) & 0xF) << 2)
205 #define AD9250_DCC_CTRL_DCC_EN (1 << 1)
206 
207 /* AD9250_REG_FAST_DETECT */
208 #define AD9250_FAST_DETECT_PIN_FCT (1 << 4)
209 #define AD9250_FAST_DETECT_FORCE_FDA_FDB_PIN (1 << 3)
210 #define AD9250_FAST_DETECT_FORCE_FDA_FDB_VAL (1 << 2)
211 #define AD9250_FAST_DETECT_OUTPUT_ENABLE (1 << 0)
212 
213 /* AD9250_REG_204B_QUICK_CFG */
214 #define AD9250_204B_QUICK_CFG(x) (((x) & 0xFF) << 0)
215 
216 /* AD9250_REG_204B_CTRL1 */
217 #define AD9250_204B_CTRL1_TAIL_BITS (1 << 6)
218 #define AD9250_204B_CTRL1_TEST_SAMPLE_EN (1 << 5)
219 #define AD9250_204B_CTRL1_ILAS_MODE(x) (((x) & 0x3) << 2)
220 #define AD9250_204B_CTRL1_POWER_DOWN (1 << 0)
221 
222 /* AD9250_REG_204B_CTRL2 */
223 #define AD9250_204B_CTRL2_INVERT_JESD_BITS (1 << 1)
224 
225 /* AD9250_REG_204B_CTRL3 */
226 #define AD9250_204B_CTRL3_TEST_DATA_INJ_PT(x) (((x) & 0x3) << 4)
227 #define AD9250_204B_CTRL3_JESD_TEST_MODE(x) (((x) & 0xF) << 0)
228 
229 /* AD9250_REG_204B_PARAM_SCR_L */
230 #define AD9250_204B_PARAM_SCR_L_SCRAMBLING (1 << 7)
231 #define AD9250_204B_PARAM_SCR_L_LANES (1 << 0)
232 
233 /* AD9250_REG_204B_PARAM_CS_N */
234 #define AD9250_204B_PARAM_CS_N_NR_CTRL_BITS(x) (((x) & 0x3) << 6)
235 #define AD9250_204B_PARAM_CS_N_ADC_RESOLUTION(x) (((x) & 0xF) << 0)
236 
237 /* AD9250_REG_204B_PARAM_NP */
238 #define AD9250_204B_PARAM_NP_JESD_SUBCLASS(x) (((x) & 0x3) << 5)
239 #define AD9250_204B_PARAM_NP_JESD_N_VAL(x) (((x) & 0xF) << 0)
240 
241 /* AD9250_REG_204B_PARAM_S */
242 #define AD9250_204B_PARAM_S(x) (((x) << 0x1F) << 0)
243 
244 /* AD9250_REG_204B_PARAM_HD_CF */
245 #define AD9250_204B_PARAM_HD_CF_HD_VAL (1 << 7)
246 #define AD9250_204B_PARAM_HD_CF_CF_VAL(x) (((x) & 0x1F) << 0)
247 
248 /* AD9250_REG_204B_LANE_ASSGN1 */
249 #define AD9250_204B_LANE_ASSGN1(x) (((x) & 0x3) << 4)
250 
251 /* AD9250_REG_204B_LANE_ASSGN2 */
252 #define AD9250_204B_LANE_ASSGN2(x) (((x) &0x3) << 0)
253 
254 /* AD9250_REG_204B_LMFC_OFFSET */
255 #define AD9250_204B_LMFC_OFFSET(x) (((x) & 0x1F) << 0)
256 
257 /*****************************************************************************/
258 /************************** Types Declarations *******************************/
259 /*****************************************************************************/
260 
277  int8_t en_clk_dcs;
311  int8_t adc_vref;
319  int8_t name[16];
320 };
321 
341  int8_t cml_level;
355  int8_t subclass;
362  int8_t ctrl_bits_no;
380  int8_t did;
382  int8_t bid;
384  int8_t lid0;
386  int8_t lid1;
391  int8_t k;
397  int8_t scrambling;
403  int8_t ilas_mode;
409  int8_t en_ilas_test;
421  int8_t en_sys_ref;
427  int8_t en_sync_in_b;
433  int8_t sys_ref_mode;
451  int8_t lane0_assign;
452  /* Option to remap converter and lane assignments.
453  * 0 = assign Logical Lane 1 to Physical Lane A
454  * 1 = assign Logical Lane 1 to Physical Lane B [default]
455  */
456  int8_t lane1_assign;
457 };
458 
469  int8_t en_fd;
475  int8_t pin_function;
481  int8_t force_pins;
489  int16_t fd_upper_tresh;
491  int16_t fd_lower_tresh;
493  int16_t df_dwell_time;
494 };
495 
496 struct ad9250_state {
500 };
501 
518 };
519 
520 struct ad9250_dev {
521  /* SPI */
523  /* Device Settings */
526 };
527 
529  /* SPI */
531  /* Device Settings */
533 };
534 
535 /******************************************************************************/
536 /************************ Functions Declarations ******************************/
537 /******************************************************************************/
538 
540 int32_t ad9250_setup(struct ad9250_dev **device,
543 int32_t ad9250_remove(struct ad9250_dev *dev);
545 int32_t ad9250_read(struct ad9250_dev *dev,
546  int32_t register_address);
548 int32_t ad9250_write(struct ad9250_dev *dev,
549  int32_t register_address,
550  int32_t register_value);
552 int32_t ad9250_transfer(struct ad9250_dev *dev);
554 int32_t ad9250_soft_reset(struct ad9250_dev *dev);
556 int32_t ad9250_chip_pwr_mode(struct ad9250_dev *dev,
557  int32_t mode);
559 int32_t ad9250_select_channel_for_config(struct ad9250_dev *dev,
560  int32_t channel);
562 int32_t ad9250_test_mode(struct ad9250_dev *dev,
563  int32_t mode);
565 int32_t ad9250_offset_adj(struct ad9250_dev *dev,
566  int32_t adj);
568 int32_t ad9250_output_disable(struct ad9250_dev *dev,
569  int32_t en);
571 int32_t ad9250_output_invert(struct ad9250_dev *dev,
572  int32_t invert);
574 int32_t ad9250_output_format(struct ad9250_dev *dev,
575  int32_t format);
577 int32_t ad9250_reset_PN29(struct ad9250_dev *dev,
578  int32_t rst);
580 int32_t ad9250_reset_pn23(struct ad9250_dev *dev,
581  int32_t rst);
583 int32_t ad9250_set_user_pattern(struct ad9250_dev *dev,
584  int32_t pattern_no,
585  int32_t user_pattern);
587 int32_t ad9250_bist_enable(struct ad9250_dev *dev,
588  int32_t enable);
590 int32_t ad9250_bist_reset(struct ad9250_dev *dev,
591  int32_t reset);
593 int32_t ad9250_jesd204b_setup(struct ad9250_dev *dev);
595 int32_t ad9250_jesd204b_pwr_mode(struct ad9250_dev *dev,
596  int32_t mode);
600  int32_t inj_point);
602 int32_t ad9250_jesd204b_test_mode(struct ad9250_dev *dev,
603  int32_t test_mode);
605 int32_t ad9250_jesd204b_invert_logic(struct ad9250_dev *dev,
606  int32_t invert);
608 int32_t ad9250_fast_detect_setup(struct ad9250_dev *dev);
610 int32_t ad9250_dcc_enable(struct ad9250_dev *dev,
611  int32_t enable);
613 int32_t ad9250_dcc_bandwidth(struct ad9250_dev *dev,
614  int32_t bw);
616 int32_t ad9250_dcc_freeze(struct ad9250_dev *dev,
617  int32_t freeze);
618 
619 #endif /* __AD9250_H__ */
AD9250_REG_204B_PARAM_NP
#define AD9250_REG_204B_PARAM_NP
Definition: ad9250.h:111
ad9250_jesd204b_setup
int32_t ad9250_jesd204b_setup(struct ad9250_dev *dev)
Configures the JESD204B interface.
Definition: ad9250.c:837
AD9250_BIST_ENABLE
#define AD9250_BIST_ENABLE
Definition: ad9250.h:171
AD9250_SHD_REG_OFFSET
@ AD9250_SHD_REG_OFFSET
Definition: ad9250.h:507
AD9250_SHD_REG_BIST
@ AD9250_SHD_REG_BIST
Definition: ad9250.h:506
AD9250_REG_USER_TEST1
#define AD9250_REG_USER_TEST1
Definition: ad9250.h:85
ad9250_output_invert
int32_t ad9250_output_invert(struct ad9250_dev *dev, int32_t invert)
Activates the inverted (1) or normal (0) output mode. Note: This function modifies a shadowed registe...
Definition: ad9250.c:585
ad9250_jesd204b_cfg::lane0_assign
int8_t lane0_assign
Definition: ad9250.h:451
AD9250_REG_DCC_CTRL
#define AD9250_REG_DCC_CTRL
Definition: ad9250.h:92
ad9250_fast_detect_cfg::en_fd
int8_t en_fd
Definition: ad9250.h:469
ad9250_jesd204b_cfg::invert_logic_bits
int8_t invert_logic_bits
Definition: ad9250.h:415
ad9250_jesd204b_select_test_injection_point
int32_t ad9250_jesd204b_select_test_injection_point(struct ad9250_dev *dev, int32_t inj_point)
Selects the point in the processing path of a lane, where the test data will be inserted.
Definition: ad9250.c:1061
AD9250_BIST_RESET
#define AD9250_BIST_RESET
Definition: ad9250.h:170
ad9250_platform_data::pll_low_encode
int8_t pll_low_encode
Definition: ad9250.h:317
AD9250_204B_CTRL2_INVERT_JESD_BITS
#define AD9250_204B_CTRL2_INVERT_JESD_BITS
Definition: ad9250.h:223
shadow_registers
shadow_registers
Definition: ad6673.h:503
SHADOW
#define SHADOW(x)
Definition: ad6673.h:64
ad9250_set_user_pattern
int32_t ad9250_set_user_pattern(struct ad9250_dev *dev, int32_t pattern_no, int32_t user_pattern)
Configures a User Test Pattern.
Definition: ad9250.c:715
ad9250_is_shadow_register
int32_t ad9250_is_shadow_register(int32_t register_address)
Checks if the register is shadowed.
Definition: ad9250.c:401
ad9250_soft_reset
int32_t ad9250_soft_reset(struct ad9250_dev *dev)
Resets all registers to their default values.
Definition: ad9250.c:325
AD9250_PDWN_EXTERN
#define AD9250_PDWN_EXTERN
Definition: ad9250.h:135
ad9250_fast_detect_cfg::pin_force_value
int8_t pin_force_value
Definition: ad9250.h:487
ad9250_jesd204b_cfg::en_sys_ref
int8_t en_sys_ref
Definition: ad9250.h:421
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
ad9250_reset_pn23
int32_t ad9250_reset_pn23(struct ad9250_dev *dev, int32_t rst)
Sets (1) or clears (0) the reset long PN sequence bit(PN23).
Definition: ad9250.c:684
ad9250_bist_enable
int32_t ad9250_bist_enable(struct ad9250_dev *dev, int32_t enable)
Enables the Build-In-Self-Test.
Definition: ad9250.c:738
ad9250_select_channel_for_config
int32_t ad9250_select_channel_for_config(struct ad9250_dev *dev, int32_t channel)
Selects a channel as the current channel for further configurations.
Definition: ad9250.c:450
ad9250_jesd204b_pwr_mode
int32_t ad9250_jesd204b_pwr_mode(struct ad9250_dev *dev, int32_t mode)
Configures the power mode of the JESD204B data transmit block.
Definition: ad9250.c:1027
ad9250_set_user_pattern
int32_t ad9250_set_user_pattern(struct ad9250_dev *dev, int32_t pattern_no, int32_t user_pattern)
Configures a User Test Pattern.
Definition: ad9250.c:715
AD9250_204B_LANE_ASSGN2
#define AD9250_204B_LANE_ASSGN2(x)
Definition: ad9250.h:252
no_os_spi.h
Header file of SPI Interface.
AD9250_CH_INDEX_ADC_B
#define AD9250_CH_INDEX_ADC_B
Definition: ad9250.h:129
ad9250_dcc_bandwidth
int32_t ad9250_dcc_bandwidth(struct ad9250_dev *dev, int32_t bw)
Selects the bandwidth value for the DC correction circuit.
Definition: ad9250.c:1242
AD9250_REG_TEST
#define AD9250_REG_TEST
Definition: ad9250.h:79
AD9250_SHD_REG_TEST
@ AD9250_SHD_REG_TEST
Definition: ad9250.h:505
AD9250_204B_CTRL1_ILAS_MODE
#define AD9250_204B_CTRL1_ILAS_MODE(x)
Definition: ad9250.h:219
ad9250_fast_detect_cfg::df_dwell_time
int16_t df_dwell_time
Definition: ad9250.h:493
AD9250_REG_204B_LID_CFG1
#define AD9250_REG_204B_LID_CFG1
Definition: ad9250.h:105
ad9250_jesd204b_cfg::lane1_assign
int8_t lane1_assign
Definition: ad9250.h:456
AD9250_OUT_MODE_JTX_BIT_ASSIGN
#define AD9250_OUT_MODE_JTX_BIT_ASSIGN(x)
Definition: ad9250.h:177
ad9250.h
Header file of AD9250 Driver.
AD9250_REG_CML
#define AD9250_REG_CML
Definition: ad9250.h:83
AD9250_SHD_REG_FAST_DETECT
@ AD9250_SHD_REG_FAST_DETECT
Definition: ad9250.h:513
AD9250_REG_VREF
#define AD9250_REG_VREF
Definition: ad9250.h:84
AD9250_REG_204B_LID_CFG0
#define AD9250_REG_204B_LID_CFG0
Definition: ad9250.h:104
ad9250_output_disable
int32_t ad9250_output_disable(struct ad9250_dev *dev, int32_t en)
Disables (1) or enables (0) the data output. Note: This function modifies a shadowed register,...
Definition: ad9250.c:550
ad9250_set_bits_to_reg
int32_t ad9250_set_bits_to_reg(struct ad9250_dev *dev, uint32_t register_address, uint8_t bits_value, uint8_t mask)
Sets a bit/group of bits inside a register without modifying other bits.
Definition: ad9250.c:360
AD9250_204B_PARAM_SCR_L_SCRAMBLING
#define AD9250_204B_PARAM_SCR_L_SCRAMBLING
Definition: ad9250.h:230
AD9250_REG_FD_LOWER_THD
#define AD9250_REG_FD_LOWER_THD
Definition: ad9250.h:96
ad9250_dcc_freeze
int32_t ad9250_dcc_freeze(struct ad9250_dev *dev, int32_t freeze)
Freezes DC correction value.
Definition: ad9250.c:1274
AD9250_REG_204B_QUICK_CFG
#define AD9250_REG_204B_QUICK_CFG
Definition: ad9250.h:98
AD9250_SHD_REG_SYS_CTRL
@ AD9250_SHD_REG_SYS_CTRL
Definition: ad9250.h:510
ad9250_transfer
int32_t ad9250_transfer(struct ad9250_dev *dev)
Initiates a transfer and waits for the operation to end. Note: This function may be called after a sh...
Definition: ad9250.c:293
AD9250_SYS_CTRL_REALIGN_ON_SYNCINB
#define AD9250_SYS_CTRL_REALIGN_ON_SYNCINB
Definition: ad9250.h:196
ad9250_platform_data::clk_selection
int8_t clk_selection
Definition: ad9250.h:284
AD9250_204B_PARAM_CS_N_NR_CTRL_BITS
#define AD9250_204B_PARAM_CS_N_NR_CTRL_BITS(x)
Definition: ad9250.h:234
AD9250_REG_204B_BID_CFG
#define AD9250_REG_204B_BID_CFG
Definition: ad9250.h:103
shadow_regs
const int32_t shadow_regs[SHADOW_REGISTER_COUNT]
Definition: ad9250.c:50
device
Definition: ad9361_util.h:75
ad9250_jesd204b_setup
int32_t ad9250_jesd204b_setup(struct ad9250_dev *dev)
Configures the JESD204B interface.
Definition: ad9250.c:837
ad9250_reset_pn23
int32_t ad9250_reset_pn23(struct ad9250_dev *dev, int32_t rst)
Sets (1) or clears (0) the reset long PN sequence bit(PN23).
Definition: ad9250.c:684
ad9250_jesd204b_cfg::en_ilas_test
int8_t en_ilas_test
Definition: ad9250.h:409
ad9250_init_param::spi_init
no_os_spi_init_param spi_init
Definition: ad9250.h:530
AD9250_SHD_REG_VREF
@ AD9250_SHD_REG_VREF
Definition: ad9250.h:509
AD9250_CLOCK_SELECTION
#define AD9250_CLOCK_SELECTION(x)
Definition: ad9250.h:141
ad9250_fast_detect_cfg
Fast Detect module configuration.
Definition: ad9250.h:463
ad9250_fast_detect_cfg::pin_function
int8_t pin_function
Definition: ad9250.h:475
AD9250_PLL_ENCODE
#define AD9250_PLL_ENCODE(x)
Definition: ad9250.h:193
ad9250_jesd204b_select_test_injection_point
int32_t ad9250_jesd204b_select_test_injection_point(struct ad9250_dev *dev, int32_t inj_point)
Selects the point in the processing path of a lane, where the test data will be inserted.
Definition: ad9250.c:1061
ad9250_jesd204b_cfg::en_sync_in_b
int8_t en_sync_in_b
Definition: ad9250.h:427
AD9250_TEST_RST_PN_SHOR
#define AD9250_TEST_RST_PN_SHOR
Definition: ad9250.h:155
AD9250_REG_SPI_CFG
#define AD9250_REG_SPI_CFG
Definition: ad9250.h:66
ad9250_setup
int32_t ad9250_setup(struct ad9250_dev **device, struct ad9250_init_param init_param)
Configures the device.
Definition: ad9250.c:91
AD9250_SPI_CFG_SOFT_RST
#define AD9250_SPI_CFG_SOFT_RST
Definition: ad9250.h:125
ad9250_jesd204b_cfg::quick_cfg_option
int8_t quick_cfg_option
Definition: ad9250.h:349
AD9250_FAST_DETECT_FORCE_FDA_FDB_VAL
#define AD9250_FAST_DETECT_FORCE_FDA_FDB_VAL
Definition: ad9250.h:210
AD9250_DCC_CTRL_DCC_EN
#define AD9250_DCC_CTRL_DCC_EN
Definition: ad9250.h:205
ad9250_dev::shadow_regs
int32_t shadow_regs[SHADOW_REGISTER_COUNT]
Definition: ad9250.h:525
ad9250_output_format
int32_t ad9250_output_format(struct ad9250_dev *dev, int32_t format)
Specifies the output format. Note: This function modifies a shadowed register, therefore a call of ad...
Definition: ad9250.c:620
ad9250_bist_enable
int32_t ad9250_bist_enable(struct ad9250_dev *dev, int32_t enable)
Enables the Build-In-Self-Test.
Definition: ad9250.c:738
AD9250_DEVICE_UPDATE_SW
#define AD9250_DEVICE_UPDATE_SW
Definition: ad9250.h:132
AD9250_SHD_REG_DCC_VAL
@ AD9250_SHD_REG_DCC_VAL
Definition: ad9250.h:512
AD9250_OUT_MODE_DISABLE
#define AD9250_OUT_MODE_DISABLE
Definition: ad9250.h:178
AD9250_REG_204B_PARAM_CS_N
#define AD9250_REG_204B_PARAM_CS_N
Definition: ad9250.h:110
ad9250_jesd204b_pwr_mode
int32_t ad9250_jesd204b_pwr_mode(struct ad9250_dev *dev, int32_t mode)
Configures the power mode of the JESD204B data transmit block.
Definition: ad9250.c:1027
ad9250_dcc_freeze
int32_t ad9250_dcc_freeze(struct ad9250_dev *dev, int32_t freeze)
Freezes DC correction value.
Definition: ad9250.c:1274
AD9250_SHD_REG_DCC_CTRL
@ AD9250_SHD_REG_DCC_CTRL
Definition: ad9250.h:511
ad9250_jesd204b_cfg::tail_bits_mode
int8_t tail_bits_mode
Definition: ad9250.h:378
ad9250_setup
int32_t ad9250_setup(struct ad9250_dev **device, struct ad9250_init_param init_param)
Configures the device.
Definition: ad9250.c:91
AD9250_REG_FD_DWELL_TIME
#define AD9250_REG_FD_DWELL_TIME
Definition: ad9250.h:97
AD9250_REG_BIST
#define AD9250_REG_BIST
Definition: ad9250.h:80
AD9250_SHD_REG_CLOCK_DIV
@ AD9250_SHD_REG_CLOCK_DIV
Definition: ad9250.h:504
AD9250_204B_LANE_ASSGN1
#define AD9250_204B_LANE_ASSGN1(x)
Definition: ad9250.h:249
ad9250_platform_data::en_clk_dcs
int8_t en_clk_dcs
Definition: ad9250.h:277
AD9250_CLOCK_DIV_PHASE
#define AD9250_CLOCK_DIV_PHASE(x)
Definition: ad9250.h:149
no_os_error.h
Error codes definition.
SHADOW_REGISTER_COUNT
@ SHADOW_REGISTER_COUNT
Definition: ad6673.h:520
AD9250_REG_204B_PARAM_SCR_L
#define AD9250_REG_204B_PARAM_SCR_L
Definition: ad9250.h:106
ad9250_jesd204b_invert_logic
int32_t ad9250_jesd204b_invert_logic(struct ad9250_dev *dev, int32_t invert)
Inverts the logic of JESD204B bits.
Definition: ad9250.c:1134
AD9250_PDWN_JTX
#define AD9250_PDWN_JTX
Definition: ad9250.h:136
AD9250_SYS_CTRL_SYSREF_EN
#define AD9250_SYS_CTRL_SYSREF_EN
Definition: ad9250.h:199
ad9250_dev::spi_desc
no_os_spi_desc * spi_desc
Definition: ad9250.h:522
ad9250_test_mode
int32_t ad9250_test_mode(struct ad9250_dev *dev, int32_t mode)
Sets the ADC's test mode.
Definition: ad9250.c:490
ad9250_state::p_fd
struct ad9250_fast_detect_cfg * p_fd
Definition: ad9250.h:499
AD9250_REG_204B_CTRL2
#define AD9250_REG_204B_CTRL2
Definition: ad9250.h:100
ad9250_platform_data::extrn_pdwnmode
int8_t extrn_pdwnmode
Definition: ad9250.h:271
AD9250_REG_204B_LANE_ASSGN1
#define AD9250_REG_204B_LANE_ASSGN1
Definition: ad9250.h:118
AD9250_FAST_DETECT_FORCE_FDA_FDB_PIN
#define AD9250_FAST_DETECT_FORCE_FDA_FDB_PIN
Definition: ad9250.h:209
AD9250_REG_PDWN
#define AD9250_REG_PDWN
Definition: ad9250.h:75
AD9250_REG_SYS_CTRL
#define AD9250_REG_SYS_CTRL
Definition: ad9250.h:91
ad9250_fast_detect_cfg::fd_lower_tresh
int16_t fd_lower_tresh
Definition: ad9250.h:491
ad9250_reset_PN29
int32_t ad9250_reset_PN29(struct ad9250_dev *dev, int32_t rst)
ad9250_jesd204b_cfg::subclass
int8_t subclass
Definition: ad9250.h:355
ad9250_jesd204b_cfg::cml_level
int8_t cml_level
Definition: ad9250.h:341
ad9250_platform_data::name
int8_t name[16]
Definition: ad9250.h:319
ad9250_state
Definition: ad9250.h:496
ad9250_dev::ad9250_st
struct ad9250_state ad9250_st
Definition: ad9250.h:524
ad9250_jesd204b_cfg::bid
int8_t bid
Definition: ad9250.h:382
ad9250_reset_pn9
int32_t ad9250_reset_pn9(struct ad9250_dev *dev, int32_t rst)
Sets (1) or clears (0) the reset short PN sequence bit(PN9).
Definition: ad9250.c:652
ad9250_jesd204b_cfg::jtx_in_standby
int8_t jtx_in_standby
Definition: ad9250.h:332
AD9250_204B_CTRL1_POWER_DOWN
#define AD9250_204B_CTRL1_POWER_DOWN
Definition: ad9250.h:220
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
AD9250_SHD_REG_FD_UPPER_THD
@ AD9250_SHD_REG_FD_UPPER_THD
Definition: ad9250.h:514
AD9250_204B_CTRL1_TAIL_BITS
#define AD9250_204B_CTRL1_TAIL_BITS
Definition: ad9250.h:217
ad9250_jesd204b_invert_logic
int32_t ad9250_jesd204b_invert_logic(struct ad9250_dev *dev, int32_t invert)
Inverts the logic of JESD204B bits.
Definition: ad9250.c:1134
AD9250_REG_OFFSET
#define AD9250_REG_OFFSET
Definition: ad9250.h:81
AD9250_SYS_CTRL_SYNCINB_EN
#define AD9250_SYS_CTRL_SYNCINB_EN
Definition: ad9250.h:200
ad9250_output_format
int32_t ad9250_output_format(struct ad9250_dev *dev, int32_t format)
Specifies the output format. Note: This function modifies a shadowed register, therefore a call of ad...
Definition: ad9250.c:620
ad9250_jesd204b_cfg::sys_ref_mode
int8_t sys_ref_mode
Definition: ad9250.h:433
AD9250_SHD_REG_CLOCK
@ AD9250_SHD_REG_CLOCK
Definition: ad9250.h:503
ad9250_offset_adj
int32_t ad9250_offset_adj(struct ad9250_dev *dev, int32_t adj)
Sets the offset adjustment.
Definition: ad9250.c:520
AD9250_SHD_REG_FD_DWELL_TIME
@ AD9250_SHD_REG_FD_DWELL_TIME
Definition: ad9250.h:516
AD9250_FAST_DETECT_PIN_FCT
#define AD9250_FAST_DETECT_PIN_FCT
Definition: ad9250.h:208
AD9250_REG_CLOCK
#define AD9250_REG_CLOCK
Definition: ad9250.h:76
ad9250_output_disable
int32_t ad9250_output_disable(struct ad9250_dev *dev, int32_t en)
Disables (1) or enables (0) the data output. Note: This function modifies a shadowed register,...
Definition: ad9250.c:550
ad9250_jesd204b_cfg
JESD204B interface configuration.
Definition: ad9250.h:326
ad9250_jesd204b_cfg::align_sys_ref
int8_t align_sys_ref
Definition: ad9250.h:445
AD9250_CLOCK_DIV_RATIO
#define AD9250_CLOCK_DIV_RATIO(x)
Definition: ad9250.h:150
AD9250_CML_DIFF_OUT_LEVEL
#define AD9250_CML_DIFF_OUT_LEVEL(x)
Definition: ad9250.h:187
ad9250_write
int32_t ad9250_write(struct ad9250_dev *dev, int32_t register_address, int32_t register_value)
Writes a value to the selected register.
Definition: ad9250.c:249
ad9250_state::p_jesd204b
struct ad9250_jesd204b_cfg * p_jesd204b
Definition: ad9250.h:498
AD9250_VREF_FS_ADJUST
#define AD9250_VREF_FS_ADJUST(x)
Definition: ad9250.h:190
ad9250_read
int32_t ad9250_read(struct ad9250_dev *dev, int32_t register_address)
Reads the value of the selected register.
Definition: ad9250.c:212
ad9250_dcc_enable
int32_t ad9250_dcc_enable(struct ad9250_dev *dev, int32_t enable)
Enables DC correction for use in the output data signal path.
Definition: ad9250.c:1208
ad9250_fast_detect_cfg::fd_upper_tresh
int16_t fd_upper_tresh
Definition: ad9250.h:489
ad9250_jesd204b_cfg::k
int8_t k
Definition: ad9250.h:391
AD9250_REG_OFFSET_ADJUST
#define AD9250_REG_OFFSET_ADJUST(x)
Definition: ad9250.h:174
ad9250_soft_reset
int32_t ad9250_soft_reset(struct ad9250_dev *dev)
Resets all registers to their default values.
Definition: ad9250.c:325
ad9250_chip_pwr_mode
int32_t ad9250_chip_pwr_mode(struct ad9250_dev *dev, int32_t mode)
Configures the power mode of the chip.
Definition: ad9250.c:417
ad9250_platform_data::clk_div_phase
int8_t clk_div_phase
Definition: ad9250.h:300
AD9250_TRANSF_LEN
#define AD9250_TRANSF_LEN(x)
Definition: ad9250.h:62
AD9250_204B_CTRL3_TEST_DATA_INJ_PT
#define AD9250_204B_CTRL3_TEST_DATA_INJ_PT(x)
Definition: ad9250.h:226
ad9250_select_channel_for_config
int32_t ad9250_select_channel_for_config(struct ad9250_dev *dev, int32_t channel)
Selects a channel as the current channel for further configurations.
Definition: ad9250.c:450
ad9250_dcc_enable
int32_t ad9250_dcc_enable(struct ad9250_dev *dev, int32_t enable)
Enables DC correction for use in the output data signal path.
Definition: ad9250.c:1208
ad9250_jesd204b_test_mode
int32_t ad9250_jesd204b_test_mode(struct ad9250_dev *dev, int32_t test_mode)
Selects a JESD204B test mode.
Definition: ad9250.c:1102
AD9250_DCC_CTRL_FREEZE_DCC
#define AD9250_DCC_CTRL_FREEZE_DCC
Definition: ad9250.h:203
ad9250_dcc_bandwidth
int32_t ad9250_dcc_bandwidth(struct ad9250_dev *dev, int32_t bw)
Selects the bandwidth value for the DC correction circuit.
Definition: ad9250.c:1242
AD9250_ADDR
#define AD9250_ADDR(x)
Definition: ad9250.h:57
AD9250_CLOCK_DUTY_CYCLE
#define AD9250_CLOCK_DUTY_CYCLE
Definition: ad9250.h:142
ad9250_state::pdata
struct ad9250_platform_data * pdata
Definition: ad9250.h:497
AD9250_DCC_CTRL_DCC_BW
#define AD9250_DCC_CTRL_DCC_BW(x)
Definition: ad9250.h:204
ad9250_write
int32_t ad9250_write(struct ad9250_dev *dev, int32_t register_address, int32_t register_value)
Writes a value to the selected register.
Definition: ad9250.c:249
AD9250_SHD_REG_FD_LOWER_THD
@ AD9250_SHD_REG_FD_LOWER_THD
Definition: ad9250.h:515
ad9250_platform_data
Platform specific information.
Definition: ad9250.h:265
ad9250_jesd204b_test_mode
int32_t ad9250_jesd204b_test_mode(struct ad9250_dev *dev, int32_t test_mode)
Selects a JESD204B test mode.
Definition: ad9250.c:1102
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
AD9250_PDWN_JESD204B
#define AD9250_PDWN_JESD204B(x)
Definition: ad9250.h:137
AD9250_SYS_CTRL_REALIGN_ON_SYSREF
#define AD9250_SYS_CTRL_REALIGN_ON_SYSREF
Definition: ad9250.h:197
ad9250_bist_reset
int32_t ad9250_bist_reset(struct ad9250_dev *dev, int32_t reset)
Resets the Build-In-Self-Test.
Definition: ad9250.c:768
AD9250_204B_QUICK_CFG
#define AD9250_204B_QUICK_CFG(x)
Definition: ad9250.h:214
AD9250_REG_204B_DID_CFG
#define AD9250_REG_204B_DID_CFG
Definition: ad9250.h:102
ad9250_jesd204b_cfg::lid1
int8_t lid1
Definition: ad9250.h:386
AD9250_REG_FAST_DETECT
#define AD9250_REG_FAST_DETECT
Definition: ad9250.h:94
AD9250_SHD_REG_OUT_MODE
@ AD9250_SHD_REG_OUT_MODE
Definition: ad9250.h:508
ad9250_read
int32_t ad9250_read(struct ad9250_dev *dev, int32_t register_address)
Reads the value of the selected register.
Definition: ad9250.c:212
ad9250_jesd204b_cfg::ctrl_bits_assign
int8_t ctrl_bits_assign
Definition: ad9250.h:372
ad9250_jesd204b_cfg::did
int8_t did
Definition: ad9250.h:380
ad9250_jesd204b_set_frames
int32_t ad9250_jesd204b_set_frames(struct ad9250_dev *dev, int32_t k_frames)
Sets number of frames per multiframe (K).
Definition: ad9250.c:800
AD9250_REG_204B_LANE_ASSGN2
#define AD9250_REG_204B_LANE_ASSGN2
Definition: ad9250.h:119
AD9250_TEST_RST_PN_LONG
#define AD9250_TEST_RST_PN_LONG
Definition: ad9250.h:154
AD9250_READ
#define AD9250_READ
Definition: ad9250.h:54
AD9250_204B_CTRL3_JESD_TEST_MODE
#define AD9250_204B_CTRL3_JESD_TEST_MODE(x)
Definition: ad9250.h:227
ad9250_output_invert
int32_t ad9250_output_invert(struct ad9250_dev *dev, int32_t invert)
Activates the inverted (1) or normal (0) output mode. Note: This function modifies a shadowed registe...
Definition: ad9250.c:585
ad9250_bist_reset
int32_t ad9250_bist_reset(struct ad9250_dev *dev, int32_t reset)
Resets the Build-In-Self-Test.
Definition: ad9250.c:768
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
AD9250_REG_204B_CTRL1
#define AD9250_REG_204B_CTRL1
Definition: ad9250.h:99
AD9250_OUT_MODE_INVERT_DATA
#define AD9250_OUT_MODE_INVERT_DATA
Definition: ad9250.h:179
ad9250_platform_data::adc_vref
int8_t adc_vref
Definition: ad9250.h:311
ad9250_fast_detect_setup
int32_t ad9250_fast_detect_setup(struct ad9250_dev *dev)
Configures the Fast-Detect module.
Definition: ad9250.c:1163
ad9250_test_mode
int32_t ad9250_test_mode(struct ad9250_dev *dev, int32_t mode)
Sets the ADC's test mode.
Definition: ad9250.c:490
ad9250_platform_data::clk_div_ratio
int8_t clk_div_ratio
Definition: ad9250.h:292
SHADOW_REGISTER_COUNT
@ SHADOW_REGISTER_COUNT
Definition: ad9250.h:517
ad9250_init_param
Definition: ad9250.h:528
ad9250_jesd204b_cfg::align_sync_in_b
int8_t align_sync_in_b
Definition: ad9250.h:439
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
ad9250_jesd204b_cfg::ctrl_bits_no
int8_t ctrl_bits_no
Definition: ad9250.h:362
AD9250_REG_OUT_MODE
#define AD9250_REG_OUT_MODE
Definition: ad9250.h:82
AD9250_REG_CLOCK_DIV
#define AD9250_REG_CLOCK_DIV
Definition: ad9250.h:78
ad9250_remove
int32_t ad9250_remove(struct ad9250_dev *dev)
Free the resources allocated by ad9250_setup().
Definition: ad9250.c:193
ad9250_chip_pwr_mode
int32_t ad9250_chip_pwr_mode(struct ad9250_dev *dev, int32_t mode)
Configures the power mode of the chip.
Definition: ad9250.c:417
AD9250_REG_204B_PARAM_K
#define AD9250_REG_204B_PARAM_K
Definition: ad9250.h:108
ad9250_jesd204b_cfg::ilas_mode
int8_t ilas_mode
Definition: ad9250.h:403
AD9250_REG_DEVICE_UPDATE
#define AD9250_REG_DEVICE_UPDATE
Definition: ad9250.h:72
AD9250_REG_PLL_ENCODE
#define AD9250_REG_PLL_ENCODE
Definition: ad9250.h:89
AD9250_TEST_OUTPUT_TEST
#define AD9250_TEST_OUTPUT_TEST(x)
Definition: ad9250.h:156
ad9250_init_param::ad9250_st_init
struct ad9250_state ad9250_st_init
Definition: ad9250.h:532
AD9250_REG_204B_CTRL3
#define AD9250_REG_204B_CTRL3
Definition: ad9250.h:101
ad9250_remove
int32_t ad9250_remove(struct ad9250_dev *dev)
Free the resources allocated by ad9250_setup().
Definition: ad9250.c:193
AD9250_PDWN_CHIP
#define AD9250_PDWN_CHIP(x)
Definition: ad9250.h:138
AD9250_CH_INDEX_ADC_A
#define AD9250_CH_INDEX_ADC_A
Definition: ad9250.h:128
AD9250_OUT_MODE_DATA_FORMAT
#define AD9250_OUT_MODE_DATA_FORMAT(x)
Definition: ad9250.h:180
ad9250_dev
Definition: ad9250.h:520
AD9250_WRITE
#define AD9250_WRITE
Definition: ad9250.h:55
AD9250_REG_FD_UPPER_THD
#define AD9250_REG_FD_UPPER_THD
Definition: ad9250.h:95
ad9250_jesd204b_cfg::scrambling
int8_t scrambling
Definition: ad9250.h:397
ad9250_fast_detect_setup
int32_t ad9250_fast_detect_setup(struct ad9250_dev *dev)
Configures the Fast-Detect module.
Definition: ad9250.c:1163
AD9250_204B_CTRL1_TEST_SAMPLE_EN
#define AD9250_204B_CTRL1_TEST_SAMPLE_EN
Definition: ad9250.h:218
ad9250_offset_adj
int32_t ad9250_offset_adj(struct ad9250_dev *dev, int32_t adj)
Sets the offset adjustment.
Definition: ad9250.c:520
ad9250_fast_detect_cfg::force_pins
int8_t force_pins
Definition: ad9250.h:481
ad9250_transfer
int32_t ad9250_transfer(struct ad9250_dev *dev)
Initiates a transfer and waits for the operation to end. Note: This function may be called after a sh...
Definition: ad9250.c:293
AD9250_204B_PARAM_NP_JESD_SUBCLASS
#define AD9250_204B_PARAM_NP_JESD_SUBCLASS(x)
Definition: ad9250.h:238
AD9250_REG_CH_INDEX
#define AD9250_REG_CH_INDEX
Definition: ad9250.h:71
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
AD9250_FAST_DETECT_OUTPUT_ENABLE
#define AD9250_FAST_DETECT_OUTPUT_ENABLE
Definition: ad9250.h:211
ad9250_jesd204b_cfg::lid0
int8_t lid0
Definition: ad9250.h:384
AD9250_SYS_CTRL_SYSREF_MODE
#define AD9250_SYS_CTRL_SYSREF_MODE
Definition: ad9250.h:198