no-OS
parameters.h
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1 /***************************************************************************/
39 #ifndef __PARAMETERS_H__
40 #define __PARAMETERS_H__
41 
42 #ifdef XILINX_PLATFORM
43 /******************************************************************************/
44 /***************************** Include Files **********************************/
45 /******************************************************************************/
46 #include <xparameters.h>
47 
48 /******************************************************************************/
49 /********************** Macros and Constants Definitions **********************/
50 /******************************************************************************/
51 #define UART_BAUDRATE 921600
52 #ifdef XPAR_AXI_AD9361_0_BASEADDR
53 #define AD9361_RX_0_BASEADDR XPAR_AXI_AD9361_0_BASEADDR
54 #define AD9361_TX_0_BASEADDR XPAR_AXI_AD9361_0_BASEADDR + 0x4000
55 #else
56 #define AD9361_RX_0_BASEADDR XPAR_AXI_AD9361_BASEADDR
57 #define AD9361_TX_0_BASEADDR XPAR_AXI_AD9361_BASEADDR + 0x4000
58 #endif
59 #ifdef XPAR_AXI_AD9361_1_BASEADDR
60 #define AD9361_RX_1_BASEADDR XPAR_AXI_AD9361_1_BASEADDR
61 #define AD9361_TX_1_BASEADDR XPAR_AXI_AD9361_1_BASEADDR + 0x4000
62 #else
63 #ifdef XPAR_AXI_AD9361_0_BASEADDR
64 #define AD9361_RX_1_BASEADDR XPAR_AXI_AD9361_0_BASEADDR
65 #define AD9361_TX_1_BASEADDR XPAR_AXI_AD9361_0_BASEADDR + 0x4000
66 #else
67 #define AD9361_RX_1_BASEADDR XPAR_AXI_AD9361_BASEADDR
68 #define AD9361_TX_1_BASEADDR XPAR_AXI_AD9361_BASEADDR + 0x4000
69 #endif
70 #endif
71 #ifdef XPAR_AXI_DMAC_0_BASEADDR
72 #define CF_AD9361_RX_DMA_BASEADDR XPAR_AXI_DMAC_0_BASEADDR
73 #else
74 #define CF_AD9361_RX_DMA_BASEADDR XPAR_AXI_AD9361_ADC_DMA_BASEADDR
75 #endif
76 #ifdef XPAR_AXI_DMAC_1_BASEADDR
77 #define CF_AD9361_TX_DMA_BASEADDR XPAR_AXI_DMAC_1_BASEADDR
78 #else
79 #define CF_AD9361_TX_DMA_BASEADDR XPAR_AXI_AD9361_DAC_DMA_BASEADDR
80 #endif
81 #ifdef _XPARAMETERS_PS_H_
82 #define ADC_DDR_BASEADDR XPAR_DDR_MEM_BASEADDR + 0x800000
83 #define DAC_DDR_BASEADDR XPAR_DDR_MEM_BASEADDR + 0xA000000
84 
85 #define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
86 #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
87 
88 #ifdef XPS_BOARD_ZCU102
89 #define GPIO_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
90 #define GPIO_RESET_PIN 124
91 #define GPIO_SYNC_PIN 123
92 #define GPIO_ENABLE_PIN 125
93 #define GPIO_TXNRX_PIN 126
94 #define SPI_DEVICE_ID XPAR_PSU_SPI_0_DEVICE_ID
95 #define UART_IRQ_ID XPAR_XUARTPS_0_INTR
96 #else
97 #define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
98 #define GPIO_RESET_PIN 100
99 #define GPIO_SYNC_PIN 99
100 #define GPIO_ENABLE_PIN 101
101 #define GPIO_TXNRX_PIN 102
102 #define SPI_DEVICE_ID XPAR_PS7_SPI_0_DEVICE_ID
103 #define UART_IRQ_ID XPAR_XUARTPS_1_INTR
104 #endif
105 #define GPIO_RESET_PIN_ZC702 84
106 #define GPIO_RESET_PIN_ZC706 83
107 #define GPIO_RESET_PIN_ZED 100
108 #define GPIO_RESET_PIN_2 113
109 #define GPIO_CAL_SW1_PIN 107
110 #define GPIO_CAL_SW2_PIN 108
111 #define GPIO_CTL0_PIN 94
112 #define GPIO_CTL1_PIN 95
113 #define GPIO_CTL2_PIN 96
114 #define GPIO_CTL3_PIN 97
115 
116 #else
117 #ifdef XPAR_DDR3_SDRAM_S_AXI_BASEADDR
118 #define ADC_DDR_BASEADDR XPAR_DDR3_SDRAM_S_AXI_BASEADDR + 0x800000
119 #define DAC_DDR_BASEADDR XPAR_DDR3_SDRAM_S_AXI_BASEADDR + 0xA000000
120 #else
121 #define ADC_DDR_BASEADDR XPAR_AXI_DDR_CNTRL_BASEADDR + 0x800000
122 #define DAC_DDR_BASEADDR XPAR_AXI_DDR_CNTRL_BASEADDR + 0xA000000
123 #endif
124 
125 #define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
126 #define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
127 #define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
128 
129 #define GPIO_DEVICE_ID 0
130 #define GPIO_RESET_PIN 46
131 #ifdef XPAR_AXI_SPI_0_DEVICE_ID
132 #define SPI_DEVICE_ID XPAR_AXI_SPI_0_DEVICE_ID
133 #else
134 #define SPI_DEVICE_ID XPAR_SPI_0_DEVICE_ID
135 #endif
136 #endif
137 
138 #define SPI_CS 0
139 #define SPI_CS_2 1
140 
141 #define RX_CORE_BASEADDR AD9361_RX_0_BASEADDR
142 #define TX_CORE_BASEADDR AD9361_TX_0_BASEADDR
143 #endif
144 
145 #define DAC_BUFFER_SAMPLES 1024
146 #define ADC_BUFFER_SAMPLES 16384
147 #define ADC_CHANNELS 4
148 
149 #if defined LINUX_PLATFORM || defined GENERIC_PLATFORM
150 #define RX_CORE_BASEADDR 0
151 #define TX_CORE_BASEADDR 1
152 #define CF_AD9361_RX_DMA_BASEADDR 2
153 #define CF_AD9361_TX_DMA_BASEADDR 3
154 
155 #define SPI_DEVICE_ID 0
156 #define SPI_CS 0
157 
158 #define MAX_SIZE_BASE_ADDR 0x1000
159 
160 #define DAC_DDR_BASEADDR ((uintptr_t)out_buff)
161 #define ADC_DDR_BASEADDR ((uintptr_t)in_buff)
162 
163 #define GPIO_RESET_PIN 1006
164 #endif
165 
166 #endif // __PARAMETERS_H__