no-OS
ad9361.h
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1 /***************************************************************************/
38 #ifndef IIO_FREQUENCY_AD9361_H_
39 #define IIO_FREQUENCY_AD9361_H_
40 
41 /******************************************************************************/
42 /***************************** Include Files **********************************/
43 /******************************************************************************/
44 #include <stdint.h>
45 #include "no_os_gpio.h"
46 #include "common.h"
47 
48 /******************************************************************************/
49 /********************** Macros and Constants Definitions **********************/
50 /******************************************************************************/
51 #define REG_SPI_CONF 0x000 /* SPI Configuration */
52 #define REG_MULTICHIP_SYNC_AND_TX_MON_CTRL 0x001 /* Multi-Chip Sync and Tx Mon Control */
53 #define REG_TX_ENABLE_FILTER_CTRL 0x002 /* Tx Enable & Filter Control */
54 #define REG_RX_ENABLE_FILTER_CTRL 0x003 /* Rx Enable & Filter Control */
55 #define REG_INPUT_SELECT 0x004 /* Input Select */
56 #define REG_RFPLL_DIVIDERS 0x005 /* RFPLL Dividers */
57 #define REG_RX_CLOCK_DATA_DELAY 0x006 /* Rx Clock & Data Delay */
58 #define REG_TX_CLOCK_DATA_DELAY 0x007 /* Tx Clock & Data Delay */
59 #define REG_CLOCK_ENABLE 0x009 /* Clock Enable */
60 #define REG_BBPLL 0x00A /* BBPLL */
61 #define REG_TEMP_OFFSET 0x00B /* Offset */
62 #define REG_START_TEMP_READING 0x00C /* Start Temp Reading */
63 #define REG_TEMP_SENSE2 0x00D /* Temp Sense2 */
64 #define REG_TEMPERATURE 0x00E /* Temperature */
65 #define REG_TEMP_SENSOR_CONFIG 0x00F /* Temp Sensor Config */
66 #define REG_PARALLEL_PORT_CONF_1 0x010 /* Parallel Port Configuration 1 */
67 #define REG_PARALLEL_PORT_CONF_2 0x011 /* Parallel Port Configuration 2 */
68 #define REG_PARALLEL_PORT_CONF_3 0x012 /* Parallel Port Configuration 3 */
69 #define REG_ENSM_MODE 0x013 /* ENSM Mode */
70 #define REG_ENSM_CONFIG_1 0x014 /* ENSM Config 1 */
71 #define REG_ENSM_CONFIG_2 0x015 /* ENSM Config 2 */
72 #define REG_CALIBRATION_CTRL 0x016 /* Calibration Control */
73 #define REG_STATE 0x017 /* State */
74 #define REG_AUXDAC_1_WORD 0x018 /* AuxDAC 1 Word */
75 #define REG_AUXDAC_2_WORD 0x019 /* AuxDAC 2 Word */
76 #define REG_AUXDAC_1_CONFIG 0x01A /* AuxDAC 1 Config */
77 #define REG_AUXDAC_2_CONFIG 0x01B /* AuxDAC 2 Config */
78 #define REG_AUXADC_CLOCK_DIVIDER 0x01C /* AuxADC Clock Divider */
79 #define REG_AUXADC_CONFIG 0x01D /* Aux ADC Config */
80 #define REG_AUXADC_WORD_MSB 0x01E /* AuxADC Word MSB */
81 #define REG_AUXADC_LSB 0x01F /* AuxADC LSB */
82 #define REG_AUTO_GPO 0x020 /* Auto GPO */
83 #define REG_AGC_GAIN_LOCK_DELAY 0x021 /* AGC Gain Lock Delay */
84 #define REG_AGC_ATTACK_DELAY 0x022 /* AGC Attack Delay */
85 #define REG_AUXDAC_ENABLE_CTRL 0x023 /* AuxDAC Enable Control */
86 #define REG_RX_LOAD_SYNTH_DELAY 0x024 /* RX Load Synth Delay */
87 #define REG_TX_LOAD_SYNTH_DELAY 0x025 /* TX Load Synth Delay */
88 #define REG_EXTERNAL_LNA_CTRL 0x026 /* External LNA control */
89 #define REG_GPO_FORCE_AND_INIT 0x027 /* GPO Force and Init */
90 #define REG_GPO0_RX_DELAY 0x028 /* GPO0 Rx delay */
91 #define REG_GPO1_RX_DELAY 0x029 /* GPO1 Rx delay */
92 #define REG_GPO2_RX_DELAY 0x02A /* GPO2 Rx delay */
93 #define REG_GPO3_RX_DELAY 0x02B /* GPO3 Rx delay */
94 #define REG_GPO0_TX_DELAY 0x02C /* GPO0 Tx Delay */
95 #define REG_GPO1_TX_DELAY 0x02D /* GPO1 Tx Delay */
96 #define REG_GPO2_TX_DELAY 0x02E /* GPO2 Tx Delay */
97 #define REG_GPO3_TX_DELAY 0x02F /* GPO3 Tx Delay */
98 #define REG_AUXDAC1_RX_DELAY 0x030 /* AuxDAC1 Rx Delay */
99 #define REG_AUXDAC1_TX_DELAY 0x031 /* AuxDAC1 Tx Delay */
100 #define REG_AUXDAC2_RX_DELAY 0x032 /* AuxDAC2 Rx Delay */
101 #define REG_AUXDAC2_TX_DELAY 0x033 /* AuxDAC2 Tx Delay */
102 #define REG_CTRL_OUTPUT_POINTER 0x035 /* Control Output Pointer */
103 #define REG_CTRL_OUTPUT_ENABLE 0x036 /* Control Output Enable */
104 #define REG_PRODUCT_ID 0x037 /* Product ID */
105 #define REG_REFERENCE_CLOCK_CYCLES 0x03A /* Reference Clock Cycles */
106 #define REG_DIGITAL_IO_CTRL 0x03B /* Digital I/O Control */
107 #define REG_LVDS_BIAS_CTRL 0x03C /* LVDS Bias control */
108 #define REG_LVDS_INVERT_CTRL1 0x03D /* LVDS Invert control1 */
109 #define REG_LVDS_INVERT_CTRL2 0x03E /* LVDS Invert control2 */
110 #define REG_SDM_CTRL_1 0x03F /* SDM Control 1 */
111 #define REG_FRACT_BB_FREQ_WORD_1 0x041 /* Fractional BB Freq Word 1 */
112 #define REG_FRACT_BB_FREQ_WORD_2 0x042 /* Fractional BB Freq Word 2 */
113 #define REG_FRACT_BB_FREQ_WORD_3 0x043 /* Fractional BB Freq Word 3 */
114 #define REG_INTEGER_BB_FREQ_WORD 0x044 /* Integer BB Freq Word */
115 #define REG_CLOCK_CTRL 0x045 /* Clock Control */
116 #define REG_CP_CURRENT 0x046 /* CP Current */
117 #define REG_CP_BLEED_CURRENT 0x047 /* CP Bleed Current */
118 #define REG_LOOP_FILTER_1 0x048 /* Loop Filter 1 */
119 #define REG_LOOP_FILTER_2 0x049 /* Loop Filter 2 */
120 #define REG_LOOP_FILTER_3 0x04A /* Loop Filter 3 */
121 #define REG_VCO_CTRL 0x04B /* VCO Control */
122 #define REG_VCO_PROGRAM_1 0x04C
123 #define REG_VCO_PROGRAM_2 0x04D
124 #define REG_SDM_CTRL 0x04E /* SDM Control */
125 #define REG_RX_SYNTH_POWER_DOWN_OVERRIDE 0x050 /* Rx Synth Power Down Override */
126 #define REG_TX_SYNTH_POWER_DOWN_OVERRIDE 0x051 /* TX Synth Power Down Override */
127 #define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1 0x052 /* Rx Analog Power Down Override 1 */
128 #define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2 0x053 /* Rx Analog Power Down Override 2 */
129 #define REG_RX1_ADC_POWER_DOWN_OVERRIDE 0x054 /* Rx1 ADC Power Down Override */
130 #define REG_RX2_ADC_POWER_DOWN_OVERRIDE 0x055 /* Rx2 ADC Power Down Override */
131 #define REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1 0x056 /* Tx Analog Power Down Override 1 */
132 #define REG_ANALOG_POWER_DOWN_OVERRIDE 0x057 /* Analog Power Down Override */
133 #define REG_MISC_POWER_DOWN_OVERRIDE 0x058 /* Misc Power Down Override */
134 #define REG_CH_1_OVERFLOW 0x05E /* CH 1 Overflow */
135 #define REG_CH_2_OVERFLOW 0x05F /* CH 2 Overflow */
136 #define REG_TX_FILTER_COEF_ADDR 0x060 /* TX Filter Coefficient Address */
137 #define REG_TX_FILTER_COEF_WRITE_DATA_1 0x061 /* TX Filter Coefficient Write Data 1 */
138 #define REG_TX_FILTER_COEF_WRITE_DATA_2 0x062 /* TX Filter Coefficient Write Data 2 */
139 #define REG_TX_FILTER_COEF_READ_DATA_1 0x063 /* TX Filter Coefficient Read Data 1 */
140 #define REG_TX_FILTER_COEF_READ_DATA_2 0x064 /* TX Filter Coefficient Read Data 2 */
141 #define REG_TX_FILTER_CONF 0x065 /* TX Filter Configuration */
142 #define REG_TX_MON_LOW_GAIN 0x067 /* Tx Mon Low Gain */
143 #define REG_TX_MON_HIGH_GAIN 0x068 /* Tx Mon High Gain */
144 #define REG_TX_MON_DELAY 0x069 /* Tx Mon Delay */
145 #define REG_TX_LEVEL_THRESH 0x06A /* Tx Level Threshold */
146 #define REG_TX_RSSI1 0x06B /* TX RSSI1 */
147 #define REG_TX_RSSI2 0x06C /* TX RSSI2 */
148 #define REG_TX_RSSI_LSB 0x06D /* TX RSSI LSB */
149 #define REG_TPM_MODE_ENABLE 0x06E /* TPM Mode Enable */
150 #define REG_TX_MON_TEMP_GAIN_COEF 0x06F /* Temp Gain Coefficient */
151 #define REG_TX_MON_1_CONFIG 0x070 /* Tx Mon 1 Config */
152 #define REG_TX_MON_2_CONFIG 0x071 /* Tx Mon 2 Config */
153 #define REG_TX1_ATTEN_0 0x073 /* Tx1 Atten 0 */
154 #define REG_TX1_ATTEN_1 0x074 /* Tx1 Atten 1 */
155 #define REG_TX2_ATTEN_0 0x075 /* Tx2 Atten 0 */
156 #define REG_TX2_ATTEN_1 0x076 /* Tx2 Atten 1 */
157 #define REG_TX_ATTEN_OFFSET 0x077 /* Tx Atten Offset */
158 #define REG_TX_ATTEN_THRESH 0x078 /* Tx Atten Threshold */
159 #define REG_TX1_DIG_ATTEN 0x079 /* Tx1 Dig Attenuation */
160 #define REG_TX2_DIG_ATTEN 0x07C /* Tx2 Dig Attenuation */
161 #define REG_TX1_SYMBOL_ATTEN 0x07F /* TX1 Symbol Attenuation */
162 #define REG_TX2_SYMBOL_ATTEN 0x080 /* TX2 Symbol Attenuation */
163 #define REG_TX_SYMBOL_ATTEN_CONFIG 0x081 /* TX Symbol Atten Config */
164 #define REG_TX1_OUT_1_PHASE_CORR 0x08E /* Tx1 Out 1 Phase Corr */
165 #define REG_TX1_OUT_1_GAIN_CORR 0x08F /* Tx1 Out 1 Gain Corr */
166 #define REG_TX2_OUT_1_PHASE_CORR 0x090 /* Tx2 Out 1 Phase Corr */
167 #define REG_TX2_OUT_1_GAIN_CORR 0x091 /* Tx2 Out 1 Gain Corr */
168 #define REG_TX1_OUT_1_OFFSET_I 0x092 /* Tx1 Out 1 Offset I */
169 #define REG_TX1_OUT_1_OFFSET_Q 0x093 /* Tx1 Out 1 Offset Q */
170 #define REG_TX2_OUT_1_OFFSET_I 0x094 /* Tx2 Out 1 Offset I */
171 #define REG_TX2_OUT_1_OFFSET_Q 0x095 /* Tx2 Out 1 Offset Q */
172 #define REG_TX1_OUT_2_PHASE_CORR 0x096 /* Tx1 Out 2 Phase Corr */
173 #define REG_TX1_OUT_2_GAIN_CORR 0x097 /* Tx1 Out 2 Gain Corr */
174 #define REG_TX2_OUT_2_PHASE_CORR 0x098 /* Tx2 Out 2 Phase Corr */
175 #define REG_TX2_OUT_2_GAIN_CORR 0x099 /* Tx2 Out 2 Gain Corr */
176 #define REG_TX1_OUT_2_OFFSET_I 0x09A /* Tx1 Out 2 Offset I */
177 #define REG_TX1_OUT_2_OFFSET_Q 0x09B /* Tx1 Out 2 Offset Q */
178 #define REG_TX2_OUT_2_OFFSET_I 0x09C /* Tx2 Out 2 Offset I */
179 #define REG_TX2_OUT_2_OFFSET_Q 0x09D /* Tx2 Out 2 Offset Q */
180 #define REG_TX_FORCE_BITS 0x09F /* Force Bits */
181 #define REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET 0x0A0 /* Quad Cal NCO Freq & Phase Offset */
182 #define REG_QUAD_CAL_CTRL 0x0A1 /* Quad Cal Control */
183 #define REG_KEXP_1 0x0A2 /* Kexp 1 */
184 #define REG_KEXP_2 0x0A3 /* Kexp 2 */
185 #define REG_QUAD_SETTLE_COUNT 0x0A4 /* QUAD Settle count */
186 #define REG_MAG_FTEST_THRESH 0x0A5 /* Mag. Ftest Thresh */
187 #define REG_MAG_FTEST_THRESH_2 0x0A6 /* Mag. Ftest Thresh 2 */
188 #define REG_QUAD_CAL_STATUS_TX1 0x0A7 /* Quad cal status Tx1 */
189 #define REG_QUAD_CAL_STATUS_TX2 0x0A8 /* Quad cal status Tx2 */
190 #define REG_QUAD_CAL_COUNT 0x0A9 /* Quad cal Count */
191 #define REG_TX_QUAD_FULL_LMT_GAIN 0x0AA /* Tx Quad Full/LMT Gain */
192 #define REG_SQUARER_CONFIG 0x0AB /* Squarer Config */
193 #define REG_TX_QUAD_CAL_ATTEN 0x0AC /* TX Quad Cal Atten */
194 #define REG_THRESH_ACCUM 0x0AD /* Thresh Accum */
195 #define REG_TX_QUAD_LPF_GAIN 0x0AE /* Tx Quad LPF Gain */
196 #define REG_TXDAC_VDS_I 0x0B0 /* TxDAC Vds I */
197 #define REG_TXDAC_VDS_Q 0x0B1 /* TxDAC Vds Q */
198 #define REG_TXDAC_GN_I 0x0B2 /* TxDAC gn I */
199 #define REG_TXDAC_GN_Q 0x0B3 /* TxDAC gn Q */
200 #define REG_TXBBF_OPAMP_A 0x0C0 /* TxBBF OpAmp A */
201 #define REG_TXBBF_OPAMP_B 0x0C1 /* TxBBF OpAmp B */
202 #define REG_TX_BBF_R1 0x0C2 /* Tx BBF R1 */
203 #define REG_TX_BBF_R2 0x0C3 /* Tx BBF R2 */
204 #define REG_TX_BBF_R3 0x0C4 /* Tx BBF R3 */
205 #define REG_TX_BBF_R4 0x0C5 /* Tx BBF R4 */
206 #define REG_TX_BBF_RP 0x0C6 /* Tx BBF RP */
207 #define REG_TX_BBF_C1 0x0C7 /* Tx BBF C1 */
208 #define REG_TX_BBF_C2 0x0C8 /* Tx BBF C2 */
209 #define REG_TX_BBF_CP 0x0C9 /* Tx BBF Cp */
210 #define REG_TX_TUNE_CTRL 0x0CA /* Tx Tune Control */
211 #define REG_TX_BBF_R2B 0x0CB /* Tx BBF R2b */
212 #define REG_TX_BBF_TUNE 0x0CC /* Tx BBF Tune */
213 #define REG_CONFIG0 0x0D0 /* Config0 */
214 #define REG_RESISTOR 0x0D1 /* Resistor */
215 #define REG_CAPACITOR 0x0D2 /* Capacitor */
216 #define REG_LO_CM 0x0D3 /* LO CM */
217 #define REG_TX_BBF_TUNE_DIVIDER 0x0D6 /* TX BBF Tune Divider */
218 #define REG_TX_BBF_TUNE_MODE 0x0D7 /* TX BBF Tune Mode */
219 #define REG_RX_FILTER_COEF_ADDR 0x0F0 /* Rx Filter Coeff Addr */
220 #define REG_RX_FILTER_COEF_DATA_1 0x0F1 /* Rx Filter Coeff Data 1 */
221 #define REG_RX_FILTER_COEF_DATA_2 0x0F2 /* Rx Filter Coeff Data 2 */
222 #define REG_RX_FILTER_COEF_READ_DATA_1 0x0F3 /* Rx Filter Coeff Read Data 1 */
223 #define REG_RX_FILTER_COEF_READ_DATA_2 0x0F4 /* Rx Filter Coeff Read Data 2 */
224 #define REG_RX_FILTER_CONFIG 0x0F5 /* Rx Filter Config */
225 #define REG_RX_FILTER_GAIN 0x0F6 /* Rx Filter Gain */
226 #define REG_AGC_CONFIG_1 0x0FA /* AGC Config1 */
227 #define REG_AGC_CONFIG_2 0x0FB /* AGC config2 */
228 #define REG_AGC_CONFIG_3 0x0FC /* AGC Config3 */
229 #define REG_MAX_LMT_FULL_GAIN 0x0FD /* Max LMT/Full Gain */
230 #define REG_PEAK_WAIT_TIME 0x0FE /* Peak Wait Time */
231 #define REG_DIGITAL_GAIN 0x100 /* Digital Gain */
232 #define REG_AGC_LOCK_LEVEL 0x101 /* AGC Lock Level */
233 #define REG_ADC_NOISE_CORRECTION_FACTOR 0x102 /* ADC noise Correction Factor */
234 #define REG_GAIN_STP_CONFIG1 0x103 /* Gain Step Config1 */
235 #define REG_ADC_SMALL_OVERLOAD_THRESH 0x104 /* ADC Small Overload Threshold */
236 #define REG_ADC_LARGE_OVERLOAD_THRESH 0x105 /* ADC Large Overload Threshold */
237 #define REG_GAIN_STP_CONFIG_2 0x106 /* Gain Step Config 2 */
238 #define REG_SMALL_LMT_OVERLOAD_THRESH 0x107 /* Small LMT Overload Threshold */
239 #define REG_LARGE_LMT_OVERLOAD_THRESH 0x108 /* Large LMT Overload Threshold */
240 #define REG_RX1_MANUAL_LMT_FULL_GAIN 0x109 /* Rx1 Manual LMT/Full Gain */
241 #define REG_RX1_MANUAL_LPF_GAIN 0x10A /* Rx1 Manual LPF gain */
242 #define REG_RX1_MANUAL_DIGITALFORCED_GAIN 0x10B /* Rx1 Manual Digital/Forced Gain */
243 #define REG_RX2_MANUAL_LMT_FULL_GAIN 0x10C /* Rx2 Manual LMT/Full Gain */
244 #define REG_RX2_MANUAL_LPF_GAIN 0x10D /* Rx2 Manual LPF Gain */
245 #define REG_RX2_MANUAL_DIGITALFORCED_GAIN 0x10E /* Rx2 Manual Digital/Forced Gain */
246 #define REG_FAST_CONFIG_1 0x110 /* Config 1 */
247 #define REG_FAST_CONFIG_2_SETTLING_DELAY 0x111 /* Config 2 & Settling Delay */
248 #define REG_FAST_ENERGY_LOST_THRESH 0x112 /* Energy Lost Threshold */
249 #define REG_FAST_STRONGER_SIGNAL_THRESH 0x113 /* Stronger Signal Threshold */
250 #define REG_FAST_LOW_POWER_THRESH 0x114 /* Low Power Threshold */
251 #define REG_FAST_STRONG_SIGNAL_FREEZE 0x115 /* Strong Signal Freeze */
252 #define REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN 0x116 /* Final Over Range and Opt Gain */
253 #define REG_FAST_ENERGY_DETECT_COUNT 0x117 /* Energy Detect Count */
254 #define REG_FAST_AGCLL_UPPER_LIMIT 0x118 /* AGCLL Upper Limit */
255 #define REG_FAST_GAIN_LOCK_EXIT_COUNT 0x119 /* Gain Lock Exit Count */
256 #define REG_FAST_INITIAL_LMT_GAIN_LIMIT 0x11A /* Initial LMT Gain Limit */
257 #define REG_FAST_INCREMENT_TIME 0x11B /* Increment Time */
258 #define REG_AGC_INNER_LOW_THRESH 0x120 /* AGC Inner Low Threshold */
259 #define REG_LMT_OVERLOAD_COUNTERS 0x121 /* LMT Overload Counters */
260 #define REG_ADC_OVERLOAD_COUNTERS 0x122 /* ADC Overload Counters */
261 #define REG_GAIN_STP1 0x123 /* Gain Step1 */
262 #define REG_GAIN_UPDATE_COUNTER1 0x124 /* Gain Update Counter1 */
263 #define REG_GAIN_UPDATE_COUNTER2 0x125 /* Gain Update Counter2 */
264 #define REG_DIGITAL_SAT_COUNTER 0x128 /* Digital Sat Counter */
265 #define REG_OUTER_POWER_THRESHS 0x129 /* Outer Power Thresholds */
266 #define REG_GAIN_STP_2 0x12A /* Gain Step 2 */
267 #define REG_EXT_LNA_HIGH_GAIN 0x12C /* Ext LNA High Gain */
268 #define REG_EXT_LNA_LOW_GAIN 0x12D /* Ext LNA Low Gain */
269 #define REG_GAIN_TABLE_ADDRESS 0x130 /* Gain Table Address */
270 #define REG_GAIN_TABLE_WRITE_DATA1 0x131 /* Gain Table Write Data1 */
271 #define REG_GAIN_TABLE_WRITE_DATA2 0x132 /* Gain Table Write Data2 */
272 #define REG_GAIN_TABLE_WRITE_DATA3 0x133 /* Gain Table Write Data 3 */
273 #define REG_GAIN_TABLE_READ_DATA1 0x134 /* Gain Table Read Data 1 */
274 #define REG_GAIN_TABLE_READ_DATA2 0x135 /* Gain Table Read Data 2 */
275 #define REG_GAIN_TABLE_READ_DATA3 0x136 /* Gain Table Read Data 3 */
276 #define REG_GAIN_TABLE_CONFIG 0x137 /* Gain Table Config */
277 #define REG_GM_SUB_TABLE_ADDRESS 0x138 /* Gm Sub Table Address */
278 #define REG_GM_SUB_TABLE_GAIN_WRITE 0x139 /* Gm Sub Table Gain Word Write */
279 #define REG_GM_SUB_TABLE_BIAS_WRITE 0x13A /* Gm Sub Table Bias Word Write */
280 #define REG_GM_SUB_TABLE_CTRL_WRITE 0x13B /* Gm Sub Table Control Word Write */
281 #define REG_GM_SUB_TABLE_GAIN_READ 0x13C /* Gm Sub Table Gain Word Read */
282 #define REG_GM_SUB_TABLE_BIAS_READ 0x13D /* Gm Sub Table Bias Word Read */
283 #define REG_GM_SUB_TABLE_CTRL_READ 0x13E /* Gm Sub Table Control Word Read */
284 #define REG_GM_SUB_TABLE_CONFIG 0x13F /* Gm Sub Table Config */
285 #define REG_WORD_ADDRESS 0x140 /* Word Address */
286 #define REG_GAIN_DIFF_WORDERROR_WRITE 0x141 /* Gain Diff Word/Error Write */
287 #define REG_GAIN_ERROR_READ 0x142 /* Gain Error Read */
288 #define REG_CONFIG 0x143 /* Config */
289 #define REG_LNA_GAIN_DIFF_READ_BACK 0x144 /* LNA Gain Diff Read Back */
290 #define REG_MAX_MIXER_CALIBRATION_GAIN_INDEX 0x145 /* Max Mixer Calibration Gain Index */
291 #define REG_TEMP_GAIN_COEF 0x146 /* Temp Gain Coefficient */
292 #define REG_SETTLE_TIME 0x147 /* Settle Time */
293 #define REG_MEASURE_DURATION 0x148 /* Measure Duration */
294 #define REG_CAL_TEMP_SENSOR_WORD 0x149 /* Cal Temp sensor word */
295 #define REG_MEASURE_DURATION_01 0x150 /* Measure Duration 0&1 */
296 #define REG_MEASURE_DURATION_23 0x151 /* Measure Duration 2&3 */
297 #define REG_RSSI_WEIGHT_0 0x152 /* RSSI Weight 0 */
298 #define REG_RSSI_WEIGHT_1 0x153 /* RSSI Weight 1 */
299 #define REG_RSSI_WEIGHT_2 0x154 /* RSSI Weight 2 */
300 #define REG_RSSI_WEIGHT_3 0x155 /* RSSI Weight 3 */
301 #define REG_RSSI_DELAY 0x156 /* RSSI delay */
302 #define REG_RSSI_WAIT_TIME 0x157 /* RSSI wait time */
303 #define REG_RSSI_CONFIG 0x158 /* RSSI Config */
304 #define REG_ADC_MEASURE_DURATION_01 0x159 /* ADC Measure Duration 0&1 */
305 #define REG_ADC_WEIGHT_0 0x15A /* ADC Weight 0 */
306 #define REG_ADC_WEIGHT_1 0x15B /* ADC Weight 1 */
307 #define REG_DEC_POWER_MEASURE_DURATION_0 0x15C /* Dec Power Measure Duration 0 */
308 #define REG_LNA_GAIN 0x15D /* LNA Gain */
309 #define REG_CH1_ADC_POWER 0x160 /* CH1 ADC Power */
310 #define REG_CH1_RX_FILTER_POWER 0x161 /* CH1 Rx filter Power */
311 #define REG_CH2_ADC_POWER 0x162 /* CH2 ADC Power */
312 #define REG_CH2_RX_FILTER_POWER 0x163 /* CH2 Rx filter Power */
313 #define REG_RX_QUAD_CAL_LEVEL 0x168 /* Rx Quad Cal Level */
314 #define REG_CALIBRATION_CONFIG_1 0x169 /* Calibration Config 1 */
315 #define REG_CALIBRATION_CONFIG_2 0x16A /* Calibration config2 */
316 #define REG_CALIBRATION_CONFIG_3 0x16B /* Calibration config3 */
317 #define REG_CALIB_COUNT 0x16C /* Calib count */
318 #define REG_SETTLE_COUNT 0x16D /* Settle count */
319 #define REG_RX_QUAD_GAIN1 0x16E /* Rx Quad gain1 */
320 #define REG_RX_QUAD_GAIN2 0x16F /* Rx Quad gain2 */
321 #define REG_RX1_INPUT_A_PHASE_CORR 0x170 /* Rx1 Input A Phase Corr */
322 #define REG_RX1_INPUT_A_GAIN_CORR 0x171 /* Rx1 Input A Gain Corr */
323 #define REG_RX2_INPUT_A_PHASE_CORR 0x172 /* Rx2 Input A Phase Corr */
324 #define REG_RX2_INPUT_A_GAIN_CORR 0x173 /* Rx2 Input A Gain Corr */
325 #define REG_RX1_INPUT_A_Q_OFFSET 0x174 /* Rx1 Input A Q" Offset */
326 #define REG_RX1_INPUT_A_OFFSETS 0x175 /* Rx1 Input A Offsets */
327 #define REG_INPUT_A_OFFSETS_1 0x176 /* Input A Offsets 1 */
328 #define REG_RX2_INPUT_A_OFFSETS 0x177 /* Rx2 Input A Offsets */
329 #define REG_RX2_INPUT_A_I_OFFSET 0x178 /* Rx2 Input A "I" Offset */
330 #define REG_RX1_INPUT_BC_PHASE_CORR 0x179 /* Rx1 Input B&C Phase Corr */
331 #define REG_RX1_INPUT_BC_GAIN_CORR 0x17A /* Rx1 Input B&C Gain Corr */
332 #define REG_RX2_INPUT_BC_PHASE_CORR 0x17B /* Rx2 Input B&C Phase Corr */
333 #define REG_RX2_INPUT_BC_GAIN_CORR 0x17C /* Rx2 Input B&C Gain Corr */
334 #define REG_RX1_INPUT_BC_Q_OFFSET 0x17D /* Rx1 Input B&C "Q" Offset */
335 #define REG_RX1_INPUT_BC_OFFSETS 0x17E /* Rx1 Input B&C Offsets */
336 #define REG_INPUT_BC_OFFSETS_1 0x17F /* Input B&C Offsets 1 */
337 #define REG_RX2_INPUT_BC_OFFSETS 0x180 /* Rx2 Input B&C Offsets */
338 #define REG_RX2_INPUT_BC_I_OFFSET 0x181 /* Rx2 Input B&C "I" Offset */
339 #define REG_FORCE_BITS 0x182 /* Force Bits */
340 #define REG_WAIT_COUNT 0x185 /* Wait Count */
341 #define REG_RF_DC_OFFSET_COUNT 0x186 /* RF DC Offset Count */
342 #define REG_RF_DC_OFFSET_CONFIG_1 0x187 /* RF DC Offset Config1 */
343 #define REG_RF_DC_OFFSET_ATTEN 0x188 /* RF DC Offset Attenuation */
344 #define REG_INVERT_BITS 0x189 /* Invert Bits */
345 #define REG_DC_OFFSET_CONFIG2 0x18B /* DC Offset Config2 */
346 #define REG_RF_CAL_GAIN_INDEX 0x18C /* RF Cal Gain Index */
347 #define REG_SOI_THRESH 0x18D /* SOI Threshold */
348 #define REG_BB_DC_OFFSET_SHIFT 0x190 /* BB DC Offset Shift */
349 #define REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT 0x191 /* BB DC Offset Fast Settle Shift */
350 #define REG_BB_FAST_SETTLE_DUR 0x192 /* BB Fast Settle Dur */
351 #define REG_BB_DC_OFFSET_COUNT 0x193 /* BB DC Offset Count */
352 #define REG_BB_DC_OFFSET_ATTEN 0x194 /* BB DC Offset Attenuation */
353 #define REG_RX1_BB_DC_WORD_I_MSB 0x19A /* RX1 BB DC word I MSB */
354 #define REG_RX1_BB_DC_WORD_I_LSB 0x19B /* RX1 BB DC word I LSB */
355 #define REG_RX1_BB_DC_WORD_Q_MSB 0x19C /* RX1 BB DC word Q MSB */
356 #define REG_RX1_BB_DC_WORD_Q_LSB 0x19D /* RX1 BB DC word Q LSB */
357 #define REG_RX2_BB_DC_WORD_I_MSB 0x19E /* RX2 BB DC word I MSB */
358 #define REG_RX2_BB_DC_WORD_I_LSB 0x19F /* RX2 BB DC word I LSB */
359 #define REG_RX2_BB_DC_WORD_Q_MSB 0x1A0 /* RX2 BB DC word Q MSB */
360 #define REG_RX2_BB_DC_WORD_Q_LSB 0x1A1 /* RX2 BB DC word Q LSB */
361 #define REG_BB_TRACK_CORR_WORD_I_MSB 0x1A2 /* BB Track corr word I MSB */
362 #define REG_BB_TRACK_CORR_WORD_I_LSB 0x1A3 /* BB Track corr word I LSB */
363 #define REG_BB_TRACK_CORR_WORD_Q_MSB 0x1A4 /* BB Track corr word Q MSB */
364 #define REG_BB_TRACK_CORR_WORD_Q_LSB 0x1A5 /* BB Track corr word Q LSB */
365 #define REG_RX1_RSSI_SYMBOL 0x1A7 /* Rx1 RSSI Symbol */
366 #define REG_RX1_RSSI_PREAMBLE 0x1A8 /* Rx1 RSSI preamble */
367 #define REG_RX2_RSSI_SYMBOL 0x1A9 /* Rx2 RSSI symbol */
368 #define REG_RX2_RSSI_PREAMBLE 0x1AA /* Rx2 RSSI preamble */
369 #define REG_SYMBOL_LSB 0x1AB /* Symbol LSB */
370 #define REG_PREAMBLE_LSB 0x1AC /* Preamble LSB */
371 #define REG_RX_PATH_GAIN_MSB 0x1AD /* Rx Path Gain */
372 #define REG_RX_PATH_GAIN_LSB 0x1AE /* Rx Path Gain */
373 #define REG_RX_DIFF_LNA_FORCE 0x1B0 /* Rx Diff LNA Force */
374 #define REG_RX_LNA_BIAS_COARSE 0x1B1 /* Rx LNA Bias Coarse */
375 #define REG_RX_LNA_BIAS_FINE_0 0x1B2 /* Rx LNA Bias Fine 0 */
376 #define REG_RX_LNA_BIAS_FINE_1 0x1B3 /* Rx LNA Bias Fine 1 */
377 #define REG_RX_MIX_GM_CONFIG 0x1C0 /* Rx Mix Gm Config */
378 #define REG_RX1_MIX_GM_FORCE 0x1C1 /* Rx1 Mix Gm Force */
379 #define REG_RX1_MIX_GM_BIAS_FORCE 0x1C2 /* Rx1 Mix Gm Bias (Force) */
380 #define REG_RX2_MIX_GM_FORCE 0x1C3 /* Rx2 Mix Gm Force */
381 #define REG_RX2_MIX_GM_BIAS_FORCE 0x1C4 /* Rx2 Mix Gm Bias (Force) */
382 #define REG_INPUT_A_MSBS 0x1C8 /* Input A MSBs */
383 #define REG_INPUT_A_RX1_I 0x1C9 /* Input A RX1 I */
384 #define REG_INPUT_A_RX1_Q 0x1CA /* Input A RX1 Q */
385 #define REG_INPUT_A_RX2_I 0x1CB /* Input A RX2 I */
386 #define REG_INPUT_A_RX2_Q 0x1CC /* Input A RX2 Q */
387 #define REG_INPUTS_BC_RX1_I 0x1CD /* Inputs B&C RX1 I */
388 #define REG_BAND1_RX1_Q 0x1CE /* Band1 RX1 Q */
389 #define REG_INPUTS_BC_RX2_I 0x1CF /* Inputs B&C RX2 I */
390 #define REG_INPUTS_BC_RX2_Q 0x1D0 /* Inputs B&C RX2 Q */
391 #define REG_INPUTS_BC_MSBS 0x1D1 /* Inputs B&C MSBs */
392 #define REG_FORCE_OS_DAC 0x1D2 /* Force OS DAC */
393 #define REG_RX_MIX_LO_CM 0x1D5 /* Rx Mix LO CM */
394 #define REG_RX_CGB_SEG_ENABLE 0x1D6 /* Rx CGB Seg Enable */
395 #define REG_RX_MIX_INPUTBIAS 0x1D7 /* Rx Mix Input/Bias */
396 #define REG_RX_TIA_CONFIG 0x1DB /* Rx TIA Config */
397 #define REG_TIA1_C_LSB 0x1DC /* TIA1 C LSB */
398 #define REG_TIA1_C_MSB 0x1DD /* TIA1 C MSB */
399 #define REG_TIA2_C_LSB 0x1DE /* TIA2 C LSB */
400 #define REG_TIA2_C_MSB 0x1DF /* TIA2 C MSB */
401 #define REG_RX1_BBF_R1A 0x1E0 /* Rx1 BBF R1A */
402 #define REG_RX2_BBF_R1A 0x1E1 /* Rx2 BBF R1A */
403 #define REG_RX1_TUNE_CTRL 0x1E2 /* Rx1 Tune Control */
404 #define REG_RX2_TUNE_CTRL 0x1E3 /* Rx2 Tune Control */
405 #define REG_RX1_BBF_R5 0x1E4 /* Rx1 BBF R5 */
406 #define REG_RX2_BBF_R5 0x1E5 /* Rx2 BBF R5 */
407 #define REG_RX_BBF_R2346 0x1E6 /* Rx BBF R2346 */
408 #define REG_RX_BBF_C1_MSB 0x1E7 /* Rx BBF C1 MSB */
409 #define REG_RX_BBF_C1_LSB 0x1E8 /* Rx BBF C1 LSB */
410 #define REG_RX_BBF_C2_MSB 0x1E9 /* Rx BBF C2 MSB */
411 #define REG_RX_BBF_C2_LSB 0x1EA /* Rx BBF C2 LSB */
412 #define REG_RX_BBF_C3_MSB 0x1EB /* Rx BBF C3 MSB */
413 #define REG_RX_BBF_C3_LSB 0x1EC /* Rx BBF C3 LSB */
414 #define REG_RX_BBF_CC1_CTR 0x1ED /* Rx BBF CC1 Ctr */
415 #define REG_RX_BBF_POW_RZ_BYTE0 0x1EE /* Rx BBF Pow Rz Byte0 */
416 #define REG_RX_BBF_CC2_CTR 0x1EF /* Rx BBF CC2 Ctr */
417 #define REG_RX_BBF_POW_RZ_BYTE1 0x1F0 /* Rx BBF Pow Rz Byte1 */
418 #define REG_RX_BBF_CC3_CTR 0x1F1 /* Rx BBF CC3 Ctr */
419 #define REG_RX_BBF_R5_TUNE 0x1F2 /* Rx BBF R5 Tune */
420 #define REG_RX_BBF_TUNE 0x1F3 /* Rx BBF Tune */
421 #define REG_RX1_BBF_MAN_GAIN 0x1F4 /* Rx1 BBF Man Gain */
422 #define REG_RX2_BBF_MAN_GAIN 0x1F5 /* Rx2 BBF Man Gain */
423 #define REG_RX_BBF_TUNE_DIVIDE 0x1F8 /* RX BBF Tune Divide */
424 #define REG_RX_BBF_TUNE_CONFIG 0x1F9 /* RX BBF Tune Config */
425 #define REG_POLE_GAIN 0x1FA /* Pole gain */
426 #define REG_RX_BBBW_MHZ 0x1FB /* Rx BBBW MHz */
427 #define REG_RX_BBBW_KHZ 0x1FC /* Rx BBBW kHz */
428 #define REG_FB_DAC_CLK_DELAY1 0x201 /* FB DAC Clk Delay1 */
429 #define REG_FB_DAC_CLK_DELAY2 0x202 /* FB DAC Clk Delay2 */
430 #define REG_FLASH_SAMPLE_CLK_DELAY_3P 0x203 /* Flash Sample Clk Delay 3p */
431 #define REG_FLASH_SAMPLE_CLK_DELAY_3N 0x204 /* Flash Sample Clk Delay 3n */
432 #define REG_TEST_MUX_2I 0x205 /* Test MUX 2i */
433 #define REG_TEST_MUX_2Q 0x206 /* Test MUX 2q */
434 #define REG_INTEGRATOR_1_RESISTANCE 0x207 /* Integrator 1 Resistance */
435 #define REG_INTEGRATOR_1_CAPACITANCE 0x208 /* Integrator 1 Capacitance */
436 #define REG_INTEGRATOR_23_RESISTANCE 0x209 /* Integrator 23 Resistance */
437 #define REG_INTEGRATOR_2_RESISTANCE 0x20A /* Integrator 2 Resistance */
438 #define REG_INTEGRATOR_2_CAPACITANCE 0x20B /* Integrator 2 Capacitance */
439 #define REG_INTEGRATOR_3_RESISTANCE 0x20C /* Integrator 3 Resistance */
440 #define REG_INTEGRATOR_3_CAPACITANCE 0x20D /* Integrator 3 Capacitance */
441 #define REG_INTEGRATOR_AMP_CC 0x20E /* Integrator Amp Cc */
442 #define REG_INT_1_FB_DAC_NMOS_CURRENT_SOURCE 0x20F /* Int 1 FB DAC NMOS Current Source */
443 #define REG_INT_1_FB_DAC_NMOS_CASOADE_BIAS_CURRENT 0x210 /* Int 1 FB DAC NMOS Casoade Bias Current */
444 #define REG_INT_1_FB_DAC_PMOS_CURRENT_SOURCE 0x211 /* Int 1 FB DAC PMOS Current Source */
445 #define REG_INT_2_FB_DAC_NMOS_CURRENT_SOURCE 0x212 /* Int 2 FB DAC NMOS Current Source */
446 #define REG_INT_2_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x213 /* Int 2 FB DAC NMOS Cascode Bias Current */
447 #define REG_INT_2_FB_DAC_PMOS_CURRENT_SOURCE 0x214 /* Int 2 FB DAC PMOS Current Source */
448 #define REG_INT_3_FB_DAC_NMOS_CURRENT_SOURCE 0x215 /* Int 3 FB DAC NMOS Current Source */
449 #define REG_INT_3_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x216 /* Int 3 FB DAC NMOS Cascode Bias Current */
450 #define REG_INT_3_FB_DAC_PMOS_CURRENT_SOURCE 0x217 /* Int 3 FB DAC PMOS Current Source */
451 #define REG_FB_DAC_BIAS_CURRENT 0x218 /* FB DAC Bias Current */
452 #define REG_INT_1_1ST_STAGE_CURRENT 0x219 /* Int 1 1st Stage Current */
453 #define REG_INT_1_1ST_STAGE_CASCODE_CURRENT 0x21A /* Int 1 1st Stage Cascode Current */
454 #define REG_INT_1_2ND_STAGE_CURRENT 0x21B /* Int 1 2nd Stage Current */
455 #define REG_INTEGRATOR_2_1ST_STAGE_CURRENT 0x21C /* Integrator 2 1st Stage Current */
456 #define REG_INT_2_1ST_STAGE_CASCODE_CURRENT 0x21D /* Int 2 1st Stage Cascode Current */
457 #define REG_INT_2_2ND_STAGE_CURRENT 0x21E /* Int 2 2nd Stage Current */
458 #define REG_INT_3_1ST_STAGE_CURRENT 0x21F /* Int 3 1st Stage Current */
459 #define REG_INT_3_1ST_STAGE_CASCODE_CURRENT 0x220 /* Int 3 1st Stage Cascode Current */
460 #define REG_INT_3_2ND_STAGE_CURRENT 0x221 /* Int 3 2nd Stage Current */
461 #define REG_FLASH_BIAS_CURRENT 0x222 /* Flash Bias Current */
462 #define REG_FLASH_LADDER_BIAS 0x223 /* Flash Ladder Bias */
463 #define REG_FLASH_LADDER_CASCODE_CURRENT 0x224 /* Flash Ladder Cascode Current */
464 #define REG_FLASH_LADDER_BIAS2 0x225 /* Flash Ladder Bias2 */
465 #define REG_RESET 0x226 /* Reset */
466 #define REG_RX_PFD_CONFIG 0x230 /* RX PFD Config */
467 #define REG_RX_INTEGER_BYTE_0 0x231 /* RX Integer Byte 0 */
468 #define REG_RX_INTEGER_BYTE_1 0x232 /* RX Integer Byte 1 */
469 #define REG_RX_FRACT_BYTE_0 0x233 /* RX Fractional Byte 0 */
470 #define REG_RX_FRACT_BYTE_1 0x234 /* RX Fractional Byte 1 */
471 #define REG_RX_FRACT_BYTE_2 0x235 /* RX Fractional Byte 2 */
472 #define REG_RX_FORCE_ALC 0x236 /* RX Force ALC */
473 #define REG_RX_FORCE_VCO_TUNE_0 0x237 /* RX Force VCO Tune 0 */
474 #define REG_RX_FORCE_VCO_TUNE_1 0x238 /* RX Force VCO Tune 1 */
475 #define REG_RX_ALC_VARACTOR 0x239 /* RX ALC/Varactor */
476 #define REG_RX_VCO_OUTPUT 0x23A /* RX VCO Output */
477 #define REG_RX_CP_CURRENT 0x23B /* RX CP Current */
478 #define REG_RX_CP_OFFSET 0x23C /* RX CP Offset */
479 #define REG_RX_CP_CONFIG 0x23D /* RX CP Config */
480 #define REG_RX_LOOP_FILTER_1 0x23E /* RX Loop Filter 1 */
481 #define REG_RX_LOOP_FILTER_2 0x23F /* RX Loop Filter 2 */
482 #define REG_RX_LOOP_FILTER_3 0x240 /* RX Loop Filter 3 */
483 #define REG_RX_DITHERCP_CAL 0x241 /* RX Dither/CP Cal */
484 #define REG_RX_VCO_BIAS_1 0x242 /* RX VCO Bias 1 */
485 #define REG_RX_CAL_STATUS 0x244 /* RX Cal Status */
486 #define REG_RX_VCO_CAL_REF 0x245 /* RX VCO Cal Ref */
487 #define REG_RX_VCO_PD_OVERRIDES 0x246 /* RX VCO Pd Overrides */
488 #define REG_RX_CP_OVERRANGE_VCO_LOCK 0x247 /* RX CP Over Range/VCO Lock */
489 #define REG_RX_VCO_LDO 0x248 /* RX VCO LDO */
490 #define REG_RX_VCO_CAL 0x249 /* RX VCO Cal */
491 #define REG_RX_LOCK_DETECT_CONFIG 0x24A /* RX Lock Detect Config */
492 #define REG_RX_CP_LEVEL_DETECT 0x24B /* RX CP Level Detect */
493 #define REG_RX_DSM_SETUP_0 0x24C /* RX DSM Setup 0 */
494 #define REG_RX_DSM_SETUP_1 0x24D /* RX DSM Setup 1 */
495 #define REG_RX_CORRECTION_WORD0 0x24E /* RX Correction Word0 */
496 #define REG_RX_CORRECTION_WORD1 0x24F /* RX Correction Word1 */
497 #define REG_RX_VCO_VARACTOR_CTRL_0 0x250 /* RX VCO Varactor Control 0 */
498 #define REG_RX_VCO_VARACTOR_CTRL_1 0x251 /* RX VCO Varactor Control 1 */
499 #define REG_RX_FAST_LOCK_SETUP 0x25A /* Rx Fast Lock Setup */
500 #define REG_RX_FAST_LOCK_SETUP_INIT_DELAY 0x25B /* Rx Fast Lock Setup Init Delay */
501 #define REG_RX_FAST_LOCK_PROGRAM_ADDR 0x25C /* Rx Fast Lock Program Addr */
502 #define REG_RX_FAST_LOCK_PROGRAM_DATA 0x25D /* Rx Fast Lock Program Data */
503 #define REG_RX_FAST_LOCK_PROGRAM_READ 0x25E /* Rx Fast Lock Program Read */
504 #define REG_RX_FAST_LOCK_PROGRAM_CTRL 0x25F /* Rx Fast Lock Program Control */
505 #define REG_RX_LO_GEN_POWER_MODE 0x261 /* Rx LO Gen Power Mode */
506 #define REG_TX_PFD_CONFIG 0x270 /* TX PFD Config */
507 #define REG_TX_INTEGER_BYTE_0 0x271 /* TX Integer Byte 0 */
508 #define REG_TX_INTEGER_BYTE_1 0x272 /* TX Integer Byte 1 */
509 #define REG_TX_FRACT_BYTE_0 0x273 /* TX Fractional Byte 0 */
510 #define REG_TX_FRACT_BYTE_1 0x274 /* TX Fractional Byte 1 */
511 #define REG_TX_FRACT_BYTE_2 0x275 /* TX Fractional Byte 2 */
512 #define REG_TX_FORCE_ALC 0x276 /* TX Force ALC */
513 #define REG_TX_FORCE_VCO_TUNE_0 0x277 /* TX Force VCO Tune 0 */
514 #define REG_TX_FORCE_VCO_TUNE_1 0x278 /* TX Force VCO Tune 1 */
515 #define REG_TX_ALCVARACT_OR 0x279 /* TX ALC/Varact or */
516 #define REG_TX_VCO_OUTPUT 0x27A /* TX VCO Output */
517 #define REG_TX_CP_CURRENT 0x27B /* TX CP Current */
518 #define REG_TX_CP_OFFSET 0x27C /* TX CP Offset */
519 #define REG_TX_CP_CONFIG 0x27D /* TX CP Config */
520 #define REG_TX_LOOP_FILTER_1 0x27E /* TX Loop Filter 1 */
521 #define REG_TX_LOOP_FILTER_2 0x27F /* TX Loop Filter 2 */
522 #define REG_TX_LOOP_FILTER_3 0x280 /* TX Loop Filter 3 */
523 #define REG_TX_DITHERCP_CAL 0x281 /* TX Dither/CP Cal */
524 #define REG_TX_VCO_BIAS_1 0x282 /* TX VCO Bias 1 */
525 #define REG_TX_VCO_BIAS_2 0x283 /* TX VCO Bias 2 */
526 #define REG_TX_CAL_STATUS 0x284 /* TX Cal Status */
527 #define REG_TX_VCO_CAL_REF 0x285 /* TX VCO Cal Ref */
528 #define REG_TX_VCO_PD_OVERRIDES 0x286 /* TX VCO Pd Overrides */
529 #define REG_TX_CP_OVERRANGE_VCO_LOCK 0x287 /* TX CP Over Range/VCO Lock */
530 #define REG_TX_VCO_LDO 0x288 /* TX VCO LDO */
531 #define REG_TX_VCO_CAL 0x289 /* TX VCO Cal */
532 #define REG_TX_LOCK_DETECT_CONFIG 0x28A /* TX Lock Detect Config */
533 #define REG_TX_CP_LEVEL_DETECT 0x28B /* TX CP Level Detect */
534 #define REG_TX_DSM_SETUP_0 0x28C /* TX DSM Setup 0 */
535 #define REG_TX_DSM_SETUP_1 0x28D /* TX DSM Setup 1 */
536 #define REG_TX_CORRECTION_WORD0 0x28E /* TX Correction Word0 */
537 #define REG_TX_CORRECTION_WORD1 0x28F /* TX Correction Word1 */
538 #define REG_TX_VCO_VARACTOR_CTRL_0 0x290 /* TX VCO Varactor Control 0 */
539 #define REG_TX_VCO_VARACTOR_CTRL_1 0x291 /* TX VCO Varactor Control 1 */
540 #define REG_DCXO_COARSE_TUNE 0x292 /* DCXO Coarse Tune */
541 #define REG_DCXO_FINE_TUNE_HIGH 0x293 /* DCXO Fine Tune2 */
542 #define REG_DCXO_FINE_TUNE_LOW 0x294 /* DCXO Fine Tune1 */
543 #define REG_DCXO_CONFIG 0x295 /* DCXO Config */
544 #define REG_DCXO_TEMPCO_WRITE 0x296 /* DCXO Tempco Write */
545 #define REG_DCXO_TEMPCO_READ 0x297 /* DCXO Tempco Read */
546 #define REG_DCXO_TEMPCO_ADDR 0x298 /* DCXO Tempco Addr */
547 #define REG_DELTA_T_READ 0x299 /* Delta T Read */
548 #define REG_TX_FAST_LOCK_SETUP 0x29A /* Tx Fast Lock Setup */
549 #define REG_TX_FAST_LOCK_SETUP_INIT_DELAY 0x29B /* Tx Fast Lock Setup Init Delay */
550 #define REG_TX_FAST_LOCK_PROGRAM_ADDR 0x29C /* Tx Fast Lock Program Addr */
551 #define REG_TX_FAST_LOCK_PROGRAM_DATA 0x29D /* Tx Fast Lock Program Data */
552 #define REG_TX_FAST_LOCK_PROGRAM_READ 0x29E /* Tx Fast Lock Program Read */
553 #define REG_TX_FAST_LOCK_PROGRAM_CTRL 0x29F /* Tx Fast Lock Program Ctrl */
554 #define REG_TX_LO_GEN_POWER_MODE 0x2A1 /* Tx LO Gen Power Mode */
555 #define REG_BANDGAP_CONFIG0 0x2A6 /* Bandgap Config0 */
556 #define REG_BANDGAP_CONFIG1 0x2A8 /* Bandgap Config1 */
557 #define REG_REF_DIVIDE_CONFIG_1 0x2AB /* Ref Divide Config 1 */
558 #define REG_REF_DIVIDE_CONFIG_2 0x2AC /* Ref Divide Config 2 */
559 #define REG_GAIN_RX1 0x2B0 /* Gain Rx1 */
560 #define REG_LPF_GAIN_RX1 0x2B1 /* LPF Gain Rx1 */
561 #define REG_DIG_GAIN_RX1 0x2B2 /* Dig gain Rx1 */
562 #define REG_FAST_ATTACK_STATE 0x2B3 /* Fast Attack State */
563 #define REG_SLOW_LOOP_STATE 0x2B4 /* Slow Loop State */
564 #define REG_GAIN_RX2 0x2B5 /* Gain Rx2 */
565 #define REG_LPF_GAIN_RX2 0x2B6 /* LPF Gain Rx2 */
566 #define REG_DIG_GAIN_RX2 0x2B7 /* Dig Gain Rx2 */
567 #define REG_OVRG_SIGS_RX1 0x2B8 /* Ovrg Sigs Rx1 */
568 #define REG_OVRG_SIGS_RX2 0x2B9 /* Ovrg Sigs Rx2 */
569 #define REG_CTRL 0x3DF /* Control */
570 #define REG_BIST_CONFIG 0x3F4 /* BIST Config */
571 #define REG_OBSERVE_CONFIG 0x3F5 /* Observe Config */
572 #define REG_BIST_AND_DATA_PORT_TEST_CONFIG 0x3F6 /* BIST and Data Port Test Config */
573 #define REG_DAC_TEST_0 0x3FC /* DAC Test 0 */
574 #define REG_DAC_TEST_1 0x3FD /* DAC Test 1 */
575 #define REG_DAC_TEST_2 0x3FE /* DAC Test 2 */
576 
577 /*
578 * REG_SPI_CONF
579 */
580 #define SOFT_RESET (1 << 7) /* Soft Reset */
581 #define WIRE3_SPI (1 << 6) /* 3-Wire SPI */
582 #define LSB_FIRST (1 << 5) /* LSB First */
583 #define _LSB_FIRST (1 << 2) /* LSB First */
584 #define _WIRE3_SPI (1 << 1) /* 3-Wire SPI */
585 #define _SOFT_RESET (1 << 0) /* Soft reset */
586 
587 /*
588 * REG_MULTICHIP_SYNC_AND_TX_MON_CTRL
589 */
590 #define TX2_MONITOR_ENABLE (1 << 6) /* Tx2 Monitor Enable */
591 #define TX1_MONITOR_ENABLE (1 << 5) /* Tx1 Monitor Enable */
592 #define MCS_RF_ENABLE (1 << 3) /* MCS RF Enable */
593 #define MCS_BBPLL_ENABLE (1 << 2) /* MCS BBPLL enable */
594 #define MCS_DIGITAL_CLK_ENABLE (1 << 1) /* MCS Digital CLK Enable */
595 #define MCS_BB_ENABLE (1 << 0) /* MCS BB Enable */
596 
597 /*
598 * REG_TX_ENABLE_FILTER_CTRL
599 */
600 #define THB2_EN (1 << 3) /* THB2 Enable */
601 #define THB1_EN (1 << 2) /* THB1 Enable */
602 #define TX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6) /* Tx channel Enable<1:0> */
603 #define THB3_ENABLE_INTERP(x) (((x) & 0x3) << 4) /* THB3 Enable & Interp<1:0> */
604 #define TX_FIR_ENABLE_INTERPOLATION(x) (((x) & 0x3) << 0) /* Tx FIR Enable & Interpolation<1:0> */
605 #define TX_1 1
606 #define TX_2 2
607 #define TX_ENABLE 1
608 #define TX_DISABLE 0
609 
610 /*
611 * REG_RX_ENABLE_FILTER_CTRL
612 */
613 #define RHB2_EN (1 << 3) /* RHB2 Enable */
614 #define RHB1_EN (1 << 2) /* RHB1 Enable */
615 #define RX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6) /* Rx channel Enable<1:0> */
616 #define DEC3_ENABLE_DECIMATION(x) (((x) & 0x3) << 4) /* DEC3 Enable & Decimation<1:0> */
617 #define RX_FIR_ENABLE_DECIMATION(x) (((x) & 0x3) << 0) /* Rx FIR Enable & Decimation<1:0> */
618 #define RX_1 1
619 #define RX_2 2
620 #define RX_ENABLE 1
621 #define RX_DISABLE 0
622 
623 /*
624 * REG_INPUT_SELECT
625 */
626 #define TX_OUTPUT (1 << 6) /* TX Output */
627 #define RX_INPUT(x) (((x) & 0x3F) << 0) /* RX Input <5:0> */
628 
629 /*
630 * REG_RFPLL_DIVIDERS
631 */
632 #define TX_VCO_DIVIDER(x) (((x) & 0xF) << 4) /* TX VCO Divider<3:0> */
633 #define RX_VCO_DIVIDER(x) (((x) & 0xF) << 0) /* RX VCO Divider<3:0> */
634 
635 /*
636 * REG_RX_CLOCK_DATA_DELAY
637 */
638 #define DATA_CLK_DELAY(x) (((x) & 0xF) << 4) /* DATA_CLK Delay<3:0> */
639 #define RX_DATA_DELAY(x) (((x) & 0xF) << 0) /* Rx Data Delay <3:0> */
640 
641 /*
642 * REG_TX_CLOCK_DATA_DELAY
643 */
644 #define FB_CLK_DELAY(x) (((x) & 0xF) << 4) /* FB_CLK Delay<3:0> */
645 #define TX_DATA_DELAY(x) (((x) & 0xF) << 0) /* Tx Data Delay <3:0> */
646 
647 /*
648 * REG_CLOCK_ENABLE
649 */
650 #define XO_BYPASS (1 << 4) /* XO Bypass */
651 #define DIGITAL_POWER_UP (1 << 2) /* Digital Power Up */
652 #define CLOCK_ENABLE_DFLT (1 << 1) /* Set to 1 */
653 #define BBPLL_ENABLE (1 << 0) /* BBPLL Enable */
654 
655 /*
656 * REG_BBPLL
657 */
658 #define CLKOUT_ENABLE (1 << 4) /* CLKOUT Enable */
659 #define DAC_CLK_DIV2 (1 << 3) /* DAC Clk div2 */
660 #define CLKOUT_SELECT(x) (((x) & 0x7) << 5) /* CLKOUT Select<2:0> */
661 #define BBPLL_DIVIDER(x) (((x) & 0x7) << 0) /* BBPLL Divider <2:0> */
662 
663 /*
664 * REG_START_TEMP_READING
665 */
666 #define START_TEMP_READING (1 << 0) /* Start Temp Reading */
667 
668 /*
669 * REG_TEMP_SENSE2
670 */
671 #define TEMP_SENSE_PERIODIC_ENABLE (1 << 0) /* Temp Sense Periodic Enable */
672 #define MEASUREMENT_TIME_INTERVAL(x) (((x) & 0x7F) << 1) /* Measurement Time Interval<6:0> */
673 
674 /*
675 * REG_TEMP_SENSOR_CONFIG
676 */
677 #define TEMP_SENSOR_DECIMATION(x) (((x) & 0x7) << 0) /* Temp Sensor Decimation<2:0> */
678 
679 /*
680 * REG_PARALLEL_PORT_CONF_1
681 */
682 #define PP_TX_SWAP_IQ (1 << 7) /* PP Tx Swap IQ */
683 #define PP_RX_SWAP_IQ (1 << 6) /* PP Rx Swap IQ */
684 #define TX_CHANNEL_SWAP (1 << 5) /* Tx Channel swap */
685 #define RX_CHANNEL_SWAP (1 << 4) /* Rx Channel swap */
686 #define RX_FRAME_PULSE_MODE (1 << 3) /* Rx Frame Pulse Mode */
687 #define R2T2_TIMING (1 << 2) /* 2R2T Timing */
688 #define INVERT_DATA_BUS (1 << 1) /* Invert data bus */
689 #define INVERT_DATA_CLK (1 << 0) /* Invert DATA CLK */
690 
691 /*
692 * REG_PARALLEL_PORT_CONF_2
693 */
694 #define FDD_ALT_WORD_ORDER (1 << 7) /* FDD Alt Word Order */
695 #define INVERT_RX1 (1 << 6) /* Invert Rx1 */
696 #define INVERT_RX2 (1 << 5) /* Invert Rx2 */
697 #define INVERT_TX1 (1 << 4) /* Invert Tx1 */
698 #define INVERT_TX2 (1 << 3) /* Invert Tx2 */
699 #define INVERT_RX_FRAME (1 << 2) /* Invert Rx Frame */
700 #define DELAY_RX_DATA(x) (((x) & 0x3) << 0) /* Delay Rx Data<1:0> */
701 
702 /*
703 * REG_PARALLEL_PORT_CONF_3
704 */
705 #define FDD_RX_RATE_2TX_RATE (1 << 7) /* FDD Rx Rate = 2*Tx Rate */
706 #define SWAP_PORTS (1 << 6) /* Swap Ports */
707 #define SINGLE_DATA_RATE (1 << 5) /* Single Data Rate */
708 #define LVDS_MODE (1 << 4) /* LVDS Mode */
709 #define HALF_DUPLEX_MODE (1 << 3) /* Half Duplex Mode */
710 #define SINGLE_PORT_MODE (1 << 2) /* Single Port Mode */
711 #define FULL_PORT (1 << 1) /* Full Port */
712 #define FULL_DUPLEX_SWAP_BITS (1 << 0) /* Full Duplex Swap Bits */
713 
714 /*
715 * REG_ENSM_MODE
716 */
717 #define FDD_MODE (1 << 0) /* FDD Mode */
718 
719 /*
720 * REG_ENSM_CONFIG_1
721 */
722 #define ENABLE_RX_DATA_PORT_FOR_CAL (1 << 7) /* Enable Rx Data Port for Cal */
723 #define FORCE_RX_ON (1 << 6) /* Force Rx On */
724 #define FORCE_TX_ON (1 << 5) /* Force Tx On */
725 #define ENABLE_ENSM_PIN_CTRL (1 << 4) /* Enable ENSM Pin Control */
726 #define LEVEL_MODE (1 << 3) /* Level Mode */
727 #define FORCE_ALERT_STATE (1 << 2) /* Force Alert State */
728 #define AUTO_GAIN_LOCK (1 << 1) /* Auto Gain Lock */
729 #define TO_ALERT (1 << 0) /* To Alert */
730 
731 /*
732 * REG_ENSM_CONFIG_2
733 */
734 #define FDD_EXTERNAL_CTRL_ENABLE (1 << 7) /* FDD External Control Enable */
735 #define POWER_DOWN_RX_SYNTH (1 << 6) /* Power Down Rx Synth */
736 #define POWER_DOWN_TX_SYNTH (1 << 5) /* Power Down Tx Synth */
737 #define TXNRX_SPI_CTRL (1 << 4) /* TXNRX SPI Control */
738 #define SYNTH_ENABLE_PIN_CTRL_MODE (1 << 3) /* Synth Enable Pin Control Mode */
739 #define DUAL_SYNTH_MODE (1 << 2) /* Dual Synth Mode */
740 #define RX_SYNTH_READY_MASK (1 << 1) /* Rx Synth Ready Mask */
741 #define TX_SYNTH_READY_MASK (1 << 0) /* Tx Synth Ready Mask */
742 
743 /*
744 * REG_CALIBRATION_CTRL
745 */
746 #define RX_BB_TUNE_CAL (1 << 7) /* Rx BB Tune */
747 #define TX_BB_TUNE_CAL (1 << 6) /* Tx BB Tune */
748 #define RX_QUAD_CAL (1 << 5) /* Rx Quad Cal */
749 #define TX_QUAD_CAL (1 << 4) /* Tx Quad Cal */
750 #define RX_GAIN_STEP_CAL (1 << 3) /* Rx Gain Step Cal */
751 #define TXMON_CAL (1 << 2)
752 #define RFDC_CAL (1 << 1) /* DC Cal RF Start */
753 #define BBDC_CAL (1 << 0) /* DC cal BB Start */
754 
755 
756 /*
757 * REG_STATE
758 */
759 #define CALIBRATION_SEQUENCE_STATE(x) (((x) & 0xF) << 4) /* Calibration Sequence State<3:0> */
760 #define ENSM_STATE(x) (((x) & 0xF) << 0) /* ENSM State<3:0> */
761 #define ENSM_STATE_SLEEP_WAIT 0x0
762 #define ENSM_STATE_ALERT 0x5
763 #define ENSM_STATE_TX 0x6
764 #define ENSM_STATE_TX_FLUSH 0x7
765 #define ENSM_STATE_RX 0x8
766 #define ENSM_STATE_RX_FLUSH 0x9
767 #define ENSM_STATE_FDD 0xA
768 #define ENSM_STATE_FDD_FLUSH 0xB
769 #define ENSM_STATE_INVALID 0xFF
770 #define ENSM_STATE_SLEEP 0x80
771 
772 /*
773 * REG_AUXDAC_2_WORD
774 */
775 #define AUXDAC_2_WORD_MSB(x) (((x) & 0x3F) << 2) /* AuxDAC 2 Word<9:2> */
776 #define AUXDAC_1_WORD(x) (((x) & 0x3) << 0) /* AuxDAC 1 Word <1:0> */
777 
778 /*
779 * REG_AUXDAC_1_CONFIG
780 */
781 #define COMP_CTRL_1 (1 << 5) /* Comp Ctrl 1 */
782 #define AUXDAC1_STP_FACTOR (1 << 4) /* AuxDAC1 Step Factor */
783 #define AUXDAC_1_VREF(x) (((x) & 0x3) << 2) /* AuxDAC 1 Vref<1:0> */
784 #define AUXDAC_1_WORD_LSB(x) (((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */
785 
786 /*
787 * REG_AUXDAC_2_CONFIG
788 */
789 #define COMP_CTRL_2 (1 << 5) /* Comp Ctrl 2 */
790 #define AUXDAC2_STP_FACTOR (1 << 4) /* AuxDAC2 Step Factor */
791 #define AUXDAC_2_VREF(x) (((x) & 0xF) << 2) /* AuxDAC 2 Vref<1:0> */
792 #define AUXDAC_2_WORD_LSB(x) (((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */
793 
794 /*
795 * REG_AUXADC_CLOCK_DIVIDER
796 */
797 #define AUXADC_CLOCK_DIVIDER(x) (((x) & 0x3F) << 0) /* AuxADC Clock Divider<5:0> */
798 
799 /*
800 * REG_AUXADC_CONFIG
801 */
802 #define AUXADC_POWER_DOWN (1 << 0) /* AuxADC Power Down */
803 #define AUX_ADC_DECIMATION(x) (((x) & 0x7) << 1) /* Aux ADC Decimation<2:0> */
804 
805 /*
806 * REG_AUXADC_LSB
807 */
808 #define AUXADC_WORD_LSB(x) (((x) & 0xF) << 0) /* AuxADC Word LSB<3:0> */
809 
810 /*
811 * REG_AUTO_GPO
812 */
813 #define GPO_ENABLE_AUTO_RX(x) (((x) & 0xF) << 4) /* GPO Enable Auto Rx<3:0> */
814 #define GPO_ENABLE_AUTO_TX(x) (((x) & 0xF) << 0) /* GPO Enable Auto Tx<3:0> */
815 
816 /*
817 * REG_AGC_ATTACK_DELAY
818 */
819 #define INVERT_BYPASSED_LNA_POLARITY (1 << 6) /* Invert Bypassed LNA Polarity */
820 #define AGC_ATTACK_DELAY(x) (((x) & 0x3F) << 0) /* AGC Attack Delay<5:0> */
821 
822 /*
823 * REG_AUXDAC_ENABLE_CTRL
824 */
825 #define AUXDAC_MANUAL_BAR(x) (((x) & 0x3) << 6) /* AuxDac Manual Bar<1:0> */
826 #define AUXDAC_AUTO_TX_BAR(x) (((x) & 0x3) << 4) /* AuxDAC Auto Tx Bar<1:0> */
827 #define AUXDAC_AUTO_RX_BAR(x) (((x) & 0x3) << 2) /* AuxDAC Auto Rx Bar<1:0> */
828 #define AUXDAC_INIT_BAR(x) (((x) & 0x3) << 0) /* AuxDAC Init Bar<1:0> */
829 
830 /*
831 * REG_EXTERNAL_LNA_CTRL
832 */
833 #define AUXDAC_MANUAL_SELECT (1 << 7) /* AuxDAC Manual Select */
834 #define EXTERNAL_LNA2_CTRL (1 << 6) /* External LNA2 control */
835 #define EXTERNAL_LNA1_CTRL (1 << 5) /* External LNA1 control */
836 #define GPO_MANUAL_SELECT (1 << 4) /* GPO manual select */
837 #define OPEN(x) (((x) & 0xF) << 0) /* Open<3:0> */
838 
839 /*
840 * REG_GPO_FORCE_AND_INIT
841 */
842 #define GPO_MANUAL_CTRL(x) (((x) & 0xF) << 4) /* GPO Manual Control<3:0> */
843 #define GPO_INIT_STATE(x) (((x) & 0xF) << 0) /* GPO Init State<3:0> */
844 
845 /*
846 * REG_CTRL_OUTPUT_ENABLE
847 */
848 #define EN_CTRL7 (1 << 7) /* En ctrl7 */
849 #define EN_CTRL6 (1 << 6) /* En ctrl6 */
850 #define EN_CTRL5 (1 << 5) /* En ctrl5 */
851 #define EN_CTRL4 (1 << 4) /* En ctrl4 */
852 #define EN_CTRL3 (1 << 3) /* En ctrl3 */
853 #define EN_CTRL2 (1 << 2) /* En ctrl2 */
854 #define EN_CTRL1 (1 << 1) /* En ctrl1 */
855 #define EN_CTRL0 (1 << 0) /* En ctrl0 */
856 
857 /*
858 * REG_PRODUCT_ID
859 */
860 #define PRODUCT_ID_MASK 0xF8
861 #define PRODUCT_ID_9361 0x08
862 #define REV_MASK 0x07
863 
864 /*
865 * REG_REFERENCE_CLOCK_CYCLES
866 */
867 #define REFERENCE_CLOCK_CYCLES_PER_US(x) (((x) & 0x7F) << 0) /* Reference Clock Cycles per us<6:0> */
868 
869 /*
870 * REG_DIGITAL_IO_CTRL
871 */
872 #define CLK_OUT_DRIVE (1 << 7) /* CLK Out Drive */
873 #define DATACLK_DRIVE (1 << 6) /* DATACLK drive */
874 #define DATA_PORT_DRIVE (1 << 2) /* Data Port Drive */
875 #define DATACLK_SLEW(x) (((x) & 0x3) << 4) /* DATACLK slew <1:0> */
876 #define DATA_PORT_SLEW(x) (((x) & 0x3) << 0) /* Data Port Slew<1:0> */
877 
878 /*
879 * REG_LVDS_BIAS_CTRL
880 */
881 #define RX_ON_CHIP_TERM (1 << 5) /* Rx On Chip Term */
882 #define LVDS_BYPASS_BIAS_R (1 << 4) /* Bypass Bias R */
883 #define LVDS_TX_LO_VCM (1 << 3) /* LVDS Tx LO VCM */
884 #define CLK_OUT_SLEW(x) (((x) & 0x3) << 6) /* CLK Out Slew<1:0> */
885 #define LVDS_BIAS(x) (((x) & 0x7) << 0) /* LVDS Bias <2:0> */
886 
887 /*
888 * REG_SDM_CTRL_1
889 */
890 #define INIT_BB_FO_CAL (1 << 2) /* Init BB FO CAL */
891 #define BBPLL_RESET_BAR (1 << 0) /* BBPLL Reset Bar */
892 
893 /*
894 * REG_CLOCK_CTRL
895 */
896 #define REF_FREQ_SCALER(x) (((x) & 0x3) << 0) /* Ref Frequency Scaler */
897 
898 /*
899 * REG_CP_CURRENT
900 */
901 #define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */
902 
903 /*
904 * REG_CP_BLEED_CURRENT
905 */
906 #define MCS_REFCLK_SCALE_EN (1 << 7) /* MCS refclk Scale En */
907 
908 /*
909 * REG_LOOP_FILTER_1
910 */
911 #define C1_WORD(x) (((x) & 0x7) << 5) /* C1 Word<2:0> */
912 #define R1_WORD(x) (((x) & 0x1F) << 0) /* R1 Word<4:0> */
913 
914 /*
915 * REG_LOOP_FILTER_2
916 */
917 #define R2_WORD (1 << 7) /* R2 Word<0> */
918 #define C2_WORD(x) (((x) & 0x1F) << 2) /* C2 Word<4:0> */
919 #define C1_WORD_LSB(x) (((x) & 0x3) << 0) /* C1 Word<4:3> */
920 
921 /*
922 * REG_LOOP_FILTER_3
923 */
924 #define BYPASS_C3 (1 << 7) /* Bypass C3 */
925 #define BYPASS_R2 (1 << 6) /* Bypass R2 */
926 #define C3_WORD(x) (((x) & 0xF) << 2) /* C3 Word<3:0> */
927 #define R2_WORD_LSB(x) (((x) & 0x3) << 0) /* R2 Word<2:1> */
928 
929 /*
930 * REG_VCO_CTRL
931 */
932 #define FREQ_CAL_ENABLE (1 << 7) /* Freq Cal Enable */
933 #define FREQ_CAL_RESET (1 << 4) /* Freq Cal Reset */
934 #define FREQ_CAL_COUNT_LENGTH(x) (((x) & 0x3) << 5) /* Freq Cal Count Length<1:0> */
935 
936 /*
937 * REG_SDM_CTRL
938 */
939 #define CAL_CLOCK_DIV_4 (1 << 4) /* Cal Clock div 4 */
940 
941 /*
942 * REG_RX_SYNTH_POWER_DOWN_OVERRIDE
943 */
944 #define RX_LO_POWER_DOWN (1 << 4) /* Rx LO Power Down */
945 #define RX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3) /* Rx Synth VCO ALC Power Down */
946 #define RX_SYNTH_PTAT_POWER_DOWN (1 << 2) /* Rx Synth PTAT Power Down */
947 #define RX_SYNTH_VCO_POWER_DOWN (1 << 1) /* Rx Synth VCO Power Down */
948 #define RX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0) /* Rx Synth VCO LDO Power Down */
949 
950 /*
951 * REG_TX_SYNTH_POWER_DOWN_OVERRIDE
952 */
953 #define TX_LO_POWER_DOWN (1 << 4) /* Tx LO Power Down */
954 #define TX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3) /* Tx Synth VCO ALC Power Down */
955 #define TX_SYNTH_PTAT_POWER_DOWN (1 << 2) /* Tx Synth PTAT Power Down */
956 #define TX_SYNTH_VCO_POWER_DOWN (1 << 1) /* Tx Synth VCO Power Down */
957 #define TX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0) /* Tx Synth VCO LDO Power Down */
958 
959 /*
960 * REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1
961 */
962 #define RX_OFFSET_DAC_CGIN_POWER_DOWN(x) (((x) & 0x3) << 6) /* Rx Offset DAC CGin Power Down<1:0> */
963 #define RX_LMT_OVERLOAD_POWER_DOWN(x) (((x) & 0x3) << 4) /* Rx LMT Overload Power Down<1:0> */
964 #define RX_MIXER_GM_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Mixer Gm Power Down<1:0> */
965 #define RX_CGB_POWER_DOWN(x) (((x) & 0x3) << 0) /* Rx CGB Power Down<1:0> */
966 
967 /*
968 * REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2
969 */
970 #define RX_BBF_POWER_DOWN(x) (((x) & 0x3) << 6) /* Rx BBF Power Down<1:0> */
971 #define RX_TIA_POWER_DOWN(x) (((x) & 0x3) << 4) /* Rx TIA Power Down<1:0> */
972 #define RX_MIXER_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Mixer Power Down<1:0> */
973 #define RX_OFFSET_DAC_CGOUT_POWER_DOWN(x) (((x) & 0x3) << 0) /* Rx Offset DAC CGOut Power Down<1:0> */
974 
975 /*
976 * REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1
977 */
978 #define TX_SECONDARY_FILTER_POWER_DOWN(x) (((x) & 0x3) << 6) /* Tx Secondary Filter Power Down<1:0> */
979 #define TX_BBF_POWER_DOWN(x) (((x) & 0x3) << 4) /* Tx BBF Power Down<1:0> */
980 #define TX_DAC_POWER_DOWN(x) (((x) & 0x3) << 2) /* Tx DAC Power Down<1:0> */
981 #define TX_DAC_BIAS_POWER_DOWN(x) (((x) & 0x3) << 0) /* Tx DAC Bias Power Down<1:0> */
982 
983 /*
984 * REG_ANALOG_POWER_DOWN_OVERRIDE
985 */
986 #define RX_EXT_VCO_BUFFER_POWER_DOWN (1 << 5) /* Rx Ext VCO Buffer Power Down */
987 #define TX_EXT_VCO_BUFFER_POWER_DOWN (1 << 4) /* Tx Ext VCO Buffer Power Down */
988 #define TX_MONITOR_POWER_DOWN(x) (((x) & 0x3) << 2) /* Tx Monitor Power Down<1:0> */
989 #define TX_UPCONVERTER_POWER_DOWN(x) (((x) & 0x3) << 0) /* Tx Upconverter Power Down<1:0> */
990 
991 /*
992 * REG_MISC_POWER_DOWN_OVERRIDE
993 */
994 #define RX_LNA_POWER_DOWN (1 << 6) /* Rx LNA Power Down */
995 #define DCXO_POWER_DOWN (1 << 1) /* DCXO Power Down */
996 #define MASTER_BIAS_POWER_DOWN (1 << 0) /* Master Bias Power Down */
997 #define RX_CALIBRATION_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Calibration Power Down<1:0> */
998 
999 /*
1000 * REG_CH_1_OVERFLOW
1001 */
1002 #define BBPLL_LOCK (1 << 7) /* BBPLL Lock */
1003 #define CH_1_INT3 (1 << 6) /* CH 1 INT3 */
1004 #define CH1_HB3 (1 << 5) /* CH1 HB3 */
1005 #define CH1_HB2 (1 << 4) /* CH1 HB2 */
1006 #define CH1_QEC (1 << 3) /* CH1 QEC */
1007 #define CH1_HB1 (1 << 2) /* CH1 HB1 */
1008 #define CH1_TFIR (1 << 1) /* CH1 TFIR */
1009 #define CH1_RFIR (1 << 0) /* CH1 RFIR */
1010 
1011 /*
1012 * REG_CH_2_OVERFLOW
1013 */
1014 #define CH2_INT3 (1 << 6) /* CH2 INT3 */
1015 #define CH2_HB3 (1 << 5) /* CH2 HB3 */
1016 #define CH2_HB2 (1 << 4) /* CH2 HB2 */
1017 #define CH2_QEC (1 << 3) /* CH2 QEC */
1018 #define CH2_HB1 (1 << 2) /* CH2 HB1 */
1019 #define CH2_TFIR (1 << 1) /* CH2 TFIR */
1020 #define CH2_RFIR (1 << 0) /* CH2 RFIR */
1021 
1022 /*
1023 * REG_TX_FILTER_CONF
1024 */
1025 #define TX_FIR_GAIN_6DB (1 << 0) /* Filter Gain */
1026 #define FIR_START_CLK (1 << 1) /* Start Tx/Rx Clock */
1027 #define FIR_WRITE (1 << 2) /* Write Tx/Rx */
1028 #define FIR_SELECT(x) (((x) & 0x3) << 3) /* Select Tx/Rx CH<1:0> */
1029 #define FIR_NUM_TAPS(x) (((x) & 0x7) << 5) /* Number of Taps<2:0> */
1030 
1031 /*
1032 * REG_TX_MON_LOW_GAIN
1033 */
1034 #define TX_MON_TRACK (1 << 5) /* Tx Mon Track */
1035 #define TX_MON_LOW_GAIN(x) (((x) & 0x1F) << 0) /* Tx Mon Low Gain<4:0> */
1036 
1037 /*
1038 * REG_TX_MON_HIGH_GAIN
1039 */
1040 #define TX_MON_HIGH_GAIN(x) (((x) & 0x1F) << 0) /* Tx Mon High Gain<4:0> */
1041 
1042 /*
1043 * REG_TX_LEVEL_THRESH
1044 */
1045 #define TX_LEVEL_THRESH(x) (((x) & 0x3F) << 2) /* Tx Level Threshold<5:0> */
1046 #define TX_MON_DELAY_COUNTER(x) (((x) & 0x3) << 0) /* Tx Mon Delay Counter<9:8> */
1047 
1048 /*
1049 * REG_TX_RSSI_LSB
1050 */
1051 #define TX_RSSI_2 (1 << 1) /* Tx RSSI 2<0> */
1052 #define TX_RSSI_1 (1 << 0) /* TX RSSI 1<0> */
1053 
1054 /*
1055 * REG_TPM_MODE_ENABLE
1056 */
1057 #define TX2_MON_ENABLE (1 << 7) /* Tx2 Monitor Enable */
1058 #define TX1_MON_ENABLE (1 << 5) /* Tx1 Monitor Enable */
1059 #define ONE_SHOT_MODE (1 << 6) /* One Shot Mode */
1060 #define TX_MON_DURATION(x) (((x) & 0xF) << 0) /* Tx Mon Duration<3:0> */
1061 
1062 /*
1063 * REG_TX_MON_1_CONFIG
1064 */
1065 #define TX_MON_1_LO_CM(x) (((x) & 0x3F) << 2) /* Tx Mon 1 LO CM<5:0> */
1066 #define TX_MON_1_GAIN(x) (((x) & 0x3) << 0) /* Tx Mon 1 Gain<1:0> */
1067 
1068 /*
1069 * REG_TX_MON_2_CONFIG
1070 */
1071 #define TX_MON_2_LO_CM(x) (((x) & 0x3F) << 2) /* Tx Mon 2 LO CM<5:0> */
1072 #define TX_MON_2_GAIN(x) (((x) & 0x3) << 0) /* Tx Mon 2 Gain<1:0> */
1073 
1074 /*
1075 * REG_TX1_ATTEN_1
1076 */
1077 #define TX_1_ATTEN (1 << 0) /* Tx 1 Atten <8> */
1078 
1079 /*
1080 * REG_TX2_ATTEN_1
1081 */
1082 #define TX_2_ATTEN (1 << 0) /* Tx 2 Atten <8> */
1083 
1084 /*
1085 * REG_TX_ATTEN_OFFSET
1086 */
1087 #define MASK_CLR_ATTEN_UPDATE (1 << 6) /* Mask Clr Atten Update */
1088 #define TX_ATTEN_OFFSET(x) (((x) & 0x3F) << 0) /* Tx Atten Offset<5:0> */
1089 
1090 /*
1091 * REG_TX1_DIG_ATTEN
1092 */
1093 #define SEL_TX1_TX2 (1 << 6) /* Sel Tx1 & Ttx2 */
1094 
1095 /*
1096 * REG_TX2_DIG_ATTEN
1097 */
1098 #define IMMEDIATELY_UPDATE_TPC_ATTEN (1 << 6) /* Immediately Update TPC Atten */
1099 
1100 /*
1101 * REG_TX1_SYMBOL_ATTEN
1102 */
1103 #define TX_1_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0) /* Tx 1 Symbol Attenuation<6:0> */
1104 
1105 /*
1106 * REG_TX2_SYMBOL_ATTEN
1107 */
1108 #define TX_2_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0) /* Tx 2 Symbol Attenuation<6:0> */
1109 
1110 /*
1111 * REG_TX_SYMBOL_ATTEN_CONFIG
1112 */
1113 #define USE_TX1_PIN_SYMBOL_ATTEN (1 << 3) /* Use Tx1 Pin & Symbol Atten */
1114 #define USE_CTRL_IN_FOR_SYMBOL_ATTEN (1 << 1) /* Use CTRL IN for symbol Atten */
1115 #define ENABLE_SYMBOL_ATTEN (1 << 0) /* Enable Symbol Atten */
1116 
1117 /*
1118 * REG_TX_FORCE_BITS
1119 */
1120 #define FORCE_OUT_2_TX2_OFFSET (1 << 7) /* Force Out 2 Tx2 Offset */
1121 #define FORCE_OUT_2_TX1_OFFSET (1 << 6) /* Force Out 2 Tx1 Offset */
1122 #define FORCE_OUT_2_TX2_PHASE_GAIN (1 << 5) /* Force Out 2 Tx2 Phase & Gain */
1123 #define FORCE_OUT_2_TX1_PHASE_GAIN (1 << 4) /* Force Out 2 Tx1 Phase & Gain */
1124 #define FORCE_OUT_1_TX2_OFFSET (1 << 3) /* Force Out 1 Tx2 Offset */
1125 #define FORCE_OUT_1_TX1_OFFSET (1 << 2) /* Force Out 1 Tx1 Offset */
1126 #define FORCE_OUT_1_TX2_PHASE_GAIN (1 << 1) /* Force Out 1 Tx2 Phase & Gain */
1127 #define FORCE_OUT_1_TX1_PHASE_GAIN (1 << 0) /* Force Out 1 Tx1 Phase & Gain */
1128 
1129 /*
1130 * REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET
1131 */
1132 #define RX_NCO_FREQ(x) (((x) & 0x3) << 5) /* Rx NCO Frequency<1:0> */
1133 #define RX_NCO_PHASE_OFFSET(x) (((x) & 0x1F) << 0) /* Rx NCO Phase Offset<4:0> */
1134 
1135 /*
1136 * REG_QUAD_CAL_CTRL
1137 */
1138 #define FREE_RUN_ENABLE (1 << 7) /* Free Run Enable */
1139 #define SETTLE_MAIN_ENABLE (1 << 6) /* Settle Main Enable */
1140 #define DC_OFFSET_ENABLE (1 << 5) /* DC Offset Enable */
1141 #define GAIN_ENABLE (1 << 4) /* Gain Enable */
1142 #define PHASE_ENABLE (1 << 3) /* Phase Enable */
1143 #define QUAD_CAL_SOFT_RESET (1 << 2) /* Quad Cal Soft Reset */
1144 #define M_DECIM(x) (((x) & 0x3) << 0) /* M<1:0> */
1145 
1146 /*
1147 * REG_KEXP_1
1148 */
1149 #define KEXP_TX(x) (((x) & 0x3) << 6) /* Kexp Tx<1:0> */
1150 #define KEXP_TX_COMP(x) (((x) & 0x3) << 4) /* Kexp Tx_comp <1:0> */
1151 #define KEXP_DC_I(x) (((x) & 0x3) << 2) /* Kexp DC I <1:0> */
1152 #define KEXP_DC_Q(x) (((x) & 0x3) << 0) /* Kexp DC Q <1:0> */
1153 
1154 /*
1155 * REG_KEXP_2
1156 */
1157 #define INVERT_I_DATA (1 << 5) /* Invert I data */
1158 #define INVERT_Q_DATA (1 << 4) /* Invert Q data */
1159 #define TX_NCO_FREQ(x) (((x) & 0x3) << 6) /* Tx NCO frequency<1:0> */
1160 #define KEXP_PHASE(x) (((x) & 0x3) << 2) /* Kexp Phase <1:0> */
1161 #define KEXP_AMP(x) (((x) & 0x3) << 0) /* Kexp Amp <1:0> */
1162 
1163 /*
1164 * REG_QUAD_CAL_STATUS_TX1
1165 */
1166 #define TX1_LO_CONV (1 << 1) /* Tx1 LO Conv */
1167 #define TX1_SSB_CONV (1 << 0) /* Tx1 SSB Conv */
1168 #define TX1_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2) /* Tx1 Convergence Count<5:0> */
1169 
1170 /*
1171 * REG_QUAD_CAL_STATUS_TX2
1172 */
1173 #define TX2_LO_CONV (1 << 1) /* Tx2 LO Conv */
1174 #define TX2_SSB_CONV (1 << 0) /* Tx2 SSB Conv */
1175 #define TX2_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2) /* Tx2 Convergence Count<5:0> */
1176 
1177 /*
1178 * REG_TX_QUAD_FULL_LMT_GAIN
1179 */
1180 #define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0) /* RX Full table/LMT table gain<6:0> */
1181 
1182 /*
1183 * REG_SQUARER_CONFIG
1184 */
1185 #define GM_STAGE_TIME_CON_OVERRIDE (1 << 5) /* Gm Stage Time Con Override */
1186 #define GM_STAGE_MV_HP_POLE (1 << 4) /* Gm Stage MV HP Pole */
1187 #define GM_STAGE_LOWER_CM (1 << 3) /* Gm Stage Lower CM */
1188 #define BYPASS_BIAS_R (1 << 0) /* Bypass Bias R */
1189 #define VBIAS_CTRL(x) (((x) & 0x3) << 1) /* Vbias Control<1:0> */
1190 
1191 /*
1192 * REG_THRESH_ACCUM
1193 */
1194 #define THRESH_ACCUMULATOR(x) (((x) & 0xF) << 0) /* Threshold Accumulator<3:0> */
1195 
1196 /*
1197 * REG_TX_QUAD_LPF_GAIN
1198 */
1199 #define RX_LPF_GAIN(x) (((x) & 0x1F) << 0) /* RX LPF gain<4:0> */
1200 
1201 /*
1202 * REG_TXDAC_VDS_I
1203 */
1204 #define TXDAC_VDS_I(x) (((x) & 0x3F) << 0) /* TxDAC Vds I<5:0> */
1205 
1206 /*
1207 * REG_TXDAC_VDS_Q
1208 */
1209 #define TXDAC_VDS_Q(x) (((x) & 0x3F) << 0) /* TxDAC Vds Q<5:0> */
1210 
1211 /*
1212 * REG_TXDAC_GN_I
1213 */
1214 #define TXDAC_GN_I(x) (((x) & 0x3F) << 0) /* txDAC_gn_I<5:0> */
1215 
1216 /*
1217 * REG_TXDAC_GN_Q
1218 */
1219 #define TXDAC_GN_Q(x) (((x) & 0x3F) << 0) /* txDAC_gn_Q<5:0> */
1220 
1221 /*
1222 * REG_TXBBF_OPAMP_A
1223 */
1224 #define OPAMPA_OUTPUT_BIAS(x) (((x) & 0x3) << 5) /* OpAmpA Output Bias<1:0> */
1225 #define OPAMPA_RZ(x) (((x) & 0x3) << 3) /* OpAmpA RZ<1:0> */
1226 #define OPAMP_A_CC(x) (((x) & 0x7) << 0) /* OpAmp A CC<2:0> */
1227 
1228 /*
1229 * REG_TXBBF_OPAMP_B
1230 */
1231 #define OPAMPB_OUTPUT_BIAS(x) (((x) & 0x3) << 5) /* OpAmpB Output Bias<1:0> */
1232 #define OPAMPB_RZ(x) (((x) & 0x3) << 3) /* OpAmpB RZ<1:0> */
1233 #define OPAMP_B_CC(x) (((x) & 0x7) << 0) /* OpAmp B CC<2:0> */
1234 
1235 /*
1236 * REG_TX_BBF_R1
1237 */
1238 #define OVERRIDE_ENABLE (1 << 7) /* Override enable */
1239 #define R1(x) (((x) & 0x1F) << 0) /* R1<4:0> */
1240 
1241 /*
1242 * REG_TX_BBF_R2
1243 */
1244 #define R2(x) (((x) & 0x1F) << 0) /* R2<4:0> */
1245 
1246 /*
1247 * REG_TX_BBF_R3
1248 */
1249 #define R3(x) (((x) & 0x1F) << 0) /* R3<4:0> */
1250 
1251 /*
1252 * REG_TX_BBF_R4
1253 */
1254 #define R4(x) (((x) & 0x1F) << 0) /* R4<4:0> */
1255 
1256 /*
1257 * REG_TX_BBF_RP
1258 */
1259 #define RP(x) (((x) & 0x1F) << 0) /* Rp<4:0> */
1260 
1261 /*
1262 * REG_TX_BBF_C1
1263 */
1264 #define C1(x) (((x) & 0x3F) << 0) /* C1<5:0> */
1265 
1266 /*
1267 * REG_TX_BBF_C2
1268 */
1269 #define C2(x) (((x) & 0x3F) << 0) /* C2<5:0> */
1270 
1271 /*
1272 * REG_TX_BBF_CP
1273 */
1274 #define CP(x) (((x) & 0x3F) << 0) /* Cp<5:0> */
1275 
1276 /*
1277 * REG_TX_TUNE_CTRL
1278 */
1279 #define PD_TUNE (1 << 2) /* PD Tune */
1280 #define TUNER_RESAMPLE (1 << 1) /* Tuner Resample */
1281 #define TUNER_RESAMPLE_PHASE (1 << 0) /* Tuner Resample Phase */
1282 #define TUNE_CTRL(x) (((x) & 0x3) << 5) /* Tune Control<1:0> */
1283 
1284 /*
1285 * REG_TX_BBF_R2B
1286 */
1287 #define TX_BBF_BYPASS_BIAS_R (1 << 7) /* Bypass Bias R */
1288 #define R2B_OVR (1 << 5) /* R2b Ovr */
1289 #define R2B(x) (((x) & 0x1F) << 0) /* R2b<4:0> */
1290 
1291 /*
1292 * REG_TX_BBF_TUNE
1293 */
1294 #define BBF1_COMP_I (1 << 3) /* BBF1 Comp I */
1295 #define BBF1_COMP_Q (1 << 2) /* BBF1 Comp Q */
1296 #define BBF2_COMP_I (1 << 1) /* BBF2 Comp I */
1297 #define BBF2_COMP_Q (1 << 0) /* BBF2 Comp Q */
1298 
1299 /*
1300 * REG_CONFIG0
1301 */
1302 #define BIAS(x) (((x) & 0x3) << 6) /* Bias<1:0> */
1303 #define RGM(x) (((x) & 0x3) << 4) /* Rgm<1:0> */
1304 #define CC(x) (((x) & 0x3) << 2) /* Cc<1:0> */
1305 #define AMPBIAS(x) (((x) & 0x3) << 0) /* AmpBias<1:0> */
1306 
1307 /*
1308 * REG_RESISTOR
1309 */
1310 #define RESISTOR(x) (((x) & 0xF) << 0) /* Resistor<3:0> */
1311 
1312 /*
1313 * REG_CAPACITOR
1314 */
1315 #define CAPACITOR(x) (((x) & 0x3F) << 0) /* Capacitor<5:0> */
1316 
1317 /*
1318 * REG_LO_CM
1319 */
1320 #define LO_COMMON_MODE(x) (((x) & 0x3) << 5) /* LO Common Mode<1:0> */
1321 
1322 /*
1323 * REG_TX_BBF_TUNE_MODE
1324 */
1325 #define EVALTIME (1 << 4) /* EvalTime */
1326 #define TX_BBF_TUNE_DIVIDER (1 << 0) /* TX BBF Tune Divider<8> */
1327 #define TUNE_COMP_MASK(x) (((x) & 0x3) << 5) /* Tune Comp Mask<1:0> */
1328 #define TUNER_MODE(x) (((x) & 0x7) << 1) /* Tuner Mode<2:0> */
1329 
1330 /*
1331 * REG_RX_FILTER_CONFIG
1332 */
1333 #define WRITE_RX (1 << 2) /* Write Rx */
1334 #define START_RX_CLOCK (1 << 1) /* Start Rx Clock */
1335 #define NUMBER_OF_TAPS(x) (((x) & 0x7) << 5) /* Number of Taps */
1336 #define SELECT_RX_CH(x) (((x) & 0x3) << 3) /* Select Rx Ch<1:0> */
1337 
1338 /*
1339 * REG_RX_FILTER_GAIN
1340 */
1341 #define FILTER_GAIN(x) (((x) & 0x3) << 0) /* Filter gain<1:0> */
1342 
1343 /*
1344 * REG_AGC_CONFIG_1
1345 */
1346 #define DEC_PWR_FOR_LOW_PWR (1 << 7) /* Dec Pwr for Low Pwr */
1347 #define DEC_PWR_FOR_LOCK_LEVEL (1 << 6) /* Dec Pwr for Lock Level */
1348 #define DEC_PWR_FOR_GAIN_LOCK_EXIT (1 << 5) /* Dec Pwr for Gain Lock Exit */
1349 #define SLOW_ATTACK_HYBRID_MODE (1 << 4) /* Slow Attack Hybrid Mode */
1350 #define RX2_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 2) /* Rx 2 Gain Control Setup<1:0> */
1351 #define RX1_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 0) /* Rx 1 Gain Control Setup<1:0> */
1352 #define RX_GAIN_CTL_MASK 0x03
1353 #define RX2_GAIN_CTRL_SHIFT 2
1354 #define RX1_GAIN_CTRL_SHIFT 0
1355 #define RX_GAIN_CTL_MGC 0x00
1356 #define RX_GAIN_CTL_AGC_FAST_ATK 0x01
1357 #define RX_GAIN_CTL_AGC_SLOW_ATK 0x02
1358 #define RX_GAIN_CTL_AGC_SLOW_ATK_HYBD 0x03
1359 
1360 /*
1361 * REG_AGC_CONFIG_2
1362 */
1363 #define AGC_SOFT_RESET (1 << 7) /* Soft Reset */
1364 #define AGC_GAIN_UNLOCK_CTRL (1 << 6) /* Gain Unlock Control */
1365 #define AGC_USE_FULL_GAIN_TABLE (1 << 3) /* Use Full Gain Table */
1366 #define DIG_GAIN_EN (1 << 2) /* Enable Digital Gain */
1367 #define MAN_GAIN_CTRL_RX2 (1 << 1) /* Manual Gain Control Rx 2 */
1368 #define MAN_GAIN_CTRL_RX1 (1 << 0) /* Manual Gain Control Rx 1 */
1369 
1370 /*
1371 * REG_AGC_CONFIG_3
1372 */
1373 #define INCDEC_LMT_GAIN (1 << 4) /* Inc/Dec LMT Gain */
1374 #define USE_AGC_FOR_LMTLPF_GAIN (1 << 3) /* Use AGC for LMT/LPF Gain */
1375 #define MANUAL_INCR_STEP_SIZE(x) (((x) & 0x7) << 5) /* Manual (CTRL_IN) Incr Gain Step Size<2:0> */
1376 #define ADC_OVERRANGE_SAMPLE_SIZE(x) (((x) & 0x7) << 0) /* ADC Overrange Sample Size<2:0> */
1377 
1378 /*
1379 * REG_MAX_LMT_FULL_GAIN
1380 */
1381 #define MAXIMUM_FULL_TABLELMT_TABLE_INDEX(x) (((x) & 0x7F) << 0) /* Maximum Full Table/LMT Table Index<6:0> */
1382 
1383 /*
1384 * REG_PEAK_WAIT_TIME
1385 */
1386 #define MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE(x) (((x) & 0x7) << 5) /* Manual (CTRL_IN) Decr Gain Step Size<2:0> */
1387 #define PEAK_OVERLOAD_WAIT_TIME(x) (((x) & 0x1F) << 0) /* Peak Overload Wait Time<4:0> */
1388 
1389 /*
1390 * REG_DIGITAL_GAIN
1391 */
1392 #define DIG_GAIN_STP_SIZE(x) (((x) & 0x7) << 5) /* Dig Gain Step Size<2:0> */
1393 #define MAXIMUM_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Maximum Digital Gain<4:0> */
1394 
1395 /*
1396 * REG_AGC_LOCK_LEVEL
1397 */
1398 #define ENABLE_DIG_SAT_OVRG (1 << 7) /* Enable Dig Sat Ovrg */
1399 #define AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW(x) (((x) & 0x7F) << 0) /* AGC Lock Level (Fast)/ AGC Inner High Threshold (Slow) <6:0> */
1400 
1401 /*
1402 * REG_GAIN_STP_CONFIG1
1403 */
1404 #define LMT_DETECTOR_SETTLING_TIME(x) (((x) & 0x7) << 5) /* LMT Detector Settling Time<2:0> */
1405 #define DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD(x) (((x) & 0x7) << 2) /* Dec Step Size for: Large LMT Overload/ Full Table Case #3 <2:0> */
1406 #define ADC_NOISE_CORRECTION_FACTOR(x) (((x) & 0x3) << 0) /* ADC Noise Correction Factor<1:0> */
1407 
1408 /*
1409 * REG_GAIN_STP_CONFIG_2
1410 */
1411 #define DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE(x) (((x) & 0x7) << 4) /* Fast Attack Only. Decrement Step Size for: Small LPF Gain Change / Full Table Case #2 <2:0> */
1412 #define LARGE_LPF_GAIN_STEP(x) (((x) & 0xF) << 0) /* Decrement Step Size for: Large LPF Gain Change / Full Table Case #1<3:0> */
1413 
1414 /*
1415 * REG_SMALL_LMT_OVERLOAD_THRESH
1416 */
1417 #define FORCE_PD_RESET_RX2 (1 << 7) /* Force PD Reset Rx2 */
1418 #define FORCE_PD_RESET_RX1 (1 << 6) /* Force PD Reset Rx1 */
1419 #define SMALL_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0) /* Small LMT Overload Threshold<5:0> */
1420 
1421 /*
1422 * REG_LARGE_LMT_OVERLOAD_THRESH
1423 */
1424 #define LARGE_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0) /* Large LMT Overload Threshold<5:0> */
1425 
1426 /*
1427 * REG_RX1_MANUAL_LMT_FULL_GAIN
1428 */
1429 #define POWER_MEAS_IN_STATE_5_MSB (1 << 7) /* Power Meas in State 5 <3> */
1430 #define RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Rx1 Manual Full table/LMT table Gain Index<6:0> */
1431 #define RX_FULL_TBL_IDX_MASK RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(~0)
1432 
1433 /*
1434 * REG_RX1_MANUAL_LPF_GAIN
1435 */
1436 #define POWER_MEAS_IN_STATE_5(x) (((x) & 0x7) << 5) /* Power Meas in State 5<2:0> */
1437 #define RX1_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx1 Manual LPF Gain <4:0> */
1438 #define RX_LPF_IDX_MASK RX1_MANUAL_LPF_GAIN(~0)
1439 
1440 /*
1441 * REG_RX1_MANUAL_DIGITALFORCED_GAIN
1442 */
1443 #define FORCE_RX1_DIGITAL_GAIN (1 << 5) /* Force Rx1 Digital Gain */
1444 #define RX1_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Rx1 Manual/Forced Digital Gain<4:0> */
1445 #define RX_DIGITAL_IDX_MASK RX1_MANUALFORCED_DIGITAL_GAIN(~0)
1446 /*
1447 * REG_RX2_MANUAL_LMT_FULL_GAIN
1448 */
1449 #define RX2_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Rx2 Manual Full table/ LMT table Gain Index<6:0> */
1450 
1451 /*
1452 * REG_RX2_MANUAL_LPF_GAIN
1453 */
1454 #define RX2_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx2 Manual LPF Gain<4:0> */
1455 
1456 /*
1457 * REG_RX2_MANUAL_DIGITALFORCED_GAIN
1458 */
1459 #define FORCE_RX2_DIGITAL_GAIN (1 << 5) /* Force Rx2 Digital Gain */
1460 #define RX2_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Rx2 Manual/Forced Digital Gain<4:0> */
1461 
1462 /*
1463 * REG_FAST_CONFIG_1
1464 */
1465 #define ENABLE_GAIN_INC_AFTER_GAIN_LOCK (1 << 7) /* Enable Gain Inc after Gain Lock */
1466 #define GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH (1 << 6) /* Goto Opt Gain if Energy Lost or EN_AGC High */
1467 #define GOTO_SET_GAIN_IF_EN_AGC_HIGH (1 << 5) /* Goto Set Gain if EN_AGC High */
1468 #define GOTO_SET_GAIN_IF_EXIT_RX_STATE (1 << 4) /* Goto Set Gain if Exit Rx State */
1469 #define DONT_UNLOCK_GAIN_IF_ENERGY_LOST (1 << 3) /* Don't Unlock Gain if Energy Lost */
1470 #define GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE (1 << 2) /* Goto Optimized Gain if Exit Rx State */
1471 #define DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG (1 << 1) /* Don't Unlock Gain If Lg ADC or LMT Ovrg */
1472 #define ENABLE_INCR_GAIN (1 << 0) /* Enable Incr Gain */
1473 
1474 /*
1475 * REG_FAST_CONFIG_2_SETTLING_DELAY
1476 */
1477 #define USE_LAST_LOCK_LEVEL_FOR_SET_GAIN (1 << 7) /* Use Last Lock Level for Set Gain */
1478 #define ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL (1 << 6) /* Enable LMT Gain Inc for Lock Level */
1479 #define GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH (1 << 5) /* Goto Max Gain or Opt Gain if EN_AGC High */
1480 #define SETTLING_DELAY(x) (((x) & 0x1F) << 0) /* Settling Delay<4:0> */
1481 
1482 /*
1483 * REG_FAST_ENERGY_LOST_THRESH
1484 */
1485 #define POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE(x) (((x) & 0x3) << 6) /* Post Lock Level Step Size for: LPF Table/ Full Table <1:0> */
1486 #define ENERGY_LOST_THRESH(x) (((x) & 0x3F) << 0) /* Energy lost threshold<5:0> */
1487 
1488 /*
1489 * REG_FAST_STRONGER_SIGNAL_THRESH
1490 */
1491 #define POST_LOCK_LEVEL_STP_FOR_LMT_TABLE(x) (((x) & 0x3) << 6) /* Post Lock Level Step for LMT Table <1:0> */
1492 #define STRONGER_SIGNAL_THRESH(x) (((x) & 0x3F) << 0) /* Stronger Signal Threshold<5:0> */
1493 
1494 /*
1495 * REG_FAST_LOW_POWER_THRESH
1496 */
1497 #define DONT_UNLOCK_GAIN_IF_ADC_OVRG (1 << 7) /* Don't unlock gain if ADC Ovrg */
1498 #define LOW_POWER_THRESH(x) (((x) & 0x7F) << 0) /* Low Power Threshold<6:0> */
1499 
1500 /*
1501 * REG_FAST_STRONG_SIGNAL_FREEZE
1502 */
1503 #define DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL (1 << 7) /* Don't unlock gain if Stronger Signal */
1504 
1505 /*
1506 * REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN
1507 */
1508 #define FINAL_OVER_RANGE_COUNT(x) (((x) & 0x7) << 5) /* Final Over Range Count<2:0> */
1509 #define OPTIMIZE_GAIN_OFFSET(x) (((x) & 0xF) << 0) /* Optimize Gain Offset<3:0> */
1510 
1511 /*
1512 * REG_FAST_ENERGY_DETECT_COUNT
1513 */
1514 #define INCREMENT_GAIN_STP_LPFLMT(x) (((x) & 0x7) << 5) /* Increment Gain Step (LPF/LMT)<2:0> */
1515 #define ENERGY_DETECT_COUNT(x) (((x) & 0x1F) << 0) /* Energy Detect count<4:0> */
1516 
1517 /*
1518 * REG_FAST_AGCLL_UPPER_LIMIT
1519 */
1520 #define AGCLL_MAX_INCREASE(x) (((x) & 0x3F) << 0) /* AGCLL Max Increase<5:0> */
1521 
1522 /*
1523 * REG_FAST_GAIN_LOCK_EXIT_COUNT
1524 */
1525 #define GAIN_LOCK_EXIT_COUNT(x) (((x) & 0x3F) << 0) /* Gain Lock Exit Count<5:0> */
1526 
1527 /*
1528 * REG_FAST_INITIAL_LMT_GAIN_LIMIT
1529 */
1530 #define INITIAL_LMT_GAIN_LIMIT(x) (((x) & 0x7F) << 0) /* Initial LMT Gain Limit<6:0> */
1531 
1532 /*
1533 * REG_AGC_INNER_LOW_THRESH
1534 */
1535 #define PREVENT_GAIN_INC (1 << 7) /* Prevent Gain Inc */
1536 #define AGC_INNER_LOW_THRESH(x) (((x) & 0x7F) << 0) /* AGC Inner Low Threshold<6:0> */
1537 
1538 /*
1539 * REG_LMT_OVERLOAD_COUNTERS
1540 */
1541 #define LARGE_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4) /* Large LMT Overload Exceeded Counter<3:0> */
1542 #define SMALL_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Small LMT Overload Exceeded Counter<3:0> */
1543 
1544 /*
1545 * REG_ADC_OVERLOAD_COUNTERS
1546 */
1547 #define LARGE_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4) /* Large ADC Overload Exceeded Counter<3:0> */
1548 #define SMALL_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Small ADC Overload Exceeded Counter<3:0> */
1549 
1550 /*
1551 * REG_GAIN_STP1
1552 */
1553 #define IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD (1 << 7) /* Immed. Gain Change if Lg LMT Overload */
1554 #define IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD (1 << 3) /* Immed. Gain Change if Lg ADC Overload */
1555 #define AGC_INNER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 4) /* AGC Inner High Threshold Exceeded Step Size<2:0> */
1556 #define AGC_INNER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 0) /* AGC Inner Low Threshold Exceeded Step Size<2:0> */
1557 
1558 /*
1559 * REG_DIGITAL_SAT_COUNTER
1560 */
1561 #define DOUBLE_GAIN_COUNTER (1 << 5) /* Double Gain Counter */
1562 #define ENABLE_SYNC_FOR_GAIN_COUNTER (1 << 4) /* Enable Sync for Gain Counter */
1563 #define DIG_SATURATION_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Dig Saturation Exceeded Counter<3:0> */
1564 
1565 /*
1566 * REG_OUTER_POWER_THRESHS
1567 */
1568 #define AGC_OUTER_HIGH_THRESH(x) (((x) & 0xF) << 4) /* AGC Outer High Threshold<3:0> */
1569 #define AGC_OUTER_LOW_THRESH(x) (((x) & 0xF) << 0) /* AGC Outer Low Threshold<3:0> */
1570 
1571 /*
1572 * REG_GAIN_STP_2
1573 */
1574 #define AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 4) /* AGC outer High Threshold Exceeded Step Size<3:0> */
1575 #define AGC_OUTER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 0) /* AGC Outer Low Threshold Exceeded Step Size<3:0> */
1576 
1577 /*
1578 * REG_EXT_LNA_HIGH_GAIN
1579 */
1580 #define EXT_LNA_HIGH_GAIN(x) (((x) & 0x3F) << 0) /* Ext LNA High Gain<5:0> */
1581 
1582 /*
1583 * REG_EXT_LNA_LOW_GAIN
1584 */
1585 #define EXT_LNA_LOW_GAIN(x) (((x) & 0x3F) << 0) /* Ext LNA Low Gain<5:0> */
1586 
1587 /*
1588 * REG_GAIN_TABLE_ADDRESS
1589 */
1590 #define GAIN_TABLE_ADDRESS(x) (((x) & 0x7F) << 0) /* Gain Table Address<6:0> */
1591 
1592 /*
1593 * REG_GAIN_TABLE_WRITE_DATA1
1594 */
1595 #define EXT_LNA_CTRL (1 << 7) /* Ext LNA Ctrl */
1596 #define LNA_GAIN(x) (((x) & 0x3) << 5) /* LNA Gain <1:0> */
1597 #define MIXER_GM_GAIN(x) (((x) & 0x1F) << 0) /* Mixer Gm Gain <4:0> */
1598 
1599 /*
1600 * REG_GAIN_TABLE_WRITE_DATA2
1601 */
1602 #define TIA_GAIN (1 << 5) /* TIA Gain */
1603 #define LPF_GAIN(x) (((x) & 0x1F) << 0) /* LPF Gain <4:0> */
1604 
1605 /*
1606 * REG_GAIN_TABLE_WRITE_DATA_3
1607 */
1608 #define RF_DC_CAL (1 << 5) /* RF DC Cal */
1609 #define DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Digital Gain <4:0> */
1610 
1611 /*
1612 * REG_GAIN_TABLE_READ_DATA_1
1613 */
1614 #define TO_LNA_GAIN(x) (((x) >> 5) & 0x3) /* LNA Gain <1:0> */
1615 #define TO_MIXER_GM_GAIN(x) (((x) >> 0) & 0x1F) /* Mixer Gm Gain <4:0> */
1616 
1617 /*
1618 * REG_GAIN_TABLE_READ_DATA_2
1619 */
1620 #define TO_LPF_GAIN(x) (((x) >> 0) & 0x1F) /* LPF Gain <4:0> */
1621 
1622 /*
1623 * REG_GAIN_TABLE_READ_DATA_3
1624 */
1625 #define TO_DIGITAL_GAIN(x) (((x) >> 0) & 0x1F) /* Digital Gain <4:0> */
1626 
1627 /*
1628 * REG_GAIN_TABLE_CONFIG
1629 */
1630 #define WRITE_GAIN_TABLE (1 << 2) /* Write Gain Table */
1631 #define START_GAIN_TABLE_CLOCK (1 << 1) /* Start Gain Table Clock */
1632 #define RECEIVER_SELECT(x) (((x) & 0x3) << 3) /* Receiver Select<1:0> */
1633 #define GT_RX1 1
1634 #define GT_RX2 2
1635 
1636 
1637 /*
1638 * REG_GM_SUB_TABLE_GAIN_WRITE
1639 */
1640 #define GM_SUB_TABLE_GAIN_WRITE(x) (((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Write<6:0> */
1641 
1642 /*
1643 * REG_GM_SUB_TABLE_BIAS_WRITE
1644 */
1645 #define GM_SUB_TABLE_BIAS_WRITE(x) (((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Write<4:0> */
1646 
1647 /*
1648 * REG_GM_SUB_TABLE_CTRL_WRITE
1649 */
1650 #define GM_SUB_TABLE_CTRL_WRITE(x) (((x) & 0x3F) << 0) /* Gm Sub Table Control Word Write<5:0> */
1651 
1652 /*
1653 * REG_GM_SUB_TABLE_GAIN_READ
1654 */
1655 #define GM_SUB_TABLE_GAIN_READ(x) (((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Read<6:0> */
1656 
1657 /*
1658 * REG_GM_SUB_TABLE_BIAS_READ
1659 */
1660 #define GM_SUB_TABLE_BIAS_READ(x) (((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Read<4:0> */
1661 
1662 /*
1663 * REG_GM_SUB_TABLE_CTRL_READ
1664 */
1665 #define GM_SUB_TABLE_CTRL_READ(x) (((x) & 0x3F) << 0) /* Gm Sub Table Control Word Read<5:0> */
1666 
1667 /*
1668 * REG_GM_SUB_TABLE_CONFIG
1669 */
1670 #define WRITE_GM_SUB_TABLE (1 << 2) /* Write Gm Sub Table */
1671 #define START_GM_SUB_TABLE_CLOCK (1 << 1) /* Start Gm Sub Table Clock */
1672 
1673 /*
1674 * REG_GAIN_DIFF_WORDERROR_WRITE
1675 */
1676 #define CALIB_TABLE_GAIN_DIFFERROR_WORD(x) (((x) & 0x3F) << 0) /* Calib Table Gain Diff/Error Word<5:0> */
1677 
1678 /*
1679 * REG_GAIN_ERROR_READ
1680 */
1681 #define CALIB_TABLE_GAIN_ERROR(x) (((x) & 0x1F) << 0) /* Calib Table Gain Error<4:0> */
1682 
1683 /*
1684 * REG_CONFIG
1685 */
1686 #define READ_SELECT (1 << 4) /* Read Select */
1687 #define WRITE_MIXER_ERROR_TABLE (1 << 3) /* Write Mixer Error Table */
1688 #define WRITE_LNA_ERROR_TABLE (1 << 2) /* Write LNA Error Table */
1689 #define WRITE_LNA_GAIN_DIFF (1 << 1) /* Write LNA Gain Diff */
1690 #define START_CALIB_TABLE_CLOCK (1 << 0) /* Start Calib Table Clock */
1691 #define CALIB_TABLE_SELECT(x) (((x) & 0x3) << 5) /* Calib Table Select<1:0> */
1692 
1693 /*
1694 * REG_LNA_GAIN_DIFF_READ_BACK
1695 */
1696 #define LNA_CALIB_TABLE_GAIN_DIFFERENCE_WORD(x) (((x) & 0x3F) << 0) /* LNA Calib Table Gain Difference Word<5:0> */
1697 
1698 /*
1699 * REG_MAX_MIXER_CALIBRATION_GAIN_INDEX
1700 */
1701 #define MAX_MIXER_CALIBRATION_GAIN_INDEX(x) (((x) & 0x1F) << 0) /* Max Mixer Calibration Gain Index<4:0> */
1702 
1703 /*
1704 * REG_SETTLE_TIME
1705 */
1706 #define ENABLE_DIG_GAIN_CORR (1 << 7) /* Enable Dig Gain Corr */
1707 #define FORCE_TEMP_SENSOR_FOR_CAL (1 << 6) /* Force Temp Sensor for Cal */
1708 #define SETTLE_TIME(x) (((x) & 0x3F) << 0) /* Settle Time<5:0> */
1709 
1710 /*
1711 * REG_MEASURE_DURATION
1712 */
1713 #define GAIN_CAL_MEAS_DURATION(x) (((x) & 0xF) << 0) /* Gain Cal Meas Duration<3:0> */
1714 
1715 /*
1716 * REG_MEASURE_DURATION_01
1717 */
1718 #define MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4) /* Measurement duration 1 <3:0> */
1719 #define MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0) /* Measurement duration 0 <3:0> */
1720 
1721 /*
1722 * REG_MEASURE_DURATION_23
1723 */
1724 #define MEASUREMENT_DURATION_3(x) (((x) & 0xF) << 4) /* Measurement duration 3 <3:0> */
1725 #define MEASUREMENT_DURATION_2(x) (((x) & 0xF) << 0) /* Measurement duration 2 <3:0> */
1726 
1727 /*
1728 * REG_RSSI_CONFIG
1729 */
1730 #define START_RSSI_MEAS (1 << 5) /* Start RSSI Meas (Mode 4) */
1731 #define ENABLE_ADC_POWER_MEAS (1 << 1) /* Enable ADC Power Meas. */
1732 #define DEFAULT_RSSI_MEAS_MODE (1 << 0) /* Default RSSI Meas Mode */
1733 #define RFIR_FOR_RSSI_MEASUREMENT(x) (((x) & 0x3) << 6) /* RFIR for RSSI measurement<1:0> */
1734 #define RSSI_MODE_SELECT(x) (((x) & 0x7) << 2) /* RSSI Mode Select<2:0> */
1735 
1736 /*
1737 * REG_ADC_MEASURE_DURATION_01
1738 */
1739 #define ADC_POWER_MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4) /* ADC Power Measurement Duration 1<3:0> */
1740 #define ADC_POWER_MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0) /* ADC Power Measurement Duration 0 <3:0> */
1741 
1742 /*
1743 * REG_DEC_POWER_MEASURE_DURATION_0
1744 */
1745 #define USE_HB3_OUT_FOR_ADC_PWR_MEAS (1 << 7) /* Use HB3 Out for ADC Pwr Meas */
1746 #define USE_HB1_OUT_FOR_DEC_PWR_MEAS (1 << 6) /* Use HB1 Out for Dec pwr Meas */
1747 #define ENABLE_DEC_PWR_MEAS (1 << 5) /* Enable Dec Pwr Meas */
1748 #define DEFAULT_MODE_ADC_POWER (1 << 4) /* Default Mode ADC Power */
1749 #define DEC_POWER_MEASUREMENT_DURATION(x) (((x) & 0xF) << 0) /* Dec Power Measurement Duration <3:0> */
1750 
1751 /*
1752 * REG_LNA_GAIN
1753 */
1754 #define DB_GAIN_READBACK_CHANNEL (1 << 0) /* dB Gain Read-back Channel */
1755 #define MAX_LNA_GAIN(x) (((x) & 0x7F) << 1) /* Max LNA Gain<6:0> */
1756 
1757 /*
1758 * REG_RX_QUAD_CAL_LEVEL
1759 */
1760 #define RX_QUAD_CAL_LEVEL(x) (((x) & 0xF) << 0) /* Rx Quad Cal Level <3 :0> */
1761 
1762 /*
1763 * REG_CALIBRATION_CONFIG_1
1764 */
1765 #define ENABLE_PHASE_CORR (1 << 7) /* Enable Phase Corr */
1766 #define ENABLE_GAIN_CORR (1 << 6) /* Enable Gain Corr */
1767 #define USE_SETTLE_COUNT_FOR_DC_CAL_WAIT (1 << 5) /* Use Settle Count for DC Cal Wait */
1768 #define FIXED_DC_CAL_WAIT_TIME (1 << 4) /* Fixed DC Cal Wait Time */
1769 #define FREE_RUN_MODE (1 << 3) /* Free Run Mode */
1770 #define ENABLE_CORR_WORD_DECIMATION (1 << 2) /* Enable Corr Word Decimation */
1771 #define ENABLE_TRACKING_MODE_CH2 (1 << 1) /* Enable Tracking Mode CH2 */
1772 #define ENABLE_TRACKING_MODE_CH1 (1 << 0) /* Enable Tracking Mode CH1 */
1773 
1774 /*
1775 * REG_CALIBRATION_CONFIG_2
1776 */
1777 #define SOFT_RESET (1 << 7) /* Soft Reset */
1778 #define CALIBRATION_CONFIG2_DFLT (0x3 << 5) /* Must be 2'b11 */
1779 #define K_EXP_PHASE(x) (((x) & 0x1F) << 0) /* K exp Phase<4:0> */
1780 
1781 /*
1782 * REG_CALIBRATION_CONFIG_3
1783 */
1784 #define PREVENT_POS_LOOP_GAIN (1 << 7) /* Prevent Pos Loop Gain */
1785 #define K_EXP_AMPLITUDE(x) (((x) & 0x1F) << 0) /* K exp Amplitude<4:0> */
1786 
1787 /*
1788 * REG_RX_QUAD_GAIN1
1789 */
1790 #define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0) /* Rx Full table/LMT table gain<6:0> */
1791 
1792 /*
1793 * REG_RX_QUAD_GAIN2
1794 */
1795 #define CORRECTION_WORD_DECIMATION_M(x) (((x) & 0x7) << 5) /* Correction Word Decimation M<2:0> */
1796 #define RX_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx LPF gain<4:0> */
1797 
1798 /*
1799 * REG_RX1_INPUT_A_OFFSETS
1800 */
1801 #define RX1_INPUT_A_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2) /* Rx1 Input A "I" DC Offset<5:0> */
1802 #define RX1_INPUT_A_Q_DC_OFFSET(x) (((x) & 0x3) << 0) /* Rx1 Input A "Q" DC Offset<9:8> */
1803 
1804 /*
1805 * REG_INPUT_A_OFFSETS_1
1806 */
1807 #define RX2_INPUT_A_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4) /* Rx2 Input A "Q" DC Offset<3:0> */
1808 #define RX1_INPUT_A_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0) /* Rx1 Input A "I" DC Offset<9:6> */
1809 
1810 /*
1811 * REG_RX2_INPUT_A_OFFSETS
1812 */
1813 #define RX2_INPUT_A_I_DC_OFFSET(x) (((x) & 0x3) << 6) /* Rx2 Input A "I" DC Offset<1:0> */
1814 #define RX2_INPUT_A_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0) /* Rx2 Input A "Q" DC Offset<9:4> */
1815 
1816 /*
1817 * REG_RX1_INPUT_BC_OFFSETS
1818 */
1819 #define RX1_INPUT_BC_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2) /* Rx1 Input B&C "I" DC Offset<5:0> */
1820 #define RX1_INPUT_BC_Q_DC_OFFSET(x) (((x) & 0x3) << 0) /* Rx1 Input B&C "Q" DC Offset<9:8> */
1821 
1822 /*
1823 * REG_INPUT_BC_OFFSETS_1
1824 */
1825 #define RX2_INPUT_BC_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4) /* Rx2 Input B&C "Q" DC Offset<3:0> */
1826 #define RX1_INPUT_BC_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0) /* Rx1 Input B&C "I" DC Offset<9:6> */
1827 
1828 /*
1829 * REG_RX2_INPUT_BC_OFFSETS
1830 */
1831 #define RX2_INPUT_BC_I_DC_OFFSET(x) (((x) & 0x3) << 6) /* Rx2 Input B&C "I" DC Offset<1:0> */
1832 #define RX2_INPUT_BC_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0) /* Rx2 Input B&C "Q" DC Offset<9:4> */
1833 
1834 /*
1835 * REG_FORCE_BITS
1836 */
1837 #define RX2_INPUT_BC_FORCE_OFFSET (1 << 7) /* Rx2 Input B&C Force offset */
1838 #define RX1_INPUT_BC_FORCE_OFFSET (1 << 6) /* Rx1 Input B&C Force offset */
1839 #define RX2_INPUT_BC_FORCE_PHGAIN (1 << 5) /* Rx2 Input B&C Force Ph/Gain */
1840 #define RX1_INPUT_BC_FORCE_PHGAIN (1 << 4) /* Rx1 Input B&C Force Ph/Gain */
1841 #define RX2_INPUT_A_FORCE_OFFSET (1 << 3) /* Rx2 Input A Force offset */
1842 #define RX1_INPUT_A_FORCE_OFFSET (1 << 2) /* Rx1 Input A Force offset */
1843 #define RX2_INPUT_A_FORCE_PHGAIN (1 << 1) /* Rx2 Input A Force Ph/Gain */
1844 #define RX1_INPUT_A_FORCE_PHGAIN (1 << 0) /* Rx1 Input A Force Ph/Gain */
1845 
1846 /*
1847 * REG_RF_DC_OFFSET_CONFIG_1
1848 */
1849 #define DAC_FS(x) (((x) & 0x3) << 4) /* DAC FS<1:0> */
1850 #define RF_DC_CALIBRATION_COUNT(x) (((x) & 0xF) << 0) /* RF DC Calibration Count<3:0> */
1851 
1852 /*
1853 * REG_RF_DC_OFFSET_ATTEN
1854 */
1855 #define RF_DC_OFFSET_TABLE_UPDATE_COUNT(x) (((x) & 0x7) << 5) /* RF DC Offset Table Update Count<2:0> */
1856 #define RF_DC_OFFSET_ATTEN(x) (((x) & 0x1F) << 0) /* RF DC Offset Attenuation<4:0> */
1857 
1858 /*
1859 * REG_INVERT_BITS
1860 */
1861 #define INVERT_RX2_RF_DC_CGIN_WORD (1 << 7) /* Invert Rx2 RF DC CGin Word */
1862 #define INVERT_RX1_RF_DC_CGIN_WORD (1 << 6) /* Invert Rx1 RF DC CGin Word */
1863 #define INVERT_RX2_RF_DC_CGOUT_WORD (1 << 5) /* Invert Rx2 RF DC CGout Word */
1864 #define INVERT_RX1_RF_DC_CGOUT_WORD (1 << 4) /* Invert Rx1 RF DC CGout Word */
1865 
1866 /*
1867 * REG_DC_OFFSET_CONFIG2
1868 */
1869 #define USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL (1 << 7) /* Use Wait Counter for RF DC Init Cal */
1870 #define ENABLE_FAST_SETTLE_MODE (1 << 6) /* Enable Fast Settle Mode */
1871 #define ENABLE_BB_DC_OFFSET_TRACKING (1 << 5) /* Enable BB DC Offset Tracking */
1872 #define RESET_ACC_ON_GAIN_CHANGE (1 << 4) /* Reset Acc on Gain Change */
1873 #define ENABLE_RF_OFFSET_TRACKING (1 << 3) /* Enable RF Offset Tracking */
1874 #define DC_OFFSET_UPDATE(x) (((x) & 0x7) << 0) /* DC Offset Update<2:0> */
1875 
1876 /*
1877 * REG_RF_CAL_GAIN_INDEX
1878 */
1879 #define RF_MINIMUM_CALIBRATION_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* RF Minimum Calibration Gain Index<6:0> */
1880 
1881 /*
1882 * REG_SOI_THRESH
1883 */
1884 #define RF_SOI_THRESH(x) (((x) & 0x7F) << 0) /* RF SOI Threshold<6:0> */
1885 
1886 /*
1887 * REG_BB_DC_OFFSET_SHIFT
1888 */
1889 #define INCREASE_COUNT_DURATION (1 << 7) /* Increase Count Duration */
1890 #define BB_TRACKING_DECIMATE(x) (((x) & 0x3) << 5) /* BB Tracking Decimate<1:0> */
1891 #define BB_DC_M_SHIFT(x) (((x) & 0x1F) << 0) /* BB DC M Shift<4:0> */
1892 
1893 /*
1894 * REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT
1895 */
1896 #define READ_BACK_CH_SEL (1 << 7) /* Read Back CH Sel */
1897 #define UPDATE_TRACKING_WORD (1 << 6) /* Update Tracking Word */
1898 #define FORCE_RX_NULL (1 << 5) /* Force Rx Null */
1899 #define BB_DC_TRACKING_FAST_SETTLE_M_SHIFT(x) (((x) & 0x1F) << 0) /* BB DC Tracking Fast Settle M Shift<4:0> */
1900 
1901 /*
1902 * REG_BB_DC_OFFSET_ATTEN
1903 */
1904 #define BB_DC_OFFSET_ATTEN(x) (((x) & 0xF) << 0) /* BB DC Offset Atten<3:0> */
1905 
1906 /*
1907 * REG_RX1_BB_DC_WORD_I_MSB
1908 */
1909 #define RX1_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word I<14:8> */
1910 
1911 /*
1912 * REG_RX1_BB_DC_WORD_Q_MSB
1913 */
1914 #define RX1_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word Q<14:8> */
1915 
1916 /*
1917 * REG_RX2_BB_DC_WORD_I_MSB
1918 */
1919 #define RX2_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word I<14:8> */
1920 
1921 /*
1922 * REG_RX2_BB_DC_WORD_Q_MSB
1923 */
1924 #define RX2_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word Q<14:8> */
1925 
1926 /*
1927 * REG_BB_TRACK_CORR_WORD_I_MSB
1928 */
1929 #define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word I<14:8> */
1930 
1931 /*
1932 * REG_BB_TRACK_CORR_WORD_Q_MSB
1933 */
1934 #define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word Q<14:8> */
1935 
1936 /*
1937 * REG_SYMBOL_LSB
1938 */
1939 #define RX2_RSSI_SYMBOL (1 << 1) /* Rx2 RSSI symbol <0> */
1940 #define RX1_RSSI_SYMBOL (1 << 0) /* Rx1 RSSI symbol <0> */
1941 
1942 /*
1943 * REG_PREAMBLE_LSB
1944 */
1945 #define RX2_RSSI_PREAMBLE (1 << 1) /* Rx2 RSSI preamble <0> */
1946 #define RX1_RSSI_PREAMBLE (1 << 0) /* Rx1 RSSI preamble <0> */
1947 
1948 /*
1949 * REG_RX1_RSSI_SYMBOL, REG_RX1_RSSI_PREAMBLE,
1950 * REG_RX2_RSSI_SYMBOL, REG_RX2_RSSI_PREAMBLE
1951 */
1952 #define RSSI_LSB_SHIFT 1
1953 #define RSSI_LSB_MASK1 0x01
1954 #define RSSI_LSB_MASK2 0x02
1955 
1956 /*
1957 * REG_RX_PATH_GAIN_LSB
1958 */
1959 #define RX_PATH_GAIN (1 << 0) /* Rx Path Gain<0> */
1960 
1961 /*
1962 * REG_RX_DIFF_LNA_FORCE
1963 */
1964 #define FORCE_RX2_LNA_GAIN (1 << 7) /* Force Rx2 LNA Gain */
1965 #define RX2_LNA_BYPASS (1 << 6) /* Rx2 LNA Bypass */
1966 #define FORCE_RX1_LNA_GAIN (1 << 3) /* Force Rx1 LNA Gain */
1967 #define RX1_LNA_BYPASS (1 << 2) /* Rx1 LNA Bypass */
1968 #define RX2_LNA_GAIN(x) (((x) & 0x3) << 4) /* Rx2 LNA Gain<1:0> */
1969 #define RX1_LNA_GAIN(x) (((x) & 0x3) << 0) /* Rx1 LNA Gain<1:0> */
1970 
1971 /*
1972 * REG_RX_LNA_BIAS_COARSE
1973 */
1974 #define RX_LNA_BIAS_COARSE(x) (((x) & 0xF) << 0) /* Rx LNA Bias Coarse<3:0> */
1975 
1976 /*
1977 * REG_RX_LNA_BIAS_FINE_0
1978 */
1979 #define RX_LNA_PCASCODE_BIAS(x) (((x) & 0x7) << 5) /* Rx LNA p-Cascode Bias<2:0> */
1980 #define RX_LNA_BIAS(x) (((x) & 0x1F) << 0) /* Rx LNA Bias<4:0> */
1981 
1982 /*
1983 * REG_RX_LNA_BIAS_FINE_1
1984 */
1985 #define RX_LNA_P_CASCODE_BIAS_FINE(x) (((x) & 0x3) << 0) /* Rx LNA p- Cascode Bias Fine<4:3> */
1986 
1987 /*
1988 * REG_RX_MIX_GM_CONFIG
1989 */
1990 #define RX_MIX_GM_CM_OUT(x) (((x) & 0x7) << 5) /* Rx Mix Gm CM Out<2:0> */
1991 #define RX_MIX_GM_PLOAD(x) (((x) & 0x3) << 0) /* Rx Mix Gm pload <1:0> */
1992 
1993 /*
1994 * REG_RX1_MIX_GM_FORCE
1995 */
1996 #define FORCE_RX1_MIX_GM (1 << 6) /* Force Rx1 Mix Gm */
1997 #define RX1_MIX_GM_GAIN(x) (((x) & 0x3F) << 0) /* Rx1 Mix Gm Gain<5:0> */
1998 
1999 /*
2000 * REG_RX1_MIX_GM_BIAS_FORCE
2001 */
2002 #define RX1_MIX_GM_BIAS(x) (((x) & 0x1F) << 0) /* Rx1 Mix Gm Bias<4:0> */
2003 
2004 /*
2005 * REG_RX2_MIX_GM_FORCE
2006 */
2007 #define FORCE_RX2_MIX_GM (1 << 6) /* Force Rx2 Mix Gm */
2008 #define RX2_MIX_GM_GAIN(x) (((x) & 0x3F) << 0) /* Rx2 Mix Gm Gain<5:0> */
2009 
2010 /*
2011 * REG_RX2_MIX_GM_BIAS_FORCE
2012 */
2013 #define RX2_MIX_GM_BIAS(x) (((x) & 0x1F) << 0) /* Rx2 Mix Gm Bias<4:0> */
2014 
2015 /*
2016 * REG_INPUT_A_MSBS
2017 */
2018 #define INPUT_A_RX1_Q(x) (((x) & 0x3) << 6) /* Input A RX1 Q<9:8> */
2019 #define INPUT_A_RX1_I(x) (((x) & 0x3) << 4) /* Input A RX1 I<9:8> */
2020 #define INPUT_A_RX2_I(x) (((x) & 0x3) << 2) /* Input A RX2 I<9:8> */
2021 #define INPUT_A_RX2_Q(x) (((x) & 0x3) << 0) /* Input A RX2 Q<9:8> */
2022 
2023 /*
2024 * REG_INPUTS_BC_MSBS
2025 */
2026 #define INPUTS_BC_RX1_Q(x) (((x) & 0x3) << 6) /* Inputs B&C RX1 Q<9:8> */
2027 #define INPUTS_BC_RX1_I(x) (((x) & 0x3) << 4) /* Inputs B&C RX1 I<9:8> */
2028 #define INPUTS_BC_RX2_I(x) (((x) & 0x3) << 2) /* Inputs B&C RX2 I<9:8> */
2029 #define INPUTS_BC_RX2_Q(x) (((x) & 0x3) << 0) /* Inputs B&C RX2 Q<9:8> */
2030 
2031 /*
2032 * REG_FORCE_OS_DAC
2033 */
2034 #define FORCE_CGIN_DAC (1 << 2) /* Force CGin DAC */
2035 
2036 /*
2037 * REG_RX_MIX_LO_CM
2038 */
2039 #define RX_MIX_LO_CM(x) (((x) & 0x3F) << 0) /* Rx Mix LO CM<5:0> */
2040 
2041 /*
2042 * REG_RX_CGB_SEG_ENABLE
2043 */
2044 #define RX_CGB_SEG_ENABLE(x) (((x) & 0x3F) << 0) /* Rx CGB Seg Enable<5:0> */
2045 
2046 /*
2047 * REG_RX_MIX_INPUTBIAS
2048 */
2049 #define RX_CGB_INPUT_CM_SEL(x) (((x) & 0x3) << 4) /* Rx CGB Input CM Sel<1:0> */
2050 #define RX_CGB_BIAS(x) (((x) & 0xF) << 0) /* Rx CGB Bias<3:0> */
2051 
2052 /*
2053 * REG_RX_TIA_CONFIG
2054 */
2055 #define TIA2_OVERRIDE_C (1 << 3) /* TIA2 Override C */
2056 #define TIA2_OVERRIDE_R (1 << 2) /* TIA2 Override R */
2057 #define TIA1_OVERRIDE_C (1 << 1) /* TIA1 Override C */
2058 #define TIA1_OVERRIDE_R (1 << 0) /* TIA1 Override R */
2059 #define TIA_SEL_CC(x) (((x) & 0x7) << 5) /* TIA Sel CC<2:0> */
2060 
2061 /*
2062 * REG_TIA1_C_LSB
2063 */
2064 #define TIA1_RF(x) (((x) & 0x3) << 6) /* TIA1 RF<1:0> */
2065 #define TIA1_C_LSB(x) (((x) & 0x3F) << 0) /* TIA1 C LSB<5:0> */
2066 
2067 /*
2068 * REG_TIA1_C_MSB
2069 */
2070 #define TIA1_C_MSB(x) (((x) & 0x7F) << 0) /* TIA1 C MSB<6:0> */
2071 
2072 /*
2073 * REG_TIA2_C_LSB
2074 */
2075 #define TIA2_RF(x) (((x) & 0x3) << 6) /* TIA2 RF<1:0> */
2076 #define TIA2_C_LSB(x) (((x) & 0x3F) << 0) /* TIA2 C LSB<5:0> */
2077 
2078 /*
2079 * REG_TIA2_C_MSB
2080 */
2081 #define TIA2_C_MSB(x) (((x) & 0x7F) << 0) /* TIA2 C MSB<6:0> */
2082 
2083 /*
2084 * REG_RX1_BBF_R1A
2085 */
2086 #define FORCE_RX1_RESISTORS (1 << 7) /* Force Rx1 Resistors */
2087 #define RX1_BBF_R1A(x) (((x) & 0x3F) << 0) /* Rx1 BBF R1A<5:0> */
2088 
2089 /*
2090 * REG_RX2_BBF_R1A
2091 */
2092 #define FORCE_RX2_RESISTORS (1 << 7) /* Force Rx2 Resistors */
2093 #define RX2_BBF_R1A(x) (((x) & 0x3F) << 0) /* Rx2 BBF R1A<5:0> */
2094 
2095 /*
2096 * REG_RX1_TUNE_CTRL
2097 */
2098 #define RX1_TUNE_RESAMPLE_PHASE (1 << 2) /* Rx1 Tune Resample Phase */
2099 #define RX1_TUNE_RESAMPLE (1 << 1) /* Rx1 Tune Resample */
2100 #define RX1_PD_TUNE (1 << 0) /* Rx1 PD Tune */
2101 
2102 /*
2103 * REG_RX2_TUNE_CTRL
2104 */
2105 #define RX2_TUNE_RESAMPLE_PHASE (1 << 2) /* Rx2 Tune Resam ple Phase */
2106 #define RX2_TUNE_RESAMPLE (1 << 1) /* Rx2 Tune Resample */
2107 #define RX2_PD_TUNE (1 << 0) /* Rx2 PD Tune */
2108 
2109 /*
2110 * REG_RX_BBF_R2346
2111 */
2112 #define TUNE_OVERRIDE (1 << 7) /* Tune Override */
2113 #define RX_BBF_R2346(x) (((x) & 0x7) << 0) /* Rx BBF R2346<2:0> */
2114 
2115 /*
2116 * REG_RX_BBF_C1_MSB
2117 */
2118 #define RX_BBF_C1_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C1 MSB<5:0> */
2119 
2120 /*
2121 * REG_RX_BBF_C1_LSB
2122 */
2123 #define RX_BBF_C1_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C1 LSB<6:0> */
2124 
2125 /*
2126 * REG_RX_BBF_C2_MSB
2127 */
2128 #define RX_BBF_C2_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C2 MSB<5:0> */
2129 
2130 /*
2131 * REG_RX_BBF_C2_LSB
2132 */
2133 #define RX_BBF_C2_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C2 LSB<6:0> */
2134 
2135 /*
2136 * REG_RX_BBF_C3_MSB
2137 */
2138 #define RX_BBF_C3_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C3 MSB<5:0> */
2139 
2140 /*
2141 * REG_RX_BBF_C3_LSB
2142 */
2143 #define RX_BBF_C3_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C3 LSB<6:0> */
2144 
2145 /*
2146 * REG_RX_BBF_CC1_CTR
2147 */
2148 #define RX_BBF_CC1_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC1 Ctr<6:0> */
2149 
2150 /*
2151 * REG_RX_BBF_POW_RZ_BYTE0
2152 */
2153 #define MUST_BE_ZERO (1 << 7) /* Must be zero */
2154 #define RX1_BBF_POW_CTR(x) (((x) & 0x3) << 5) /* Rx1 BBF Pow Ctr<1:0> */
2155 #define RX_BBF_RZ1_CTR(x) (((x) & 0x3) << 3) /* Rx BBF Rz1 Ctr<1:0> */
2156 
2157 /*
2158 * REG_RX_BBF_CC2_CTR
2159 */
2160 #define RX_BBF_CC2_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC2 Ctr<6:0> */
2161 
2162 /*
2163 * REG_RX_BBF_POW_RZ_BYTE1
2164 */
2165 #define RX_BBF_POW3_CTR(x) (((x) & 0x3) << 6) /* Rx BBF Pow3 Ctr<1:0> */
2166 #define RX_BBF_RZ3_CTR(x) (((x) & 0x3) << 4) /* Rx BBF RZ3 Ctr<1:0> */
2167 #define RX_BBF_POW2_CTR(x) (((x) & 0x3) << 2) /* Rx BBF Pow2 Ctr<1:0> */
2168 #define RX_BBF_RZ2_CTR(x) (((x) & 0x3) << 0) /* Rx BBF Rz2 Ctr<1:0> */
2169 
2170 /*
2171 * REG_RX_BBF_CC3_CTR
2172 */
2173 #define RX_BBF_CC3_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC3 Ctr<6:0> */
2174 
2175 /*
2176 * REG_RX_BBF_TUNE
2177 */
2178 #define RXBBF_BYPASS_BIAS_R (1 << 7) /* RxBBF Bypass Bias R */
2179 #define RX_BBF_R5_TUNE (1 << 4) /* Rx BBF R5 Tune */
2180 #define RX1_BBF_TUNE_COMP_I (1 << 3) /* Rx1 BBF Tune Comp I */
2181 #define RX1_BBF_TUNE_COMP_Q (1 << 2) /* Rx1 BBF Tune Comp Q */
2182 #define RX2_BBF_TUNE_COMP_I (1 << 1) /* Rx2 BBF Tune Comp I */
2183 #define RX2_BBF_TUNE_COMP_Q (1 << 0) /* Rx2 BBF Tune Comp Q */
2184 #define RX_BBF_TUNE_CTR(x) (((x) & 0x3) << 5) /* Rx BBF Tune Ctr<1:0> */
2185 
2186 /*
2187 * REG_RX1_BBF_MAN_GAIN
2188 */
2189 #define RX1_BBF_FORCE_GAIN (1 << 5) /* Rx1 BBF Force Gain */
2190 #define RX1_BBF_BQ_GAIN(x) (((x) & 0x3) << 3) /* Rx1 BBF BQ Gain<1:0> */
2191 #define RX1_BBF_POLE_GAIN(x) (((x) & 0x7) << 0) /* Rx1 BBF Pole Gain<2:0> */
2192 
2193 /*
2194 * REG_RX2_BBF_MAN_GAIN
2195 */
2196 #define RX2_BBF_FORCE_GAIN (1 << 5) /* Rx2 BBF Force Gain */
2197 #define RX2_BBF_BQ_GAIN(x) (((x) & 0x3) << 3) /* Rx2 BBF BQ Gain<1:0> */
2198 #define RX2_BBF_POLE_GAIN(x) (((x) & 0x7) << 0) /* Rx2 BBF Pole Gain<2:0> */
2199 
2200 /*
2201 * REG_RX_BBF_TUNE_CONFIG
2202 */
2203 #define RX_TUNE_EVALTIME (1 << 4) /* Rx Tune Evaltime */
2204 #define RX_BBF_TUNE_DIVIDE (1 << 0) /* RX BBF Tune Divide<8> */
2205 #define TUNE_COMP_MASK(x) (((x) & 0x3) << 5) /* Tune Comp Mask <1:0> */
2206 #define RX_TUNE_MODE(x) (((x) & 0x7) << 1) /* Rx Tune Mode<2:0> */
2207 
2208 /*
2209 * REG_POLE_GAIN
2210 */
2211 #define POLE_GAIN_TUNE(x) (((x) & 0x3) << 0) /* Pole Gain Tune<1:0> */
2212 
2213 /*
2214 * REG_RX_BBBW_MHZ
2215 */
2216 #define RX_TUNE_BBBW_MHZ(x) (((x) & 0x1F) << 0) /* Rx Tune BBBW MHz<4::0> */
2217 
2218 /*
2219 * REG_RX_BBBW_KHZ
2220 */
2221 #define RX_TUNE_BBBW_KHZ(x) (((x) & 0x7F) << 0) /* Rx Tune BBBW kHz<6:0> */
2222 
2223 /*
2224 * REG_RX_PFD_CONFIG
2225 */
2226 #define BYPASS_LD_SYNTH (1 << 0) /* Bypass Ld Synth */
2227 
2228 /*
2229 * REG_RX_INTEGER_BYTE_1
2230 */
2231 #define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */
2232 
2233 /*
2234 * REG_RX_FRACT_BYTE_2
2235 */
2236 #define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */
2237 
2238 /*
2239 * REG_RX_FORCE_VCO_TUNE_1
2240 */
2241 #define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */
2242 
2243 /*
2244 * REG_RX_ALC_VARACTOR
2245 */
2246 #define INIT_ALC_VALUE(x) (((x) & 0xF) << 4) /* Init ALC Value<3:0> */
2247 #define VCO_VARACTOR(x) (((x) & 0xF) << 0) /* VCO Varactor<3:0> */
2248 
2249 /*
2250 * REG_RX_VCO_OUTPUT
2251 */
2252 #define PORB_VCO_LOGIC (1 << 6) /* PORb VCO Logic */
2253 #define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0) /* VCO Output Level<3:0> */
2254 
2255 /*
2256 * REG_RX_CP_CURRENT
2257 */
2258 #define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */
2259 
2260 /*
2261 * REG_RX_CP_OFFSET
2262 */
2263 #define SYNTH_RECAL (1 << 7) /* Synth Re-Cal */
2264 
2265 /*
2266 * REG_RX_CP_CONFIG
2267 */
2268 #define HALF_VCO_CAL_CLK (1 << 7) /* Half Vco Cal Clk */
2269 #define CP_OFFSET_OFF (1 << 4) /* CP Offset Off */
2270 #define F_CPCAL (1 << 3) /* F Cpcal */
2271 #define CP_CAL_ENABLE (1 << 2) /* Cp Cal Enable */
2272 
2273 /*
2274 * REG_RX_LOOP_FILTER_1
2275 */
2276 #define LOOP_FILTER_C2(x) (((x) & 0xF) << 4) /* Loop Filter C2<3:0> */
2277 #define LOOP_FILTER_C1(x) (((x) & 0xF) << 0) /* Loop Filter C1<3:0> */
2278 
2279 /*
2280 * REG_RX_LOOP_FILTER_2
2281 */
2282 #define LOOP_FILTER_R1(x) (((x) & 0xF) << 4) /* Loop Filter R1<3:0> */
2283 #define LOOP_FILTER_C3(x) (((x) & 0xF) << 0) /* Loop Filter C3<3:0> */
2284 
2285 /*
2286 * REG_RX_LOOP_FILTER_3
2287 */
2288 #define LOOP_FILTER_BYPASS_R3 (1 << 7) /* Loop Filter Bypass R3 */
2289 #define LOOP_FILTER_BYPASS_R1 (1 << 6) /* Loop Filter Bypass R1 */
2290 #define LOOP_FILTER_BYPASS_C2 (1 << 5) /* Loop Filter Bypass C2 */
2291 #define LOOP_FILTER_BYPASS_C1 (1 << 4) /* Loop Filter Bypass C1 */
2292 #define LOOP_FILTER_R3(x) (((x) & 0xF) << 0) /* Loop Filter R3<3:0> */
2293 
2294 /*
2295 * REG_RX_DITHERCP_CAL
2296 */
2297 #define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */
2298 
2299 /*
2300 * REG_RX_VCO_BIAS_1
2301 */
2302 #define VCO_BIAS_TCF(x) (((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */
2303 #define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */
2304 
2305 /*
2306 * REG_RX_CAL_STATUS
2307 */
2308 #define CP_CAL_VALID (1 << 7) /* CP Cal Valid */
2309 #define CP_CAL_DONE (1 << 5) /* CP Cal Done */
2310 #define VCO_CAL_BUSY (1 << 4) /* VCO Cal Busy */
2311 #define CP_CAL_WORD(x) (((x) & 0xF) << 0) /* CP Cal Word<3:0> */
2312 
2313 /*
2314 * REG_RX_VCO_CAL_REF
2315 */
2316 #define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */
2317 
2318 /*
2319 * REG_RX_VCO_PD_OVERRIDES
2320 */
2321 #define POWER_DOWN_VARACTOR_REF (1 << 3) /* Power Down Varactor Ref */
2322 #define PWR_DOWN_VARACT_REF_TCF (1 << 2) /* Pwr Down Varact Ref Tcf */
2323 #define POWER_DOWN_CAL_TCF (1 << 1) /* Power Down Cal Tcf */
2324 #define POWER_DOWN_VCO_BUFFFER (1 << 0) /* Power Down VCO Bufffer */
2325 
2326 /*
2327 * REG_RX_CP_OVERRANGE_VCO_LOCK
2328 */
2329 #define CP_OVRG_HIGH (1 << 7) /* CP Ovrg High */
2330 #define CP_OVRG_LOW (1 << 6) /* CP Ovrg Low */
2331 #define VCO_LOCK (1 << 1) /* Lock */
2332 
2333 /*
2334 * REG_RX_VCO_LDO
2335 */
2336 #define VCO_LDO_BYPASS (1 << 7) /* VCO LDO Bypass */
2337 #define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */
2338 #define VCO_LDO_SEL(x) (((x) & 0x7) << 2) /* VCO LDO Sel<2:0> */
2339 #define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */
2340 
2341 /*
2342 * REG_RX_VCO_CAL
2343 */
2344 #define VCO_CAL_EN (1 << 7) /* VCO Cal En */
2345 #define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4) /* VCO Cal ALC Wait <2:0> */
2346 #define VCO_CAL_COUNT(x) (((x) & 0x3) << 2) /* VCO Cal Count <1:0> */
2347 
2348 /*
2349 * REG_RX_LOCK_DETECT_CONFIG
2350 */
2351 #define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2) /* Lock Detect Count<1:0> */
2352 #define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */
2353 
2354 /*
2355 * REG_RX_CP_LEVEL_DETECT
2356 */
2357 #define CP_LEVEL_DETECT_POWER_DOWN (1 << 6) /* CP Level Detect Power Down */
2358 #define CP_LEVEL_THRESH_LOW(x) (((x) & 0x7) << 3) /* CP Level Threshold Low<2:0> */
2359 #define CP_LEVEL_THRESH_HIGH(x) (((x) & 0x7) << 0) /* CP Level Threshold High<2:0> */
2360 
2361 /*
2362 * REG_RX_DSM_SETUP_0
2363 */
2364 #define DSM_PROG(x) (((x) & 0xF) << 0) /* DSM Prog<3:0> */
2365 
2366 /*
2367 * REG_RX_DSM_SETUP_1
2368 */
2369 #define SIF_CLOCK (1 << 6) /* SIF clock */
2370 #define SIF_RESET_BAR (1 << 5) /* SIF Reset Bar */
2371 #define SIF_ADDR(x) (((x) & 0x1F) << 0) /* SIF Addr<4:0> */
2372 
2373 /*
2374 * REG_RX_CORRECTION_WORD0
2375 */
2376 #define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2377 #define READ_EFFECTIVE_TUNING_WORD (1 << 5) /* Read Effective Tuning Word */
2378 #define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */
2379 
2380 /*
2381 * REG_RX_CORRECTION_WORD1
2382 */
2383 #define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2384 #define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */
2385 
2386 /*
2387 * REG_RX_VCO_VARACTOR_CTRL_0
2388 */
2389 #define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */
2390 #define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */
2391 
2392 /*
2393 * REG_RX_VCO_VARACTOR_CTRL_1
2394 */
2395 #define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */
2396 
2397 /*
2398 * REG_RX_FAST_LOCK_SETUP
2399 */
2400 #define RX_FAST_LOCK_LOAD_SYNTH (1 << 3) /* Rx Fast Lock Load Synth */
2401 #define RX_FAST_LOCK_PROFILE_INIT (1 << 2) /* Rx Fast Lock Profile Init */
2402 #define RX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1) /* Rx Fast Lock Profile Pin Select */
2403 #define RX_FAST_LOCK_MODE_ENABLE (1 << 0) /* Rx Fast Lock Mode Enable */
2404 #define RX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5) /* Rx Fast Lock Profile<2:0> */
2405 
2406 /*
2407 * REG_RX_FAST_LOCK_PROGRAM_ADDR
2408 */
2409 #define RX_FAST_LOCK_PROFILE_ADDR(x) (((x) & 0x7) << 4) /* Rx Fast Lock Profile<2:0> */
2410 #define RX_FAST_LOCK_PROFILE_WORD(x) (((x) & 0xF) << 0) /* Configuration Word <3:0> */
2411 
2412 
2413 /*
2414 * REG_RX_FAST_LOCK_PROGRAM_CTRL
2415 */
2416 #define RX_FAST_LOCK_PROGRAM_WRITE (1 << 1) /* Rx Fast Lock Program Write */
2417 #define RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0) /* Rx Fast Lock Program Clock Enable */
2418 
2419 #define RX_FAST_LOCK_CONFIG_WORD_NUM 16
2420 
2421 /*
2422 * REG_RX_LO_GEN_POWER_MODE
2423 */
2424 #define RX_LO_GEN_POWER_MODE(x) (((x) & 0x3) << 4) /* Power Mode<3:0> */
2425 
2426 /*
2427 * REG_TX_PFD_CONFIG
2428 */
2429 #define DIV_TEST_EN (1 << 5) /* Div Test En */
2430 #define PFD_CLK_EDGE (1 << 1) /* PFD Clk Edge */
2431 #define BYPASS_LD_SYNTH (1 << 0) /* Bypass Ld Synth */
2432 #define PFD_WIDTH(x) (((x) & 0x3) << 2) /* PFD Width <1:0> */
2433 
2434 /*
2435 * REG_TX_INTEGER_BYTE_1
2436 */
2437 #define SDM_BYPASS (1 << 7) /* SDM Bypass */
2438 #define SDM_POWER_DOWN (1 << 6) /* SDM Power Down */
2439 #define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */
2440 
2441 /*
2442 * REG_TX_FRACT_BYTE_2
2443 */
2444 #define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */
2445 
2446 /*
2447 * REG_TX_FORCE_ALC
2448 */
2449 #define FORCE_ALC_ENABLE (1 << 7) /* Force ALC Enable */
2450 #define FORCE_ALC_WORD(x) (((x) & 0x7F) << 0) /* Force ALC Word<6:0> */
2451 
2452 /*
2453 * REG_TX_FORCE_VCO_TUNE_1
2454 */
2455 #define BYPASS_LOAD_DELAY (1 << 7) /* Bypass Load Delay */
2456 #define FORCE_VCO_TUNE_ENABLE (1 << 1) /* Force VCO Tune Enable */
2457 #define FORCE_VCO_TUNE (1 << 0) /* Force VCO Tune */
2458 #define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */
2459 
2460 /*
2461 * REG_TX_ALCVARACT_OR
2462 */
2463 #define INIT_ALC_VALUE(x) (((x) & 0xF) << 4) /* Init ALC Value<3:0> */
2464 #define VCO_VARACTOR(x) (((x) & 0xF) << 0) /* VCO Varactor<3:0> */
2465 
2466 /*
2467 * REG_TX_VCO_OUTPUT
2468 */
2469 #define PORB_VCO_LOGIC (1 << 6) /* PORb VCO Logic */
2470 #define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0) /* VCO Output Level<3:0> */
2471 
2472 /*
2473 * REG_TX_CP_CURRENT
2474 */
2475 #define TX_CP_CURRENT_DFLT (1 << 7) /* Set to 1 */
2476 #define VTUNE_FORCE (1 << 6) /* Vtune Force */
2477 #define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */
2478 
2479 /*
2480 * REG_TX_CP_OFFSET
2481 */
2482 #define SYNTH_RECAL (1 << 7) /* Synth Re-Cal */
2483 #define CHARGE_PUMP_OFFSET(x) (((x) & 0x3F) << 0) /* Charge Pump Offset<5:0> */
2484 
2485 /*
2486 * REG_TX_CP_CONFIG
2487 */
2488 #define HALF_VCO_CAL_CLK (1 << 7) /* Half Vco Cal Clk */
2489 #define DITHER_MODE (1 << 6) /* Dither Mode */
2490 #define CP_OFFSET_OFF (1 << 4) /* Cp Offset Off */
2491 #define F_CPCAL (1 << 3) /* F Cpcal */
2492 #define CP_CAL_ENABLE (1 << 2) /* Cp Cal Enable */
2493 #define CP_TEST(x) (((x) & 0x3) << 0) /* Cp Test <1:0> */
2494 
2495 /*
2496 * REG_TX_LOOP_FILTER_1
2497 */
2498 #define LOOP_FILTER_C2(x) (((x) & 0xF) << 4) /* Loop Filter C2<3:0> */
2499 #define LOOP_FILTER_C1(x) (((x) & 0xF) << 0) /* Loop Filter C1<3:0> */
2500 
2501 /*
2502 * REG_TX_LOOP_FILTER_2
2503 */
2504 #define LOOP_FILTER_R1(x) (((x) & 0xF) << 4) /* Loop Filter R1<3:0> */
2505 #define LOOP_FILTER_C3(x) (((x) & 0xF) << 0) /* Loop Filter C3<3:0> */
2506 
2507 /*
2508 * REG_TX_LOOP_FILTER_3
2509 */
2510 #define LOOP_FILTER_BYPASS_R3 (1 << 7) /* Loop Filter Bypass R3 */
2511 #define LOOP_FILTER_BYPASS_R1 (1 << 6) /* Loop Filter Bypass R1 */
2512 #define LOOP_FILTER_BYPASS_C2 (1 << 5) /* Loop Filter Bypass C2 */
2513 #define LOOP_FILTER_BYPASS_C1 (1 << 4) /* Loop Filter Bypass C1 */
2514 #define LOOP_FILTER_R3(x) (((x) & 0xF) << 0) /* Loop Filter R3<3:0> */
2515 
2516 /*
2517 * REG_TX_DITHERCP_CAL
2518 */
2519 #define NUMBER_SDM_DITHER_BITS(x) (((x) & 0xF) << 4) /* Number SDM Dither Bits<3:0> */
2520 #define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */
2521 
2522 /*
2523 * REG_TX_VCO_BIAS_1
2524 */
2525 #define MUST_BE_ZEROS(x) (((x) & 0x3) << 5) /* Must be zeros */
2526 #define VCO_BIAS_TCF(x) (((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */
2527 #define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */
2528 
2529 /*
2530 * REG_TX_VCO_BIAS_2
2531 */
2532 #define VCO_BYPASS_BIAS_DAC_R (1 << 7) /* VCO Bypass Bias DAC R */
2533 #define VCO_COMP_BYPASS_BIAS_R (1 << 4) /* VCO Comp Bypass Bias R */
2534 #define BYPASS_PRESCALE_R (1 << 3) /* Bypass Prescale R */
2535 #define LAST_ALC_ENABLE (1 << 2) /* Last ALC Enable */
2536 #define PRESCALE_BIAS(x) (((x) & 0x3) << 0) /* Prescale Bias <1:0> */
2537 
2538 /*
2539 * REG_TX_CAL_STATUS
2540 */
2541 #define CP_CAL_VALID (1 << 7) /* CP Cal Valid */
2542 #define COMP_OUT (1 << 6) /* Comp Out */
2543 #define CP_CAL_DONE (1 << 5) /* CP Cal Done */
2544 #define VCO_CAL_BUSY (1 << 4) /* VCO Cal Busy */
2545 #define CP_CAL_WORD(x) (((x) & 0xF) << 0) /* CP Cal Word<3:0> */
2546 
2547 /*
2548 * REG_TX_VCO_CAL_REF
2549 */
2550 #define VCO_CAL_REF_MONITOR (1 << 3) /* VCO Cal Ref Monitor */
2551 #define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */
2552 
2553 /*
2554 * REG_TX_VCO_PD_OVERRIDES
2555 */
2556 #define POWER_DOWN_VARACTOR_REF (1 << 3) /* Power Down Varactor Ref */
2557 #define POWER_DOWN_VARACT_REF_TCF (1 << 2) /* Power Down Varact Ref Tcf */
2558 #define POWER_DOWN_CAL_TCF (1 << 1) /* Power Down Cal Tcf */
2559 #define POWER_DOWN_VCO_BUFFFER (1 << 0) /* Power Down VCO Bufffer */
2560 
2561 /*
2562 * REG_TX_CP_OVERRANGE_VCO_LOCK
2563 */
2564 #define CP_OVRG_HIGH (1 << 7) /* CP Ovrg High */
2565 #define CP_OVRG_LOW (1 << 6) /* CP Ovrg Low */
2566 #define VCO_LOCK (1 << 1) /* Lock */
2567 
2568 /*
2569 * REG_TX_VCO_LDO
2570 */
2571 #define VCO_LDO_BYPASS (1 << 7) /* VCO LDO Bypass */
2572 #define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */
2573 #define VCO_LDO_VOUT_SEL(x) (((x) & 0x7) << 2) /* VCO LDO Vout Sel<2:0> */
2574 #define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */
2575 
2576 /*
2577 * REG_TX_VCO_CAL
2578 */
2579 #define VCO_CAL_EN (1 << 7) /* VCO Cal En */
2580 #define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4) /* VCO Cal ALC Wait<2:0) */
2581 #define VCO_CAL_COUNT(x) (((x) & 0x3) << 2) /* VCO Cal Count<1:0> */
2582 #define FB_CLOCK_ADV(x) (((x) & 0x3) << 0) /* FB Clock Adv<1:0> */
2583 
2584 /*
2585 * REG_TX_LOCK_DETECT_CONFIG
2586 */
2587 #define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2) /* Lock Detect Count<1:0> */
2588 #define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */
2589 
2590 /*
2591 * REG_TX_CP_LEVEL_DETECT
2592 */
2593 #define CP_LEVEL_DETECT_POWER_DOWN (1 << 6) /* CP Level Detect Power Down */
2594 #define CP_LEVEL_DETECT_THRESH_LOW(x) (((x) & 0x7) << 3) /* CP Level Detect Threshold Low<2:0> */
2595 #define CP_LEVEL_DETECT_THRESH_HIGH(x) (((x) & 0x7) << 0) /* CP Level Detect Threshold High<2:0> */
2596 
2597 /*
2598 * REG_TX_DSM_SETUP_0
2599 */
2600 #define DSM_PROG(x) (((x) & 0xF) << 0) /* DSM Prog<3:0> */
2601 
2602 /*
2603 * REG_TX_DSM_SETUP_1
2604 */
2605 #define SIF_CLOCK (1 << 6) /* SIF clock */
2606 #define SIF_RESET_BAR (1 << 5) /* SIF Reset Bar */
2607 #define SIF_ADDR(x) (((x) & 0x1F) << 0) /* SIF Addr<4:0> */
2608 
2609 /*
2610 * REG_TX_CORRECTION_WORD0
2611 */
2612 #define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2613 #define READ_EFFECTIVE_TUNING_WORD (1 << 5) /* Read Effective Tuning Word */
2614 #define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */
2615 
2616 /*
2617 * REG_TX_CORRECTION_WORD1
2618 */
2619 #define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2620 #define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */
2621 
2622 /*
2623 * REG_TX_VCO_VARACTOR_CTRL_0
2624 */
2625 #define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */
2626 #define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */
2627 
2628 /*
2629 * REG_TX_VCO_VARACTOR_CTRL_1
2630 */
2631 #define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */
2632 
2633 /*
2634 * REG_DCXO_COARSE_TUNE
2635 */
2636 #define DCXO_TUNE_COARSE(x) (((x) & 0x3F) << 0) /* DCXO Tune Coarse<5:0> */
2637 
2638 /*
2639 * REG_DCXO_FINE_TUNE_LOW
2640 */
2641 #define DCXO_TUNE_FINE_LOW(x) (((x) & 0x1F) << 3) /* DCXO Tune Fine<4:0> */
2642 
2643 /*
2644 * REG_DCXO_FINE_TUNE_HIGH
2645 */
2646 #define DCXO_TUNE_FINE_HIGH(x) ((x) >> 5) /* DCXO Tune Fine<12:5> */
2647 
2648 /*
2649 * REG_DCXO_CONFIG
2650 */
2651 #define MUST_BE_ZERO (1 << 7) /* Must be zero */
2652 #define DCXO_RTAIL(x) (((x) & 0x7) << 4) /* DCXO Rtail<2:0> */
2653 #define DCXO_RD(x) (((x) & 0x3) << 2) /* DCXO Rd<1:0> */
2654 
2655 /*
2656 * REG_DCXO_TEMPCO_ADDR
2657 */
2658 #define DCXO_TEMPCO_EN (1 << 7) /* DCXO Tempco En */
2659 #define DCXO_TEMPCO_CLK (1 << 6) /* DCXO Tempco Clk */
2660 #define DCXO_TEMPERATURE_COEF_ADDRESS(x) (((x) & 0x3F) << 0) /* DCXO Temperature Coefficient Address<5:0> */
2661 
2662 /*
2663 * REG_TX_FAST_LOCK_SETUP
2664 */
2665 #define TX_FAST_LOCK_LOAD_SYNTH (1 << 3) /* Tx Fast Lock Load Synth */
2666 #define TX_FAST_LOCK_PROFILE_INIT (1 << 2) /* Tx Fast Lock Profile Init */
2667 #define TX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1) /* Tx Fast Lock Profile Pin Select */
2668 #define TX_FAST_LOCK_MODE_ENABLE (1 << 0) /* Tx Fast Lock Mode Enable */
2669 #define TX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5) /* Tx Fast Lock Profile<2:0> */
2670 
2671 /*
2672 * REG_TX_FAST_LOCK_PROGRAM_CTRL
2673 */
2674 #define TX_FAST_LOCK_PROGRAM_WRITE (1 << 1) /* Tx Fast Lock Program Write */
2675 #define TX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0) /* Tx Fast Lock Program Clock Enable */
2676 
2677 /*
2678 * REG_TX_LO_GEN_POWER_MODE
2679 */
2680 #define TX_LO_GEN_POWER_MODE(x) (((x) & 0xF) << 4) /* Power Mode<3:0> */
2681 
2682 /*
2683 * REG_BANDGAP_CONFIG0
2684 */
2685 #define POWER_DOWN_BANDGAP_REF (1 << 7) /* Power Down Bandgap Ref */
2686 #define MASTER_BIAS_FILTER_BYPASS (1 << 6) /* Master Bias Filter Bypass */
2687 #define MASTER_BIAS_REF_SEL (1 << 5) /* Master Bias Ref Sel */
2688 #define MASTER_BIAS_TRIM(x) (((x) & 0x1F) << 0) /* Master Bias Trim<4:0> */
2689 
2690 /*
2691 * REG_BANDGAP_CONFIG1
2692 */
2693 #define VCO_LDO_FILTER_BYPASS (1 << 7) /* VCO LDO Filter Bypass */
2694 #define VCO_LDO_REF_SEL (1 << 6) /* VCO LDO Ref Sel */
2695 #define BANDGAP_REF_RESET (1 << 5) /* Bandgap Ref Reset */
2696 #define BANDGAP_TEMP_TRIM(x) (((x) & 0x1F) << 0) /* Bandgap Temp Trim<4:0> */
2697 
2698 /*
2699 * REG_REF_DIVIDE_CONFIG_1
2700 */
2701 #define REF_DIVIDE_CONFIG_1_DFLT (1 << 2) /* Set to 1 */
2702 #define RX_REF_RESET_BAR (1 << 1) /* Rx Ref Reset Bar */
2703 #define RX_REF_DIVIDER_MSB (1 << 0) /* Rx Ref Divider<1> */
2704 
2705 /*
2706 * REG_REF_DIVIDE_CONFIG_2
2707 */
2708 #define RX_REF_DIVIDER_LSB (1 << 7) /* Rx Ref Divider< 0> */
2709 #define TX_REF_RESET_BAR (1 << 4) /* Tx Ref Reset Bar */
2710 #define RX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 5) /* Rx Ref Doubler FB Delay<1:0> */
2711 #define TX_REF_DIVIDER(x) (((x) & 0x3) << 2) /* Tx Ref Divider<1:0> */
2712 #define TX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 0) /* Tx Ref Doubler FB Delay<1:0> */
2713 
2714 /*
2715 * REG_GAIN_RX1,2
2716 */
2717 #define FULL_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Full Table Gain Index Rx1/LMT Gain Rx1<6:0> */
2718 
2719 /*
2720 * REG_LPF_GAIN_RX1,2
2721 */
2722 #define LPF_GAIN_RX(x) (((x) & 0x1F) << 0) /* LPF gain Rx1<4:0> */
2723 
2724 /*
2725 * REG_DIG_GAIN_RX1,2
2726 */
2727 #define DIGITAL_GAIN_RX(x) (((x) & 0x1F) << 0) /* Digital gain Rx1<4:0> */
2728 
2729 /*
2730 * REG_FAST_ATTACK_STATE
2731 */
2732 #define FAST_ATTACK_STATE_RX2(x) (((x) & 0x7) << 4) /* Fast Attack State Rx2<2:0> */
2733 #define FAST_ATTACK_STATE_RX1(x) (((x) & 0x7) << 0) /* Fast Attack State Rx1<2:0> */
2734 #define FAST_ATK_MASK 0x7
2735 #define RX1_FAST_ATK_SHIFT 0
2736 #define RX2_FAST_ATK_SHIFT 4
2737 #define FAST_ATK_RESET 0
2738 #define FAST_ATK_PEAK_DETECT 1
2739 #define FAST_ATK_PWR_MEASURE 2
2740 #define FAST_ATK_FINAL_SETTELING 3
2741 #define FAST_ATK_FINAL_OVER 4
2742 #define FAST_ATK_GAIN_LOCKED 5
2743 
2744 /*
2745 * REG_SLOW_LOOP_STATE
2746 */
2747 #define SLOW_LOOP_STATE_RX2(x) (((x) & 0x7) << 4) /* Slow Loop State Rx2<2:0> */
2748 #define SLOW_LOOP_STATE_RX1(x) (((x) & 0x7) << 0) /* Slow Loop State Rx1<2:0> */
2749 
2750 
2751 /*
2752 * REG_OVRG_SIGS_RX1,2
2753 */
2754 #define GAIN_LOCK_1 (1 << 6) /* Gain Lock 1 */
2755 #define LOW_POWER_1 (1 << 5) /* Low Power 1 */
2756 #define LARGE_LMT_OL (1 << 4) /* Large LMT OL */
2757 #define SMALL_LMT_OL (1 << 3) /* Small LMT OL */
2758 #define LARGE_ADC_OL (1 << 2) /* Large ADC OL */
2759 #define SMALL_ADC_OL (1 << 1) /* Small ADC OL */
2760 #define DIG_SAT (1 << 0) /* Dig Sat */
2761 /*
2762 * REG_CTRL
2763 */
2764 #define CTRL_ENABLE (1 << 0) /* Set to 1 */
2765 
2766 /*
2767 * REG_BIST_CONFIG
2768 */
2769 #define TONE_PRBS (1 << 1) /* Tone/ PRBS */
2770 #define BIST_ENABLE (1 << 0) /* BIST Enable */
2771 #define TONE_FREQ(x) (((x) & 0x3) << 6) /* Tone Frequency<1:0> */
2772 #define TONE_LEVEL(x) (((x) & 0x3) << 4) /* Tone Level<1:0> */
2773 #define BIST_CTRL_POINT(x) (((x) & 0x3) << 2) /* BIST Control Point <1:0> */
2774 
2775 /*
2776 * REG_OBSERVE_CONFIG
2777 */
2778 #define DATA_PORT_SP_HD_LOOP_TEST_OE (1 << 7) /* Data Port SP, HD Loop Test OE */
2779 #define RX_MASK (1 << 6) /* Rx Mask */
2780 #define CHANNEL (1 << 5) /* Channel */
2781 #define DATA_PORT_LOOP_TEST_ENABLE (1 << 0) /* Data Port Loop Test Enable */
2782 #define OBSERVATION_POINT(x) (((x) & 0xF) << 1) /* Observation Point<2:0> */
2783 
2784 /*
2785 * REG_BIST_AND_DATA_PORT_TEST_CONFIG
2786 */
2787 #define BIST_MASK_CHANNEL_2_Q_DATA (1 << 5) /* BIST Mask Channel 2 Q data */
2788 #define BIST_MASK_CHANNEL_2_I_DATA (1 << 4) /* BIST Mask Channel 2 I data */
2789 #define BIST_MASK_CHANNEL_1_Q_DATA (1 << 3) /* BIST Mask Channel 1 Q data */
2790 #define BIST_MASK_CHANNEL_1_I_DATA (1 << 2) /* BIST Mask Channel 1 I data */
2791 #define DATA_PORT_HILOW (1 << 1) /* Data Port Hi/Low */
2792 #define USE_DATA_PORT (1 << 0) /* Use Data Port */
2793 #define TEMP_SENSE_VBE_TEST(x) (((x) & 0x3) << 6) /* Temp Sense Vbe Test<1:0> */
2794 
2795 /*
2796 * REG_DAC_TEST_2
2797 */
2798 #define DAC_TEST_ENABLE (1 << 7) /* DAC Test Enable */
2799 #define DAC_TEST_WORD(x) (((x) & 0x7F) << 0) /* DAC test Word <22:16> */
2800 
2801 /*
2802 * SPI Comm Helpers
2803 */
2804 #define AD_READ (0 << 15)
2805 #define AD_WRITE (1 << 15)
2806 #define AD_CNT(x) ((((x) - 1) & 0x7) << 12)
2807 #define AD_ADDR(x) ((x) & 0x3FF)
2808 
2809 
2810 /*
2811 * AD9361 Limits
2812 */
2813 
2814 #define RSSI_MULTIPLIER 100
2815 #define RSSI_RESOLUTION ((int) (0.25 * RSSI_MULTIPLIER))
2816 #define RSSI_MAX_WEIGHT 255
2817 
2818 #define MAX_LMT_INDEX 40
2819 #define MAX_LPF_GAIN 24
2820 #define MAX_DIG_GAIN 31
2821 
2822 #define MAX_BBPLL_FREF 70007000UL /* 70 MHz + 100ppm */
2823 #define MIN_BBPLL_FREQ 714928500UL /* 715 MHz - 100ppm */
2824 #define MAX_BBPLL_FREQ 1430143000UL /* 1430 MHz + 100ppm */
2825 #define MAX_BBPLL_DIV 64
2826 #define MIN_BBPLL_DIV 2
2827 
2828 /*
2829  * The ADC minimum and maximum operating output data rates
2830  * are 25MHz and 640MHz respectively.
2831  * For more information see here: https://ez.analog.com/docs/DOC-12763
2832  */
2833 
2834 #define MIN_ADC_CLK 25000000U /* 25 MHz */
2835 //#define MIN_ADC_CLK (MIN_BBPLL_FREQ / MAX_BBPLL_DIV) /* 11.17MHz */
2836 #define MAX_ADC_CLK 640000000U /* 640 MHz */
2837 #define MAX_DAC_CLK (MAX_ADC_CLK / 2)
2838 
2839 /* Associated with outputs of stage */
2840 #define MAX_RX_HB1 245760000UL
2841 #define MAX_RX_HB2 320000000UL
2842 #define MAX_RX_HB3 640000000UL
2843 /* Associated with inputs of stage */
2844 #define MAX_TX_HB1 160000000UL
2845 #define MAX_TX_HB2 320000000UL
2846 #define MAX_TX_HB3 320000000UL
2847 
2848 #define MAX_BASEBAND_RATE 61440000UL
2849 
2850 #define MAX_MBYTE_SPI 8
2851 
2852 #define RFPLL_MODULUS 8388593UL
2853 #define BBPLL_MODULUS 2088960UL
2854 
2855 #define MAX_SYNTH_FREF 80008000UL /* 80 MHz + 100ppm */
2856 #define MIN_SYNTH_FREF 9999000UL /* 10 MHz - 100ppm */
2857 #define MIN_VCO_FREQ_HZ 6000000000ULL
2858 #define MAX_CARRIER_FREQ_HZ 6000000000ULL
2859 #define MIN_RX_CARRIER_FREQ_HZ 70000000ULL
2860 #define MIN_TX_CARRIER_FREQ_HZ 46875001ULL
2861 
2862 #define AD9363A_MAX_CARRIER_FREQ_HZ 3800000000ULL
2863 #define AD9363A_MIN_CARRIER_FREQ_HZ 325000000ULL
2864 
2865 #define MAX_TX_ATTENUATION_DB 89750
2866 
2867 /*
2868 * Driver
2869 */
2870 
2874 };
2875 
2881 };
2882 
2884  uint64_t start;
2885  uint64_t end;
2886  uint8_t max_index;
2887  uint8_t split_table;
2888  int8_t *abs_gain_tbl;
2889  uint8_t (*tab)[3];
2890 };
2891 
2892 enum fir_dest {
2893  FIR_TX1 = 0x01,
2894  FIR_TX2 = 0x02,
2895  FIR_TX1_TX2 = 0x03,
2896  FIR_RX1 = 0x81,
2897  FIR_RX2 = 0x82,
2898  FIR_RX1_RX2 = 0x83,
2899  FIR_IS_RX = 0x80,
2900 };
2901 
2903  uint32_t ant;
2904  uint8_t mode;
2905 };
2906 
2912 };
2913 
2919 };
2920 
2924 
2925  /* Common */
2926  uint8_t adc_ovr_sample_size; /* 1..8 Sum x samples, AGC_CONFIG_3 */
2927  uint8_t adc_small_overload_thresh; /* 0..255, 0x105 */
2928  uint8_t adc_large_overload_thresh; /* 0..255, 0x104 */
2929 
2930  uint16_t lmt_overload_high_thresh; /* 16..800 mV, 0x107 */
2931  uint16_t lmt_overload_low_thresh; /* 16..800 mV, 0x108 */
2932  uint16_t dec_pow_measuremnt_duration; /* Samples, 0x15C */
2933  uint8_t low_power_thresh; /* -64..0 dBFS, 0x114 */
2934  bool use_rx_fir_out_for_dec_pwr_meas; /* clears 0x15C:6 USE_HB1_OUT_FOR_DEC_PWR_MEAS */
2935 
2936  bool dig_gain_en; /* should be turned off, since ADI GT doesn't use dig gain */
2937  uint8_t max_dig_gain; /* 0..31 */
2938 
2939  /* MGC */
2940  bool mgc_rx1_ctrl_inp_en; /* Enables Pin control on RX1 default SPI ctrl */
2941  bool mgc_rx2_ctrl_inp_en; /* Enables Pin control on RX2 default SPI ctrl */
2942 
2943  uint8_t mgc_inc_gain_step; /* 1..8 */
2944  uint8_t mgc_dec_gain_step; /* 1..8 */
2945  uint8_t mgc_split_table_ctrl_inp_gain_mode; /* 0=AGC determine this, 1=only in LPF, 2=only in LMT */
2946 
2947  /* AGC */
2948  uint8_t agc_attack_delay_extra_margin_us; /* 0..31 us */
2949 
2958 
2959  uint8_t adc_small_overload_exceed_counter; /* 0..15, 0x122 */
2960  uint8_t adc_large_overload_exceed_counter; /* 0..15, 0x122 */
2961  uint8_t adc_large_overload_inc_steps; /* 0..15, 0x106 */
2962 
2964 
2965  uint8_t lmt_overload_large_exceed_counter; /* 0..15, 0x121 */
2966  uint8_t lmt_overload_small_exceed_counter; /* 0..15, 0x121 */
2967  uint8_t lmt_overload_large_inc_steps; /* 0..7, 0x121 */
2968 
2969  uint8_t dig_saturation_exceed_counter; /* 0..15, 0x128 */
2970  uint8_t dig_gain_step_size; /* 1..8, 0x100 */
2971  bool sync_for_gain_counter_en; /* 0x128:4 !Hybrid */
2972 
2973  uint32_t gain_update_interval_us; /* in us */
2976 
2977  /*
2978  * Fast AGC
2979  */
2980  uint32_t f_agc_dec_pow_measuremnt_duration; /* Samples, 0x15C */
2981  uint32_t f_agc_state_wait_time_ns; /* 0x117 0..31 RX samples -> time_ns */
2982  /* Fast AGC - Low Power */
2983  bool f_agc_allow_agc_gain_increase; /* 0x110:1 */
2984  uint8_t f_agc_lp_thresh_increment_time; /* 0x11B RX samples */
2985  uint8_t f_agc_lp_thresh_increment_steps; /* 0x117 1..8 */
2986 
2987  /* Fast AGC - Lock Level */
2988  uint8_t f_agc_lock_level; /* NOT USED: 0x101 0..-127 dBFS same as agc_inner_thresh_high */
2991  /* Fast AGC - Peak Detectors and Final Settling */
2992  uint8_t f_agc_lpf_final_settling_steps; /* 0x112:6 0..3 (Post Lock Level Step)*/
2993  uint8_t f_agc_lmt_final_settling_steps; /* 0x113:6 0..3 (Post Lock Level Step)*/
2994  uint8_t f_agc_final_overrange_count; /* 0x116:5 0..7 */
2995  /* Fast AGC - Final Power Test */
2997  /* Fast AGC - Unlocking the Gain */
2998  /* 0 = MAX Gain, 1 = Set Gain, 2 = Optimized Gain */
3000  f_agc_gain_index_type_after_exit_rx_mode; /* 0x110:[4,2] */
3002  uint8_t f_agc_optimized_gain_offset; /*0x116 0..15 steps */
3004  uint8_t f_agc_rst_gla_stronger_sig_thresh_above_ll; /*0x113 0..63 dbFS */
3008  uint8_t f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* 0x119 0..63 RX samples */
3009  bool f_agc_rst_gla_large_adc_overload_en; /*0x110:~1 and 0x114:~7 */
3012  /* 0 = Max Gain, 1 = Set Gain, 2 = Optimized Gain, 3 = No Gain Change */
3013 
3015  f_agc_rst_gla_if_en_agc_pulled_high_mode; /* 0x0FB, 0x111 */
3016  uint8_t f_agc_power_measurement_duration_in_state5; /* 0x109, 0x10a RX samples 0..524288*/
3017  uint8_t f_agc_large_overload_inc_steps; /* 0x106 [D6:D4] 0..7 */
3018 };
3019 
3023 
3025 
3029 
3033 
3038 };
3039 
3047 };
3048 
3051  bool rssi_unit_is_rx_samples; /* default unit is time */
3052  uint32_t rssi_delay;
3053  uint32_t rssi_wait;
3054  uint32_t rssi_duration;
3055 };
3056 
3060  int32_t max_gain_db;
3061  int32_t gain_step_db;
3062  int32_t max_idx;
3064 };
3065 
3067  uint8_t pp_conf[3];
3072  uint8_t lvds_invert[2];
3073 };
3074 
3076  uint8_t index;
3077  uint8_t en_mask;
3078 };
3079 
3081  uint16_t gain_mdB;
3084  bool elna_1_control_en; /* GPO0 */
3085  bool elna_2_control_en; /* GPO1 */
3087 };
3088 
3090  int8_t offset;
3096 };
3097 
3098 struct gpo_control {
3121 };
3122 
3127  uint8_t low_gain_dB;
3128  uint8_t high_gain_dB;
3129  uint16_t tx_mon_delay;
3133  uint8_t tx1_mon_lo_cm;
3134  uint8_t tx2_mon_lo_cm;
3135 };
3136 
3145 };
3146 
3155 };
3156 
3165 };
3166 
3168  bool rx2tx2;
3169  bool fdd;
3171  bool split_gt;
3190  uint32_t dcxo_coarse;
3191  uint32_t dcxo_fine;
3199  uint64_t rx_synth_freq;
3200  uint64_t tx_synth_freq;
3203  int32_t tx_atten;
3208 
3210 
3220 };
3221 
3222 struct rf_rx_gain {
3223  uint32_t ant; /* Antenna number to read gain */
3224  int32_t gain_db; /* gain value in dB */
3225  uint32_t fgt_lmt_index; /* Full Gain Table / LNA-MIXER-TIA gain index */
3226  uint32_t lmt_gain; /* LNA-MIXER-TIA gain in dB (Split GT mode only)*/
3227  uint32_t lpf_gain; /* Low pass filter gain in dB / index (Split GT mode only)*/
3228  uint32_t digital_gain; /* Digital gain in dB / index */
3229  /* Debug only */
3230  uint32_t lna_index; /* LNA Index (Split GT mode only) */
3231  uint32_t tia_index; /* TIA Index (Split GT mode only) */
3232  uint32_t mixer_index; /* MIXER Index (Split GT mode only) */
3233 
3234 };
3235 struct rf_rssi {
3236  uint32_t ant; /* Antenna number for which RSSI is reported */
3237  uint32_t symbol; /* Runtime RSSI */
3238  uint32_t preamble; /* Initial RSSI */
3239  int32_t multiplier; /* Multiplier to convert reported RSSI */
3240  uint8_t duration; /* Duration to be considered for measuring */
3241 };
3242 
3243 struct SynthLUT {
3244  uint16_t VCO_MHz;
3246  uint8_t VCO_Varactor;
3247  uint8_t VCO_Bias_Ref;
3248  uint8_t VCO_Bias_Tcf;
3252  uint8_t LF_C2;
3253  uint8_t LF_C1;
3254  uint8_t LF_R1;
3255  uint8_t LF_C3;
3256  uint8_t LF_R3;
3257 };
3258 
3259 enum {
3264 };
3265 
3289 };
3290 
3293  const char *propname;
3294  void *out_value;
3295  uint32_t val;
3296  uint8_t size;
3297  uint8_t cmd;
3298 };
3299 
3301 #define FASTLOOK_INIT 1
3302  uint8_t flags;
3303  uint8_t alc_orig;
3304  uint8_t alc_written;
3305 };
3306 
3308  uint8_t save_profile;
3309  uint8_t current_profile[2];
3311 };
3312 
3320 };
3321 
3326 };
3327 
3332 };
3333 
3334 enum dev_id {
3338 };
3339 
3347 #ifndef AXI_ADC_NOT_PRESENT
3348  struct axi_adc *rx_adc;
3349  struct axi_dac *tx_dac;
3350 #endif
3354  uint32_t (*ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv);
3355  int32_t (*ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv,
3356  uint32_t rate);
3357  int32_t (*ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv,
3358  uint32_t rate);
3364  uint8_t cached_synth_pd[2];
3366  uint32_t current_table;
3369 
3380  uint32_t flags;
3384  uint32_t rxbbf_div;
3385  uint32_t rate_governor;
3392  uint32_t filt_rx_bw_Hz;
3393  uint32_t filt_tx_bw_Hz;
3394  uint8_t tx_fir_int;
3395  uint8_t tx_fir_ntaps;
3396  uint8_t rx_fir_dec;
3397  uint8_t rx_fir_ntaps;
3398  uint8_t agc_mode[2];
3403  uint16_t auxdac1_value;
3404  uint16_t auxdac2_value;
3411  int32_t bist_config;
3416  uint32_t bist_tone_mask;
3418 };
3419 
3423  uint32_t mult;
3424  uint32_t div;
3427 };
3428 
3438 };
3439 
3440 /******************************************************************************/
3441 /************************ Functions Declarations ******************************/
3442 /******************************************************************************/
3443 int32_t ad9361_spi_readm(struct no_os_spi_desc *spi, uint32_t reg,
3444  uint8_t *rbuf, uint32_t num);
3445 int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg);
3446 int32_t ad9361_spi_write(struct no_os_spi_desc *spi,
3447  uint32_t reg, uint32_t val);
3448 int32_t ad9361_reset(struct ad9361_rf_phy *phy);
3449 int32_t ad9361_register_clocks(struct ad9361_rf_phy *phy);
3450 int32_t ad9361_unregister_clocks(struct ad9361_rf_phy *phy);
3451 uint32_t ad9361_gt(struct ad9361_rf_phy *phy);
3452 int32_t ad9361_init_gain_tables(struct ad9361_rf_phy *phy);
3453 int32_t ad9361_setup(struct ad9361_rf_phy *phy);
3454 int32_t ad9361_post_setup(struct ad9361_rf_phy *phy);
3455 int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl);
3456 int32_t ad9361_ensm_set_state(struct ad9361_rf_phy *phy, uint8_t ensm_state,
3457  bool pinctrl);
3458 int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy,
3459  uint32_t rx_id, struct rf_rx_gain *rx_gain);
3460 int32_t ad9361_get_rx_gain(struct ad9361_rf_phy *phy,
3461  uint32_t rx_id, struct rf_rx_gain *rx_gain);
3462 int32_t ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,
3463  uint32_t rf_rx_bw, uint32_t rf_tx_bw);
3465  uint32_t tx_sample_rate,
3466  uint32_t rate_gov,
3467  uint32_t *rx_path_clks,
3468  uint32_t *tx_path_clks);
3469 int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy,
3470  uint32_t *rx_path_clks,
3471  uint32_t *tx_path_clks);
3472 int32_t ad9361_get_trx_clock_chain(struct ad9361_rf_phy *phy,
3473  uint32_t *rx_path_clks,
3474  uint32_t *tx_path_clks);
3475 uint32_t ad9361_to_clk(uint64_t freq);
3476 uint64_t ad9361_from_clk(uint32_t freq);
3477 int32_t ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi);
3478 int32_t ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy,
3479  struct rf_gain_ctrl *gain_ctrl);
3480 int32_t ad9361_load_fir_filter_coef(struct ad9361_rf_phy *phy,
3481  enum fir_dest dest, int32_t gain_dB,
3482  uint32_t ntaps, short *coef);
3483 int32_t ad9361_validate_enable_fir(struct ad9361_rf_phy *phy);
3484 int32_t ad9361_set_tx_atten(struct ad9361_rf_phy *phy, uint32_t atten_mdb,
3485  bool tx1, bool tx2, bool immed);
3486 int32_t ad9361_get_tx_atten(struct ad9361_rf_phy *phy, uint32_t tx_num);
3487 uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv,
3488  uint32_t parent_rate);
3489 int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv,
3490  uint32_t rate,
3491  uint32_t *prate);
3492 int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate,
3493  uint32_t parent_rate);
3494 uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv,
3495  uint32_t parent_rate);
3496 int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate,
3497  uint32_t *prate);
3498 int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate,
3499  uint32_t parent_rate);
3500 uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv,
3501  uint32_t parent_rate);
3502 int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv,
3503  uint32_t rate,
3504  uint32_t *prate);
3505 int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate,
3506  uint32_t parent_rate);
3507 uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv);
3508 int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv,
3509  uint32_t rate);
3510 uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv);
3511 int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate);
3512 int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate);
3513 int32_t ad9361_clk_mux_set_parent(struct refclk_scale *clk_priv, uint8_t index);
3514 int32_t ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track,
3515  bool rfdc_track, bool rxquad_track);
3516 int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode);
3517 void ad9361_get_bist_loopback(struct ad9361_rf_phy *phy, int32_t *mode);
3518 int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode);
3519 void ad9361_get_bist_prbs(struct ad9361_rf_phy *phy,
3520  enum ad9361_bist_mode *mode);
3521 int32_t ad9361_bist_tone(struct ad9361_rf_phy *phy,
3522  enum ad9361_bist_mode mode, uint32_t freq_Hz,
3523  uint32_t level_dB, uint32_t mask);
3524 void ad9361_get_bist_tone(struct ad9361_rf_phy *phy,
3525  enum ad9361_bist_mode *mode, uint32_t *freq_Hz,
3526  uint32_t *level_dB, uint32_t *mask);
3527 int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out,
3528  uint32_t rx_inputs, uint32_t txb);
3529 int32_t ad9361_mcs(struct ad9361_rf_phy *phy, int32_t step);
3530 int32_t ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal,
3531  int32_t arg);
3532 int32_t ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx,
3533  uint32_t profile);
3534 int32_t ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx,
3535  uint32_t profile);
3536 int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx,
3537  uint32_t profile, uint8_t *values);
3538 int32_t ad9361_fastlock_save(struct ad9361_rf_phy *phy, bool tx,
3539  uint32_t profile, uint8_t *values);
3540 void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state);
3541 uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy);
3542 void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state);
3545  uint32_t freq);
3546 int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start);
3547 int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable);
3549  char *buf, int32_t buflen);
3550 int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq,
3551  enum dig_tune_flags flags);
3552 int32_t ad9361_en_dis_tx(struct ad9361_rf_phy *phy, uint32_t tx_if,
3553  uint32_t enable);
3554 int32_t ad9361_en_dis_rx(struct ad9361_rf_phy *phy, uint32_t rx_if,
3555  uint32_t enable);
3556 int32_t ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx,
3557  int32_t channel);
3558 int32_t ad9361_rssi_gain_step_calib(struct ad9361_rf_phy *phy);
3559 int32_t ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy,
3560  uint32_t coarse, uint32_t fine);
3561 int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state);
3562 uint32_t ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, uint32_t bw);
3563 int32_t ad9361_get_temp(struct ad9361_rf_phy *phy);
3565  enum synth_pd_ctrl rx,
3566  enum synth_pd_ctrl tx);
3567 void ad9361_clear_state(struct ad9361_rf_phy *phy);
3568 #endif
REG_GAIN_UPDATE_COUNTER2
#define REG_GAIN_UPDATE_COUNTER2
Definition: ad9361.h:263
REG_PREAMBLE_LSB
#define REG_PREAMBLE_LSB
Definition: ad9361.h:370
ad9361_spi_read
int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg)
Definition: ad9361.c:740
REG_GPO1_RX_DELAY
#define REG_GPO1_RX_DELAY
Definition: ad9361.h:91
ENABLE_BB_DC_OFFSET_TRACKING
#define ENABLE_BB_DC_OFFSET_TRACKING
Definition: ad9361.h:1871
gain_control::agc_inner_thresh_low
uint8_t agc_inner_thresh_low
Definition: ad9361.h:2954
RX_MIX_GM_PLOAD
#define RX_MIX_GM_PLOAD(x)
Definition: ad9361.h:1991
REG_AGC_INNER_LOW_THRESH
#define REG_AGC_INNER_LOW_THRESH
Definition: ad9361.h:258
REG_DIGITAL_SAT_COUNTER
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Definition: ad9361.h:264
TX2_MON_ENABLE
#define TX2_MON_ENABLE
Definition: ad9361.h:1057
RSSI_MULTIPLIER
#define RSSI_MULTIPLIER
Definition: ad9361.h:2814
ad9361_rf_port_setup
int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out, uint32_t rx_inputs, uint32_t txb)
Definition: ad9361.c:3609
port_control::lvds_bias_ctrl
uint8_t lvds_bias_ctrl
Definition: ad9361.h:3071
gpo_control::gpo3_slave_rx_en
bool gpo3_slave_rx_en
Definition: ad9361.h:3111
REG_GM_SUB_TABLE_CTRL_WRITE
#define REG_GM_SUB_TABLE_CTRL_WRITE
Definition: ad9361.h:280
AD_ADDR
#define AD_ADDR(x)
Definition: ad9361.h:2807
REG_TX_FILTER_COEF_READ_DATA_1
#define REG_TX_FILTER_COEF_READ_DATA_1
Definition: ad9361.h:139
DIG_GAIN_EN
#define DIG_GAIN_EN
Definition: ad9361.h:1366
REG_GPO_FORCE_AND_INIT
#define REG_GPO_FORCE_AND_INIT
Definition: ad9361.h:89
gain_control::lmt_overload_large_inc_steps
uint8_t lmt_overload_large_inc_steps
Definition: ad9361.h:2967
MAX_DIG_GAIN
#define MAX_DIG_GAIN
Definition: ad9361.h:2820
REG_RX_ENABLE_FILTER_CTRL
#define REG_RX_ENABLE_FILTER_CTRL
Definition: ad9361.h:54
RF_GAIN_HYBRID_AGC
@ RF_GAIN_HYBRID_AGC
Definition: ad9361.h:2911
rx_gain_info::tbl_type
enum rx_gain_table_type tbl_type
Definition: ad9361.h:3058
ENSM_STATE_SLEEP
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Definition: ad9361.h:770
REG_CTRL_OUTPUT_ENABLE
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Definition: ad9361.h:103
LOOP_FILTER_R1
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Definition: ad9361.h:2504
ad9361_validate_enable_fir
int32_t ad9361_validate_enable_fir(struct ad9361_rf_phy *phy)
Definition: ad9361.c:6055
gain_control::f_agc_rst_gla_large_lmt_overload_en
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Definition: ad9361.h:3010
gain_table_info::start
uint64_t start
Definition: ad9361.h:2884
ad9361_phy_platform_data::port_ctrl
struct port_control port_ctrl
Definition: ad9361.h:3213
REG_MAG_FTEST_THRESH
#define REG_MAG_FTEST_THRESH
Definition: ad9361.h:186
port_control::pp_conf
uint8_t pp_conf[3]
Definition: ad9361.h:3067
REG_AUXDAC_2_CONFIG
#define REG_AUXDAC_2_CONFIG
Definition: ad9361.h:77
ad9361_phy_platform_data::fdd_independent_mode
bool fdd_independent_mode
Definition: ad9361.h:3170
XO_BYPASS
#define XO_BYPASS
Definition: ad9361.h:650
refclk_scale::div
uint32_t div
Definition: ad9361.h:3424
REG_QUAD_CAL_STATUS_TX1
#define REG_QUAD_CAL_STATUS_TX1
Definition: ad9361.h:188
MIN_VCO_FREQ_HZ
#define MIN_VCO_FREQ_HZ
Definition: ad9361.h:2857
rf_rx_gain::fgt_lmt_index
uint32_t fgt_lmt_index
Definition: ad9361.h:3225
ad9361_rf_phy::bbdc_track_en
bool bbdc_track_en
Definition: ad9361.h:3400
POWER_DOWN_RX_SYNTH
#define POWER_DOWN_RX_SYNTH
Definition: ad9361.h:735
REG_RSSI_CONFIG
#define REG_RSSI_CONFIG
Definition: ad9361.h:303
ad9361_phy_platform_data::dc_offset_attenuation_high
uint8_t dc_offset_attenuation_high
Definition: ad9361.h:3183
TX_REF_DIVIDER
#define TX_REF_DIVIDER(x)
Definition: ad9361.h:2711
BB_REFCLK
@ BB_REFCLK
Definition: ad9361.h:3267
AUXDAC_INIT_BAR
#define AUXDAC_INIT_BAR(x)
Definition: ad9361.h:828
AGC_GAIN_UNLOCK_CTRL
#define AGC_GAIN_UNLOCK_CTRL
Definition: ad9361.h:1364
timeout
uint32_t timeout
Definition: ad413x.c:54
REG_RX_TIA_CONFIG
#define REG_RX_TIA_CONFIG
Definition: ad9361.h:396
REG_TX_ATTEN_OFFSET
#define REG_TX_ATTEN_OFFSET
Definition: ad9361.h:157
ad9361_fastlock_load
int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition: ad9361.c:4970
ENABLE_ENSM_PIN_CTRL
#define ENABLE_ENSM_PIN_CTRL
Definition: ad9361.h:725
RX_REF_DIVIDER_LSB
#define RX_REF_DIVIDER_LSB
Definition: ad9361.h:2708
axiadc_converter
Definition: ad9361_util.h:93
DUAL_SYNTH_MODE
#define DUAL_SYNTH_MODE
Definition: ad9361.h:739
TX_LO_GEN_POWER_MODE
#define TX_LO_GEN_POWER_MODE(x)
Definition: ad9361.h:2680
ENABLE_CORR_WORD_DECIMATION
#define ENABLE_CORR_WORD_DECIMATION
Definition: ad9361.h:1770
MANUAL_INCR_STEP_SIZE
#define MANUAL_INCR_STEP_SIZE(x)
Definition: ad9361.h:1375
DBGFS_BIST_DT_ANALYSIS
@ DBGFS_BIST_DT_ANALYSIS
Definition: ad9361.h:3435
no_os_min_t
#define no_os_min_t(type, x, y)
Definition: no_os_util.h:65
RX2_GAIN_CTRL_SETUP
#define RX2_GAIN_CTRL_SETUP(x)
Definition: ad9361.h:1350
REG_RX_BBF_C3_MSB
#define REG_RX_BBF_C3_MSB
Definition: ad9361.h:412
MAN_GAIN_CTRL_RX1
#define MAN_GAIN_CTRL_RX1
Definition: ad9361.h:1368
REG_VCO_PROGRAM_2
#define REG_VCO_PROGRAM_2
Definition: ad9361.h:123
ad9361_fastlock
Definition: ad9361.h:3307
ad9361_debugfs_entry
Definition: ad9361.h:3291
REG_RX_CAL_STATUS
#define REG_RX_CAL_STATUS
Definition: ad9361.h:485
ad9361_get_bist_prbs
void ad9361_get_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode)
Definition: ad9361.c:1187
elna_control::elna_2_control_en
bool elna_2_control_en
Definition: ad9361.h:3085
rx_gain_table_type
rx_gain_table_type
Definition: ad9361.h:2871
REG_EXT_LNA_HIGH_GAIN
#define REG_EXT_LNA_HIGH_GAIN
Definition: ad9361.h:267
ad9361_phy_platform_data::qec_tracking_slow_mode_en
bool qec_tracking_slow_mode_en
Definition: ad9361.h:3181
REG_RX_CP_OVERRANGE_VCO_LOCK
#define REG_RX_CP_OVERRANGE_VCO_LOCK
Definition: ad9361.h:488
ad9361_phy_platform_data::split_gt
bool split_gt
Definition: ad9361.h:3171
REG_FAST_LOW_POWER_THRESH
#define REG_FAST_LOW_POWER_THRESH
Definition: ad9361.h:250
GPO_MANUAL_SELECT
#define GPO_MANUAL_SELECT
Definition: ad9361.h:836
ad9361_rfpll_int_recalc_rate
uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6748
FAST_ATK_MASK
#define FAST_ATK_MASK
Definition: ad9361.h:2734
ad9361_get_rx_gain
int32_t ad9361_get_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition: ad9361.c:1882
BIST_MASK_CHANNEL_1_I_DATA
#define BIST_MASK_CHANNEL_1_I_DATA
Definition: ad9361.h:2790
ad9361_dig_tune
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, enum dig_tune_flags flags)
Definition: ad9361_conv.c:525
DOUBLE_GAIN_COUNTER
#define DOUBLE_GAIN_COUNTER
Definition: ad9361.h:1561
RX_FAST_LOCK_PROFILE_WORD
#define RX_FAST_LOCK_PROFILE_WORD(x)
Definition: ad9361.h:2410
REG_RX_BBF_TUNE_DIVIDE
#define REG_RX_BBF_TUNE_DIVIDE
Definition: ad9361.h:423
GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE
#define GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE
Definition: ad9361.h:1470
ad9361_fastlock_recall
int32_t ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
Definition: ad9361.c:5143
gain_control::immed_gain_change_if_large_lmt_overload
bool immed_gain_change_if_large_lmt_overload
Definition: ad9361.h:2975
TO_MIXER_GM_GAIN
#define TO_MIXER_GM_GAIN(x)
Definition: ad9361.h:1615
dev_err
#define dev_err(dev, format,...)
Definition: ad9361_util.h:69
SynthLUT::LF_R1
uint8_t LF_R1
Definition: ad9361.h:3254
gain_control::agc_inner_thresh_low_inc_steps
uint8_t agc_inner_thresh_low_inc_steps
Definition: ad9361.h:2955
REG_MULTICHIP_SYNC_AND_TX_MON_CTRL
#define REG_MULTICHIP_SYNC_AND_TX_MON_CTRL
Definition: ad9361.h:52
FORCE_VCO_TUNE
#define FORCE_VCO_TUNE
Definition: ad9361.h:2457
RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE
#define RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE
Definition: ad9361.h:2417
TEMP_SENSOR_DECIMATION
#define TEMP_SENSOR_DECIMATION(x)
Definition: ad9361.h:677
CLKOUT_SELECT
#define CLKOUT_SELECT(x)
Definition: ad9361.h:660
ad9361_rf_phy::gpio_desc_cal_sw2
struct no_os_gpio_desc * gpio_desc_cal_sw2
Definition: ad9361.h:3346
ad9361_clk_factor_round_rate
int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6477
AUX_ADC_DECIMATION
#define AUX_ADC_DECIMATION(x)
Definition: ad9361.h:803
TX_BBF_TUNE_DIVIDER
#define TX_BBF_TUNE_DIVIDER
Definition: ad9361.h:1326
VCO_LOCK
#define VCO_LOCK
Definition: ad9361.h:2566
REG_GAIN_STP_CONFIG1
#define REG_GAIN_STP_CONFIG1
Definition: ad9361.h:234
LO_DONTCARE
@ LO_DONTCARE
Definition: ad9361.h:3329
REG_CALIBRATION_CONFIG_1
#define REG_CALIBRATION_CONFIG_1
Definition: ad9361.h:314
SYNTH_ENABLE_PIN_CTRL_MODE
#define SYNTH_ENABLE_PIN_CTRL_MODE
Definition: ad9361.h:738
POWER_MEAS_IN_STATE_5_MSB
#define POWER_MEAS_IN_STATE_5_MSB
Definition: ad9361.h:1429
gain_control::adc_large_overload_inc_steps
uint8_t adc_large_overload_inc_steps
Definition: ad9361.h:2961
ad9361_rfpll_int_round_rate
int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6804
gpo_control::gpo0_inactive_state_high_en
bool gpo0_inactive_state_high_en
Definition: ad9361.h:3101
TX_SYNTH_VCO_ALC_POWER_DOWN
#define TX_SYNTH_VCO_ALC_POWER_DOWN
Definition: ad9361.h:954
ad9361_rf_phy::clks
struct no_os_clk * clks[NUM_AD9361_CLKS]
Definition: ad9361.h:3352
ad9361_fastlock_save
int32_t ad9361_fastlock_save(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition: ad9361.c:5199
BE_VERBOSE
@ BE_VERBOSE
Definition: ad9361.h:3314
TX_MONITOR_POWER_DOWN
#define TX_MONITOR_POWER_DOWN(x)
Definition: ad9361.h:988
CP_CAL_VALID
#define CP_CAL_VALID
Definition: ad9144.h:672
ad9361_phy_platform_data::tx_synth_freq
uint64_t tx_synth_freq
Definition: ad9361.h:3200
REG_RF_DC_OFFSET_COUNT
#define REG_RF_DC_OFFSET_COUNT
Definition: ad9361.h:341
gpo_control::gpo3_inactive_state_high_en
bool gpo3_inactive_state_high_en
Definition: ad9361.h:3104
rf_rx_gain
Definition: ad9361.h:3222
rssi_control::rssi_unit_is_rx_samples
bool rssi_unit_is_rx_samples
Definition: ad9361.h:3051
DEC3_ENABLE_DECIMATION
#define DEC3_ENABLE_DECIMATION(x)
Definition: ad9361.h:616
MIN_BBPLL_DIV
#define MIN_BBPLL_DIV
Definition: ad9361.h:2826
REG_FAST_INITIAL_LMT_GAIN_LIMIT
#define REG_FAST_INITIAL_LMT_GAIN_LIMIT
Definition: ad9361.h:256
SIZE_FULL_TABLE
#define SIZE_FULL_TABLE
Definition: ad9361.c:400
auxdac_control::dac1_rx_delay_us
uint8_t dac1_rx_delay_us
Definition: ad9361.h:3034
CHARGE_PUMP_CURRENT
#define CHARGE_PUMP_CURRENT(x)
Definition: ad9361.h:2477
gain_control::adc_lmt_small_overload_prevent_gain_inc
bool adc_lmt_small_overload_prevent_gain_inc
Definition: ad9361.h:2963
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:83
FIR_START_CLK
#define FIR_START_CLK
Definition: ad9361.h:1026
REG_TIA1_C_MSB
#define REG_TIA1_C_MSB
Definition: ad9361.h:398
REG_AUXDAC_1_CONFIG
#define REG_AUXDAC_1_CONFIG
Definition: ad9361.h:76
REG_RX_LOOP_FILTER_3
#define REG_RX_LOOP_FILTER_3
Definition: ad9361.h:482
FREQ_CAL_COUNT_LENGTH
#define FREQ_CAL_COUNT_LENGTH(x)
Definition: ad9361.h:934
FORCE_ALC_ENABLE
#define FORCE_ALC_ENABLE
Definition: ad9361.h:2449
ad9361_rf_phy::adc_state
struct axiadc_state * adc_state
Definition: ad9361.h:3409
REG_BIST_AND_DATA_PORT_TEST_CONFIG
#define REG_BIST_AND_DATA_PORT_TEST_CONFIG
Definition: ad9361.h:572
RX_ENABLE
#define RX_ENABLE
Definition: ad9361.h:620
REG_FRACT_BB_FREQ_WORD_1
#define REG_FRACT_BB_FREQ_WORD_1
Definition: ad9361.h:111
SPI_WRITE_TO_REGISTER
@ SPI_WRITE_TO_REGISTER
Definition: ad9361.h:3045
ad9361_rf_phy::rx_fir_ntaps
uint8_t rx_fir_ntaps
Definition: ad9361.h:3397
REFERENCE_CLOCK_CYCLES_PER_US
#define REFERENCE_CLOCK_CYCLES_PER_US(x)
Definition: ad9361.h:867
NUM_RX_CLOCKS
@ NUM_RX_CLOCKS
Definition: ad9361.h:3144
RX_DISABLE
#define RX_DISABLE
Definition: ad9361.h:621
AGC_ATTACK_DELAY
#define AGC_ATTACK_DELAY(x)
Definition: ad9361.h:820
ad9361_fastlock_entry
Definition: ad9361.h:3300
MAX_LMT_INDEX
#define MAX_LMT_INDEX
Definition: ad9361.h:2818
REG_TX_TUNE_CTRL
#define REG_TX_TUNE_CTRL
Definition: ad9361.h:210
REF_FREQ_SCALER
#define REF_FREQ_SCALER(x)
Definition: ad9361.h:896
REG_CALIBRATION_CONFIG_2
#define REG_CALIBRATION_CONFIG_2
Definition: ad9361.h:315
ad9361_phy_platform_data::lo_powerdown_managed_en
uint8_t lo_powerdown_managed_en
Definition: ad9361.h:3189
rssi_control
Definition: ad9361.h:3049
REG_TPM_MODE_ENABLE
#define REG_TPM_MODE_ENABLE
Definition: ad9361.h:149
REG_RX2_TUNE_CTRL
#define REG_RX2_TUNE_CTRL
Definition: ad9361.h:404
SYNTH_INTEGER_WORD
#define SYNTH_INTEGER_WORD(x)
Definition: ad9361.h:2439
ad9361_en_dis_rx
int32_t ad9361_en_dis_rx(struct ad9361_rf_phy *phy, uint32_t rx_if, uint32_t enable)
Definition: ad9361.c:1062
ad9361_reset
int32_t ad9361_reset(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1014
no_os_spi.h
Header file of SPI Interface.
ad9361_register_clocks
int32_t ad9361_register_clocks(struct ad9361_rf_phy *phy)
Definition: ad9361.c:7258
REG_GM_SUB_TABLE_CONFIG
#define REG_GM_SUB_TABLE_CONFIG
Definition: ad9361.h:284
DBGFS_BIST_PRBS
@ DBGFS_BIST_PRBS
Definition: ad9361.h:3433
ad9361_rf_phy::manual_tx_quad_cal_en
bool manual_tx_quad_cal_en
Definition: ad9361.h:3371
MAX_ADC_CLK
#define MAX_ADC_CLK
Definition: ad9361.h:2836
REG_RX_VCO_CAL_REF
#define REG_RX_VCO_CAL_REF
Definition: ad9361.h:486
REG_FAST_ATTACK_STATE
#define REG_FAST_ATTACK_STATE
Definition: ad9361.h:562
FB_CLOCK_ADV
#define FB_CLOCK_ADV(x)
Definition: ad9361.h:2582
ctrl_outs_control::index
uint8_t index
Definition: ad9361.h:3076
ad9361_debugfs_entry::phy
struct ad9361_rf_phy * phy
Definition: ad9361.h:3292
fir_dest
fir_dest
Definition: ad9361.h:2892
TONE_FREQ
#define TONE_FREQ(x)
Definition: ad9361.h:2771
auxdac_control::dac2_in_rx_en
bool dac2_in_rx_en
Definition: ad9361.h:3030
ADC_CLK_DIV_4
@ ADC_CLK_DIV_4
Definition: ad9361.h:3162
gain_control::f_agc_rst_gla_engergy_lost_sig_thresh_below_ll
uint8_t f_agc_rst_gla_engergy_lost_sig_thresh_below_ll
Definition: ad9361.h:3007
MEASUREMENT_TIME_INTERVAL
#define MEASUREMENT_TIME_INTERVAL(x)
Definition: ad9361.h:672
TX_MON_TRACK
#define TX_MON_TRACK
Definition: ad9361.h:1034
REG_QUAD_CAL_COUNT
#define REG_QUAD_CAL_COUNT
Definition: ad9361.h:190
gain_control::lmt_overload_small_exceed_counter
uint8_t lmt_overload_small_exceed_counter
Definition: ad9361.h:2966
PHASE_ENABLE
#define PHASE_ENABLE
Definition: ad9361.h:1142
MAX_TX_HB3
#define MAX_TX_HB3
Definition: ad9361.h:2846
elna_control::elna_in_gaintable_all_index_en
bool elna_in_gaintable_all_index_en
Definition: ad9361.h:3086
gain_control::adc_ovr_sample_size
uint8_t adc_ovr_sample_size
Definition: ad9361.h:2926
REG_TIA2_C_MSB
#define REG_TIA2_C_MSB
Definition: ad9361.h:400
ad9361_fastlock::current_profile
uint8_t current_profile[2]
Definition: ad9361.h:3309
REG_AUXADC_CONFIG
#define REG_AUXADC_CONFIG
Definition: ad9361.h:79
ad9361_ensm_restore_state
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:2041
rx_gain_info
Definition: ad9361.h:3057
FDD_MODE
#define FDD_MODE
Definition: ad9361.h:717
MAX_GAIN
@ MAX_GAIN
Definition: ad9361.h:2915
MAX_CARRIER_FREQ_HZ
#define MAX_CARRIER_FREQ_HZ
Definition: ad9361.h:2858
REG_RX_SYNTH_POWER_DOWN_OVERRIDE
#define REG_RX_SYNTH_POWER_DOWN_OVERRIDE
Definition: ad9361.h:125
REG_TEMP_OFFSET
#define REG_TEMP_OFFSET
Definition: ad9361.h:61
ENABLE_TRACKING_MODE_CH2
#define ENABLE_TRACKING_MODE_CH2
Definition: ad9361.h:1771
T1_CLK
@ T1_CLK
Definition: ad9361.h:3278
AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN
@ AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN
Definition: ad9361.h:3041
REG_TX_QUAD_FULL_LMT_GAIN
#define REG_TX_QUAD_FULL_LMT_GAIN
Definition: ad9361.h:191
ad9361_clear_state
void ad9361_clear_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:5274
RX_GAIN_CTL_AGC_FAST_ATK
#define RX_GAIN_CTL_AGC_FAST_ATK
Definition: ad9361.h:1356
DCXO_TUNE_COARSE
#define DCXO_TUNE_COARSE(x)
Definition: ad9361.h:2636
gpo_control::gpo_manual_mode_en
bool gpo_manual_mode_en
Definition: ad9361.h:3100
ENABLE_INCR_GAIN
#define ENABLE_INCR_GAIN
Definition: ad9361.h:1472
REG_TEMP_SENSE2
#define REG_TEMP_SENSE2
Definition: ad9361.h:63
REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET
#define REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET
Definition: ad9361.h:181
REG_BBPLL
#define REG_BBPLL
Definition: ad9361.h:60
ad9361_rf_phy::rfdc_track_en
bool rfdc_track_en
Definition: ad9361.h:3399
POST_LOCK_LEVEL_STP_FOR_LMT_TABLE
#define POST_LOCK_LEVEL_STP_FOR_LMT_TABLE(x)
Definition: ad9361.h:1491
REG_RFPLL_DIVIDERS
#define REG_RFPLL_DIVIDERS
Definition: ad9361.h:56
RX_SYNTH_PTAT_POWER_DOWN
#define RX_SYNTH_PTAT_POWER_DOWN
Definition: ad9361.h:946
MAN_GAIN_CTRL_RX2
#define MAN_GAIN_CTRL_RX2
Definition: ad9361.h:1367
ad9361_spi_readm
int32_t ad9361_spi_readm(struct no_os_spi_desc *spi, uint32_t reg, uint8_t *rbuf, uint32_t num)
Definition: ad9361.c:699
elna_control::elna_1_control_en
bool elna_1_control_en
Definition: ad9361.h:3084
printk
#define printk(format,...)
Definition: ad9361_util.h:72
MAX_LPF_GAIN
#define MAX_LPF_GAIN
Definition: ad9361.h:2819
ad9361_ensm_force_state
void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:1961
REG_RX_VCO_LDO
#define REG_RX_VCO_LDO
Definition: ad9361.h:489
TONE_LEVEL
#define TONE_LEVEL(x)
Definition: ad9361.h:2772
gain_control::f_agc_rst_gla_engergy_lost_goto_optim_gain_en
bool f_agc_rst_gla_engergy_lost_goto_optim_gain_en
Definition: ad9361.h:3006
SynthLUT::VCO_Cal_Offset
uint8_t VCO_Cal_Offset
Definition: ad9361.h:3249
ad9361_fastlock_load
int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition: ad9361.c:4970
SynthLUT::VCO_Bias_Tcf
uint8_t VCO_Bias_Tcf
Definition: ad9361.h:3248
gpo_control::gpo3_tx_delay_us
uint8_t gpo3_tx_delay_us
Definition: ad9361.h:3120
FORCE_RX_ON
#define FORCE_RX_ON
Definition: ad9361.h:723
ad9361_en_dis_rx
int32_t ad9361_en_dis_rx(struct ad9361_rf_phy *phy, uint32_t rx_if, uint32_t enable)
Definition: ad9361.c:1062
ad9361_reset
int32_t ad9361_reset(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1014
TX_SYNTH_PTAT_POWER_DOWN
#define TX_SYNTH_PTAT_POWER_DOWN
Definition: ad9361.h:955
FIR_WRITE
#define FIR_WRITE
Definition: ad9361.h:1027
RX_FAST_LOCK_PROFILE_ADDR
#define RX_FAST_LOCK_PROFILE_ADDR(x)
Definition: ad9361.h:2409
ad9361_set_trx_clock_chain
int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4612
ad9361_get_temp
int32_t ad9361_get_temp(struct ad9361_rf_phy *phy)
Definition: ad9361.c:4186
HAVE_TDD_SYNTH_TABLE
#define HAVE_TDD_SYNTH_TABLE
Definition: app_config.h:43
ad9361_get_bist_loopback
void ad9361_get_bist_loopback(struct ad9361_rf_phy *phy, int32_t *mode)
Definition: ad9361.c:1145
RX_BBF_R2346
#define RX_BBF_R2346(x)
Definition: ad9361.h:2113
EXT_REF_CLK
@ EXT_REF_CLK
Definition: ad9361.h:3288
auxadc_control::offset
int8_t offset
Definition: ad9361.h:3090
RX_LO_POWER_DOWN
#define RX_LO_POWER_DOWN
Definition: ad9361.h:944
AD9363A_MAX_CARRIER_FREQ_HZ
#define AD9363A_MAX_CARRIER_FREQ_HZ
Definition: ad9361.h:2862
ad9361_get_tx_atten
int32_t ad9361_get_tx_atten(struct ad9361_rf_phy *phy, uint32_t tx_num)
Definition: ad9361.c:1653
REG_MEASURE_DURATION_23
#define REG_MEASURE_DURATION_23
Definition: ad9361.h:296
ad9361_adi_gt_info
struct gain_table_info ad9361_adi_gt_info[]
Definition: ad9361.c:604
CALIBRATION_CONFIG2_DFLT
#define CALIBRATION_CONFIG2_DFLT
Definition: ad9361.h:1778
DEC_PWR_FOR_LOCK_LEVEL
#define DEC_PWR_FOR_LOCK_LEVEL
Definition: ad9361.h:1347
FORCE_PD_RESET_RX2
#define FORCE_PD_RESET_RX2
Definition: ad9361.h:1417
REG_GM_SUB_TABLE_GAIN_READ
#define REG_GM_SUB_TABLE_GAIN_READ
Definition: ad9361.h:281
ID_AD9364
@ ID_AD9364
Definition: ad9361.h:3336
REG_TIA2_C_LSB
#define REG_TIA2_C_LSB
Definition: ad9361.h:399
REG_RX1_MANUAL_DIGITALFORCED_GAIN
#define REG_RX1_MANUAL_DIGITALFORCED_GAIN
Definition: ad9361.h:242
refclk_scale
Definition: ad9361.h:3420
GPO_ENABLE_AUTO_RX
#define GPO_ENABLE_AUTO_RX(x)
Definition: ad9361.h:813
auxdac_control::dac2_default_value
uint16_t dac2_default_value
Definition: ad9361.h:3022
MAX_RX_HB3
#define MAX_RX_HB3
Definition: ad9361.h:2842
GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH
#define GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH
Definition: ad9361.h:1479
ad9361_phy_platform_data::rf_dc_offset_count_low
uint8_t rf_dc_offset_count_low
Definition: ad9361.h:3186
no_os_delay.h
Header file of Delay functions.
AD_READ
#define AD_READ
Definition: ad9361.h:2804
rx_gain_info::gain_step_db
int32_t gain_step_db
Definition: ad9361.h:3061
rf_rssi::duration
uint8_t duration
Definition: ad9361.h:3240
ENSM_STATE_INVALID
#define ENSM_STATE_INVALID
Definition: ad9361.h:769
SynthLUT::LF_R3
uint8_t LF_R3
Definition: ad9361.h:3256
ad9361_phy_platform_data::dig_interface_tune_skipmode
uint8_t dig_interface_tune_skipmode
Definition: ad9361.h:3187
TX_SAMPL_FREQ
@ TX_SAMPL_FREQ
Definition: ad9361.h:3153
RX_1
#define RX_1
Definition: ad9361.h:618
FDD_EXTERNAL_CTRL_ENABLE
#define FDD_EXTERNAL_CTRL_ENABLE
Definition: ad9361.h:734
AGC_INNER_HIGH_THRESH_EXED_STP_SIZE
#define AGC_INNER_HIGH_THRESH_EXED_STP_SIZE(x)
Definition: ad9361.h:1555
START_GM_SUB_TABLE_CLOCK
#define START_GM_SUB_TABLE_CLOCK
Definition: ad9361.h:1671
gain_control
Definition: ad9361.h:2921
gain_table_info::end
uint64_t end
Definition: ad9361.h:2885
NO_GAIN_CHANGE
@ NO_GAIN_CHANGE
Definition: ad9361.h:2918
LEVEL_MODE
#define LEVEL_MODE
Definition: ad9361.h:726
RX_FAST_LOCK_PROFILE
#define RX_FAST_LOCK_PROFILE(x)
Definition: ad9361.h:2404
PORB_VCO_LOGIC
#define PORB_VCO_LOGIC
Definition: ad9361.h:2469
REG_TX_CLOCK_DATA_DELAY
#define REG_TX_CLOCK_DATA_DELAY
Definition: ad9361.h:58
REG_TX_MON_HIGH_GAIN
#define REG_TX_MON_HIGH_GAIN
Definition: ad9361.h:143
PREVENT_GAIN_INC
#define PREVENT_GAIN_INC
Definition: ad9361.h:1535
REG_GAIN_STP1
#define REG_GAIN_STP1
Definition: ad9361.h:261
REG_AUXADC_LSB
#define REG_AUXADC_LSB
Definition: ad9361.h:81
REG_RX_FAST_LOCK_PROGRAM_CTRL
#define REG_RX_FAST_LOCK_PROGRAM_CTRL
Definition: ad9361.h:504
REG_TEMPERATURE
#define REG_TEMPERATURE
Definition: ad9361.h:64
axi_adc
AXI ADC Device Descriptor.
Definition: axi_adc_core.h:125
REG_FRACT_BB_FREQ_WORD_3
#define REG_FRACT_BB_FREQ_WORD_3
Definition: ad9361.h:113
KEXP_DC_Q
#define KEXP_DC_Q(x)
Definition: ad9361.h:1152
REG_RX_BBF_C3_LSB
#define REG_RX_BBF_C3_LSB
Definition: ad9361.h:413
ad9361_spi_writef
#define ad9361_spi_writef(spi, reg, mask, val)
Definition: ad9361.c:857
ad9361_tx_mute
int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state)
Definition: ad9361.c:1678
TX_SYNTH_READY_MASK
#define TX_SYNTH_READY_MASK
Definition: ad9361.h:741
rf_rssi::multiplier
int32_t multiplier
Definition: ad9361.h:3239
REG_GAIN_UPDATE_COUNTER1
#define REG_GAIN_UPDATE_COUNTER1
Definition: ad9361.h:262
FREQ_CAL_ENABLE
#define FREQ_CAL_ENABLE
Definition: ad9361.h:932
ad9361_phy_platform_data::dig_interface_tune_fir_disable
uint8_t dig_interface_tune_fir_disable
Definition: ad9361.h:3188
ad9361_rf_phy::agc_mode
uint8_t agc_mode[2]
Definition: ad9361.h:3398
gpo_control::gpo0_tx_delay_us
uint8_t gpo0_tx_delay_us
Definition: ad9361.h:3114
gain_table_info::abs_gain_tbl
int8_t * abs_gain_tbl
Definition: ad9361.h:2888
no_os_clk
Definition: no_os_clk.h:59
REG_AUXDAC_2_WORD
#define REG_AUXDAC_2_WORD
Definition: ad9361.h:75
TO_ALERT
#define TO_ALERT
Definition: ad9361.h:729
REG_RX_FRACT_BYTE_0
#define REG_RX_FRACT_BYTE_0
Definition: ad9361.h:469
TX_MON_2_GAIN
#define TX_MON_2_GAIN(x)
Definition: ad9361.h:1072
gpo_control::gpo3_slave_tx_en
bool gpo3_slave_tx_en
Definition: ad9361.h:3112
MAX_SYNTH_FREF
#define MAX_SYNTH_FREF
Definition: ad9361.h:2855
SMALL_LMT_OVERLOAD_THRESH
#define SMALL_LMT_OVERLOAD_THRESH(x)
Definition: ad9361.h:1419
BBPLL_LOCK
#define BBPLL_LOCK
Definition: ad9361.h:1002
gpo_control::gpo_manual_mode_enable_mask
uint32_t gpo_manual_mode_enable_mask
Definition: ad9361.h:3099
REG_TX_VCO_OUTPUT
#define REG_TX_VCO_OUTPUT
Definition: ad9361.h:516
TBL_1300_4000_MHZ
@ TBL_1300_4000_MHZ
Definition: ad9361.h:2878
FORCE_ALC_WORD
#define FORCE_ALC_WORD(x)
Definition: ad9361.h:2450
ad9361_rf_phy::spi
struct no_os_spi_desc * spi
Definition: ad9361.h:3342
LVDS_MODE
#define LVDS_MODE
Definition: ad9361.h:708
RX_NCO_FREQ
#define RX_NCO_FREQ(x)
Definition: ad9361.h:1132
CLKOUT_ENABLE
@ CLKOUT_ENABLE
Definition: ad5758.h:294
TX_REF_RESET_BAR
#define TX_REF_RESET_BAR
Definition: ad9361.h:2709
REG_DCXO_FINE_TUNE_LOW
#define REG_DCXO_FINE_TUNE_LOW
Definition: ad9361.h:542
ENSM_STATE_SLEEP_WAIT
#define ENSM_STATE_SLEEP_WAIT
Definition: ad9361.h:761
REG_CALIBRATION_CTRL
#define REG_CALIBRATION_CTRL
Definition: ad9361.h:72
GT_RX1
#define GT_RX1
Definition: ad9361.h:1633
gain_control::f_agc_optimized_gain_offset
uint8_t f_agc_optimized_gain_offset
Definition: ad9361.h:3002
ad9361_phy_platform_data::tx_fastlock_delay_ns
uint32_t tx_fastlock_delay_ns
Definition: ad9361.h:3206
TBL_4000_6000_MHZ
@ TBL_4000_6000_MHZ
Definition: ad9361.h:2879
DONT_UNLOCK_GAIN_IF_ENERGY_LOST
#define DONT_UNLOCK_GAIN_IF_ENERGY_LOST
Definition: ad9361.h:1469
DIG_GAIN_STP_SIZE
#define DIG_GAIN_STP_SIZE(x)
Definition: ad9361.h:1392
REG_LARGE_LMT_OVERLOAD_THRESH
#define REG_LARGE_LMT_OVERLOAD_THRESH
Definition: ad9361.h:239
ad9361_rf_port_setup
int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out, uint32_t rx_inputs, uint32_t txb)
Definition: ad9361.c:3609
ENABLE_RF_OFFSET_TRACKING
#define ENABLE_RF_OFFSET_TRACKING
Definition: ad9361.h:1873
REG_RX_BBF_R2346
#define REG_RX_BBF_R2346
Definition: ad9361.h:407
REG_AGC_LOCK_LEVEL
#define REG_AGC_LOCK_LEVEL
Definition: ad9361.h:232
FINAL_OVER_RANGE_COUNT
#define FINAL_OVER_RANGE_COUNT(x)
Definition: ad9361.h:1508
port_control::rx_clk_data_delay
uint8_t rx_clk_data_delay
Definition: ad9361.h:3068
TX_OUTPUT
#define TX_OUTPUT
Definition: ad9361.h:626
ERR_PTR
void * ERR_PTR(long error)
ERR_PTR.
Definition: ad9361_util.c:314
REG_FAST_AGCLL_UPPER_LIMIT
#define REG_FAST_AGCLL_UPPER_LIMIT
Definition: ad9361.h:254
ilog2
int32_t ilog2(int32_t x)
ilog2
Definition: ad9361_util.c:255
ad9361_debugfs_entry::cmd
uint8_t cmd
Definition: ad9361.h:3297
REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN
#define REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN
Definition: ad9361.h:252
REG_TX_MON_LOW_GAIN
#define REG_TX_MON_LOW_GAIN
Definition: ad9361.h:142
REG_GAIN_ERROR_READ
#define REG_GAIN_ERROR_READ
Definition: ad9361.h:287
DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG
#define DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG
Definition: ad9361.h:1471
ad9361_rf_phy::current_tx_use_tdd_table
bool current_tx_use_tdd_table
Definition: ad9361.h:3376
SynthLUT::VCO_Output_Level
uint8_t VCO_Output_Level
Definition: ad9361.h:3245
DBGFS_NONE
@ DBGFS_NONE
Definition: ad9361.h:3430
ad9361_rfpll_int_set_rate
int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6833
gpo_control::gpo2_rx_delay_us
uint8_t gpo2_rx_delay_us
Definition: ad9361.h:3117
ad9361_rf_phy::cached_rx_rfpll_div
uint8_t cached_rx_rfpll_div
Definition: ad9361.h:3362
TX_MON_DELAY_COUNTER
#define TX_MON_DELAY_COUNTER(x)
Definition: ad9361.h:1046
rf_rx_gain::ant
uint32_t ant
Definition: ad9361.h:3223
REG_RX_BBBW_MHZ
#define REG_RX_BBBW_MHZ
Definition: ad9361.h:426
_SOFT_RESET
#define _SOFT_RESET
Definition: ad9361.h:585
REG_CTRL
#define REG_CTRL
Definition: ad9361.h:569
ad9361_util.h
AD9361 Header file of Util driver.
RX2_FAST_ATK_SHIFT
#define RX2_FAST_ATK_SHIFT
Definition: ad9361.h:2736
refclk_scale::parent_source
enum ad9361_clocks parent_source
Definition: ad9361.h:3426
ONE_SHOT_MODE
#define ONE_SHOT_MODE
Definition: ad9361.h:1059
RHB1_EN
#define RHB1_EN
Definition: ad9361.h:614
ad9361_set_dcxo_tune
int32_t ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy, uint32_t coarse, uint32_t fine)
Definition: ad9361.c:3495
rf_rx_gain::lmt_gain
uint32_t lmt_gain
Definition: ad9361.h:3226
FIR_RX1
@ FIR_RX1
Definition: ad9361.h:2896
ad9361_set_gain_ctrl_mode
int32_t ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy, struct rf_gain_ctrl *gain_ctrl)
Definition: ad9361.c:2350
tx_monitor_control::tx1_mon_lo_cm
uint8_t tx1_mon_lo_cm
Definition: ad9361.h:3133
DAC_FREQ
@ DAC_FREQ
Definition: ad9361.h:3149
REG_GPO0_TX_DELAY
#define REG_GPO0_TX_DELAY
Definition: ad9361.h:94
REG_DCXO_COARSE_TUNE
#define REG_DCXO_COARSE_TUNE
Definition: ad9361.h:540
ad9361_rfpll_round_rate
int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7022
ad9361_clk_mux_set_parent
int32_t ad9361_clk_mux_set_parent(struct refclk_scale *clk_priv, uint8_t index)
Definition: ad9361.c:7121
RX_RFPLL_DUMMY
@ RX_RFPLL_DUMMY
Definition: ad9361.h:3283
LOOP_FILTER_R3
#define LOOP_FILTER_R3(x)
Definition: ad9361.h:2514
ENABLE_GAIN_CORR
#define ENABLE_GAIN_CORR
Definition: ad9361.h:1766
TX_QUAD_CAL
#define TX_QUAD_CAL
Definition: ad9361.h:749
ad9361_fastlock::save_profile
uint8_t save_profile
Definition: ad9361.h:3308
ad9361_rf_phy::clk_refin
struct no_os_clk * clk_refin
Definition: ad9361.h:3351
REG_TX_MON_2_CONFIG
#define REG_TX_MON_2_CONFIG
Definition: ad9361.h:152
gain_control::mgc_inc_gain_step
uint8_t mgc_inc_gain_step
Definition: ad9361.h:2943
REG_CLOCK_CTRL
#define REG_CLOCK_CTRL
Definition: ad9361.h:115
ad9361_1rx1tx_channel_map
int32_t ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx, int32_t channel)
Definition: ad9361.c:990
REG_PEAK_WAIT_TIME
#define REG_PEAK_WAIT_TIME
Definition: ad9361.h:230
NO_OS_ARRAY_SIZE
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
TX_EXT_VCO_BUFFER_POWER_DOWN
#define TX_EXT_VCO_BUFFER_POWER_DOWN
Definition: ad9361.h:987
REG_GAIN_TABLE_WRITE_DATA3
#define REG_GAIN_TABLE_WRITE_DATA3
Definition: ad9361.h:272
REG_MEASURE_DURATION_01
#define REG_MEASURE_DURATION_01
Definition: ad9361.h:295
ad9361_rf_phy::filt_tx_path_clks
uint32_t filt_tx_path_clks[NUM_TX_CLOCKS]
Definition: ad9361.h:3391
REG_RSSI_WEIGHT_0
#define REG_RSSI_WEIGHT_0
Definition: ad9361.h:297
ad9361_rfpll_recalc_rate
uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:6980
BIST_MASK_CHANNEL_1_Q_DATA
#define BIST_MASK_CHANNEL_1_Q_DATA
Definition: ad9361.h:2789
MIN_TX_CARRIER_FREQ_HZ
#define MIN_TX_CARRIER_FREQ_HZ
Definition: ad9361.h:2860
CLK_IGNORE_UNUSED
#define CLK_IGNORE_UNUSED
Definition: ad9361_util.h:56
K_EXP_AMPLITUDE
#define K_EXP_AMPLITUDE(x)
Definition: ad9361.h:1785
ENSM_STATE_TX
#define ENSM_STATE_TX
Definition: ad9361.h:763
refclk_scale::phy
struct ad9361_rf_phy * phy
Definition: ad9361.h:3422
REG_FAST_INCREMENT_TIME
#define REG_FAST_INCREMENT_TIME
Definition: ad9361.h:257
POWER_MEAS_IN_STATE_5
#define POWER_MEAS_IN_STATE_5(x)
Definition: ad9361.h:1436
REG_AUXDAC1_TX_DELAY
#define REG_AUXDAC1_TX_DELAY
Definition: ad9361.h:99
TEMP_SENSE_PERIODIC_ENABLE
#define TEMP_SENSE_PERIODIC_ENABLE
Definition: ad9361.h:671
SynthLUT::VCO_Varactor_Reference
uint8_t VCO_Varactor_Reference
Definition: ad9361.h:3250
RX_NCO_PHASE_OFFSET
#define RX_NCO_PHASE_OFFSET(x)
Definition: ad9361.h:1133
RX1_TUNE_RESAMPLE
#define RX1_TUNE_RESAMPLE
Definition: ad9361.h:2099
gain_control::f_agc_allow_agc_gain_increase
bool f_agc_allow_agc_gain_increase
Definition: ad9361.h:2983
ad9361_ensm_states
const char * ad9361_ensm_states[]
Definition: ad9361.c:686
DC_OFFSET_UPDATE
#define DC_OFFSET_UPDATE(x)
Definition: ad9361.h:1874
T1_FREQ
@ T1_FREQ
Definition: ad9361.h:3151
no_os_clk::name
const char * name
Definition: no_os_clk.h:62
ad9361_rf_phy::current_rx_path_clks
uint32_t current_rx_path_clks[NUM_RX_CLOCKS]
Definition: ad9361.h:3378
REG_TX_SYMBOL_ATTEN_CONFIG
#define REG_TX_SYMBOL_ATTEN_CONFIG
Definition: ad9361.h:163
REG_AUXDAC2_TX_DELAY
#define REG_AUXDAC2_TX_DELAY
Definition: ad9361.h:101
REG_TX_FILTER_COEF_WRITE_DATA_2
#define REG_TX_FILTER_COEF_WRITE_DATA_2
Definition: ad9361.h:138
RSSI_RESOLUTION
#define RSSI_RESOLUTION
Definition: ad9361.h:2815
gain_control::adc_large_overload_exceed_counter
uint8_t adc_large_overload_exceed_counter
Definition: ad9361.h:2960
LUT_FTDD_60
@ LUT_FTDD_60
Definition: ad9361.h:3261
REG_TX_FILTER_COEF_WRITE_DATA_1
#define REG_TX_FILTER_COEF_WRITE_DATA_1
Definition: ad9361.h:137
BIST_DISABLE
@ BIST_DISABLE
Definition: ad9361.h:3323
SynthLUT::Charge_Pump_Current
uint8_t Charge_Pump_Current
Definition: ad9361.h:3251
REG_GPO2_RX_DELAY
#define REG_GPO2_RX_DELAY
Definition: ad9361.h:92
ad9361_rfpll_dummy_set_rate
int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:6965
ad9361_set_trx_clock_chain
int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4612
port_control::tx_clk_data_delay
uint8_t tx_clk_data_delay
Definition: ad9361.h:3069
REG_BB_DC_OFFSET_SHIFT
#define REG_BB_DC_OFFSET_SHIFT
Definition: ad9361.h:348
tx_monitor_control::tx_mon_delay
uint16_t tx_mon_delay
Definition: ad9361.h:3129
REG_ADC_LARGE_OVERLOAD_THRESH
#define REG_ADC_LARGE_OVERLOAD_THRESH
Definition: ad9361.h:236
ad9361_rf_phy::tx_quad_lpf_tia_match
int32_t tx_quad_lpf_tia_match
Definition: ad9361.h:3365
REG_RX_MIX_LO_CM
#define REG_RX_MIX_LO_CM
Definition: ad9361.h:393
AD_WRITE
#define AD_WRITE
Definition: ad9361.h:2805
gain_control::adc_large_overload_thresh
uint8_t adc_large_overload_thresh
Definition: ad9361.h:2928
ad9361_ensm_get_state
uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1948
REG_RX_FRACT_BYTE_1
#define REG_RX_FRACT_BYTE_1
Definition: ad9361.h:470
rx_gain_info::max_gain_db
int32_t max_gain_db
Definition: ad9361.h:3060
ad9361_rfpll_round_rate
int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7022
REG_TX_LO_GEN_POWER_MODE
#define REG_TX_LO_GEN_POWER_MODE
Definition: ad9361.h:554
ad9361_pdata_tx_freq
ad9361_pdata_tx_freq
Definition: ad9361.h:3147
RF_DC_OFFSET_ATTEN
#define RF_DC_OFFSET_ATTEN(x)
Definition: ad9361.h:1856
DO_IDELAY
@ DO_IDELAY
Definition: ad9361.h:3316
ad9361_rf_phy::auxdac1_value
uint16_t auxdac1_value
Definition: ad9361.h:3403
MCS_DIGITAL_CLK_ENABLE
#define MCS_DIGITAL_CLK_ENABLE
Definition: ad9361.h:594
REG_STATE
#define REG_STATE
Definition: ad9361.h:73
RX_REF_DOUBLER_FB_DELAY
#define RX_REF_DOUBLER_FB_DELAY(x)
Definition: ad9361.h:2710
WRITE_MIXER_ERROR_TABLE
#define WRITE_MIXER_ERROR_TABLE
Definition: ad9361.h:1687
ad9361_hdl_loopback
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
Definition: ad9361_conv.c:113
ENSM_STATE_FDD
#define ENSM_STATE_FDD
Definition: ad9361.h:767
TX_REF_DOUBLER_FB_DELAY
#define TX_REF_DOUBLER_FB_DELAY(x)
Definition: ad9361.h:2712
RHB2_EN
#define RHB2_EN
Definition: ad9361.h:613
REG_GAIN_TABLE_READ_DATA2
#define REG_GAIN_TABLE_READ_DATA2
Definition: ad9361.h:274
RX_SAMPL_CLK
@ RX_SAMPL_CLK
Definition: ad9361.h:3275
ad9361_set_rx_gain
int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition: ad9361.c:2197
ADC_CLK_DIV_8
@ ADC_CLK_DIV_8
Definition: ad9361.h:3163
BIST_INJ_RX
@ BIST_INJ_RX
Definition: ad9361.h:3325
THB2_EN
#define THB2_EN
Definition: ad9361.h:600
ad9361_rf_phy::bist_prbs_mode
enum ad9361_bist_mode bist_prbs_mode
Definition: ad9361.h:3412
ad9361_gt
uint32_t ad9361_gt(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1348
INIT_BB_FO_CAL
#define INIT_BB_FO_CAL
Definition: ad9361.h:890
gain_control::agc_outer_thresh_high
uint8_t agc_outer_thresh_high
Definition: ad9361.h:2950
ad9361_rf_phy::current_tx_lo_freq
uint64_t current_tx_lo_freq
Definition: ad9361.h:3374
gain_control::f_agc_lmt_final_settling_steps
uint8_t f_agc_lmt_final_settling_steps
Definition: ad9361.h:2993
TX1_LO_CONV
#define TX1_LO_CONV
Definition: ad9361.h:1166
MAX_TX_HB1
#define MAX_TX_HB1
Definition: ad9361.h:2844
gain_control::mgc_rx1_ctrl_inp_en
bool mgc_rx1_ctrl_inp_en
Definition: ad9361.h:2940
tx_monitor_control
Definition: ad9361.h:3123
PD_TUNE
#define PD_TUNE
Definition: ad9361.h:1279
REG_WAIT_COUNT
#define REG_WAIT_COUNT
Definition: ad9361.h:340
REG_AUXDAC1_RX_DELAY
#define REG_AUXDAC1_RX_DELAY
Definition: ad9361.h:98
RSSI_MODE_SELECT
#define RSSI_MODE_SELECT(x)
Definition: ad9361.h:1734
CLKRF_FREQ
@ CLKRF_FREQ
Definition: ad9361.h:3142
RX2_GAIN_CTRL_SHIFT
#define RX2_GAIN_CTRL_SHIFT
Definition: ad9361.h:1353
RX_SYNTH_READY_MASK
#define RX_SYNTH_READY_MASK
Definition: ad9361.h:740
ad9361_rf_phy::curr_ensm_state
uint8_t curr_ensm_state
Definition: ad9361.h:3361
SYNTH_FRACT_WORD
#define SYNTH_FRACT_WORD(x)
Definition: ad9361.h:2444
ad9361_spi_write
int32_t ad9361_spi_write(struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)
Definition: ad9361.c:796
ad9361_find_opt
int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start)
Definition: ad9361.c:954
AGC_OUTER_LOW_THRESH
#define AGC_OUTER_LOW_THRESH(x)
Definition: ad9361.h:1569
IMMEDIATELY_UPDATE_TPC_ATTEN
#define IMMEDIATELY_UPDATE_TPC_ATTEN
Definition: ad9361.h:1098
MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE
#define MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE(x)
Definition: ad9361.h:1386
gain_table_info::split_table
uint8_t split_table
Definition: ad9361.h:2887
ad9361_phy_platform_data::tx_path_clks
uint32_t tx_path_clks[NUM_TX_CLOCKS]
Definition: ad9361.h:3197
dev_warn
#define dev_warn(dev, format,...)
Definition: ad9361_util.h:70
REG_GPO3_RX_DELAY
#define REG_GPO3_RX_DELAY
Definition: ad9361.h:93
ENERGY_DETECT_COUNT
#define ENERGY_DETECT_COUNT(x)
Definition: ad9361.h:1515
gain_control::f_agc_gain_index_type_after_exit_rx_mode
enum f_agc_target_gain_index_type f_agc_gain_index_type_after_exit_rx_mode
Definition: ad9361.h:2999
gain_control::f_agc_rst_gla_stronger_sig_thresh_exceeded_en
bool f_agc_rst_gla_stronger_sig_thresh_exceeded_en
Definition: ad9361.h:3003
TX_RFPLL
@ TX_RFPLL
Definition: ad9361.h:3286
rf_rssi::preamble
uint32_t preamble
Definition: ad9361.h:3238
no_os_do_div
uint64_t no_os_do_div(uint64_t *n, uint64_t base)
ad9361_rssi_gain_step_calib
int32_t ad9361_rssi_gain_step_calib(struct ad9361_rf_phy *phy)
Definition: ad9361.c:7393
VCO_VARACTOR
#define VCO_VARACTOR(x)
Definition: ad9361.h:2464
REG_TX_ATTEN_THRESH
#define REG_TX_ATTEN_THRESH
Definition: ad9361.h:158
MAX_MIXER_CALIBRATION_GAIN_INDEX
#define MAX_MIXER_CALIBRATION_GAIN_INDEX(x)
Definition: ad9361.h:1701
ENERGY_LOST_THRESH
#define ENERGY_LOST_THRESH(x)
Definition: ad9361.h:1486
gain_control::f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en
bool f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en
Definition: ad9361.h:3005
TUNE_CTRL
#define TUNE_CTRL(x)
Definition: ad9361.h:1282
ad9361_phy_platform_data::tdd_skip_vco_cal
bool tdd_skip_vco_cal
Definition: ad9361.h:3177
gain_control::dig_gain_en
bool dig_gain_en
Definition: ad9361.h:2936
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
ad9361_ensm_get_state
uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1948
REG_GAIN_RX1
#define REG_GAIN_RX1
Definition: ad9361.h:559
R1_FREQ
@ R1_FREQ
Definition: ad9361.h:3141
DIGITAL_GAIN_RX
#define DIGITAL_GAIN_RX(x)
Definition: ad9361.h:2727
ad9361_phy_platform_data::dcxo_coarse
uint32_t dcxo_coarse
Definition: ad9361.h:3190
ad9361_set_trx_clock_chain_freq
int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, uint32_t freq)
Definition: ad9361.c:4860
ad9361_phy_platform_data::auxdac_ctrl
struct auxdac_control auxdac_ctrl
Definition: ad9361.h:3217
AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE
#define AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE(x)
Definition: ad9361.h:1574
REG_FAST_ENERGY_DETECT_COUNT
#define REG_FAST_ENERGY_DETECT_COUNT
Definition: ad9361.h:253
ad9361_debugfs_entry::out_value
void * out_value
Definition: ad9361.h:3294
gpo_control::gpo0_slave_tx_en
bool gpo0_slave_tx_en
Definition: ad9361.h:3106
START_GAIN_TABLE_CLOCK
#define START_GAIN_TABLE_CLOCK
Definition: ad9361.h:1631
ad9361_post_setup
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
Definition: ad9361_conv.c:605
ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL
#define ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL
Definition: ad9361.h:1478
no_os_min
#define no_os_min(x, y)
Definition: no_os_util.h:63
ad9361_do_calib_run
int32_t ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg)
Definition: ad9361.c:5647
REG_REFERENCE_CLOCK_CYCLES
#define REG_REFERENCE_CLOCK_CYCLES
Definition: ad9361.h:105
ad9361_set_ensm_mode
int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
Definition: ad9361.c:4880
ad9361_ensm_restore_state
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:2041
GPO_MANUAL_CTRL
#define GPO_MANUAL_CTRL(x)
Definition: ad9361.h:842
ad9361_set_rx_gain
int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition: ad9361.c:2197
NUM_TX_CLOCKS
@ NUM_TX_CLOCKS
Definition: ad9361.h:3154
auxdac_control::dac1_default_value
uint16_t dac1_default_value
Definition: ad9361.h:3021
RX1_GAIN_CTRL_SETUP
#define RX1_GAIN_CTRL_SETUP(x)
Definition: ad9361.h:1351
USE_HB1_OUT_FOR_DEC_PWR_MEAS
#define USE_HB1_OUT_FOR_DEC_PWR_MEAS
Definition: ad9361.h:1746
RESTORE_DEFAULT
@ RESTORE_DEFAULT
Definition: ad9361.h:3319
AGCLL_MAX_INCREASE
#define AGCLL_MAX_INCREASE(x)
Definition: ad9361.h:1520
REG_CLOCK_ENABLE
#define REG_CLOCK_ENABLE
Definition: ad9361.h:59
ad9361_gt
uint32_t ad9361_gt(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1348
ad9361_tracking_control
int32_t ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track, bool rfdc_track, bool rxquad_track)
Definition: ad9361.c:3289
REG_QUAD_CAL_CTRL
#define REG_QUAD_CAL_CTRL
Definition: ad9361.h:182
RSSI_LSB_MASK2
#define RSSI_LSB_MASK2
Definition: ad9361.h:1954
REG_RX_VCO_VARACTOR_CTRL_0
#define REG_RX_VCO_VARACTOR_CTRL_0
Definition: ad9361.h:497
ad9361_phy_platform_data::update_tx_gain_via_alert
bool update_tx_gain_via_alert
Definition: ad9361.h:3204
ad9361_rfpll_set_rate
int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7064
GPO_INIT_STATE
#define GPO_INIT_STATE(x)
Definition: ad9361.h:843
ad9361.h
Header file of AD9361 Driver.
REG_GAIN_STP_2
#define REG_GAIN_STP_2
Definition: ad9361.h:266
REG_RX_CP_LEVEL_DETECT
#define REG_RX_CP_LEVEL_DETECT
Definition: ad9361.h:492
VCO_BIAS_TCF
#define VCO_BIAS_TCF(x)
Definition: ad9361.h:2526
NO_OS_DIV_ROUND_UP
#define NO_OS_DIV_ROUND_UP(x, y)
Definition: no_os_util.h:56
MCS_BBPLL_ENABLE
#define MCS_BBPLL_ENABLE
Definition: ad9361.h:593
REG_INPUT_SELECT
#define REG_INPUT_SELECT
Definition: ad9361.h:55
DBGFS_RXGAIN_1
@ DBGFS_RXGAIN_1
Definition: ad9361.h:3436
SETTLING_DELAY
#define SETTLING_DELAY(x)
Definition: ad9361.h:1480
REG_CAPACITOR
#define REG_CAPACITOR
Definition: ad9361.h:215
ad9361_rf_phy::prev_ensm_state
uint8_t prev_ensm_state
Definition: ad9361.h:3360
ID_AD9363A
@ ID_AD9363A
Definition: ad9361.h:3337
REG_SMALL_LMT_OVERLOAD_THRESH
#define REG_SMALL_LMT_OVERLOAD_THRESH
Definition: ad9361.h:238
FIR_RX2
@ FIR_RX2
Definition: ad9361.h:2897
REG_TX_FILTER_COEF_ADDR
#define REG_TX_FILTER_COEF_ADDR
Definition: ad9361.h:136
REG_GAIN_DIFF_WORDERROR_WRITE
#define REG_GAIN_DIFF_WORDERROR_WRITE
Definition: ad9361.h:286
RX_REFCLK
@ RX_REFCLK
Definition: ad9361.h:3268
VCO_VARACTOR_REFERENCE
#define VCO_VARACTOR_REFERENCE(x)
Definition: ad9361.h:2631
AUXDAC_AUTO_RX_BAR
#define AUXDAC_AUTO_RX_BAR(x)
Definition: ad9361.h:827
SOFT_RESET
@ SOFT_RESET
Definition: ad738x.h:141
RX_FAST_LOCK_PROFILE_PIN_SELECT
#define RX_FAST_LOCK_PROFILE_PIN_SELECT
Definition: ad9361.h:2402
MAX_RX_HB1
#define MAX_RX_HB1
Definition: ad9361.h:2840
REG_RX_FILTER_COEF_ADDR
#define REG_RX_FILTER_COEF_ADDR
Definition: ad9361.h:219
ad9361_phy_platform_data::rf_tx_output_sel
uint32_t rf_tx_output_sel
Definition: ad9361.h:3193
REG_RX_INTEGER_BYTE_1
#define REG_RX_INTEGER_BYTE_1
Definition: ad9361.h:468
ad9361_get_auxadc
int32_t ad9361_get_auxadc(struct ad9361_rf_phy *phy)
Definition: ad9361.c:4202
ad9361_rf_phy::filt_rx_path_clks
uint32_t filt_rx_path_clks[NUM_RX_CLOCKS]
Definition: ad9361.h:3390
ad9361_calculate_rf_clock_chain
int32_t ad9361_calculate_rf_clock_chain(struct ad9361_rf_phy *phy, uint32_t tx_sample_rate, uint32_t rate_gov, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4738
TX_MON_1_GAIN
#define TX_MON_1_GAIN(x)
Definition: ad9361.h:1066
rf_gain_ctrl_mode
rf_gain_ctrl_mode
Definition: ad9361.h:2907
REG_TX_FRACT_BYTE_2
#define REG_TX_FRACT_BYTE_2
Definition: ad9361.h:511
ad9361_get_bist_loopback
void ad9361_get_bist_loopback(struct ad9361_rf_phy *phy, int32_t *mode)
Definition: ad9361.c:1145
CALIB_TABLE_SELECT
#define CALIB_TABLE_SELECT(x)
Definition: ad9361.h:1691
axiadc_state
Definition: ad9361_util.h:83
REG_AGC_ATTACK_DELAY
#define REG_AGC_ATTACK_DELAY
Definition: ad9361.h:84
ADC_CLK_DIV_3
@ ADC_CLK_DIV_3
Definition: ad9361.h:3161
TXNRX_SPI_CTRL
#define TXNRX_SPI_CTRL
Definition: ad9361.h:737
IGNORE
@ IGNORE
Definition: ad9361.h:3148
REG_DEC_POWER_MEASURE_DURATION_0
#define REG_DEC_POWER_MEASURE_DURATION_0
Definition: ad9361.h:307
SKIP_STORE_RESULT
@ SKIP_STORE_RESULT
Definition: ad9361.h:3318
gpo_control::gpo1_slave_rx_en
bool gpo1_slave_rx_en
Definition: ad9361.h:3107
DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD
#define DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD(x)
Definition: ad9361.h:1405
REG_RF_DC_OFFSET_CONFIG_1
#define REG_RF_DC_OFFSET_CONFIG_1
Definition: ad9361.h:342
REG_REF_DIVIDE_CONFIG_1
#define REG_REF_DIVIDE_CONFIG_1
Definition: ad9361.h:557
BUFFERED_XTALN_DCXO
@ BUFFERED_XTALN_DCXO
Definition: ad9361.h:3159
TX_MON_LOW_GAIN
#define TX_MON_LOW_GAIN(x)
Definition: ad9361.h:1035
ad9361_phy_platform_data::rf_tx_bandwidth_Hz
uint32_t rf_tx_bandwidth_Hz
Definition: ad9361.h:3202
REG_LVDS_INVERT_CTRL1
#define REG_LVDS_INVERT_CTRL1
Definition: ad9361.h:108
REG_GAIN_TABLE_WRITE_DATA2
#define REG_GAIN_TABLE_WRITE_DATA2
Definition: ad9361.h:271
REG_TX_FILTER_COEF_READ_DATA_2
#define REG_TX_FILTER_COEF_READ_DATA_2
Definition: ad9361.h:140
ad9361_phy_platform_data::ad9361_clkout_mode
enum ad9361_clkout ad9361_clkout_mode
Definition: ad9361.h:3209
ad9361_set_tx_atten
int32_t ad9361_set_tx_atten(struct ad9361_rf_phy *phy, uint32_t atten_mdb, bool tx1, bool tx2, bool immed)
Definition: ad9361.c:1614
GAIN_CHANGE_OCCURS
@ GAIN_CHANGE_OCCURS
Definition: ad9361.h:3044
ad9361_rf_phy::gpio_desc_cal_sw1
struct no_os_gpio_desc * gpio_desc_cal_sw1
Definition: ad9361.h:3345
TX_REFCLK
@ TX_REFCLK
Definition: ad9361.h:3269
ad9361_set_ensm_mode
int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
Definition: ad9361.c:4880
gain_control::f_agc_state_wait_time_ns
uint32_t f_agc_state_wait_time_ns
Definition: ad9361.h:2981
DCXO_TUNE_FINE_LOW
#define DCXO_TUNE_FINE_LOW(x)
Definition: ad9361.h:2641
REG_OUTER_POWER_THRESHS
#define REG_OUTER_POWER_THRESHS
Definition: ad9361.h:265
ad9361_rf_phy::bypass_rx_fir
bool bypass_rx_fir
Definition: ad9361.h:3386
have_tdd_tables
const bool have_tdd_tables
Definition: ad9361.c:62
ad9361_clk_factor_set_rate
int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6511
REG_RX_VCO_BIAS_1
#define REG_RX_VCO_BIAS_1
Definition: ad9361.h:484
ad9361_ensm_restore_prev_state
void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:2096
ad9361_phy_platform_data::rx1tx1_mode_use_rx_num
uint32_t rx1tx1_mode_use_rx_num
Definition: ad9361.h:3194
RF_GAIN_MGC
@ RF_GAIN_MGC
Definition: ad9361.h:2908
gain_control::f_agc_lock_level_lmt_gain_increase_en
bool f_agc_lock_level_lmt_gain_increase_en
Definition: ad9361.h:2989
ENTERS_RX_MODE
@ ENTERS_RX_MODE
Definition: ad9361.h:3043
VCO_CAL_OFFSET
#define VCO_CAL_OFFSET(x)
Definition: ad9361.h:2458
ENSM_STATE_RX
#define ENSM_STATE_RX
Definition: ad9361.h:765
REG_ANALOG_POWER_DOWN_OVERRIDE
#define REG_ANALOG_POWER_DOWN_OVERRIDE
Definition: ad9361.h:132
RX_BB_TUNE_CAL
#define RX_BB_TUNE_CAL
Definition: ad9361.h:746
ENABLE_DEC_PWR_MEAS
#define ENABLE_DEC_PWR_MEAS
Definition: ad9361.h:1747
BIST_CTRL_POINT
#define BIST_CTRL_POINT(x)
Definition: ad9361.h:2773
REG_RX_LO_GEN_POWER_MODE
#define REG_RX_LO_GEN_POWER_MODE
Definition: ad9361.h:505
MAX_BBPLL_FREQ
#define MAX_BBPLL_FREQ
Definition: ad9361.h:2824
ad9361_synth_lo_powerdown
int ad9361_synth_lo_powerdown(struct ad9361_rf_phy *phy, enum synth_pd_ctrl rx, enum synth_pd_ctrl tx)
Definition: ad9361.c:3440
ad9361_tx_mute
int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state)
Definition: ad9361.c:1678
DEFAULT_RSSI_MEAS_MODE
#define DEFAULT_RSSI_MEAS_MODE
Definition: ad9361.h:1732
gain_control::dig_saturation_exceed_counter
uint8_t dig_saturation_exceed_counter
Definition: ad9361.h:2969
ad9361_validate_rf_bw
uint32_t ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, uint32_t bw)
Definition: ad9361.c:912
REG_GPO3_TX_DELAY
#define REG_GPO3_TX_DELAY
Definition: ad9361.h:97
SETTLE_MAIN_ENABLE
#define SETTLE_MAIN_ENABLE
Definition: ad9361.h:1139
ad9361_update_rf_bandwidth
int32_t ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t rf_rx_bw, uint32_t rf_tx_bw)
Definition: ad9361.c:5688
ad9361_rf_phy::bist_tone_level_dB
uint32_t bist_tone_level_dB
Definition: ad9361.h:3415
REG_GAIN_STP_CONFIG_2
#define REG_GAIN_STP_CONFIG_2
Definition: ad9361.h:237
ad9361_bist_prbs
int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode)
Definition: ad9361.c:1156
READ_SELECT
#define READ_SELECT
Definition: ad9361.h:1686
ad9361_clk_factor_recalc_rate
uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6459
ad9361_rfpll_dummy_set_rate
int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:6965
ENABLE_TRACKING_MODE_CH1
#define ENABLE_TRACKING_MODE_CH1
Definition: ad9361.h:1772
FORCE_TX_ON
#define FORCE_TX_ON
Definition: ad9361.h:724
gain_control::agc_outer_thresh_low
uint8_t agc_outer_thresh_low
Definition: ad9361.h:2956
ad9361_phy_platform_data::rf_rx_bandwidth_Hz
uint32_t rf_rx_bandwidth_Hz
Definition: ad9361.h:3201
VCO_CAL_REF_TCF
#define VCO_CAL_REF_TCF(x)
Definition: ad9144.h:949
refclk_scale::source
enum ad9361_clocks source
Definition: ad9361.h:3425
ad9361_setup
int32_t ad9361_setup(struct ad9361_rf_phy *phy)
Definition: ad9361.c:5333
REG_RX_FORCE_ALC
#define REG_RX_FORCE_ALC
Definition: ad9361.h:472
FORCE_PD_RESET_RX1
#define FORCE_PD_RESET_RX1
Definition: ad9361.h:1418
REG_RX1_MANUAL_LMT_FULL_GAIN
#define REG_RX1_MANUAL_LMT_FULL_GAIN
Definition: ad9361.h:240
gain_control::lmt_overload_low_thresh
uint16_t lmt_overload_low_thresh
Definition: ad9361.h:2931
FORCE_ALERT_STATE
#define FORCE_ALERT_STATE
Definition: ad9361.h:727
TX_LO_POWER_DOWN
#define TX_LO_POWER_DOWN
Definition: ad9361.h:953
refclk_scale::spi
struct no_os_spi_desc * spi
Definition: ad9361.h:3421
CORRECTION_WORD_DECIMATION_M
#define CORRECTION_WORD_DECIMATION_M(x)
Definition: ad9361.h:1795
TX_MON_DURATION
#define TX_MON_DURATION(x)
Definition: ad9361.h:1060
RX_REF_DIVIDER_MSB
#define RX_REF_DIVIDER_MSB
Definition: ad9361.h:2703
REG_RSSI_WEIGHT_1
#define REG_RSSI_WEIGHT_1
Definition: ad9361.h:298
ad9361_phy_platform_data::rx1rx2_phase_inversion_en
bool rx1rx2_phase_inversion_en
Definition: ad9361.h:3180
ad9361_rf_phy::rx_fir_dec
uint8_t rx_fir_dec
Definition: ad9361.h:3396
ad9361_get_bist_prbs
void ad9361_get_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode)
Definition: ad9361.c:1187
ad9361_fastlock::entry
struct ad9361_fastlock_entry entry[2][8]
Definition: ad9361.h:3310
ad9361_phy_platform_data::gpo_ctrl
struct gpo_control gpo_ctrl
Definition: ad9361.h:3218
TX_NCO_FREQ
#define TX_NCO_FREQ(x)
Definition: ad9361.h:1159
ad9361_rfpll_int_recalc_rate
uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6748
ad9361_phy_platform_data::auxadc_ctrl
struct auxadc_control auxadc_ctrl
Definition: ad9361.h:3216
ad9361_get_bist_tone
void ad9361_get_bist_tone(struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode, uint32_t *freq_Hz, uint32_t *level_dB, uint32_t *mask)
Definition: ad9361.c:1260
REG_MAX_LMT_FULL_GAIN
#define REG_MAX_LMT_FULL_GAIN
Definition: ad9361.h:229
ad9361_fastlock_recall
int32_t ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
Definition: ad9361.c:5143
SynthLUT::VCO_Varactor
uint8_t VCO_Varactor
Definition: ad9361.h:3246
ad9361_rf_phy::gpio_desc_resetb
struct no_os_gpio_desc * gpio_desc_resetb
Definition: ad9361.h:3343
REG_GAIN_TABLE_CONFIG
#define REG_GAIN_TABLE_CONFIG
Definition: ad9361.h:276
ad9361_rf_phy::auto_cal_en
bool auto_cal_en
Definition: ad9361.h:3370
ad9361_clkout
ad9361_clkout
Definition: ad9361.h:3157
rf_rx_gain::mixer_index
uint32_t mixer_index
Definition: ad9361.h:3232
REG_BB_DC_OFFSET_ATTEN
#define REG_BB_DC_OFFSET_ATTEN
Definition: ad9361.h:352
T2_CLK
@ T2_CLK
Definition: ad9361.h:3277
TX_BB_TUNE_CAL
#define TX_BB_TUNE_CAL
Definition: ad9361.h:747
ad9361_bist_loopback
int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode)
Definition: ad9361.c:1097
ad9361_load_fir_filter_coef
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Definition: ad9361.c:5799
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Definition: ad9361.h:3130
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Definition: ad9361.h:762
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Definition: ad9361.h:617
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Definition: ad9361.h:2948
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Definition: ad9361.h:424
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Definition: ad9361.h:3228
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Definition: ad9361.h:601
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Definition: ad9361.h:292
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Definition: ad9361.h:100
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Definition: ad9361.h:2806
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Definition: ad9361.h:707
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Definition: ad9361.h:67
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Definition: ad9361.h:633
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Definition: ad9361.h:3203
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Definition: ad9361.h:2895
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Definition: ad9361.h:185
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Definition: ad9361.c:7393
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Definition: ad9361.h:3423
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Definition: ad9361.h:126
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Definition: ad9361.h:2688
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Definition: ad9361.h:3124
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Definition: ad9361.c:2350
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Definition: ad9361.h:301
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Definition: ad9361_util.c:67
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Definition: ad9361.h:2646
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Definition: ad9361.h:476
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