no-OS
ad9361_api.h
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1 /***************************************************************************/
39 #ifndef AD9361_API_H_
40 #define AD9361_API_H_
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include "ad9361_util.h"
46 #include "no_os_gpio.h"
47 #include "no_os_spi.h"
48 
49 /******************************************************************************/
50 /*************************** Types Declarations *******************************/
51 /******************************************************************************/
52 typedef struct {
53  /* Device selection */
54  enum dev_id dev_sel;
55  /* Reference Clock */
57  /* Base Configuration */
58  uint8_t two_rx_two_tx_mode_enable; /* adi,2rx-2tx-mode-enable */
59  uint8_t one_rx_one_tx_mode_use_rx_num; /* adi,1rx-1tx-mode-use-rx-num */
60  uint8_t one_rx_one_tx_mode_use_tx_num; /* adi,1rx-1tx-mode-use-tx-num */
61  uint8_t frequency_division_duplex_mode_enable; /* adi,frequency-division-duplex-mode-enable */
62  uint8_t frequency_division_duplex_independent_mode_enable; /* adi,frequency-division-duplex-independent-mode-enable */
63  uint8_t tdd_use_dual_synth_mode_enable; /* adi,tdd-use-dual-synth-mode-enable */
64  uint8_t tdd_skip_vco_cal_enable; /* adi,tdd-skip-vco-cal-enable */
65  uint32_t tx_fastlock_delay_ns; /* adi,tx-fastlock-delay-ns */
66  uint32_t rx_fastlock_delay_ns; /* adi,rx-fastlock-delay-ns */
67  uint8_t rx_fastlock_pincontrol_enable; /* adi,rx-fastlock-pincontrol-enable */
68  uint8_t tx_fastlock_pincontrol_enable; /* adi,tx-fastlock-pincontrol-enable */
69  uint8_t external_rx_lo_enable; /* adi,external-rx-lo-enable */
70  uint8_t external_tx_lo_enable; /* adi,external-tx-lo-enable */
71  uint8_t dc_offset_tracking_update_event_mask; /* adi,dc-offset-tracking-update-event-mask */
72  uint8_t dc_offset_attenuation_high_range; /* adi,dc-offset-attenuation-high-range */
73  uint8_t dc_offset_attenuation_low_range; /* adi,dc-offset-attenuation-low-range */
74  uint8_t dc_offset_count_high_range; /* adi,dc-offset-count-high-range */
75  uint8_t dc_offset_count_low_range; /* adi,dc-offset-count-low-range */
76  uint8_t split_gain_table_mode_enable; /* adi,split-gain-table-mode-enable */
77  uint32_t trx_synthesizer_target_fref_overwrite_hz; /* adi,trx-synthesizer-target-fref-overwrite-hz */
78  uint8_t qec_tracking_slow_mode_enable; /* adi,qec-tracking-slow-mode-enable */
79  /* ENSM Control */
80  uint8_t ensm_enable_pin_pulse_mode_enable; /* adi,ensm-enable-pin-pulse-mode-enable */
81  uint8_t ensm_enable_txnrx_control_enable; /* adi,ensm-enable-txnrx-control-enable */
82  /* LO Control */
83  uint64_t rx_synthesizer_frequency_hz; /* adi,rx-synthesizer-frequency-hz */
84  uint64_t tx_synthesizer_frequency_hz; /* adi,tx-synthesizer-frequency-hz */
85  uint8_t tx_lo_powerdown_managed_enable; /* adi,tx-lo-powerdown-managed-enable */
86  /* Rate & BW Control */
87  uint32_t rx_path_clock_frequencies[6]; /* adi,rx-path-clock-frequencies */
88  uint32_t tx_path_clock_frequencies[6]; /* adi,tx-path-clock-frequencies */
89  uint32_t rf_rx_bandwidth_hz; /* adi,rf-rx-bandwidth-hz */
90  uint32_t rf_tx_bandwidth_hz; /* adi,rf-tx-bandwidth-hz */
91  /* RF Port Control */
92  uint32_t rx_rf_port_input_select; /* adi,rx-rf-port-input-select */
93  uint32_t tx_rf_port_input_select; /* adi,tx-rf-port-input-select */
94  /* TX Attenuation Control */
95  int32_t tx_attenuation_mdB; /* adi,tx-attenuation-mdB */
96  uint8_t update_tx_gain_in_alert_enable; /* adi,update-tx-gain-in-alert-enable */
97  /* Reference Clock Control */
98  uint8_t xo_disable_use_ext_refclk_enable; /* adi,xo-disable-use-ext-refclk-enable */
99  uint32_t dcxo_coarse_and_fine_tune[2]; /* adi,dcxo-coarse-and-fine-tune */
100  uint32_t clk_output_mode_select; /* adi,clk-output-mode-select */
101  /* Gain Control */
102  uint8_t gc_rx1_mode; /* adi,gc-rx1-mode */
103  uint8_t gc_rx2_mode; /* adi,gc-rx2-mode */
104  uint8_t gc_adc_large_overload_thresh; /* adi,gc-adc-large-overload-thresh */
105  uint8_t gc_adc_ovr_sample_size; /* adi,gc-adc-ovr-sample-size */
106  uint8_t gc_adc_small_overload_thresh; /* adi,gc-adc-small-overload-thresh */
107  uint16_t gc_dec_pow_measurement_duration; /* adi,gc-dec-pow-measurement-duration */
108  uint8_t gc_dig_gain_enable; /* adi,gc-dig-gain-enable */
109  uint16_t gc_lmt_overload_high_thresh; /* adi,gc-lmt-overload-high-thresh */
110  uint16_t gc_lmt_overload_low_thresh; /* adi,gc-lmt-overload-low-thresh */
111  uint8_t gc_low_power_thresh; /* adi,gc-low-power-thresh */
112  uint8_t gc_max_dig_gain; /* adi,gc-max-dig-gain */
113  uint8_t gc_use_rx_fir_out_for_dec_pwr_meas_enable; /* adi,gc-use-rx-fir-out-for-dec-pwr-meas-enable */
114  /* Gain MGC Control */
115  uint8_t mgc_dec_gain_step; /* adi,mgc-dec-gain-step */
116  uint8_t mgc_inc_gain_step; /* adi,mgc-inc-gain-step */
117  uint8_t mgc_rx1_ctrl_inp_enable; /* adi,mgc-rx1-ctrl-inp-enable */
118  uint8_t mgc_rx2_ctrl_inp_enable; /* adi,mgc-rx2-ctrl-inp-enable */
119  uint8_t mgc_split_table_ctrl_inp_gain_mode; /* adi,mgc-split-table-ctrl-inp-gain-mode */
120  /* Gain AGC Control */
121  uint8_t agc_adc_large_overload_exceed_counter; /* adi,agc-adc-large-overload-exceed-counter */
122  uint8_t agc_adc_large_overload_inc_steps; /* adi,agc-adc-large-overload-inc-steps - Name is misleading should be dec-steps*/
123  uint8_t agc_adc_lmt_small_overload_prevent_gain_inc_enable; /* adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable */
124  uint8_t agc_adc_small_overload_exceed_counter; /* adi,agc-adc-small-overload-exceed-counter */
125  uint8_t agc_dig_gain_step_size; /* adi,agc-dig-gain-step-size */
126  uint8_t agc_dig_saturation_exceed_counter; /* adi,agc-dig-saturation-exceed-counter */
127  uint32_t agc_gain_update_interval_us; /* adi,agc-gain-update-interval-us */
128  uint8_t agc_immed_gain_change_if_large_adc_overload_enable; /* adi,agc-immed-gain-change-if-large-adc-overload-enable */
129  uint8_t agc_immed_gain_change_if_large_lmt_overload_enable; /* adi,agc-immed-gain-change-if-large-lmt-overload-enable */
130  uint8_t agc_inner_thresh_high; /* adi,agc-inner-thresh-high */
131  uint8_t agc_inner_thresh_high_dec_steps; /* adi,agc-inner-thresh-high-dec-steps */
132  uint8_t agc_inner_thresh_low; /* adi,agc-inner-thresh-low */
133  uint8_t agc_inner_thresh_low_inc_steps; /* adi,agc-inner-thresh-low-inc-steps */
134  uint8_t agc_lmt_overload_large_exceed_counter; /* adi,agc-lmt-overload-large-exceed-counter */
135  uint8_t agc_lmt_overload_large_inc_steps; /* adi,agc-lmt-overload-large-inc-steps */
136  uint8_t agc_lmt_overload_small_exceed_counter; /* adi,agc-lmt-overload-small-exceed-counter */
137  uint8_t agc_outer_thresh_high; /* adi,agc-outer-thresh-high */
138  uint8_t agc_outer_thresh_high_dec_steps; /* adi,agc-outer-thresh-high-dec-steps */
139  uint8_t agc_outer_thresh_low; /* adi,agc-outer-thresh-low */
140  uint8_t agc_outer_thresh_low_inc_steps; /* adi,agc-outer-thresh-low-inc-steps */
141  uint32_t agc_attack_delay_extra_margin_us; /* adi,agc-attack-delay-extra-margin-us */
142  uint8_t agc_sync_for_gain_counter_enable; /* adi,agc-sync-for-gain-counter-enable */
143  /* Fast AGC */
144  uint32_t fagc_dec_pow_measuremnt_duration; /* adi,fagc-dec-pow-measurement-duration */
145  uint32_t fagc_state_wait_time_ns; /* adi,fagc-state-wait-time-ns */
146  /* Fast AGC - Low Power */
147  uint8_t fagc_allow_agc_gain_increase; /* adi,fagc-allow-agc-gain-increase-enable */
148  uint32_t fagc_lp_thresh_increment_time; /* adi,fagc-lp-thresh-increment-time */
149  uint32_t fagc_lp_thresh_increment_steps; /* adi,fagc-lp-thresh-increment-steps */
150  /* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */
151  uint8_t fagc_lock_level_lmt_gain_increase_en; /* adi,fagc-lock-level-lmt-gain-increase-enable */
152  uint32_t fagc_lock_level_gain_increase_upper_limit; /* adi,fagc-lock-level-gain-increase-upper-limit */
153  /* Fast AGC - Peak Detectors and Final Settling */
154  uint32_t fagc_lpf_final_settling_steps; /* adi,fagc-lpf-final-settling-steps */
155  uint32_t fagc_lmt_final_settling_steps; /* adi,fagc-lmt-final-settling-steps */
156  uint32_t fagc_final_overrange_count; /* adi,fagc-final-overrange-count */
157  /* Fast AGC - Final Power Test */
158  uint8_t fagc_gain_increase_after_gain_lock_en; /* adi,fagc-gain-increase-after-gain-lock-enable */
159  /* Fast AGC - Unlocking the Gain */
160  uint32_t fagc_gain_index_type_after_exit_rx_mode; /* adi,fagc-gain-index-type-after-exit-rx-mode */
161  uint8_t fagc_use_last_lock_level_for_set_gain_en; /* adi,fagc-use-last-lock-level-for-set-gain-enable */
162  uint8_t fagc_rst_gla_stronger_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable */
163  uint32_t fagc_optimized_gain_offset; /* adi,fagc-optimized-gain-offset */
164  uint32_t fagc_rst_gla_stronger_sig_thresh_above_ll; /* adi,fagc-rst-gla-stronger-sig-thresh-above-ll */
165  uint8_t fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable */
166  uint8_t fagc_rst_gla_engergy_lost_goto_optim_gain_en; /* adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable */
167  uint32_t fagc_rst_gla_engergy_lost_sig_thresh_below_ll; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll */
168  uint32_t fagc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt */
169  uint8_t fagc_rst_gla_large_adc_overload_en; /* adi,fagc-rst-gla-large-adc-overload-enable */
170  uint8_t fagc_rst_gla_large_lmt_overload_en; /* adi,fagc-rst-gla-large-lmt-overload-enable */
171  uint8_t fagc_rst_gla_en_agc_pulled_high_en; /* adi,fagc-rst-gla-en-agc-pulled-high-enable */
172  uint32_t fagc_rst_gla_if_en_agc_pulled_high_mode; /* adi,fagc-rst-gla-if-en-agc-pulled-high-mode */
173  uint32_t fagc_power_measurement_duration_in_state5; /* adi,fagc-power-measurement-duration-in-state5 */
174  uint32_t fagc_large_overload_inc_steps; /* adi,fagc-adc-large-overload-inc-steps - Name is misleading should be dec-steps */
175  /* RSSI Control */
176  uint32_t rssi_delay; /* adi,rssi-delay */
177  uint32_t rssi_duration; /* adi,rssi-duration */
178  uint8_t rssi_restart_mode; /* adi,rssi-restart-mode */
179  uint8_t rssi_unit_is_rx_samples_enable; /* adi,rssi-unit-is-rx-samples-enable */
180  uint32_t rssi_wait; /* adi,rssi-wait */
181  /* Aux ADC Control */
182  uint32_t aux_adc_decimation; /* adi,aux-adc-decimation */
183  uint32_t aux_adc_rate; /* adi,aux-adc-rate */
184  /* AuxDAC Control */
185  uint8_t aux_dac_manual_mode_enable; /* adi,aux-dac-manual-mode-enable */
186  uint32_t aux_dac1_default_value_mV; /* adi,aux-dac1-default-value-mV */
187  uint8_t aux_dac1_active_in_rx_enable; /* adi,aux-dac1-active-in-rx-enable */
188  uint8_t aux_dac1_active_in_tx_enable; /* adi,aux-dac1-active-in-tx-enable */
189  uint8_t aux_dac1_active_in_alert_enable; /* adi,aux-dac1-active-in-alert-enable */
190  uint32_t aux_dac1_rx_delay_us; /* adi,aux-dac1-rx-delay-us */
191  uint32_t aux_dac1_tx_delay_us; /* adi,aux-dac1-tx-delay-us */
192  uint32_t aux_dac2_default_value_mV; /* adi,aux-dac2-default-value-mV */
193  uint8_t aux_dac2_active_in_rx_enable; /* adi,aux-dac2-active-in-rx-enable */
194  uint8_t aux_dac2_active_in_tx_enable; /* adi,aux-dac2-active-in-tx-enable */
195  uint8_t aux_dac2_active_in_alert_enable; /* adi,aux-dac2-active-in-alert-enable */
196  uint32_t aux_dac2_rx_delay_us; /* adi,aux-dac2-rx-delay-us */
197  uint32_t aux_dac2_tx_delay_us; /* adi,aux-dac2-tx-delay-us */
198  /* Temperature Sensor Control */
199  uint32_t temp_sense_decimation; /* adi,temp-sense-decimation */
200  uint16_t temp_sense_measurement_interval_ms; /* adi,temp-sense-measurement-interval-ms */
201  int8_t temp_sense_offset_signed; /* adi,temp-sense-offset-signed */
202  uint8_t temp_sense_periodic_measurement_enable; /* adi,temp-sense-periodic-measurement-enable */
203  /* Control Out Setup */
204  uint8_t ctrl_outs_enable_mask; /* adi,ctrl-outs-enable-mask */
205  uint8_t ctrl_outs_index; /* adi,ctrl-outs-index */
206  /* External LNA Control */
207  uint32_t elna_settling_delay_ns; /* adi,elna-settling-delay-ns */
208  uint32_t elna_gain_mdB; /* adi,elna-gain-mdB */
209  uint32_t elna_bypass_loss_mdB; /* adi,elna-bypass-loss-mdB */
210  uint8_t elna_rx1_gpo0_control_enable; /* adi,elna-rx1-gpo0-control-enable */
211  uint8_t elna_rx2_gpo1_control_enable; /* adi,elna-rx2-gpo1-control-enable */
212  uint8_t elna_gaintable_all_index_enable; /* adi,elna-gaintable-all-index-enable */
213  /* Digital Interface Control */
214  uint8_t digital_interface_tune_skip_mode; /* adi,digital-interface-tune-skip-mode */
215  uint8_t digital_interface_tune_fir_disable; /* adi,digital-interface-tune-fir-disable */
216  uint8_t pp_tx_swap_enable; /* adi,pp-tx-swap-enable */
217  uint8_t pp_rx_swap_enable; /* adi,pp-rx-swap-enable */
218  uint8_t tx_channel_swap_enable; /* adi,tx-channel-swap-enable */
219  uint8_t rx_channel_swap_enable; /* adi,rx-channel-swap-enable */
220  uint8_t rx_frame_pulse_mode_enable; /* adi,rx-frame-pulse-mode-enable */
221  uint8_t two_t_two_r_timing_enable; /* adi,2t2r-timing-enable */
222  uint8_t invert_data_bus_enable; /* adi,invert-data-bus-enable */
223  uint8_t invert_data_clk_enable; /* adi,invert-data-clk-enable */
224  uint8_t fdd_alt_word_order_enable; /* adi,fdd-alt-word-order-enable */
225  uint8_t invert_rx_frame_enable; /* adi,invert-rx-frame-enable */
226  uint8_t fdd_rx_rate_2tx_enable; /* adi,fdd-rx-rate-2tx-enable */
227  uint8_t swap_ports_enable; /* adi,swap-ports-enable */
228  uint8_t single_data_rate_enable; /* adi,single-data-rate-enable */
229  uint8_t lvds_mode_enable; /* adi,lvds-mode-enable */
230  uint8_t half_duplex_mode_enable; /* adi,half-duplex-mode-enable */
231  uint8_t single_port_mode_enable; /* adi,single-port-mode-enable */
232  uint8_t full_port_enable; /* adi,full-port-enable */
233  uint8_t full_duplex_swap_bits_enable; /* adi,full-duplex-swap-bits-enable */
234  uint32_t delay_rx_data; /* adi,delay-rx-data */
235  uint32_t rx_data_clock_delay; /* adi,rx-data-clock-delay */
236  uint32_t rx_data_delay; /* adi,rx-data-delay */
237  uint32_t tx_fb_clock_delay; /* adi,tx-fb-clock-delay */
238  uint32_t tx_data_delay; /* adi,tx-data-delay */
239  uint32_t lvds_bias_mV; /* adi,lvds-bias-mV */
240  uint8_t lvds_rx_onchip_termination_enable; /* adi,lvds-rx-onchip-termination-enable */
241  uint8_t rx1rx2_phase_inversion_en; /* adi,rx1-rx2-phase-inversion-enable */
242  uint8_t lvds_invert1_control; /* adi,lvds-invert1-control */
243  uint8_t lvds_invert2_control; /* adi,lvds-invert2-control */
244  /* GPO Control */
245  uint8_t gpo_manual_mode_enable; /* adi,gpo-manual-mode-enable */
246  uint32_t gpo_manual_mode_enable_mask; /* adi,gpo-manual-mode-enable-mask */
247  uint8_t gpo0_inactive_state_high_enable; /* adi,gpo0-inactive-state-high-enable */
248  uint8_t gpo1_inactive_state_high_enable; /* adi,gpo1-inactive-state-high-enable */
249  uint8_t gpo2_inactive_state_high_enable; /* adi,gpo2-inactive-state-high-enable */
250  uint8_t gpo3_inactive_state_high_enable; /* adi,gpo3-inactive-state-high-enable */
251  uint8_t gpo0_slave_rx_enable; /* adi,gpo0-slave-rx-enable */
252  uint8_t gpo0_slave_tx_enable; /* adi,gpo0-slave-tx-enable */
253  uint8_t gpo1_slave_rx_enable; /* adi,gpo1-slave-rx-enable */
254  uint8_t gpo1_slave_tx_enable; /* adi,gpo1-slave-tx-enable */
255  uint8_t gpo2_slave_rx_enable; /* adi,gpo2-slave-rx-enable */
256  uint8_t gpo2_slave_tx_enable; /* adi,gpo2-slave-tx-enable */
257  uint8_t gpo3_slave_rx_enable; /* adi,gpo3-slave-rx-enable */
258  uint8_t gpo3_slave_tx_enable; /* adi,gpo3-slave-tx-enable */
259  uint8_t gpo0_rx_delay_us; /* adi,gpo0-rx-delay-us */
260  uint8_t gpo0_tx_delay_us; /* adi,gpo0-tx-delay-us */
261  uint8_t gpo1_rx_delay_us; /* adi,gpo1-rx-delay-us */
262  uint8_t gpo1_tx_delay_us; /* adi,gpo1-tx-delay-us */
263  uint8_t gpo2_rx_delay_us; /* adi,gpo2-rx-delay-us */
264  uint8_t gpo2_tx_delay_us; /* adi,gpo2-tx-delay-us */
265  uint8_t gpo3_rx_delay_us; /* adi,gpo3-rx-delay-us */
266  uint8_t gpo3_tx_delay_us; /* adi,gpo3-tx-delay-us */
267  /* Tx Monitor Control */
268  uint32_t low_high_gain_threshold_mdB; /* adi,txmon-low-high-thresh */
269  uint32_t low_gain_dB; /* adi,txmon-low-gain */
270  uint32_t high_gain_dB; /* adi,txmon-high-gain */
271  uint8_t tx_mon_track_en; /* adi,txmon-dc-tracking-enable */
272  uint8_t one_shot_mode_en; /* adi,txmon-one-shot-mode-enable */
273  uint32_t tx_mon_delay; /* adi,txmon-delay */
274  uint32_t tx_mon_duration; /* adi,txmon-duration */
275  uint32_t tx1_mon_front_end_gain; /* adi,txmon-1-front-end-gain */
276  uint32_t tx2_mon_front_end_gain; /* adi,txmon-2-front-end-gain */
277  uint32_t tx1_mon_lo_cm; /* adi,txmon-1-lo-cm */
278  uint32_t tx2_mon_lo_cm; /* adi,txmon-2-lo-cm */
279  /* GPIO definitions */
280  struct no_os_gpio_init_param gpio_resetb; /* reset-gpios */
281  /* MCS Sync */
282  struct no_os_gpio_init_param gpio_sync; /* sync-gpios */
283  struct no_os_gpio_init_param gpio_cal_sw1; /* cal-sw1-gpios */
284  struct no_os_gpio_init_param gpio_cal_sw2; /* cal-sw2-gpios */
285 
286  struct no_os_spi_init_param spi_param;
287 
288  /* External LO clocks */
289  uint32_t (*ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv);
290  int32_t (*ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv,
291  uint32_t rate);
292  int32_t (*ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv,
293  uint32_t rate);
294 #ifndef AXI_ADC_NOT_PRESENT
297 #endif
299 
300 typedef struct {
301  uint32_t rx; /* 1, 2, 3(both) */
302  int32_t rx_gain; /* -12, -6, 0, 6 */
303  uint32_t rx_dec; /* 1, 2, 4 */
304  int16_t rx_coef[128];
305  uint8_t rx_coef_size;
306  uint32_t rx_path_clks[6];
307  uint32_t rx_bandwidth;
309 
310 typedef struct {
311  uint32_t tx; /* 1, 2, 3(both) */
312  int32_t tx_gain; /* -6, 0 */
313  uint32_t tx_int; /* 1, 2, 4 */
314  int16_t tx_coef[128];
315  uint8_t tx_coef_size;
316  uint32_t tx_path_clks[6];
317  uint32_t tx_bandwidth;
319 
329 };
330 
331 #define ENABLE 1
332 #define DISABLE 0
333 
334 #define RX1 0
335 #define RX2 1
336 
337 #define TX1 0
338 #define TX2 1
339 
340 #define A_BALANCED 0
341 #define B_BALANCED 1
342 #define C_BALANCED 2
343 #define A_N 3
344 #define A_P 4
345 #define B_N 5
346 #define B_P 6
347 #define C_N 7
348 #define C_P 8
349 #define TX_MON1 9
350 #define TX_MON2 10
351 #define TX_MON1_2 11
352 
353 #define TXA 0
354 #define TXB 1
355 
356 #define MODE_1x1 1
357 #define MODE_2x2 2
358 
359 #define HIGHEST_OSR 0
360 #define NOMINAL_OSR 1
361 
362 #define INT_LO 0
363 #define EXT_LO 1
364 
365 #define ON 0
366 #define OFF 1
367 
368 /******************************************************************************/
369 /************************ Functions Declarations ******************************/
370 /******************************************************************************/
371 /* Initialize the AD9361 part. */
372 int32_t ad9361_init (struct ad9361_rf_phy **ad9361_phy,
374 /* Free the allocated resources. */
375 int32_t ad9361_remove(struct ad9361_rf_phy *phy);
376 /* Set the Enable State Machine (ENSM) mode. */
378  uint32_t mode);
379 /* Get the Enable State Machine (ENSM) mode. */
381  uint32_t *mode);
382 /* Set the receive RF gain for the selected channel. */
383 int32_t ad9361_set_rx_rf_gain (struct ad9361_rf_phy *phy, uint8_t ch,
384  int32_t gain_db);
385 /* Get current receive RF gain for the selected channel. */
386 int32_t ad9361_get_rx_rf_gain (struct ad9361_rf_phy *phy, uint8_t ch,
387  int32_t *gain_db);
388 /* Set the RX RF bandwidth. */
389 int32_t ad9361_set_rx_rf_bandwidth (struct ad9361_rf_phy *phy,
390  uint32_t bandwidth_hz);
391 /* Get the RX RF bandwidth. */
392 int32_t ad9361_get_rx_rf_bandwidth (struct ad9361_rf_phy *phy,
393  uint32_t *bandwidth_hz);
394 /* Set the RX sampling frequency. */
395 int32_t ad9361_set_rx_sampling_freq (struct ad9361_rf_phy *phy,
396  uint32_t sampling_freq_hz);
397 /* Get current RX sampling frequency. */
398 int32_t ad9361_get_rx_sampling_freq (struct ad9361_rf_phy *phy,
399  uint32_t *sampling_freq_hz);
400 /* Set the RX LO frequency. */
401 int32_t ad9361_set_rx_lo_freq (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz);
402 /* Get current RX LO frequency. */
403 int32_t ad9361_get_rx_lo_freq (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz);
404 /* Switch between internal and external LO. */
405 int32_t ad9361_set_rx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext);
406 /* Get the RSSI for the selected channel. */
407 int32_t ad9361_get_rx_rssi (struct ad9361_rf_phy *phy, uint8_t ch,
408  struct rf_rssi *rssi);
409 /* Set the gain control mode for the selected channel. */
410 int32_t ad9361_set_rx_gain_control_mode (struct ad9361_rf_phy *phy, uint8_t ch,
411  uint8_t gc_mode);
412 /* Get the gain control mode for the selected channel. */
413 int32_t ad9361_get_rx_gain_control_mode (struct ad9361_rf_phy *phy, uint8_t ch,
414  uint8_t *gc_mode);
415 /* Set the RX FIR filter configuration. */
416 int32_t ad9361_set_rx_fir_config (struct ad9361_rf_phy *phy,
417  AD9361_RXFIRConfig fir_cfg);
418 /* Get the RX FIR filter configuration. */
419 int32_t ad9361_get_rx_fir_config(struct ad9361_rf_phy *phy, uint8_t rx_ch,
420  AD9361_RXFIRConfig *fir_cfg);
421 /* Enable/disable the RX FIR filter. */
422 int32_t ad9361_set_rx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis);
423 /* Get the status of the RX FIR filter. */
424 int32_t ad9361_get_rx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis);
425 /* Enable/disable the RX RFDC Tracking. */
427  uint8_t en_dis);
428 /* Get the status of the RX RFDC Tracking. */
430  uint8_t *en_dis);
431 /* Enable/disable the RX BasebandDC Tracking. */
433  uint8_t en_dis);
434 /* Get the status of the RX BasebandDC Tracking. */
436  uint8_t *en_dis);
437 /* Enable/disable the RX Quadrature Tracking. */
439  uint8_t en_dis);
440 /* Get the status of the RX Quadrature Tracking. */
442  uint8_t *en_dis);
443 /* Set the RX RF input port. */
444 int32_t ad9361_set_rx_rf_port_input (struct ad9361_rf_phy *phy, uint32_t mode);
445 /* Get the selected RX RF input port. */
446 int32_t ad9361_get_rx_rf_port_input (struct ad9361_rf_phy *phy, uint32_t *mode);
447 /* Store RX fastlock profile. */
448 int32_t ad9361_rx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile);
449 /* Recall RX fastlock profile. */
450 int32_t ad9361_rx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile);
451 /* Load RX fastlock profile. */
452 int32_t ad9361_rx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile,
453  uint8_t *values);
454 /* Save RX fastlock profile. */
455 int32_t ad9361_rx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile,
456  uint8_t *values);
457 /* Power down the RX Local Oscillator. */
458 int32_t ad9361_rx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option);
459 /* Get the RX Local Oscillator power status. */
460 int32_t ad9361_get_rx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option);
461 /* Set the transmit attenuation for the selected channel. */
462 int32_t ad9361_set_tx_attenuation (struct ad9361_rf_phy *phy, uint8_t ch,
463  uint32_t attenuation_mdb);
464 /* Get current transmit attenuation for the selected channel. */
465 int32_t ad9361_get_tx_attenuation (struct ad9361_rf_phy *phy, uint8_t ch,
466  uint32_t *attenuation_mdb);
467 /* Set the TX RF bandwidth. */
468 int32_t ad9361_set_tx_rf_bandwidth (struct ad9361_rf_phy *phy,
469  uint32_t bandwidth_hz);
470 /* Get the TX RF bandwidth. */
471 int32_t ad9361_get_tx_rf_bandwidth (struct ad9361_rf_phy *phy,
472  uint32_t *bandwidth_hz);
473 /* Set the TX sampling frequency. */
474 int32_t ad9361_set_tx_sampling_freq (struct ad9361_rf_phy *phy,
475  uint32_t sampling_freq_hz);
476 /* Get current TX sampling frequency. */
477 int32_t ad9361_get_tx_sampling_freq (struct ad9361_rf_phy *phy,
478  uint32_t *sampling_freq_hz);
479 /* Set the TX LO frequency. */
480 int32_t ad9361_set_tx_lo_freq (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz);
481 /* Get current TX LO frequency. */
482 int32_t ad9361_get_tx_lo_freq (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz);
483 /* Switch between internal and external LO. */
484 int32_t ad9361_set_tx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext);
485 /* Set the TX FIR filter configuration. */
486 int32_t ad9361_set_tx_fir_config (struct ad9361_rf_phy *phy,
487  AD9361_TXFIRConfig fir_cfg);
488 /* Get the TX FIR filter configuration. */
489 int32_t ad9361_get_tx_fir_config(struct ad9361_rf_phy *phy, uint8_t tx_ch,
490  AD9361_TXFIRConfig *fir_cfg);
491 /* Enable/disable the TX FIR filter. */
492 int32_t ad9361_set_tx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis);
493 /* Get the status of the TX FIR filter. */
494 int32_t ad9361_get_tx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis);
495 /* Get the TX RSSI for the selected channel. */
496 int32_t ad9361_get_tx_rssi (struct ad9361_rf_phy *phy, uint8_t ch,
497  uint32_t *rssi_db_x_1000);
498 /* Set the TX RF output port. */
499 int32_t ad9361_set_tx_rf_port_output (struct ad9361_rf_phy *phy, uint32_t mode);
500 /* Get the selected TX RF output port. */
501 int32_t ad9361_get_tx_rf_port_output (struct ad9361_rf_phy *phy,
502  uint32_t *mode);
503 /* Enable/disable the auto calibration. */
504 int32_t ad9361_set_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy,
505  uint8_t en_dis);
506 /* Get the status of the auto calibration flag. */
507 int32_t ad9361_get_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy,
508  uint8_t *en_dis);
509 /* Store TX fastlock profile. */
510 int32_t ad9361_tx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile);
511 /* Recall TX fastlock profile. */
512 int32_t ad9361_tx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile);
513 /* Load TX fastlock profile. */
514 int32_t ad9361_tx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile,
515  uint8_t *values);
516 /* Save TX fastlock profile. */
517 int32_t ad9361_tx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile,
518  uint8_t *values);
519 /* Power down the TX Local Oscillator. */
520 int32_t ad9361_tx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option);
521 /* Get the TX Local Oscillator power status. */
522 int32_t ad9361_get_tx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option);
523 /* Set the RX and TX path rates. */
524 int32_t ad9361_set_trx_path_clks(struct ad9361_rf_phy *phy,
525  uint32_t *rx_path_clks, uint32_t *tx_path_clks);
526 /* Get the RX and TX path rates. */
527 int32_t ad9361_get_trx_path_clks(struct ad9361_rf_phy *phy,
528  uint32_t *rx_path_clks, uint32_t *tx_path_clks);
529 /* Set the number of channels mode. */
530 int32_t ad9361_set_no_ch_mode(struct ad9361_rf_phy *phy, uint8_t no_ch_mode);
531 /* Do multi chip synchronization. */
532 int32_t ad9361_do_mcs(struct ad9361_rf_phy *phy_master,
533  struct ad9361_rf_phy *phy_slave);
534 /* Enable/disable the TRX FIR filters. */
535 int32_t ad9361_set_trx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis);
536 /* Set the OSR rate governor. */
537 int32_t ad9361_set_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t rate_gov);
538 /* Get the OSR rate governor. */
539 int32_t ad9361_get_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t *rate_gov);
540 /* Perform the selected calibration. */
541 int32_t ad9361_do_calib(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg);
542 /* Load and enable TRX FIR filters configurations. */
543 int32_t ad9361_trx_load_enable_fir(struct ad9361_rf_phy *phy,
544  AD9361_RXFIRConfig rx_fir_cfg,
545  AD9361_TXFIRConfig tx_fir_cfg);
546 /* Do DCXO coarse tuning. */
547 int32_t ad9361_do_dcxo_tune_coarse(struct ad9361_rf_phy *phy,
548  uint32_t coarse);
549 /* Do DCXO fine tuning. */
550 int32_t ad9361_do_dcxo_tune_fine(struct ad9361_rf_phy *phy,
551  uint32_t fine);
552 /* Get the temperature. */
553 int32_t ad9361_get_temperature(struct ad9361_rf_phy *phy,
554  int32_t *temp);
555 #endif
axiadc_state::pcore_version
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Definition: ad9361_util.h:85
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Definition: ad9361.c:740
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Definition: ad9361_api.h:118
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Definition: ad9361_api.c:1854
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Definition: ad9361.h:2814
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Definition: ad9361.h:3329
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Definition: ad9361.c:5199
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Definition: ad9361.h:1026
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@ ENSM_MODE_RX
Definition: ad9361_api.h:322
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Definition: ad9361_api.c:1677
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Definition: ad9361.h:3409
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Definition: ad9361_api.c:2213
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Definition: ad9361_api.h:215
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Definition: ad9361.h:862
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Definition: ad9361_api.h:130
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Definition: ad9361_api.h:68
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Definition: ad9361_api.h:127
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Definition: ad9361_api.c:1806
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Definition: ad9361_api.h:274
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Definition: ad9361.c:1014
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Header file of SPI Interface.
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Definition: ad9361.c:7258
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uint32_t low_gain_dB
Definition: ad9361_api.h:269
AD9361_InitParam::agc_lmt_overload_small_exceed_counter
uint8_t agc_lmt_overload_small_exceed_counter
Definition: ad9361_api.h:136
ctrl_outs_control::index
uint8_t index
Definition: ad9361.h:3076
fir_dest
fir_dest
Definition: ad9361.h:2892
auxdac_control::dac2_in_rx_en
bool dac2_in_rx_en
Definition: ad9361.h:3030
AD9361_InitParam::mgc_split_table_ctrl_inp_gain_mode
uint8_t mgc_split_table_ctrl_inp_gain_mode
Definition: ad9361_api.h:119
AD9361_InitParam::gpo3_inactive_state_high_enable
uint8_t gpo3_inactive_state_high_enable
Definition: ad9361_api.h:250
gain_control::f_agc_rst_gla_engergy_lost_sig_thresh_below_ll
uint8_t f_agc_rst_gla_engergy_lost_sig_thresh_below_ll
Definition: ad9361.h:3007
AD9361_InitParam::tx_synthesizer_frequency_hz
uint64_t tx_synthesizer_frequency_hz
Definition: ad9361_api.h:84
ad9361_set_tx_rf_bandwidth
int32_t ad9361_set_tx_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t bandwidth_hz)
Definition: ad9361_api.c:1423
gain_control::lmt_overload_small_exceed_counter
uint8_t lmt_overload_small_exceed_counter
Definition: ad9361.h:2966
AD9361_InitParam::gpo0_tx_delay_us
uint8_t gpo0_tx_delay_us
Definition: ad9361_api.h:260
AD9361_InitParam::gc_dec_pow_measurement_duration
uint16_t gc_dec_pow_measurement_duration
Definition: ad9361_api.h:107
elna_control::elna_in_gaintable_all_index_en
bool elna_in_gaintable_all_index_en
Definition: ad9361.h:3086
ad9361_trx_load_enable_fir
int32_t ad9361_trx_load_enable_fir(struct ad9361_rf_phy *phy, AD9361_RXFIRConfig rx_fir_cfg, AD9361_TXFIRConfig tx_fir_cfg)
Definition: ad9361_api.c:2129
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uint8_t adc_ovr_sample_size
Definition: ad9361.h:2926
ad9361_do_calib
int32_t ad9361_do_calib(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg)
Definition: ad9361_api.c:2115
AD9361_InitParam::dc_offset_tracking_update_event_mask
uint8_t dc_offset_tracking_update_event_mask
Definition: ad9361_api.h:71
AD9361_InitParam::fdd_alt_word_order_enable
uint8_t fdd_alt_word_order_enable
Definition: ad9361_api.h:224
axi_adc_init
AXI ADC Initialization Parameters structure.
Definition: axi_adc_core.h:142
ad9361_set_no_ch_mode
int32_t ad9361_set_no_ch_mode(struct ad9361_rf_phy *phy, uint8_t no_ch_mode)
Definition: ad9361_api.c:1922
T1_CLK
@ T1_CLK
Definition: ad9361.h:3278
ad9361_set_rx_gain_control_mode
int32_t ad9361_set_rx_gain_control_mode(struct ad9361_rf_phy *phy, uint8_t ch, uint8_t gc_mode)
Definition: ad9361_api.c:956
AD9361_InitParam::ensm_enable_txnrx_control_enable
uint8_t ensm_enable_txnrx_control_enable
Definition: ad9361_api.h:81
AD9361_InitParam
Definition: ad9361_api.h:52
gpo_control::gpo_manual_mode_en
bool gpo_manual_mode_en
Definition: ad9361.h:3100
AD9361_InitParam::high_gain_dB
uint32_t high_gain_dB
Definition: ad9361_api.h:270
ad9361_rf_phy::rfdc_track_en
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Definition: ad9361.h:3399
ad9361_get_en_state_machine_mode
int32_t ad9361_get_en_state_machine_mode(struct ad9361_rf_phy *phy, uint32_t *mode)
Definition: ad9361_api.c:674
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Definition: ad9361.c:699
ad9361_get_tx_lo_power
int32_t ad9361_get_tx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option)
Definition: ad9361_api.c:1865
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bool elna_1_control_en
Definition: ad9361.h:3084
AD9361_InitParam::fdd_rx_rate_2tx_enable
uint8_t fdd_rx_rate_2tx_enable
Definition: ad9361_api.h:226
AD9361_InitParam::tx_channel_swap_enable
uint8_t tx_channel_swap_enable
Definition: ad9361_api.h:218
AD9361_InitParam::full_port_enable
uint8_t full_port_enable
Definition: ad9361_api.h:232
ad9361_get_rx_fir_config
int32_t ad9361_get_rx_fir_config(struct ad9361_rf_phy *phy, uint8_t rx_ch, AD9361_RXFIRConfig *fir_cfg)
Definition: ad9361_api.c:1017
AD9361_InitParam::tx1_mon_lo_cm
uint32_t tx1_mon_lo_cm
Definition: ad9361_api.h:277
ad9361_get_tx_attenuation
int32_t ad9361_get_tx_attenuation(struct ad9361_rf_phy *phy, uint8_t ch, uint32_t *attenuation_mdb)
Definition: ad9361_api.c:1397
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bool f_agc_rst_gla_engergy_lost_goto_optim_gain_en
Definition: ad9361.h:3006
ad9361_set_rx_sampling_freq
int32_t ad9361_set_rx_sampling_freq(struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz)
Definition: ad9361_api.c:823
ad9361_fastlock_load
int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition: ad9361.c:4970
gpo_control::gpo3_tx_delay_us
uint8_t gpo3_tx_delay_us
Definition: ad9361.h:3120
AD9361_InitParam::fagc_optimized_gain_offset
uint32_t fagc_optimized_gain_offset
Definition: ad9361_api.h:163
AD9361_InitParam::fagc_power_measurement_duration_in_state5
uint32_t fagc_power_measurement_duration_in_state5
Definition: ad9361_api.h:173
AD9361_InitParam::fagc_lp_thresh_increment_time
uint32_t fagc_lp_thresh_increment_time
Definition: ad9361_api.h:148
AD9361_InitParam::one_rx_one_tx_mode_use_rx_num
uint8_t one_rx_one_tx_mode_use_rx_num
Definition: ad9361_api.h:59
ad9361_get_tx_rf_bandwidth
int32_t ad9361_get_tx_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t *bandwidth_hz)
Definition: ad9361_api.c:1445
AD9361_InitParam::invert_data_bus_enable
uint8_t invert_data_bus_enable
Definition: ad9361_api.h:222
ad9361_get_temp
int32_t ad9361_get_temp(struct ad9361_rf_phy *phy)
Definition: ad9361.c:4186
auxadc_control::offset
int8_t offset
Definition: ad9361.h:3090
RX_LO_POWER_DOWN
#define RX_LO_POWER_DOWN
Definition: ad9361.h:944
AD9361_InitParam::invert_rx_frame_enable
uint8_t invert_rx_frame_enable
Definition: ad9361_api.h:225
ad9361_rx_fastlock_store
int32_t ad9361_rx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile)
Definition: ad9361_api.c:1276
ID_AD9364
@ ID_AD9364
Definition: ad9361.h:3336
AD9361_InitParam::one_shot_mode_en
uint8_t one_shot_mode_en
Definition: ad9361_api.h:272
refclk_scale
Definition: ad9361.h:3420
AD9361_InitParam::gpo3_tx_delay_us
uint8_t gpo3_tx_delay_us
Definition: ad9361_api.h:266
auxdac_control::dac2_default_value
uint16_t dac2_default_value
Definition: ad9361.h:3022
ad9361_phy_platform_data::rf_dc_offset_count_low
uint8_t rf_dc_offset_count_low
Definition: ad9361.h:3186
no_os_delay.h
Header file of Delay functions.
rf_rssi::duration
uint8_t duration
Definition: ad9361.h:3240
ad9361_phy_platform_data::dig_interface_tune_skipmode
uint8_t dig_interface_tune_skipmode
Definition: ad9361.h:3187
TX_SAMPL_FREQ
@ TX_SAMPL_FREQ
Definition: ad9361.h:3153
AD9361_InitParam::rf_rx_bandwidth_hz
uint32_t rf_rx_bandwidth_hz
Definition: ad9361_api.h:89
AD9361_RXFIRConfig::rx_coef_size
uint8_t rx_coef_size
Definition: ad9361_api.h:305
PRODUCT_ID_9361
#define PRODUCT_ID_9361
Definition: ad9361.h:861
AD9361_InitParam::tx_data_delay
uint32_t tx_data_delay
Definition: ad9361_api.h:238
AD9361_InitParam::temp_sense_measurement_interval_ms
uint16_t temp_sense_measurement_interval_ms
Definition: ad9361_api.h:200
REG_TX_CLOCK_DATA_DELAY
#define REG_TX_CLOCK_DATA_DELAY
Definition: ad9361.h:58
AD9361_InitParam::update_tx_gain_in_alert_enable
uint8_t update_tx_gain_in_alert_enable
Definition: ad9361_api.h:96
ad9361_set_rx_lo_int_ext
int32_t ad9361_set_rx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext)
Definition: ad9361_api.c:902
ad9361_get_rx_sampling_freq
int32_t ad9361_get_rx_sampling_freq(struct ad9361_rf_phy *phy, uint32_t *sampling_freq_hz)
Definition: ad9361_api.c:848
ad9361_get_rx_rf_gain
int32_t ad9361_get_rx_rf_gain(struct ad9361_rf_phy *phy, uint8_t ch, int32_t *gain_db)
Definition: ad9361_api.c:759
ad9361_phy_platform_data::dig_interface_tune_fir_disable
uint8_t dig_interface_tune_fir_disable
Definition: ad9361.h:3188
ad9361_rf_phy::agc_mode
uint8_t agc_mode[2]
Definition: ad9361.h:3398
gpo_control::gpo0_tx_delay_us
uint8_t gpo0_tx_delay_us
Definition: ad9361.h:3114
AD9361_InitParam::fagc_rst_gla_if_en_agc_pulled_high_mode
uint32_t fagc_rst_gla_if_en_agc_pulled_high_mode
Definition: ad9361_api.h:172
no_os_clk
Definition: no_os_clk.h:59
AD9361_InitParam::gc_lmt_overload_high_thresh
uint16_t gc_lmt_overload_high_thresh
Definition: ad9361_api.h:109
ad9361_do_mcs
int32_t ad9361_do_mcs(struct ad9361_rf_phy *phy_master, struct ad9361_rf_phy *phy_slave)
Definition: ad9361_api.c:2005
gpo_control::gpo3_slave_tx_en
bool gpo3_slave_tx_en
Definition: ad9361.h:3112
ad9361_remove
int32_t ad9361_remove(struct ad9361_rf_phy *phy)
Definition: ad9361_api.c:586
gpo_control::gpo_manual_mode_enable_mask
uint32_t gpo_manual_mode_enable_mask
Definition: ad9361.h:3099
TX_DATA_DELAY
#define TX_DATA_DELAY(x)
Definition: ad9361.h:645
ad9361_rf_phy::spi
struct no_os_spi_desc * spi
Definition: ad9361.h:3342
AD9361_InitParam::fagc_use_last_lock_level_for_set_gain_en
uint8_t fagc_use_last_lock_level_for_set_gain_en
Definition: ad9361_api.h:161
ad9361_get_rx_rf_bandwidth
int32_t ad9361_get_rx_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t *bandwidth_hz)
Definition: ad9361_api.c:805
ad9361_set_tx_lo_int_ext
int32_t ad9361_set_tx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext)
Definition: ad9361_api.c:1542
ENSM_STATE_SLEEP_WAIT
#define ENSM_STATE_SLEEP_WAIT
Definition: ad9361.h:761
gain_control::f_agc_optimized_gain_offset
uint8_t f_agc_optimized_gain_offset
Definition: ad9361.h:3002
ad9361_phy_platform_data::tx_fastlock_delay_ns
uint32_t tx_fastlock_delay_ns
Definition: ad9361.h:3206
AD9361_InitParam::gpo3_slave_rx_enable
uint8_t gpo3_slave_rx_enable
Definition: ad9361_api.h:257
ad9361_do_dcxo_tune_fine
int32_t ad9361_do_dcxo_tune_fine(struct ad9361_rf_phy *phy, uint32_t fine)
Definition: ad9361_api.c:2198
ad9361_rf_port_setup
int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out, uint32_t rx_inputs, uint32_t txb)
Definition: ad9361.c:3609
AD9361_InitParam::rx_channel_swap_enable
uint8_t rx_channel_swap_enable
Definition: ad9361_api.h:219
port_control::rx_clk_data_delay
uint8_t rx_clk_data_delay
Definition: ad9361.h:3068
AD9361_InitParam::gpo1_slave_tx_enable
uint8_t gpo1_slave_tx_enable
Definition: ad9361_api.h:254
gpo_control::gpo2_rx_delay_us
uint8_t gpo2_rx_delay_us
Definition: ad9361.h:3117
AD9361_InitParam::elna_rx2_gpo1_control_enable
uint8_t elna_rx2_gpo1_control_enable
Definition: ad9361_api.h:211
_SOFT_RESET
#define _SOFT_RESET
Definition: ad9361.h:585
ad9361_tx_fastlock_load
int32_t ad9361_tx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)
Definition: ad9361_api.c:1823
ad9361_util.h
AD9361 Header file of Util driver.
ad9361_set_dcxo_tune
int32_t ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy, uint32_t coarse, uint32_t fine)
Definition: ad9361.c:3495
tx_monitor_control::tx1_mon_lo_cm
uint8_t tx1_mon_lo_cm
Definition: ad9361.h:3133
ad9361_clk_mux_set_parent
int32_t ad9361_clk_mux_set_parent(struct refclk_scale *clk_priv, uint8_t index)
Definition: ad9361.c:7121
axi_dac_core.h
Driver for the Analog Devices AXI-DAC-CORE module.
RX_RFPLL_DUMMY
@ RX_RFPLL_DUMMY
Definition: ad9361.h:3283
ad9361_rf_phy::clk_refin
struct no_os_clk * clk_refin
Definition: ad9361.h:3351
gain_control::mgc_inc_gain_step
uint8_t mgc_inc_gain_step
Definition: ad9361.h:2943
ad9361_1rx1tx_channel_map
int32_t ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx, int32_t channel)
Definition: ad9361.c:990
NO_OS_ARRAY_SIZE
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
ad9361_adi_gt_info
struct gain_table_info ad9361_adi_gt_info[]
Definition: ad9361.c:604
ad9361_rx_lo_powerdown
int32_t ad9361_rx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option)
Definition: ad9361_api.c:1339
AD9361_InitParam::fagc_gain_increase_after_gain_lock_en
uint8_t fagc_gain_increase_after_gain_lock_en
Definition: ad9361_api.h:158
ad9361_rf_phy::filt_tx_path_clks
uint32_t filt_tx_path_clks[NUM_TX_CLOCKS]
Definition: ad9361.h:3391
ad9361_rfpll_recalc_rate
uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:6980
AD9361_InitParam::invert_data_clk_enable
uint8_t invert_data_clk_enable
Definition: ad9361_api.h:223
ad9361_set_rx_rf_gain
int32_t ad9361_set_rx_rf_gain(struct ad9361_rf_phy *phy, uint8_t ch, int32_t gain_db)
Definition: ad9361_api.c:733
AD9361_InitParam::fagc_rst_gla_stronger_sig_thresh_above_ll
uint32_t fagc_rst_gla_stronger_sig_thresh_above_ll
Definition: ad9361_api.h:164
ENSM_STATE_TX
#define ENSM_STATE_TX
Definition: ad9361.h:763
ad9361_get_rx_fir_en_dis
int32_t ad9361_get_rx_fir_en_dis(struct ad9361_rf_phy *phy, uint8_t *en_dis)
Definition: ad9361_api.c:1097
AD9361_InitParam::full_duplex_swap_bits_enable
uint8_t full_duplex_swap_bits_enable
Definition: ad9361_api.h:233
zmalloc
void * zmalloc(size_t size)
zmalloc
Definition: ad9361_util.c:322
gain_control::f_agc_allow_agc_gain_increase
bool f_agc_allow_agc_gain_increase
Definition: ad9361.h:2983
AD9361_InitParam::external_rx_lo_enable
uint8_t external_rx_lo_enable
Definition: ad9361_api.h:69
AD9361_InitParam::ctrl_outs_enable_mask
uint8_t ctrl_outs_enable_mask
Definition: ad9361_api.h:204
RSSI_RESOLUTION
#define RSSI_RESOLUTION
Definition: ad9361.h:2815
AD9361_InitParam::tdd_use_dual_synth_mode_enable
uint8_t tdd_use_dual_synth_mode_enable
Definition: ad9361_api.h:63
ad9361_rx_fastlock_store
int32_t ad9361_rx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile)
Definition: ad9361_api.c:1276
gain_control::adc_large_overload_exceed_counter
uint8_t adc_large_overload_exceed_counter
Definition: ad9361.h:2960
BIST_DISABLE
@ BIST_DISABLE
Definition: ad9361.h:3323
AD9361_InitParam::aux_dac1_active_in_alert_enable
uint8_t aux_dac1_active_in_alert_enable
Definition: ad9361_api.h:189
ad9361_get_tx_auto_cal_en_dis
int32_t ad9361_get_tx_auto_cal_en_dis(struct ad9361_rf_phy *phy, uint8_t *en_dis)
Definition: ad9361_api.c:1773
ad9361_set_trx_clock_chain
int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4612
port_control::tx_clk_data_delay
uint8_t tx_clk_data_delay
Definition: ad9361.h:3069
ad9361_rx_fastlock_load
int32_t ad9361_rx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)
Definition: ad9361_api.c:1308
tx_monitor_control::tx_mon_delay
uint16_t tx_mon_delay
Definition: ad9361.h:3129
AD9361_InitParam::aux_dac2_default_value_mV
uint32_t aux_dac2_default_value_mV
Definition: ad9361_api.h:192
AD9361_InitParam::aux_dac1_default_value_mV
uint32_t aux_dac1_default_value_mV
Definition: ad9361_api.h:186
AD9361_InitParam::agc_adc_small_overload_exceed_counter
uint8_t agc_adc_small_overload_exceed_counter
Definition: ad9361_api.h:124
AD9361_InitParam::gpo2_inactive_state_high_enable
uint8_t gpo2_inactive_state_high_enable
Definition: ad9361_api.h:249
gain_control::adc_large_overload_thresh
uint8_t adc_large_overload_thresh
Definition: ad9361.h:2928
AD9361_InitParam::agc_outer_thresh_low_inc_steps
uint8_t agc_outer_thresh_low_inc_steps
Definition: ad9361_api.h:140
AD9361_InitParam::gc_dig_gain_enable
uint8_t gc_dig_gain_enable
Definition: ad9361_api.h:108
AD9361_InitParam::agc_inner_thresh_low
uint8_t agc_inner_thresh_low
Definition: ad9361_api.h:132
AD9361_InitParam::rssi_wait
uint32_t rssi_wait
Definition: ad9361_api.h:180
AD9361_InitParam::clk_output_mode_select
uint32_t clk_output_mode_select
Definition: ad9361_api.h:100
AD9361_InitParam::frequency_division_duplex_mode_enable
uint8_t frequency_division_duplex_mode_enable
Definition: ad9361_api.h:61
ad9361_set_en_state_machine_mode
int32_t ad9361_set_en_state_machine_mode(struct ad9361_rf_phy *phy, uint32_t mode)
Definition: ad9361_api.c:622
REG_STATE
#define REG_STATE
Definition: ad9361.h:73
ad9361_set_tx_fir_en_dis
int32_t ad9361_set_tx_fir_en_dis(struct ad9361_rf_phy *phy, uint8_t en_dis)
Definition: ad9361_api.c:1636
AD9361_InitParam::tx_attenuation_mdB
int32_t tx_attenuation_mdB
Definition: ad9361_api.h:95
ENSM_STATE_FDD
#define ENSM_STATE_FDD
Definition: ad9361.h:767
RX_SAMPL_CLK
@ RX_SAMPL_CLK
Definition: ad9361.h:3275
ad9361_set_rx_gain
int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition: ad9361.c:2197
AD9361_InitParam::tx2_mon_lo_cm
uint32_t tx2_mon_lo_cm
Definition: ad9361_api.h:278
AD9361_InitParam::rx_fastlock_pincontrol_enable
uint8_t rx_fastlock_pincontrol_enable
Definition: ad9361_api.h:67
ad9361_rf_phy::bist_prbs_mode
enum ad9361_bist_mode bist_prbs_mode
Definition: ad9361.h:3412
gain_control::agc_outer_thresh_high
uint8_t agc_outer_thresh_high
Definition: ad9361.h:2950
gain_control::f_agc_lmt_final_settling_steps
uint8_t f_agc_lmt_final_settling_steps
Definition: ad9361.h:2993
gain_control::mgc_rx1_ctrl_inp_en
bool mgc_rx1_ctrl_inp_en
Definition: ad9361.h:2940
AD9361_InitParam::reference_clk_rate
uint32_t reference_clk_rate
Definition: ad9361_api.h:56
ad9361_spi_write
int32_t ad9361_spi_write(struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)
Definition: ad9361.c:796
ad9361_get_trx_rate_gov
int32_t ad9361_get_trx_rate_gov(struct ad9361_rf_phy *phy, uint32_t *rate_gov)
Definition: ad9361_api.c:2096
ad9361_phy_platform_data::tx_path_clks
uint32_t tx_path_clks[NUM_TX_CLOCKS]
Definition: ad9361.h:3197
AD9361_InitParam::single_port_mode_enable
uint8_t single_port_mode_enable
Definition: ad9361_api.h:231
gain_control::f_agc_gain_index_type_after_exit_rx_mode
enum f_agc_target_gain_index_type f_agc_gain_index_type_after_exit_rx_mode
Definition: ad9361.h:2999
gain_control::f_agc_rst_gla_stronger_sig_thresh_exceeded_en
bool f_agc_rst_gla_stronger_sig_thresh_exceeded_en
Definition: ad9361.h:3003
TX_RFPLL
@ TX_RFPLL
Definition: ad9361.h:3286
ad9361_do_dcxo_tune_coarse
int32_t ad9361_do_dcxo_tune_coarse(struct ad9361_rf_phy *phy, uint32_t coarse)
Definition: ad9361_api.c:2183
gain_control::f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en
bool f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en
Definition: ad9361.h:3005
ad9361_phy_platform_data::tdd_skip_vco_cal
bool tdd_skip_vco_cal
Definition: ad9361.h:3177
gain_control::dig_gain_en
bool dig_gain_en
Definition: ad9361.h:2936
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
ad9361_phy_platform_data::dcxo_coarse
uint32_t dcxo_coarse
Definition: ad9361.h:3190
ad9361_phy_platform_data::auxdac_ctrl
struct auxdac_control auxdac_ctrl
Definition: ad9361.h:3217
AD9361_InitParam::digital_interface_tune_skip_mode
uint8_t digital_interface_tune_skip_mode
Definition: ad9361_api.h:214
ad9361_init
int32_t ad9361_init(struct ad9361_rf_phy **ad9361_phy, AD9361_InitParam *init_param)
Definition: ad9361_api.c:81
gpo_control::gpo0_slave_tx_en
bool gpo0_slave_tx_en
Definition: ad9361.h:3106
ad9361_set_tx_attenuation
int32_t ad9361_set_tx_attenuation(struct ad9361_rf_phy *phy, uint8_t ch, uint32_t attenuation_mdb)
Definition: ad9361_api.c:1371
ad9361_post_setup
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
Definition: ad9361_conv.c:605
ad9361_get_tx_fir_config
int32_t ad9361_get_tx_fir_config(struct ad9361_rf_phy *phy, uint8_t tx_ch, AD9361_TXFIRConfig *fir_cfg)
Definition: ad9361_api.c:1584
AD9361_InitParam::fagc_large_overload_inc_steps
uint32_t fagc_large_overload_inc_steps
Definition: ad9361_api.h:174
AD9361_InitParam::lvds_mode_enable
uint8_t lvds_mode_enable
Definition: ad9361_api.h:229
AD9361_InitParam::external_tx_lo_enable
uint8_t external_tx_lo_enable
Definition: ad9361_api.h:70
ad9361_tx_fastlock_recall
int32_t ad9361_tx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile)
Definition: ad9361_api.c:1806
auxdac_control::dac1_default_value
uint16_t dac1_default_value
Definition: ad9361.h:3021
AD9361_InitParam::mgc_rx1_ctrl_inp_enable
uint8_t mgc_rx1_ctrl_inp_enable
Definition: ad9361_api.h:117
ad9361_get_rx_lo_freq
int32_t ad9361_get_rx_lo_freq(struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz)
Definition: ad9361_api.c:884
ad9361_phy_platform_data::update_tx_gain_via_alert
bool update_tx_gain_via_alert
Definition: ad9361.h:3204
ENSM_MODE_PINCTRL_FDD_INDEP
@ ENSM_MODE_PINCTRL_FDD_INDEP
Definition: ad9361_api.h:328
AD9361_InitParam::gpo2_tx_delay_us
uint8_t gpo2_tx_delay_us
Definition: ad9361_api.h:264
ad9361.h
Header file of AD9361 Driver.
ad9361_get_tx_fir_config
int32_t ad9361_get_tx_fir_config(struct ad9361_rf_phy *phy, uint8_t tx_ch, AD9361_TXFIRConfig *fir_cfg)
Definition: ad9361_api.c:1584
ID_AD9363A
@ ID_AD9363A
Definition: ad9361.h:3337
FB_CLK_DELAY
#define FB_CLK_DELAY(x)
Definition: ad9361.h:644
REG_TX_FILTER_COEF_ADDR
#define REG_TX_FILTER_COEF_ADDR
Definition: ad9361.h:136
RX_REFCLK
@ RX_REFCLK
Definition: ad9361.h:3268
SOFT_RESET
@ SOFT_RESET
Definition: ad738x.h:138
AD9361_InitParam::aux_dac2_tx_delay_us
uint32_t aux_dac2_tx_delay_us
Definition: ad9361_api.h:197
axiadc_chip_info
Definition: ad9361_util.h:88
ad9361_ensm_mode
ad9361_ensm_mode
Definition: ad9361_api.h:320
AD9361_InitParam::agc_immed_gain_change_if_large_lmt_overload_enable
uint8_t agc_immed_gain_change_if_large_lmt_overload_enable
Definition: ad9361_api.h:129
ad9361_get_tx_fir_en_dis
int32_t ad9361_get_tx_fir_en_dis(struct ad9361_rf_phy *phy, uint8_t *en_dis)
Definition: ad9361_api.c:1659
REG_RX_FILTER_COEF_ADDR
#define REG_RX_FILTER_COEF_ADDR
Definition: ad9361.h:219
ad9361_phy_platform_data::rf_tx_output_sel
uint32_t rf_tx_output_sel
Definition: ad9361.h:3193
ad9361_rf_phy::filt_rx_path_clks
uint32_t filt_rx_path_clks[NUM_RX_CLOCKS]
Definition: ad9361.h:3390
rf_gain_ctrl_mode
rf_gain_ctrl_mode
Definition: ad9361.h:2907
ENSM_MODE_SLEEP
@ ENSM_MODE_SLEEP
Definition: ad9361_api.h:326
axiadc_state
Definition: ad9361_util.h:83
ad9361_get_tx_rf_port_output
int32_t ad9361_get_tx_rf_port_output(struct ad9361_rf_phy *phy, uint32_t *mode)
Definition: ad9361_api.c:1739
gpo_control::gpo1_slave_rx_en
bool gpo1_slave_rx_en
Definition: ad9361.h:3107
AD9361_InitParam::gc_rx2_mode
uint8_t gc_rx2_mode
Definition: ad9361_api.h:103
AD9361_InitParam::dc_offset_count_high_range
uint8_t dc_offset_count_high_range
Definition: ad9361_api.h:74
ad9361_set_trx_fir_en_dis
int32_t ad9361_set_trx_fir_en_dis(struct ad9361_rf_phy *phy, uint8_t en_dis)
Definition: ad9361_api.c:2051
AD9361_RXFIRConfig
Definition: ad9361_api.h:300
AD9361_InitParam::tx_mon_track_en
uint8_t tx_mon_track_en
Definition: ad9361_api.h:271
ad9361_phy_platform_data::rf_tx_bandwidth_Hz
uint32_t rf_tx_bandwidth_Hz
Definition: ad9361.h:3202
ad9361_tx_fastlock_store
int32_t ad9361_tx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile)
Definition: ad9361_api.c:1791
AD9361_InitParam::tdd_skip_vco_cal_enable
uint8_t tdd_skip_vco_cal_enable
Definition: ad9361_api.h:64
REG_TX_FILTER_COEF_READ_DATA_2
#define REG_TX_FILTER_COEF_READ_DATA_2
Definition: ad9361.h:140
ad9361_phy_platform_data::ad9361_clkout_mode
enum ad9361_clkout ad9361_clkout_mode
Definition: ad9361.h:3209
ad9361_do_dcxo_tune_coarse
int32_t ad9361_do_dcxo_tune_coarse(struct ad9361_rf_phy *phy, uint32_t coarse)
Definition: ad9361_api.c:2183
AD9361_InitParam::aux_dac1_tx_delay_us
uint32_t aux_dac1_tx_delay_us
Definition: ad9361_api.h:191
AD9361_InitParam::aux_dac1_active_in_tx_enable
uint8_t aux_dac1_active_in_tx_enable
Definition: ad9361_api.h:188
ad9361_rf_phy::gpio_desc_cal_sw1
struct no_os_gpio_desc * gpio_desc_cal_sw1
Definition: ad9361.h:3345
TX_REFCLK
@ TX_REFCLK
Definition: ad9361.h:3269
ad9361_get_tx_rssi
int32_t ad9361_get_tx_rssi(struct ad9361_rf_phy *phy, uint8_t ch, uint32_t *rssi_db_x_1000)
Definition: ad9361_api.c:1677
ad9361_set_ensm_mode
int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
Definition: ad9361.c:4880
gain_control::f_agc_state_wait_time_ns
uint32_t f_agc_state_wait_time_ns
Definition: ad9361.h:2981
ad9361_rf_phy::bypass_rx_fir
bool bypass_rx_fir
Definition: ad9361.h:3386
ad9361_set_tx_lo_freq
int32_t ad9361_set_tx_lo_freq(struct ad9361_rf_phy *phy, uint64_t lo_freq_hz)
Definition: ad9361_api.c:1507
AD9361_InitParam::elna_rx1_gpo0_control_enable
uint8_t elna_rx1_gpo0_control_enable
Definition: ad9361_api.h:210
axi_adc_read
int32_t axi_adc_read(struct axi_adc *adc, uint32_t reg_addr, uint32_t *reg_data)
AXI ADC Data read.
Definition: axi_adc_core.c:59
ad9361_phy_platform_data::rx1tx1_mode_use_rx_num
uint32_t rx1tx1_mode_use_rx_num
Definition: ad9361.h:3194
gain_control::f_agc_lock_level_lmt_gain_increase_en
bool f_agc_lock_level_lmt_gain_increase_en
Definition: ad9361.h:2989
ENSM_STATE_RX
#define ENSM_STATE_RX
Definition: ad9361.h:765
AD9361_InitParam::frequency_division_duplex_independent_mode_enable
uint8_t frequency_division_duplex_independent_mode_enable
Definition: ad9361_api.h:62
ad9361_synth_lo_powerdown
int ad9361_synth_lo_powerdown(struct ad9361_rf_phy *phy, enum synth_pd_ctrl rx, enum synth_pd_ctrl tx)
Definition: ad9361.c:3440
AD9361_InitParam::fagc_lock_level_gain_increase_upper_limit
uint32_t fagc_lock_level_gain_increase_upper_limit
Definition: ad9361_api.h:152
gain_control::dig_saturation_exceed_counter
uint8_t dig_saturation_exceed_counter
Definition: ad9361.h:2969
ad9361_set_rx_quad_track_en_dis
int32_t ad9361_set_rx_quad_track_en_dis(struct ad9361_rf_phy *phy, uint8_t en_dis)
Definition: ad9361_api.c:1190
ad9361_rf_phy::bist_tone_level_dB
uint32_t bist_tone_level_dB
Definition: ad9361.h:3415
ad9361_clk_factor_recalc_rate
uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6459
AD9361_TXFIRConfig::tx_gain
int32_t tx_gain
Definition: ad9361_api.h:312
ad9361_get_rx_lo_freq
int32_t ad9361_get_rx_lo_freq(struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz)
Definition: ad9361_api.c:884
gain_control::agc_outer_thresh_low
uint8_t agc_outer_thresh_low
Definition: ad9361.h:2956
ad9361_set_no_ch_mode
int32_t ad9361_set_no_ch_mode(struct ad9361_rf_phy *phy, uint8_t no_ch_mode)
Definition: ad9361_api.c:1922
ad9361_phy_platform_data::rf_rx_bandwidth_Hz
uint32_t rf_rx_bandwidth_Hz
Definition: ad9361.h:3201
ad9361_setup
int32_t ad9361_setup(struct ad9361_rf_phy *phy)
Definition: ad9361.c:5333
gain_control::lmt_overload_low_thresh
uint16_t lmt_overload_low_thresh
Definition: ad9361.h:2931
TX_LO_POWER_DOWN
#define TX_LO_POWER_DOWN
Definition: ad9361.h:953
ad9361_get_en_state_machine_mode
int32_t ad9361_get_en_state_machine_mode(struct ad9361_rf_phy *phy, uint32_t *mode)
Definition: ad9361_api.c:674
ad9361_phy_platform_data::rx1rx2_phase_inversion_en
bool rx1rx2_phase_inversion_en
Definition: ad9361.h:3180
ad9361_get_rx_rf_gain
int32_t ad9361_get_rx_rf_gain(struct ad9361_rf_phy *phy, uint8_t ch, int32_t *gain_db)
Definition: ad9361_api.c:759
ad9361_rf_phy::rx_fir_dec
uint8_t rx_fir_dec
Definition: ad9361.h:3396
ad9361_rx_fastlock_save
int32_t ad9361_rx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)
Definition: ad9361_api.c:1324
ad9361_phy_platform_data::gpo_ctrl
struct gpo_control gpo_ctrl
Definition: ad9361.h:3218
ad9361_rfpll_int_recalc_rate
uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6748
ad9361_phy_platform_data::auxadc_ctrl
struct auxadc_control auxadc_ctrl
Definition: ad9361.h:3216
AD9361_InitParam::agc_sync_for_gain_counter_enable
uint8_t agc_sync_for_gain_counter_enable
Definition: ad9361_api.h:142
ad9361_set_en_state_machine_mode
int32_t ad9361_set_en_state_machine_mode(struct ad9361_rf_phy *phy, uint32_t mode)
Definition: ad9361_api.c:622
ad9361_get_tx_lo_freq
int32_t ad9361_get_tx_lo_freq(struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz)
Definition: ad9361_api.c:1524
ON
#define ON
Definition: ad9361_api.h:365
ad9361_rf_phy::gpio_desc_resetb
struct no_os_gpio_desc * gpio_desc_resetb
Definition: ad9361.h:3343
AD9361_InitParam::rx_fastlock_delay_ns
uint32_t rx_fastlock_delay_ns
Definition: ad9361_api.h:66
AD9361_InitParam::aux_dac2_active_in_rx_enable
uint8_t aux_dac2_active_in_rx_enable
Definition: ad9361_api.h:193
ad9361_set_rx_lo_freq
int32_t ad9361_set_rx_lo_freq(struct ad9361_rf_phy *phy, uint64_t lo_freq_hz)
Definition: ad9361_api.c:867
ad9361_rf_phy::auto_cal_en
bool auto_cal_en
Definition: ad9361.h:3370
ad9361_clkout
ad9361_clkout
Definition: ad9361.h:3157
AD9361_InitParam::gc_low_power_thresh
uint8_t gc_low_power_thresh
Definition: ad9361_api.h:111
T2_CLK
@ T2_CLK
Definition: ad9361.h:3277
ad9361_load_fir_filter_coef
int32_t ad9361_load_fir_filter_coef(struct ad9361_rf_phy *phy, enum fir_dest dest, int32_t gain_dB, uint32_t ntaps, int16_t *coef)
Definition: ad9361.c:5799
tx_monitor_control::tx_mon_duration
uint16_t tx_mon_duration
Definition: ad9361.h:3130
ENSM_STATE_ALERT
#define ENSM_STATE_ALERT
Definition: ad9361.h:762
gain_control::agc_attack_delay_extra_margin_us
uint8_t agc_attack_delay_extra_margin_us
Definition: ad9361.h:2948
gain_control::mgc_split_table_ctrl_inp_gain_mode
uint8_t mgc_split_table_ctrl_inp_gain_mode
Definition: ad9361.h:2945
ad9361_set_tx_fir_config
int32_t ad9361_set_tx_fir_config(struct ad9361_rf_phy *phy, AD9361_TXFIRConfig fir_cfg)
Definition: ad9361_api.c:1562
AD9361_InitParam::single_data_rate_enable
uint8_t single_data_rate_enable
Definition: ad9361_api.h:228
AD9361_InitParam::gpo0_slave_rx_enable
uint8_t gpo0_slave_rx_enable
Definition: ad9361_api.h:251
ad9361_phy_platform_data::tx_atten
int32_t tx_atten
Definition: ad9361.h:3203
ad9361_rf_phy::rx_adc
struct axi_adc * rx_adc
Definition: ad9361.h:3348
tx_monitor_control::tx_mon_track_en
bool tx_mon_track_en
Definition: ad9361.h:3124
AD9361_InitParam::gc_lmt_overload_low_thresh
uint16_t gc_lmt_overload_low_thresh
Definition: ad9361_api.h:110
ad9361_set_gain_ctrl_mode
int32_t ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy, struct rf_gain_ctrl *gain_ctrl)
Definition: ad9361.c:2350
PRODUCT_ID_MASK
#define PRODUCT_ID_MASK
Definition: ad9361.h:860
clk_get_rate
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv)
clk_get_rate
Definition: ad9361_util.c:67
AD9361_TXFIRConfig::tx
uint32_t tx
Definition: ad9361_api.h:311
ad9361_rf_phy::dev_sel
enum dev_id dev_sel
Definition: ad9361.h:3341
AD9361_InitParam::gpo3_slave_tx_enable
uint8_t gpo3_slave_tx_enable
Definition: ad9361_api.h:258
AD9361_InitParam::gpo0_rx_delay_us
uint8_t gpo0_rx_delay_us
Definition: ad9361_api.h:259
ad9361_get_rx_gain_control_mode
int32_t ad9361_get_rx_gain_control_mode(struct ad9361_rf_phy *phy, uint8_t ch, uint8_t *gc_mode)
Definition: ad9361_api.c:979
REG_RX_FILTER_CONFIG
#define REG_RX_FILTER_CONFIG
Definition: ad9361.h:224
AD9361_RXFIRConfig::rx_coef
int16_t rx_coef[128]
Definition: ad9361_api.h:304
ad9361_phy_platform_data::ensm_pin_pulse_mode
bool ensm_pin_pulse_mode
Definition: ad9361.h:3173
AD9361_InitParam::fagc_lp_thresh_increment_steps
uint32_t fagc_lp_thresh_increment_steps
Definition: ad9361_api.h:149
ad9361_tx_fastlock_save
int32_t ad9361_tx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)
Definition: ad9361_api.c:1839
gain_control::f_agc_lpf_final_settling_steps
uint8_t f_agc_lpf_final_settling_steps
Definition: ad9361.h:2992
AD9361_InitParam::agc_adc_lmt_small_overload_prevent_gain_inc_enable
uint8_t agc_adc_lmt_small_overload_prevent_gain_inc_enable
Definition: ad9361_api.h:123
ad9361_rf_phy::filt_rx_bw_Hz
uint32_t filt_rx_bw_Hz
Definition: ad9361.h:3392
gain_control::agc_inner_thresh_high
uint8_t agc_inner_thresh_high
Definition: ad9361.h:2952
AD9361_InitParam::rssi_duration
uint32_t rssi_duration
Definition: ad9361_api.h:177
AD9361_InitParam::tx_fastlock_delay_ns
uint32_t tx_fastlock_delay_ns
Definition: ad9361_api.h:65
ad9361_get_rx_fir_en_dis
int32_t ad9361_get_rx_fir_en_dis(struct ad9361_rf_phy *phy, uint8_t *en_dis)
Definition: ad9361_api.c:1097
ad9361_ensm_set_state
int32_t ad9361_ensm_set_state(struct ad9361_rf_phy *phy, uint8_t ensm_state, bool pinctrl)
Definition: ad9361.c:4406
ad9361_rf_phy::bist_tone_mode
enum ad9361_bist_mode bist_tone_mode
Definition: ad9361.h:3413
FILTER_GAIN
#define FILTER_GAIN(x)
Definition: ad9361.h:1341
LO_OFF
@ LO_OFF
Definition: ad9361.h:3330
AD9361_InitParam::agc_lmt_overload_large_inc_steps
uint8_t agc_lmt_overload_large_inc_steps
Definition: ad9361_api.h:135
ad9361_set_tx_attenuation
int32_t ad9361_set_tx_attenuation(struct ad9361_rf_phy *phy, uint8_t ch, uint32_t attenuation_mdb)
Definition: ad9361_api.c:1371
R2_CLK
@ R2_CLK
Definition: ad9361.h:3272
axi_dac_init
Definition: axi_dac_core.h:67
gain_control::agc_inner_thresh_high_dec_steps
uint8_t agc_inner_thresh_high_dec_steps
Definition: ad9361.h:2953
ad9361_phy_platform_data::use_ext_rx_lo
bool use_ext_rx_lo
Definition: ad9361.h:3178
AD9361_InitParam::rssi_restart_mode
uint8_t rssi_restart_mode
Definition: ad9361_api.h:178
rf_rx_gain::gain_db
int32_t gain_db
Definition: ad9361.h:3224
ad9361_set_rx_fir_config
int32_t ad9361_set_rx_fir_config(struct ad9361_rf_phy *phy, AD9361_RXFIRConfig fir_cfg)
Definition: ad9361_api.c:995
LO_ON
@ LO_ON
Definition: ad9361.h:3331
no_os_gpio_remove
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:95
ad9361_get_tx_auto_cal_en_dis
int32_t ad9361_get_tx_auto_cal_en_dis(struct ad9361_rf_phy *phy, uint8_t *en_dis)
Definition: ad9361_api.c:1773
AD9361_InitParam::elna_gain_mdB
uint32_t elna_gain_mdB
Definition: ad9361_api.h:208
ad9361_phy_platform_data::rx2tx2
bool rx2tx2
Definition: ad9361.h:3168
ad9361_rx_fastlock_load
int32_t ad9361_rx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)
Definition: ad9361_api.c:1308
auxdac_control::dac2_rx_delay_us
uint8_t dac2_rx_delay_us
Definition: ad9361.h:3036
rssi_restart_mode
rssi_restart_mode
Definition: ad9361.h:3040
AD9361_InitParam::qec_tracking_slow_mode_enable
uint8_t qec_tracking_slow_mode_enable
Definition: ad9361_api.h:78
AD9361_InitParam::rx_rf_port_input_select
uint32_t rx_rf_port_input_select
Definition: ad9361_api.h:92
gain_control::lmt_overload_high_thresh
uint16_t lmt_overload_high_thresh
Definition: ad9361.h:2930
ad9361_set_tx_sampling_freq
int32_t ad9361_set_tx_sampling_freq(struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz)
Definition: ad9361_api.c:1463
ad9361_rf_phy::ad9361_rfpll_ext_round_rate
int32_t(* ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.h:3355
ad9361_clear_state
void ad9361_clear_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:5274
gain_control::f_agc_lock_level_gain_increase_upper_limit
uint8_t f_agc_lock_level_gain_increase_upper_limit
Definition: ad9361.h:2990
auxadc_control::temp_sensor_decimation
uint32_t temp_sensor_decimation
Definition: ad9361.h:3092
auxdac_control::dac1_in_alert_en
bool dac1_in_alert_en
Definition: ad9361.h:3028
ad9361_get_rx_rf_bandwidth
int32_t ad9361_get_rx_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t *bandwidth_hz)
Definition: ad9361_api.c:805
ad9361_phy_platform_data::trx_fastlock_pinctrl_en
bool trx_fastlock_pinctrl_en[2]
Definition: ad9361.h:3207
gain_control::f_agc_rst_gla_large_adc_overload_en
bool f_agc_rst_gla_large_adc_overload_en
Definition: ad9361.h:3009
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Definition: ad9361.h:3340
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uint8_t f_agc_lp_thresh_increment_time
Definition: ad9361.h:2984
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@ FIR_IS_RX
Definition: ad9361.h:2899
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Definition: ad9361.h:3110
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Definition: ad9361_api.h:80
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Definition: ad9361_api.h:116
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Definition: ad9361_api.c:1291
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Definition: ad9361_api.h:179
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Definition: ad9361_api.h:316
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Definition: ad9361.h:3354
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Definition: ad9361_api.h:168
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Definition: ad9361.h:3382
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Definition: ad9361_api.c:1881
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Definition: ad9361.c:6055
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Definition: ad9361_api.h:75
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Definition: ad9361_api.h:155
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Definition: ad9361.h:3081
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Definition: ad9361_api.c:81
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Definition: ad9361_api.h:201
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Definition: ad9361_api.h:202
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Definition: ad9361_api.h:301
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Definition: ad9361_api.h:121
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Definition: ad9361.h:3176
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uint8_t gpo2_slave_rx_enable
Definition: ad9361_api.h:255
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Definition: ad9361.h:3094
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Definition: ad9361.h:3401
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Definition: ad9361_api.h:145
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Definition: ad9361.h:3394
ad9361_set_tx_rf_bandwidth
int32_t ad9361_set_tx_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t bandwidth_hz)
Definition: ad9361_api.c:1423
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Definition: ad9361.h:2883
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uint32_t gpo_manual_mode_enable_mask
Definition: ad9361_api.h:246
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Definition: ad9361.h:3091
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uint8_t dc_offset_attenuation_low
Definition: ad9361.h:3184
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Definition: ad9361.h:104
ad9361_phy_platform_data::elna_ctrl
struct elna_control elna_ctrl
Definition: ad9361.h:3215
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uint8_t mgc_dec_gain_step
Definition: ad9361.h:2944
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Definition: ad9361.h:3175
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int32_t ad9361_get_tx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option)
Definition: ad9361_api.c:1865
CLKTF_CLK
@ CLKTF_CLK
Definition: ad9361.h:3279
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int32_t ad9361_get_tx_rf_port_output(struct ad9361_rf_phy *phy, uint32_t *mode)
Definition: ad9361_api.c:1739
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Definition: ad9361.h:3126
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Definition: ad9361_api.c:1135
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int32_t ad9361_set_rx_rf_port_input(struct ad9361_rf_phy *phy, uint32_t mode)
Definition: ad9361_api.c:1238
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uint64_t rx_synth_freq
Definition: ad9361.h:3199
REG_RX_FILTER_COEF_READ_DATA_2
#define REG_RX_FILTER_COEF_READ_DATA_2
Definition: ad9361.h:223
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int32_t ad9361_get_rx_quad_track_en_dis(struct ad9361_rf_phy *phy, uint8_t *en_dis)
Definition: ad9361_api.c:1211
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struct refclk_scale * ref_clk_scale[NUM_AD9361_CLKS]
Definition: ad9361.h:3353
ad9361_to_clk
uint32_t ad9361_to_clk(uint64_t freq)
Definition: ad9361.c:1364
AD9361_InitParam::rx_synthesizer_frequency_hz
uint64_t rx_synthesizer_frequency_hz
Definition: ad9361_api.h:83
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uint8_t gc_max_dig_gain
Definition: ad9361_api.h:112
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int32_t no_os_gpio_get(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Obtain the GPIO decriptor.
Definition: no_os_gpio.c:55
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int32_t ad9361_set_tx_atten(struct ad9361_rf_phy *phy, uint32_t atten_mdb, bool tx1, bool tx2, bool immed)
Definition: ad9361.c:1614
AD9361_InitParam::agc_immed_gain_change_if_large_adc_overload_enable
uint8_t agc_immed_gain_change_if_large_adc_overload_enable
Definition: ad9361_api.h:128
RX_RFPLL
@ RX_RFPLL
Definition: ad9361.h:3285
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uint8_t lvds_rx_onchip_termination_enable
Definition: ad9361_api.h:240
AD9361_InitParam::aux_dac_manual_mode_enable
uint8_t aux_dac_manual_mode_enable
Definition: ad9361_api.h:185
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int16_t tx_coef[128]
Definition: ad9361_api.h:314
ad9361_tx_fastlock_load
int32_t ad9361_tx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)
Definition: ad9361_api.c:1823
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int32_t ad9361_do_calib(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg)
Definition: ad9361_api.c:2115
AD9361_InitParam::lvds_invert1_control
uint8_t lvds_invert1_control
Definition: ad9361_api.h:242
ad9361_get_rx_rssi
int32_t ad9361_get_rx_rssi(struct ad9361_rf_phy *phy, uint8_t ch, struct rf_rssi *rssi)
Definition: ad9361_api.c:926
AD9361_InitParam::tx1_mon_front_end_gain
uint32_t tx1_mon_front_end_gain
Definition: ad9361_api.h:275
DAC_CLK
@ DAC_CLK
Definition: ad9361.h:3276
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uint8_t fagc_rst_gla_stronger_sig_thresh_exceeded_en
Definition: ad9361_api.h:162
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uint8_t max_dig_gain
Definition: ad9361.h:2937
REG_TX_RSSI_LSB
#define REG_TX_RSSI_LSB
Definition: ad9361.h:148
gain_control::f_agc_rst_gla_en_agc_pulled_high_en
bool f_agc_rst_gla_en_agc_pulled_high_en
Definition: ad9361.h:3011
tx_monitor_control::tx2_mon_lo_cm
uint8_t tx2_mon_lo_cm
Definition: ad9361.h:3134
AD9364_DEVICE
#define AD9364_DEVICE
Definition: app_config.h:46
rssi_control::restart_mode
enum rssi_restart_mode restart_mode
Definition: ad9361.h:3050
AD9361_InitParam::elna_bypass_loss_mdB
uint32_t elna_bypass_loss_mdB
Definition: ad9361_api.h:209
ad9361_get_rx_gain_control_mode
int32_t ad9361_get_rx_gain_control_mode(struct ad9361_rf_phy *phy, uint8_t ch, uint8_t *gc_mode)
Definition: ad9361_api.c:979
ad9361_get_rx_lo_power
int32_t ad9361_get_rx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option)
Definition: ad9361_api.c:1350
ad9361_set_tx_rf_port_output
int32_t ad9361_set_tx_rf_port_output(struct ad9361_rf_phy *phy, uint32_t mode)
Definition: ad9361_api.c:1719
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struct gain_control gain_ctrl
Definition: ad9361.h:3211
ctrl_outs_control::en_mask
uint8_t en_mask
Definition: ad9361.h:3077
AD9361_TXFIRConfig
Definition: ad9361_api.h:310
rf_gain_ctrl::mode
uint8_t mode
Definition: ad9361.h:2904
auxdac_control::auxdac_manual_mode_en
bool auxdac_manual_mode_en
Definition: ad9361.h:3024
auxdac_control::dac2_in_tx_en
bool dac2_in_tx_en
Definition: ad9361.h:3031
ad9361_get_temperature
int32_t ad9361_get_temperature(struct ad9361_rf_phy *phy, int32_t *temp)
Definition: ad9361_api.c:2213
auxdac_control::dac1_in_rx_en
bool dac1_in_rx_en
Definition: ad9361.h:3026
AD9361_InitParam::aux_dac1_rx_delay_us
uint32_t aux_dac1_rx_delay_us
Definition: ad9361_api.h:190
gpo_control::gpo1_rx_delay_us
uint8_t gpo1_rx_delay_us
Definition: ad9361.h:3115
TX_RFPLL_INT
@ TX_RFPLL_INT
Definition: ad9361.h:3282
ad9361_rf_phy::bist_tone_mask
uint32_t bist_tone_mask
Definition: ad9361.h:3416
EXT_LO
#define EXT_LO
Definition: ad9361_api.h:363
AD9361_InitParam::split_gain_table_mode_enable
uint8_t split_gain_table_mode_enable
Definition: ad9361_api.h:76
ad9361_phy_platform_data::ensm_pin_ctrl
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Definition: ad9361.h:3174
ad9361_rf_phy::rx_eq_2tx
bool rx_eq_2tx
Definition: ad9361.h:3388
AD9361_InitParam::aux_dac2_active_in_tx_enable
uint8_t aux_dac2_active_in_tx_enable
Definition: ad9361_api.h:194
ad9361_set_rx_fir_config
int32_t ad9361_set_rx_fir_config(struct ad9361_rf_phy *phy, AD9361_RXFIRConfig fir_cfg)
Definition: ad9361_api.c:995
FIR_NUM_TAPS
#define FIR_NUM_TAPS(x)
Definition: ad9361.h:1029
ad9361_get_tx_sampling_freq
int32_t ad9361_get_tx_sampling_freq(struct ad9361_rf_phy *phy, uint32_t *sampling_freq_hz)
Definition: ad9361_api.c:1488
AD9361_InitParam::pp_tx_swap_enable
uint8_t pp_tx_swap_enable
Definition: ad9361_api.h:216
FIR_SELECT
#define FIR_SELECT(x)
Definition: ad9361.h:1028
ad9361_get_rx_fir_config
int32_t ad9361_get_rx_fir_config(struct ad9361_rf_phy *phy, uint8_t rx_ch, AD9361_RXFIRConfig *fir_cfg)
Definition: ad9361_api.c:1017
RX_SAMPL_FREQ
@ RX_SAMPL_FREQ
Definition: ad9361.h:3143
ad9361_get_rx_rssi
int32_t ad9361_get_rx_rssi(struct ad9361_rf_phy *phy, uint8_t ch, struct rf_rssi *rssi)
Definition: ad9361_api.c:926
AD9361_InitParam::ctrl_outs_index
uint8_t ctrl_outs_index
Definition: ad9361_api.h:205
REG_RX_FILTER_COEF_READ_DATA_1
#define REG_RX_FILTER_COEF_READ_DATA_1
Definition: ad9361.h:222
ad9361_get_trx_path_clks
int32_t ad9361_get_trx_path_clks(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361_api.c:1904
AD9361_InitParam::elna_settling_delay_ns
uint32_t elna_settling_delay_ns
Definition: ad9361_api.h:207
ad9361_rf_phy::rate_governor
uint32_t rate_governor
Definition: ad9361.h:3385
AD9361_InitParam::gpo1_inactive_state_high_enable
uint8_t gpo1_inactive_state_high_enable
Definition: ad9361_api.h:248
AD9361_InitParam::fagc_rst_gla_engergy_lost_goto_optim_gain_en
uint8_t fagc_rst_gla_engergy_lost_goto_optim_gain_en
Definition: ad9361_api.h:166
AD9361_InitParam::fagc_final_overrange_count
uint32_t fagc_final_overrange_count
Definition: ad9361_api.h:156
ad9361_set_rx_fir_en_dis
int32_t ad9361_set_rx_fir_en_dis(struct ad9361_rf_phy *phy, uint8_t en_dis)
Definition: ad9361_api.c:1074
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uint8_t aux_dac2_active_in_alert_enable
Definition: ad9361_api.h:195
ad9361_mcs
int32_t ad9361_mcs(struct ad9361_rf_phy *phy, int32_t step)
Definition: ad9361.c:5219
gpo_control::gpo3_rx_delay_us
uint8_t gpo3_rx_delay_us
Definition: ad9361.h:3119
AD9361_TXFIRConfig::tx_int
uint32_t tx_int
Definition: ad9361_api.h:313
gpo_control::gpo1_slave_tx_en
bool gpo1_slave_tx_en
Definition: ad9361.h:3108
gpo_control::gpo1_inactive_state_high_en
bool gpo1_inactive_state_high_en
Definition: ad9361.h:3102
ENSM_MODE_WAIT
@ ENSM_MODE_WAIT
Definition: ad9361_api.h:325
axi_adc_init
int32_t axi_adc_init(struct axi_adc **adc_core, const struct axi_adc_init *init)
AXI ADC Main Initialization.
Definition: axi_adc_core.c:596
AD9361_TXFIRConfig::tx_coef_size
uint8_t tx_coef_size
Definition: ad9361_api.h:315
AD9361_InitParam::low_high_gain_threshold_mdB
uint32_t low_high_gain_threshold_mdB
Definition: ad9361_api.h:268
AD9361_InitParam::rx1rx2_phase_inversion_en
uint8_t rx1rx2_phase_inversion_en
Definition: ad9361_api.h:241
TX_FIR_GAIN_6DB
#define TX_FIR_GAIN_6DB
Definition: ad9361.h:1025
TX_RFPLL_DUMMY
@ TX_RFPLL_DUMMY
Definition: ad9361.h:3284
ad9361_from_clk
uint64_t ad9361_from_clk(uint32_t freq)
Definition: ad9361.c:1375
port_control::lvds_invert
uint8_t lvds_invert[2]
Definition: ad9361.h:3072
AD9361_InitParam::xo_disable_use_ext_refclk_enable
uint8_t xo_disable_use_ext_refclk_enable
Definition: ad9361_api.h:98
gpo_control::gpo2_slave_rx_en
bool gpo2_slave_rx_en
Definition: ad9361.h:3109
gain_control::f_agc_large_overload_inc_steps
uint8_t f_agc_large_overload_inc_steps
Definition: ad9361.h:3017
ad9361_phy_platform_data
Definition: ad9361.h:3167
rssi_control::rssi_delay
uint32_t rssi_delay
Definition: ad9361.h:3052
ad9361_set_rx_rfdc_track_en_dis
int32_t ad9361_set_rx_rfdc_track_en_dis(struct ad9361_rf_phy *phy, uint8_t en_dis)
Definition: ad9361_api.c:1114
AD9361_InitParam::agc_attack_delay_extra_margin_us
uint32_t agc_attack_delay_extra_margin_us
Definition: ad9361_api.h:141
AD9361_RXFIRConfig::rx_dec
uint32_t rx_dec
Definition: ad9361_api.h:303
ad9361_do_dcxo_tune_fine
int32_t ad9361_do_dcxo_tune_fine(struct ad9361_rf_phy *phy, uint32_t fine)
Definition: ad9361_api.c:2198
gpo_control::gpo2_inactive_state_high_en
bool gpo2_inactive_state_high_en
Definition: ad9361.h:3103
REG_SPI_CONF
#define REG_SPI_CONF
Definition: ad9361.h:51
ad9361_rf_phy::ad9361_rfpll_ext_set_rate
int32_t(* ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.h:3357
REG_RX_FILTER_GAIN
#define REG_RX_FILTER_GAIN
Definition: ad9361.h:225
ad9361_phy_platform_data::dc_offset_update_events
uint8_t dc_offset_update_events
Definition: ad9361.h:3182
ad9361_get_rx_rfdc_track_en_dis
int32_t ad9361_get_rx_rfdc_track_en_dis(struct ad9361_rf_phy *phy, uint8_t *en_dis)
Definition: ad9361_api.c:1135
AD9361_InitParam::aux_adc_decimation
uint32_t aux_adc_decimation
Definition: ad9361_api.h:182
auxadc_control::auxadc_decimation
uint32_t auxadc_decimation
Definition: ad9361.h:3095
gain_control::f_agc_rst_gla_stronger_sig_thresh_above_ll
uint8_t f_agc_rst_gla_stronger_sig_thresh_above_ll
Definition: ad9361.h:3004
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struct ctrl_outs_control ctrl_outs_ctrl
Definition: ad9361.h:3214
auxdac_control::dac2_tx_delay_us
uint8_t dac2_tx_delay_us
Definition: ad9361.h:3037
gain_control::mgc_rx2_ctrl_inp_en
bool mgc_rx2_ctrl_inp_en
Definition: ad9361.h:2941
ad9361_get_rx_rf_port_input
int32_t ad9361_get_rx_rf_port_input(struct ad9361_rf_phy *phy, uint32_t *mode)
Definition: ad9361_api.c:1258
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
AD9361_InitParam::fagc_dec_pow_measuremnt_duration
uint32_t fagc_dec_pow_measuremnt_duration
Definition: ad9361_api.h:144
ad9361_read_rssi
int32_t ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi)
Definition: ad9361.c:2425
tx_monitor_control::low_gain_dB
uint8_t low_gain_dB
Definition: ad9361.h:3127
ad9361_phy
struct ad9361_rf_phy * ad9361_phy
Definition: main.c:504
R1_CLK
@ R1_CLK
Definition: ad9361.h:3273
port_control::digital_io_ctrl
uint8_t digital_io_ctrl
Definition: ad9361.h:3070
gain_control::adc_small_overload_thresh
uint8_t adc_small_overload_thresh
Definition: ad9361.h:2927
ad9361_do_calib_run
int32_t ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg)
Definition: ad9361.c:5647
gain_control::agc_outer_thresh_low_inc_steps
uint8_t agc_outer_thresh_low_inc_steps
Definition: ad9361.h:2957
rf_gain_ctrl::ant
uint32_t ant
Definition: ad9361.h:2903
AD9361_InitParam::aux_dac1_active_in_rx_enable
uint8_t aux_dac1_active_in_rx_enable
Definition: ad9361_api.h:187
ad9361_rf_phy::filt_tx_bw_Hz
uint32_t filt_tx_bw_Hz
Definition: ad9361.h:3393
AD9361_InitParam::swap_ports_enable
uint8_t swap_ports_enable
Definition: ad9361_api.h:227
AD9361_InitParam::rx_adc_init
struct axi_adc_init * rx_adc_init
Definition: ad9361_api.h:295
ad9361_set_rx_lo_freq
int32_t ad9361_set_rx_lo_freq(struct ad9361_rf_phy *phy, uint64_t lo_freq_hz)
Definition: ad9361_api.c:867
ad9361_rf_phy::current_table
uint32_t current_table
Definition: ad9361.h:3366
ad9361_remove
int32_t ad9361_remove(struct ad9361_rf_phy *phy)
Definition: ad9361_api.c:586
AD9361_InitParam::fagc_rst_gla_large_lmt_overload_en
uint8_t fagc_rst_gla_large_lmt_overload_en
Definition: ad9361_api.h:170
gain_control::f_agc_lp_thresh_increment_steps
uint8_t f_agc_lp_thresh_increment_steps
Definition: ad9361.h:2985
ad9361_rx_fastlock_recall
int32_t ad9361_rx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile)
Definition: ad9361_api.c:1291
no_os_clk_set_rate
int32_t no_os_clk_set_rate(struct no_os_clk *clk, uint64_t rate)
AD9361_InitParam::gpo0_slave_tx_enable
uint8_t gpo0_slave_tx_enable
Definition: ad9361_api.h:252
ad9361_rx_fastlock_save
int32_t ad9361_rx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)
Definition: ad9361_api.c:1324
ADI_REG_VERSION
#define ADI_REG_VERSION
Definition: ad9361_api.c:68
elna_control::settling_delay_ns
uint32_t settling_delay_ns
Definition: ad9361.h:3083
gain_control::f_agc_dec_pow_measuremnt_duration
uint32_t f_agc_dec_pow_measuremnt_duration
Definition: ad9361.h:2980
AD9361_InitParam::rf_tx_bandwidth_hz
uint32_t rf_tx_bandwidth_hz
Definition: ad9361_api.h:90
ad9361_set_tx_sampling_freq
int32_t ad9361_set_tx_sampling_freq(struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz)
Definition: ad9361_api.c:1463
AD9361_InitParam::gpo1_slave_rx_enable
uint8_t gpo1_slave_rx_enable
Definition: ad9361_api.h:253
AD9361_InitParam::tx_rf_port_input_select
uint32_t tx_rf_port_input_select
Definition: ad9361_api.h:93
REG_ENSM_CONFIG_1
#define REG_ENSM_CONFIG_1
Definition: ad9361.h:70
ad9361_get_rx_lo_power
int32_t ad9361_get_rx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option)
Definition: ad9361_api.c:1350
gain_control::f_agc_use_last_lock_level_for_set_gain_en
bool f_agc_use_last_lock_level_for_set_gain_en
Definition: ad9361.h:3001
ad9361_get_rx_rf_port_input
int32_t ad9361_get_rx_rf_port_input(struct ad9361_rf_phy *phy, uint32_t *mode)
Definition: ad9361_api.c:1258
ad9361_rf_phy::current_tx_bw_Hz
uint32_t current_tx_bw_Hz
Definition: ad9361.h:3383
AD9361_InitParam::agc_dig_saturation_exceed_counter
uint8_t agc_dig_saturation_exceed_counter
Definition: ad9361_api.h:126
ad9361_do_mcs
int32_t ad9361_do_mcs(struct ad9361_rf_phy *phy_master, struct ad9361_rf_phy *phy_slave)
Definition: ad9361_api.c:2005
gpo_control::gpo1_tx_delay_us
uint8_t gpo1_tx_delay_us
Definition: ad9361.h:3116
ad9361_set_rx_rf_bandwidth
int32_t ad9361_set_rx_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t bandwidth_hz)
Definition: ad9361_api.c:783
ADC_CLK
@ ADC_CLK
Definition: ad9361.h:3271
ad9361_set_rx_sampling_freq
int32_t ad9361_set_rx_sampling_freq(struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz)
Definition: ad9361_api.c:823
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
RX_RFPLL_INT
@ RX_RFPLL_INT
Definition: ad9361.h:3281
REG_RX_CLOCK_DATA_DELAY
#define REG_RX_CLOCK_DATA_DELAY
Definition: ad9361.h:57
ad9361_unregister_clocks
int32_t ad9361_unregister_clocks(struct ad9361_rf_phy *phy)
Definition: ad9361.c:7373
gain_control::f_agc_final_overrange_count
uint8_t f_agc_final_overrange_count
Definition: ad9361.h:2994
ENSM_STATE
#define ENSM_STATE(x)
Definition: ad9361.h:760
ad9361_phy_platform_data::rf_dc_offset_count_high
uint8_t rf_dc_offset_count_high
Definition: ad9361.h:3185
ad9361_get_rx_gain
int32_t ad9361_get_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition: ad9361.c:1882
gpo_control::gpo0_rx_delay_us
uint8_t gpo0_rx_delay_us
Definition: ad9361.h:3113
rssi_control::rssi_duration
uint32_t rssi_duration
Definition: ad9361.h:3054
AD9361_InitParam::lvds_bias_mV
uint32_t lvds_bias_mV
Definition: ad9361_api.h:239
AD9361_InitParam::fagc_allow_agc_gain_increase
uint8_t fagc_allow_agc_gain_increase
Definition: ad9361_api.h:147
AD9361_InitParam::agc_outer_thresh_high
uint8_t agc_outer_thresh_high
Definition: ad9361_api.h:137
gain_control::lmt_overload_large_exceed_counter
uint8_t lmt_overload_large_exceed_counter
Definition: ad9361.h:2965
ad9361_get_trx_rate_gov
int32_t ad9361_get_trx_rate_gov(struct ad9361_rf_phy *phy, uint32_t *rate_gov)
Definition: ad9361_api.c:2096
AD9361_InitParam::gc_adc_small_overload_thresh
uint8_t gc_adc_small_overload_thresh
Definition: ad9361_api.h:106
ad9361_get_tx_sampling_freq
int32_t ad9361_get_tx_sampling_freq(struct ad9361_rf_phy *phy, uint32_t *sampling_freq_hz)
Definition: ad9361_api.c:1488
ad9361_set_tx_lo_freq
int32_t ad9361_set_tx_lo_freq(struct ad9361_rf_phy *phy, uint64_t lo_freq_hz)
Definition: ad9361_api.c:1507
no_os_gpio.h
Header file of GPIO Interface.
ad9361_bbpll_recalc_rate
uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6542
ENSM_MODE_TX
@ ENSM_MODE_TX
Definition: ad9361_api.h:321
ad9361_rf_phy::gpio_desc_sync
struct no_os_gpio_desc * gpio_desc_sync
Definition: ad9361.h:3344
gain_control::f_agc_gain_increase_after_gain_lock_en
bool f_agc_gain_increase_after_gain_lock_en
Definition: ad9361.h:2996
ad9361_tx_fastlock_save
int32_t ad9361_tx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)
Definition: ad9361_api.c:1839
ad9361_set_rx_quad_track_en_dis
int32_t ad9361_set_rx_quad_track_en_dis(struct ad9361_rf_phy *phy, uint8_t en_dis)
Definition: ad9361_api.c:1190
ad9361_rf_phy::bist_config
int32_t bist_config
Definition: ad9361.h:3411
AD9361_InitParam::gc_use_rx_fir_out_for_dec_pwr_meas_enable
uint8_t gc_use_rx_fir_out_for_dec_pwr_meas_enable
Definition: ad9361_api.h:113
AD9361_InitParam::tx_mon_delay
uint32_t tx_mon_delay
Definition: ad9361_api.h:273
ad9361_get_rx_quad_track_en_dis
int32_t ad9361_get_rx_quad_track_en_dis(struct ad9361_rf_phy *phy, uint8_t *en_dis)
Definition: ad9361_api.c:1211
ad9361_validate_rf_bw
uint32_t ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, uint32_t bw)
Definition: ad9361.c:912
ENSM_MODE_FDD
@ ENSM_MODE_FDD
Definition: ad9361_api.h:324
ad9361_update_rf_bandwidth
int32_t ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t rf_rx_bw, uint32_t rf_tx_bw)
Definition: ad9361.c:5688
gain_control::f_agc_rst_gla_if_en_agc_pulled_high_mode
enum f_agc_target_gain_index_type f_agc_rst_gla_if_en_agc_pulled_high_mode
Definition: ad9361.h:3014
ENSM_MODE_PINCTRL
@ ENSM_MODE_PINCTRL
Definition: ad9361_api.h:327
AD9361_InitParam::fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en
uint8_t fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en
Definition: ad9361_api.h:165
tx_monitor_control::tx2_mon_front_end_gain
uint8_t tx2_mon_front_end_gain
Definition: ad9361.h:3132
ad9361_phy_platform_data::rssi_ctrl
struct rssi_control rssi_ctrl
Definition: ad9361.h:3212
gain_control::use_rx_fir_out_for_dec_pwr_meas
bool use_rx_fir_out_for_dec_pwr_meas
Definition: ad9361.h:2934
AD9361_InitParam::tx_fb_clock_delay
uint32_t tx_fb_clock_delay
Definition: ad9361_api.h:237
rf_rssi
Definition: ad9361.h:3235
AD9361_InitParam::temp_sense_decimation
uint32_t temp_sense_decimation
Definition: ad9361_api.h:199
AD9361_InitParam::fagc_rst_gla_en_agc_pulled_high_en
uint8_t fagc_rst_gla_en_agc_pulled_high_en
Definition: ad9361_api.h:171
BBPLL_CLK
@ BBPLL_CLK
Definition: ad9361.h:3270
ad9361_rx_lo_powerdown
int32_t ad9361_rx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option)
Definition: ad9361_api.c:1339
ad9361_rf_phy::gt_info
struct gain_table_info * gt_info
Definition: ad9361.h:3367
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
AD9361_TXFIRConfig::tx_bandwidth
uint32_t tx_bandwidth
Definition: ad9361_api.h:317
AD9361_InitParam::gpo1_rx_delay_us
uint8_t gpo1_rx_delay_us
Definition: ad9361_api.h:261
ad9361_rf_phy::filt_valid
bool filt_valid
Definition: ad9361.h:3389
TX_RSSI_1
#define TX_RSSI_1
Definition: ad9361.h:1052
REG_TX_FILTER_CONF
#define REG_TX_FILTER_CONF
Definition: ad9361.h:141
tx_monitor_control::tx1_mon_front_end_gain
uint8_t tx1_mon_front_end_gain
Definition: ad9361.h:3131
ad9361_get_tx_rf_bandwidth
int32_t ad9361_get_tx_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t *bandwidth_hz)
Definition: ad9361_api.c:1445
ad9361_phy_platform_data::rx_path_clks
uint32_t rx_path_clks[NUM_RX_CLOCKS]
Definition: ad9361.h:3196
gain_control::dig_gain_step_size
uint8_t dig_gain_step_size
Definition: ad9361.h:2970
no_os_util.h
Implementation of utility functions.
AD9361_InitParam::delay_rx_data
uint32_t delay_rx_data
Definition: ad9361_api.h:234
ad9361_tx_lo_powerdown
int32_t ad9361_tx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option)
Definition: ad9361_api.c:1854
DATA_CLK_DELAY
#define DATA_CLK_DELAY(x)
Definition: ad9361.h:638
AD9361_InitParam::aux_adc_rate
uint32_t aux_adc_rate
Definition: ad9361_api.h:183
AD9361_InitParam::tx_dac_init
struct axi_dac_init * tx_dac_init
Definition: ad9361_api.h:296
ad9361_get_trx_clock_chain
int32_t ad9361_get_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4700
AD9361_InitParam::fagc_lock_level_lmt_gain_increase_en
uint8_t fagc_lock_level_lmt_gain_increase_en
Definition: ad9361_api.h:151
ad9361_rf_phy::pdata
struct ad9361_phy_platform_data * pdata
Definition: ad9361.h:3359
AD9361_InitParam::gpo1_tx_delay_us
uint8_t gpo1_tx_delay_us
Definition: ad9361_api.h:262
elna_control::bypass_loss_mdB
uint16_t bypass_loss_mdB
Definition: ad9361.h:3082
CLKRF_CLK
@ CLKRF_CLK
Definition: ad9361.h:3274
ad9361_rfpll_dummy_recalc_rate
uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:6952
ad9361_get_rx_bbdc_track_en_dis
int32_t ad9361_get_rx_bbdc_track_en_dis(struct ad9361_rf_phy *phy, uint8_t *en_dis)
Definition: ad9361_api.c:1173
auxdac_control::dac1_tx_delay_us
uint8_t dac1_tx_delay_us
Definition: ad9361.h:3035
ad9361_phy_platform_data::rx1tx1_mode_use_tx_num
uint32_t rx1tx1_mode_use_tx_num
Definition: ad9361.h:3195
AD9361_InitParam::rssi_delay
uint32_t rssi_delay
Definition: ad9361_api.h:176
ad9361_phy_platform_data::use_extclk
bool use_extclk
Definition: ad9361.h:3172
gain_control::immed_gain_change_if_large_adc_overload
bool immed_gain_change_if_large_adc_overload
Definition: ad9361.h:2974
ad9361_rf_phy::bist_loopback_mode
int32_t bist_loopback_mode
Definition: ad9361.h:3410
gain_control::rx1_mode
enum rf_gain_ctrl_mode rx1_mode
Definition: ad9361.h:2922
tx_monitor_control::high_gain_dB
uint8_t high_gain_dB
Definition: ad9361.h:3128
ad9361_set_trx_rate_gov
int32_t ad9361_set_trx_rate_gov(struct ad9361_rf_phy *phy, uint32_t rate_gov)
Definition: ad9361_api.c:2080
ad9361_trx_load_enable_fir
int32_t ad9361_trx_load_enable_fir(struct ad9361_rf_phy *phy, AD9361_RXFIRConfig rx_fir_cfg, AD9361_TXFIRConfig tx_fir_cfg)
Definition: ad9361_api.c:2129
ad9361_get_tx_attenuation
int32_t ad9361_get_tx_attenuation(struct ad9361_rf_phy *phy, uint8_t ch, uint32_t *attenuation_mdb)
Definition: ad9361_api.c:1397
gpo_control::gpo2_tx_delay_us
uint8_t gpo2_tx_delay_us
Definition: ad9361.h:3118
gain_control::agc_outer_thresh_high_dec_steps
uint8_t agc_outer_thresh_high_dec_steps
Definition: ad9361.h:2951
ad9361_set_trx_path_clks
int32_t ad9361_set_trx_path_clks(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361_api.c:1881
ad9361_phy_platform_data::dcxo_fine
uint32_t dcxo_fine
Definition: ad9361.h:3191
no_os_gpio_direction_output
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:124
dev_id
dev_id
Definition: ad9361.h:3334
gain_control::dec_pow_measuremnt_duration
uint16_t dec_pow_measuremnt_duration
Definition: ad9361.h:2932
OFF
#define OFF
Definition: ad9361_api.h:366
no_os_clk::rate
uint32_t rate
Definition: common.h:59
AD9361_InitParam::agc_inner_thresh_low_inc_steps
uint8_t agc_inner_thresh_low_inc_steps
Definition: ad9361_api.h:133
ad9361_phy_platform_data::use_ext_tx_lo
bool use_ext_tx_lo
Definition: ad9361.h:3179
gpo_control::gpo0_slave_rx_en
bool gpo0_slave_rx_en
Definition: ad9361.h:3105
ad9361_set_rx_rf_bandwidth
int32_t ad9361_set_rx_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t bandwidth_hz)
Definition: ad9361_api.c:783
rf_rssi::ant
uint32_t ant
Definition: ad9361.h:3236
ad9361_rf_phy::bist_tone_freq_Hz
uint32_t bist_tone_freq_Hz
Definition: ad9361.h:3414
ad9361_set_trx_rate_gov
int32_t ad9361_set_trx_rate_gov(struct ad9361_rf_phy *phy, uint32_t rate_gov)
Definition: ad9361_api.c:2080
axiadc_state::phy
struct ad9361_rf_phy * phy
Definition: ad9361_util.h:84
ad9361_phy_platform_data::rf_rx_input_sel
uint32_t rf_rx_input_sel
Definition: ad9361.h:3192
ad9361_set_rx_gain_control_mode
int32_t ad9361_set_rx_gain_control_mode(struct ad9361_rf_phy *phy, uint8_t ch, uint8_t gc_mode)
Definition: ad9361_api.c:956
ad9361_fastlock_store
int32_t ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
Definition: ad9361.c:5013
AD9361_InitParam::rx_data_delay
uint32_t rx_data_delay
Definition: ad9361_api.h:236
AD9361_InitParam::fagc_gain_index_type_after_exit_rx_mode
uint32_t fagc_gain_index_type_after_exit_rx_mode
Definition: ad9361_api.h:160
ad9361_set_tx_auto_cal_en_dis
int32_t ad9361_set_tx_auto_cal_en_dis(struct ad9361_rf_phy *phy, uint8_t en_dis)
Definition: ad9361_api.c:1756
AD9361_InitParam::agc_adc_large_overload_inc_steps
uint8_t agc_adc_large_overload_inc_steps
Definition: ad9361_api.h:122
ad9361_get_tx_atten
int32_t ad9361_get_tx_atten(struct ad9361_rf_phy *phy, uint32_t tx_num)
Definition: ad9361.c:1653
ad9361_api.h
Header file of AD9361 API Driver.
ad7616_init_param::spi_param
struct no_os_spi_init_param * spi_param
Definition: ad7616.h:167
AD9361_InitParam::dc_offset_attenuation_low_range
uint8_t dc_offset_attenuation_low_range
Definition: ad9361_api.h:73
ad9361_phy_platform_data::rx_fastlock_delay_ns
uint32_t rx_fastlock_delay_ns
Definition: ad9361.h:3205
AD9361_InitParam::pp_rx_swap_enable
uint8_t pp_rx_swap_enable
Definition: ad9361_api.h:217
gain_control::rx2_mode
enum rf_gain_ctrl_mode rx2_mode
Definition: ad9361.h:2923
gain_control::adc_small_overload_exceed_counter
uint8_t adc_small_overload_exceed_counter
Definition: ad9361.h:2959
RX_DATA_DELAY
#define RX_DATA_DELAY(x)
Definition: ad9361.h:639
ad9361_phy_platform_data::trx_synth_max_fref
uint32_t trx_synth_max_fref
Definition: ad9361.h:3198
AD9361_InitParam::agc_outer_thresh_high_dec_steps
uint8_t agc_outer_thresh_high_dec_steps
Definition: ad9361_api.h:138
AD9361_InitParam::elna_gaintable_all_index_enable
uint8_t elna_gaintable_all_index_enable
Definition: ad9361_api.h:212
AD9361_InitParam::dc_offset_attenuation_high_range
uint8_t dc_offset_attenuation_high_range
Definition: ad9361_api.h:72
f_agc_target_gain_index_type
f_agc_target_gain_index_type
Definition: ad9361.h:2914
ad9361_tracking_control
int32_t ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track, bool rfdc_track, bool rxquad_track)
Definition: ad9361.c:3289
auxdac_control::dac1_in_tx_en
bool dac1_in_tx_en
Definition: ad9361.h:3027
AD9361_InitParam::tx_lo_powerdown_managed_enable
uint8_t tx_lo_powerdown_managed_enable
Definition: ad9361_api.h:85
ad9361_set_tx_fir_en_dis
int32_t ad9361_set_tx_fir_en_dis(struct ad9361_rf_phy *phy, uint8_t en_dis)
Definition: ad9361_api.c:1636
gain_control::gain_update_interval_us
uint32_t gain_update_interval_us
Definition: ad9361.h:2973
AD9361_InitParam::one_rx_one_tx_mode_use_tx_num
uint8_t one_rx_one_tx_mode_use_tx_num
Definition: ad9361_api.h:60
ID_AD9361
@ ID_AD9361
Definition: ad9361.h:3335
ENSM_MODE_ALERT
@ ENSM_MODE_ALERT
Definition: ad9361_api.h:323
AD9361_InitParam::gpo3_rx_delay_us
uint8_t gpo3_rx_delay_us
Definition: ad9361_api.h:265
tx_monitor_control::one_shot_mode_en
bool one_shot_mode_en
Definition: ad9361.h:3125
gain_control::sync_for_gain_counter_en
bool sync_for_gain_counter_en
Definition: ad9361.h:2971
AD9361_InitParam::rx_data_clock_delay
uint32_t rx_data_clock_delay
Definition: ad9361_api.h:235
ad9361_rf_phy::adc_conv
struct axiadc_converter * adc_conv
Definition: ad9361.h:3408
AD9361_InitParam::tx2_mon_front_end_gain
uint32_t tx2_mon_front_end_gain
Definition: ad9361_api.h:276
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
auxadc_control::periodic_temp_measuremnt
bool periodic_temp_measuremnt
Definition: ad9361.h:3093
ad9361_calculate_rf_clock_chain
int32_t ad9361_calculate_rf_clock_chain(struct ad9361_rf_phy *phy, uint32_t tx_sample_rate, uint32_t rate_gov, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4738
ad9361_rf_phy::bypass_tx_fir
bool bypass_tx_fir
Definition: ad9361.h:3387
axiadc_converter::chip_info
struct axiadc_chip_info * chip_info
Definition: ad9361_util.h:94
gain_control::low_power_thresh
uint8_t low_power_thresh
Definition: ad9361.h:2933
ad9361_set_rx_rf_gain
int32_t ad9361_set_rx_rf_gain(struct ad9361_rf_phy *phy, uint8_t ch, int32_t gain_db)
Definition: ad9361_api.c:733
AD9361_RXFIRConfig::rx_bandwidth
uint32_t rx_bandwidth
Definition: ad9361_api.h:307
ad9361_set_tx_lo_int_ext
int32_t ad9361_set_tx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext)
Definition: ad9361_api.c:1542
ad9361_phy_platform_data::txmon_ctrl
struct tx_monitor_control txmon_ctrl
Definition: ad9361.h:3219
AD9361_InitParam::lvds_invert2_control
uint8_t lvds_invert2_control
Definition: ad9361_api.h:243
TX_SAMPL_CLK
@ TX_SAMPL_CLK
Definition: ad9361.h:3280
no_os_gpio_get_optional
int32_t no_os_gpio_get_optional(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Get the value of an optional GPIO.
Definition: no_os_gpio.c:75