no-OS
ad9361_util.h
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1 /***************************************************************************/
39 #ifndef __AD9361_UTIL_H__
40 #define __AD9361_UTIL_H__
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include <limits.h>
46 #include <stdint.h>
47 #include <stdio.h>
48 #include <stdlib.h>
49 #include "ad9361.h"
50 #include "common.h"
51 #include "app_config.h"
52 
53 /******************************************************************************/
54 /********************** Macros and Constants Definitions **********************/
55 /******************************************************************************/
56 #define CLK_IGNORE_UNUSED NO_OS_BIT(3)
57 #define CLK_GET_RATE_NOCACHE NO_OS_BIT(6)
58 
59 #if defined(HAVE_VERBOSE_MESSAGES)
60 #define dev_err(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
61 #define dev_warn(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
62 #if defined(HAVE_DEBUG_MESSAGES)
63 #define dev_dbg(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
64 #else
65 #define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
66 #endif
67 #define printk(format, ...) printf(format, ## __VA_ARGS__)
68 #else
69 #define dev_err(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
70 #define dev_warn(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
71 #define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
72 #define printk(format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
73 #endif
74 
75 struct device {
76 };
77 
78 struct spi_device {
79  struct device dev;
80  uint8_t id_no;
81 };
82 
83 struct axiadc_state {
84  struct ad9361_rf_phy *phy;
85  uint32_t pcore_version;
86 };
87 
89  char *name;
90  int32_t num_channels;
91 };
92 
95  uint32_t scratch_reg[16];
96 };
97 
98 #ifdef WIN32
99 #include "basetsd.h"
100 typedef SSIZE_T ssize_t;
101 #define strsep(s, ct) 0
102 #define snprintf(s, n, format, ...) 0
103 #define __func__ __FUNCTION__
104 #endif
105 
106 /******************************************************************************/
107 /************************ Functions Declarations ******************************/
108 /******************************************************************************/
109 int32_t clk_prepare_enable(struct no_os_clk *clk);
110 uint32_t clk_get_rate(struct ad9361_rf_phy *phy,
111  struct refclk_scale *clk_priv);
112 int32_t no_os_clk_set_rate(struct ad9361_rf_phy *phy,
113  struct refclk_scale *clk_priv,
114  uint32_t rate);
115 uint32_t int_sqrt(uint32_t x);
116 int32_t ilog2(int32_t x);
117 uint32_t find_first_bit(uint32_t word);
118 void * ERR_PTR(long error);
119 void *zmalloc(size_t size);
120 
121 #endif
axiadc_state::pcore_version
uint32_t pcore_version
Definition: ad9361_util.h:85
ad9361_spi_read
int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg)
Definition: ad9361.c:740
axi_adc_core.h
Driver for the Analog Devices AXI-ADC-CORE module.
ad9361_phy_platform_data::port_ctrl
struct port_control port_ctrl
Definition: ad9361.h:3213
port_control::pp_conf
uint8_t pp_conf[3]
Definition: ad9361.h:3067
ad9361_hdl_loopback
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
Definition: ad9361_conv.c:113
no_os_clk_set_rate
int32_t no_os_clk_set_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv, uint32_t rate)
clk_set_rate
Definition: ad9361_util.c:122
BB_REFCLK
@ BB_REFCLK
Definition: ad9361.h:3267
axiadc_converter
Definition: ad9361_util.h:93
dev_err
#define dev_err(dev, format,...)
Definition: ad9361_util.h:69
ad9361_clk_factor_round_rate
int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6477
ad9361_rf_phy::clks
struct no_os_clk * clks[NUM_AD9361_CLKS]
Definition: ad9361.h:3352
clk_prepare_enable
int32_t clk_prepare_enable(struct no_os_clk *clk)
clk_prepare_enable
Definition: ad9361_util.c:55
clk_get_rate
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv)
clk_get_rate
Definition: ad9361_util.c:67
BE_VERBOSE
@ BE_VERBOSE
Definition: ad9361.h:3314
ADI_REG_ID
#define ADI_REG_ID
Definition: ad9361_conv.c:56
ad9361_rf_phy::adc_state
struct axiadc_state * adc_state
Definition: ad9361.h:3409
ad9361_ensm_restore_state
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:2041
T1_CLK
@ T1_CLK
Definition: ad9361.h:3278
no_os_clk_set_rate
int32_t no_os_clk_set_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv, uint32_t rate)
clk_set_rate
Definition: ad9361_util.c:122
axi_adc_write
int32_t axi_adc_write(struct axi_adc *adc, uint32_t reg_addr, uint32_t reg_data)
AXI ADC Data Write.
Definition: axi_adc_core.c:75
printk
#define printk(format,...)
Definition: ad9361_util.h:72
ad9361_ensm_force_state
void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:1961
AXI_ADC_RSTN
#define AXI_ADC_RSTN
Definition: axi_adc_core.h:53
refclk_scale
Definition: ad9361.h:3420
spi_device::id_no
uint8_t id_no
Definition: ad9361_util.h:80
no_os_delay.h
Header file of Delay functions.
ad9361_phy_platform_data::dig_interface_tune_skipmode
uint8_t dig_interface_tune_skipmode
Definition: ad9361.h:3187
ERR_PTR
void * ERR_PTR(long error)
ERR_PTR.
Definition: ad9361_util.c:314
ilog2
int32_t ilog2(int32_t x)
ilog2
Definition: ad9361_util.c:255
REG_TX_CLOCK_DATA_DELAY
#define REG_TX_CLOCK_DATA_DELAY
Definition: ad9361.h:58
spi_device
Definition: ad9361_util.h:78
axi_adc
AXI ADC Device Descriptor.
Definition: axi_adc_core.h:125
ad9361_tx_mute
int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state)
Definition: ad9361.c:1678
no_os_clk
Definition: no_os_clk.h:59
ad9361_rf_phy::spi
struct no_os_spi_desc * spi
Definition: ad9361.h:3342
LVDS_MODE
#define LVDS_MODE
Definition: ad9361.h:708
AXI_ADC_REG_STATUS
#define AXI_ADC_REG_STATUS
Definition: axi_adc_core.h:68
device
Definition: ad9361_util.h:75
port_control::rx_clk_data_delay
uint8_t rx_clk_data_delay
Definition: ad9361.h:3068
ERR_PTR
void * ERR_PTR(long error)
ERR_PTR.
Definition: ad9361_util.c:314
ilog2
int32_t ilog2(int32_t x)
ilog2
Definition: ad9361_util.c:255
AXI_ADC_ENABLE
#define AXI_ADC_ENABLE
Definition: axi_adc_core.h:90
ad9361_util.h
AD9361 Header file of Util driver.
refclk_scale::parent_source
enum ad9361_clocks parent_source
Definition: ad9361.h:3426
RX_RFPLL_DUMMY
@ RX_RFPLL_DUMMY
Definition: ad9361.h:3283
ad9361_rf_phy::clk_refin
struct no_os_clk * clk_refin
Definition: ad9361.h:3351
NO_OS_ARRAY_SIZE
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
ad9361_rfpll_recalc_rate
uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:6980
zmalloc
void * zmalloc(size_t size)
zmalloc
Definition: ad9361_util.c:322
BIST_DISABLE
@ BIST_DISABLE
Definition: ad9361.h:3323
ad9361_rfpll_dummy_set_rate
int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:6965
ad9361_set_trx_clock_chain
int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4612
port_control::tx_clk_data_delay
uint8_t tx_clk_data_delay
Definition: ad9361.h:3069
AXI_ADC_REG_DELAY
#define AXI_ADC_REG_DELAY(l)
Definition: axi_adc_core.h:115
ad9361_rfpll_round_rate
int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7022
AXI_ADC_REG_RSTN
#define AXI_ADC_REG_RSTN
Definition: axi_adc_core.h:51
DO_IDELAY
@ DO_IDELAY
Definition: ad9361.h:3316
ENSM_STATE_FDD
#define ENSM_STATE_FDD
Definition: ad9361.h:767
RX_SAMPL_CLK
@ RX_SAMPL_CLK
Definition: ad9361.h:3275
BIST_INJ_RX
@ BIST_INJ_RX
Definition: ad9361.h:3325
NO_OS_BITS_PER_LONG
#define NO_OS_BITS_PER_LONG
Definition: ad9361_util.c:50
ad9361_spi_write
int32_t ad9361_spi_write(struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)
Definition: ad9361.c:796
ad9361_find_opt
int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start)
Definition: ad9361.c:954
ad9361_phy_platform_data::tx_path_clks
uint32_t tx_path_clks[NUM_TX_CLOCKS]
Definition: ad9361.h:3197
TX_RFPLL
@ TX_RFPLL
Definition: ad9361.h:3286
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
ad9361_ensm_get_state
uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1948
ad9361_set_trx_clock_chain_freq
int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, uint32_t freq)
Definition: ad9361.c:4860
axiadc_chip_info::name
char * name
Definition: ad9361_util.h:89
AXI_ADC_PN_OOS
#define AXI_ADC_PN_OOS
Definition: axi_adc_core.h:94
RESTORE_DEFAULT
@ RESTORE_DEFAULT
Definition: ad9361.h:3319
ad9361_rfpll_set_rate
int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7064
ad9361.h
Header file of AD9361 Driver.
RX_REFCLK
@ RX_REFCLK
Definition: ad9361.h:3268
axiadc_chip_info
Definition: ad9361_util.h:88
PCORE_VERSION_MAJOR
#define PCORE_VERSION_MAJOR(version)
Definition: ad9361_conv.c:59
axiadc_state
Definition: ad9361_util.h:83
SKIP_STORE_RESULT
@ SKIP_STORE_RESULT
Definition: ad9361.h:3318
TX_REFCLK
@ TX_REFCLK
Definition: ad9361.h:3269
ad9361_set_ensm_mode
int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
Definition: ad9361.c:4880
ad9361_clk_factor_set_rate
int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6511
axi_adc_idelay_set
void axi_adc_idelay_set(struct axi_adc *adc, uint32_t lane, uint32_t val)
Set input/output delay primitive for specific interface line.
Definition: axi_adc_core.c:168
ad9361_ensm_restore_prev_state
void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:2096
axi_adc_read
int32_t axi_adc_read(struct axi_adc *adc, uint32_t reg_addr, uint32_t *reg_data)
AXI ADC Data read.
Definition: axi_adc_core.c:59
ad9361_bist_prbs
int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode)
Definition: ad9361.c:1156
ad9361_clk_factor_recalc_rate
uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6459
AXI_ADC_REG_CHAN_CNTRL_2
#define AXI_ADC_REG_CHAN_CNTRL_2(c)
Definition: axi_adc_core.h:103
refclk_scale::source
enum ad9361_clocks source
Definition: ad9361.h:3425
ad9361_rfpll_int_recalc_rate
uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6748
T2_CLK
@ T2_CLK
Definition: ad9361.h:3277
ad9361_bist_loopback
int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode)
Definition: ad9361.c:1097
ENSM_STATE_ALERT
#define ENSM_STATE_ALERT
Definition: ad9361.h:762
ad9361_rf_phy::rx_adc
struct axi_adc * rx_adc
Definition: ad9361.h:3348
AXI_ADC_REG_CHAN_STATUS
#define AXI_ADC_REG_CHAN_STATUS(c)
Definition: axi_adc_core.h:92
clk_get_rate
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv)
clk_get_rate
Definition: ad9361_util.c:67
R2_CLK
@ R2_CLK
Definition: ad9361.h:3272
AXI_ADC_REG_CHAN_CNTRL
#define AXI_ADC_REG_CHAN_CNTRL(c)
Definition: axi_adc_core.h:82
ad9361_phy_platform_data::rx2tx2
bool rx2tx2
Definition: ad9361.h:3168
ad9361_rf_phy
Definition: ad9361.h:3340
find_first_bit
uint32_t find_first_bit(uint32_t word)
find_first_bit
Definition: ad9361_util.c:286
AXI_ADC_PN_CUSTOM
@ AXI_ADC_PN_CUSTOM
Definition: axi_adc_core.h:158
ad9361_phy_platform_data::fdd
bool fdd
Definition: ad9361.h:3169
AXI_ADC_FORMAT_ENABLE
#define AXI_ADC_FORMAT_ENABLE
Definition: axi_adc_core.h:88
ad9361_rf_phy::bbpll_initialized
bool bbpll_initialized
Definition: ad9361.h:3417
find_first_bit
uint32_t find_first_bit(uint32_t word)
find_first_bit
Definition: ad9361_util.c:286
CLKTF_CLK
@ CLKTF_CLK
Definition: ad9361.h:3279
ad9361_rf_phy::ref_clk_scale
struct refclk_scale * ref_clk_scale[NUM_AD9361_CLKS]
Definition: ad9361.h:3353
RX_RFPLL
@ RX_RFPLL
Definition: ad9361.h:3285
DAC_CLK
@ DAC_CLK
Definition: ad9361.h:3276
ad9361_rfpll_int_set_rate
int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6833
AXI_ADC_R1_MODE
#define AXI_ADC_R1_MODE
Definition: axi_adc_core.h:56
ad9361_bbpll_set_rate
int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6609
dig_tune_flags
dig_tune_flags
Definition: ad9361.h:3313
TX_RFPLL_INT
@ TX_RFPLL_INT
Definition: ad9361.h:3282
axiadc_converter::scratch_reg
uint32_t scratch_reg[16]
Definition: ad9361_util.h:95
ad9361_phy_platform_data::ensm_pin_ctrl
bool ensm_pin_ctrl
Definition: ad9361.h:3174
axi_adc_set_pnsel
int32_t axi_adc_set_pnsel(struct axi_adc *adc, uint32_t chan, enum axi_adc_pn_sel sel)
Set AXI ADC PN sequence.
Definition: axi_adc_core.c:91
AXI_ADC_STATUS
#define AXI_ADC_STATUS
Definition: axi_adc_core.h:72
NO_OS_BIT
#define NO_OS_BIT(x)
Definition: no_os_util.h:51
zmalloc
void * zmalloc(size_t size)
zmalloc
Definition: ad9361_util.c:322
DO_ODELAY
@ DO_ODELAY
Definition: ad9361.h:3317
AXI_ADC_MMCM_RSTN
#define AXI_ADC_MMCM_RSTN
Definition: axi_adc_core.h:52
TX_RFPLL_DUMMY
@ TX_RFPLL_DUMMY
Definition: ad9361.h:3284
AXI_ADC_DCFILT_OFFSET
#define AXI_ADC_DCFILT_OFFSET(x)
Definition: axi_adc_core.h:98
ad9361_dig_interface_timing_analysis
int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, char *buf, int32_t buflen)
Definition: ad9361_conv.c:288
spi_device::dev
struct device dev
Definition: ad9361_util.h:79
R1_CLK
@ R1_CLK
Definition: ad9361.h:3273
dev_dbg
#define dev_dbg(dev, format,...)
Definition: ad9361_util.h:71
AXI_ADC_REG_CHAN_CNTRL_1
#define AXI_ADC_REG_CHAN_CNTRL_1(c)
Definition: axi_adc_core.h:97
ad9361_post_setup
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
Definition: ad9361_conv.c:605
ADC_CLK
@ ADC_CLK
Definition: ad9361.h:3271
RX_RFPLL_INT
@ RX_RFPLL_INT
Definition: ad9361.h:3281
REG_RX_CLOCK_DATA_DELAY
#define REG_RX_CLOCK_DATA_DELAY
Definition: ad9361.h:57
ad9361_bbpll_round_rate
int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6569
ad9361_bbpll_recalc_rate
uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6542
ad9361_dig_tune
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, enum dig_tune_flags flags)
Definition: ad9361_conv.c:525
ad9361_rf_phy::bist_config
int32_t bist_config
Definition: ad9361.h:3411
AXI_ADC_IQCOR_ENB
#define AXI_ADC_IQCOR_ENB
Definition: axi_adc_core.h:84
ad9361_rfpll_int_round_rate
int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6804
clk_prepare_enable
int32_t clk_prepare_enable(struct no_os_clk *clk)
clk_prepare_enable
Definition: ad9361_util.c:55
BBPLL_CLK
@ BBPLL_CLK
Definition: ad9361.h:3270
ad9361_phy_platform_data::rx_path_clks
uint32_t rx_path_clks[NUM_RX_CLOCKS]
Definition: ad9361.h:3196
DATA_CLK_DELAY
#define DATA_CLK_DELAY(x)
Definition: ad9361.h:638
ad9361_rf_phy::pdata
struct ad9361_phy_platform_data * pdata
Definition: ad9361.h:3359
REG_BIST_CONFIG
#define REG_BIST_CONFIG
Definition: ad9361.h:570
CLKRF_CLK
@ CLKRF_CLK
Definition: ad9361.h:3274
ad9361_rfpll_dummy_recalc_rate
uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:6952
AXI_ADC_PN_ERR
#define AXI_ADC_PN_ERR
Definition: axi_adc_core.h:93
common.h
Header file of Common Driver.
ad9361_rf_phy::bist_loopback_mode
int32_t bist_loopback_mode
Definition: ad9361.h:3410
BE_MOREVERBOSE
@ BE_MOREVERBOSE
Definition: ad9361.h:3315
no_os_clk::rate
uint32_t rate
Definition: common.h:59
AXI_ADC_FORMAT_SIGNEXT
#define AXI_ADC_FORMAT_SIGNEXT
Definition: axi_adc_core.h:86
int_sqrt
uint32_t int_sqrt(uint32_t x)
int_sqrt
Definition: ad9361_util.c:230
NUM_AD9361_CLKS
@ NUM_AD9361_CLKS
Definition: ad9361.h:3287
axiadc_state::phy
struct ad9361_rf_phy * phy
Definition: ad9361_util.h:84
AXI_ADC_PN9
@ AXI_ADC_PN9
Definition: axi_adc_core.h:152
RX_DATA_DELAY
#define RX_DATA_DELAY(x)
Definition: ad9361.h:639
axiadc_chip_info::num_channels
int32_t num_channels
Definition: ad9361_util.h:90
int_sqrt
uint32_t int_sqrt(uint32_t x)
int_sqrt
Definition: ad9361_util.c:230
ad9361_rf_phy::adc_conv
struct axiadc_converter * adc_conv
Definition: ad9361.h:3408
axiadc_converter::chip_info
struct axiadc_chip_info * chip_info
Definition: ad9361_util.h:94
TX_SAMPL_CLK
@ TX_SAMPL_CLK
Definition: ad9361.h:3280
AXI_ADC_REG_CNTRL
#define AXI_ADC_REG_CNTRL
Definition: axi_adc_core.h:55