no-OS
parameters.h
Go to the documentation of this file.
1 /***************************************************************************/
39 #ifndef _PARAMETERS_H_
40 #define _PARAMETERS_H_
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include "app_config.h"
46 #ifdef ALTERA_PLATFORM
47 #include "system.h"
48 #else
49 #include "xparameters.h"
50 #endif
51 
52 /******************************************************************************/
53 /********************** Macros and Constants Definitions **********************/
54 /******************************************************************************/
55 #ifdef ALTERA_PLATFORM
56 
57 #define GPIO_OFFSET 0
58 
59 #define GPIO_DEVICE_ID 0
60 #define SPI_DEVICE_ID 0
61 
62 #define GPIO_BASEADDR SYS_GPIO_OUT_BASE
63 #define SPI_BASEADDR SYS_SPI_BASE
64 
65 #define DDR_MEM_BASEADDR SYS_DDR3_CNTRL_ARCH_BASE
66 #define ADC_DDR_BASEADDR SYS_DDR3_CNTRL_ARCH_BASE + 0x800000
67 #define DAC_DDR_BASEADDR SYS_DDR3_CNTRL_ARCH_BASE + 0xA000000
68 
69 #define RX_A10_FPLL_BASEADDR AD9371_RX_JESD204_LINK_PLL_RECONFIG_BASE
70 #define TX_A10_FPLL_BASEADDR AD9371_TX_JESD204_LINK_PLL_RECONFIG_BASE
71 #define RX_OS_A10_FPLL_BASEADDR AD9371_RX_OS_JESD204_LINK_PLL_RECONFIG_BASE
72 
73 #define RX_JESD_BASEADDR AD9371_RX_JESD204_LINK_RECONFIG_BASE
74 #define TX_JESD_BASEADDR AD9371_TX_JESD204_LINK_RECONFIG_BASE
75 #define RX_OS_JESD_BASEADDR AD9371_RX_OS_JESD204_LINK_RECONFIG_BASE
76 
77 #define RX_XCVR_BASEADDR AD9371_RX_JESD204_LINK_MANAGEMENT_BASE
78 #define TX_XCVR_BASEADDR AD9371_TX_JESD204_LINK_MANAGEMENT_BASE
79 #define RX_OS_XCVR_BASEADDR AD9371_RX_OS_JESD204_LINK_MANAGEMENT_BASE
80 
81 #define RX_ADXCFG_0_BASEADDR AVL_ADXCFG_0_RCFG_S1_BASE
82 #define RX_ADXCFG_1_BASEADDR AVL_ADXCFG_1_RCFG_S1_BASE
83 #define TX_ADXCFG_0_BASEADDR AVL_ADXCFG_0_RCFG_S0_BASE
84 #define TX_ADXCFG_1_BASEADDR AVL_ADXCFG_1_RCFG_S0_BASE
85 #define TX_ADXCFG_2_BASEADDR AVL_ADXCFG_2_RCFG_S0_BASE
86 #define TX_ADXCFG_3_BASEADDR AVL_ADXCFG_3_RCFG_S0_BASE
87 #define RX_OS_ADXCFG_0_BASEADDR AVL_ADXCFG_2_RCFG_S1_BASE
88 #define RX_OS_ADXCFG_1_BASEADDR AVL_ADXCFG_3_RCFG_S1_BASE
89 
90 #define TX_PLL_BASEADDR AD9371_TX_JESD204_LANE_PLL_RECONFIG_BASE
91 
92 #define RX_CORE_BASEADDR AXI_AD9371_BASE
93 #define TX_CORE_BASEADDR AXI_AD9371_BASE + 0x4000
94 #define RX_OS_CORE_BASEADDR AXI_AD9371_BASE + 0x8000
95 
96 #define RX_OBS_DMA_BASEADDR AXI_AD9371_RX_OS_DMA_BASE
97 #define RX_DMA_BASEADDR AXI_AD9371_RX_DMA_BASE
98 #define TX_DMA_BASEADDR AXI_AD9371_TX_DMA_BASE
99 #else
100 #ifdef _XPARAMETERS_PS_H_
101 #ifdef XPS_BOARD_ZCU102
102 #define GPIO_OFFSET 78
103 
104 #define GPIO_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
105 #define SPI_DEVICE_ID XPAR_PSU_SPI_0_DEVICE_ID
106 #define UART_IRQ_ID XPAR_XUARTPS_0_INTR
107 #else
108 #define GPIO_OFFSET 54
109 
110 #define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
111 #define SPI_DEVICE_ID XPAR_PS7_SPI_0_DEVICE_ID
112 #define UART_IRQ_ID XPAR_XUARTPS_1_INTR
113 #endif
114 
115 #define DDR_MEM_BASEADDR XPAR_DDR_MEM_BASEADDR
116 #else
117 #define GPIO_OFFSET 0
118 
119 #define GPIO_DEVICE_ID XPAR_GPIO_0_DEVICE_ID
120 #define SPI_DEVICE_ID XPAR_SPI_0_DEVICE_ID
121 #define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
122 
123 #define DDR_MEM_BASEADDR XPAR_AXI_DDR_CNTRL_BASEADDR
124 #endif
125 
126 #define RX_CLKGEN_BASEADDR XPAR_AXI_AD9371_RX_CLKGEN_BASEADDR
127 #define TX_CLKGEN_BASEADDR XPAR_AXI_AD9371_TX_CLKGEN_BASEADDR
128 #define RX_OS_CLKGEN_BASEADDR XPAR_AXI_AD9371_RX_OS_CLKGEN_BASEADDR
129 
130 #define RX_JESD_BASEADDR XPAR_AXI_AD9371_RX_JESD_RX_AXI_BASEADDR
131 #define TX_JESD_BASEADDR XPAR_AXI_AD9371_TX_JESD_TX_AXI_BASEADDR
132 #define RX_OS_JESD_BASEADDR XPAR_AXI_AD9371_RX_OS_JESD_RX_AXI_BASEADDR
133 
134 #define RX_XCVR_BASEADDR XPAR_AXI_AD9371_RX_XCVR_BASEADDR
135 #define TX_XCVR_BASEADDR XPAR_AXI_AD9371_TX_XCVR_BASEADDR
136 #define RX_OS_XCVR_BASEADDR XPAR_AXI_AD9371_RX_OS_XCVR_BASEADDR
137 
138 #ifdef XPAR_AXI_AD9371_CORE_BASEADDR
139 #define RX_CORE_BASEADDR XPAR_AXI_AD9371_CORE_BASEADDR
140 #define TX_CORE_BASEADDR XPAR_AXI_AD9371_CORE_BASEADDR + 0x4000
141 #define RX_OS_CORE_BASEADDR XPAR_AXI_AD9371_CORE_BASEADDR + 0x8000
142 #else
143 #define RX_CORE_BASEADDR XPAR_RX_AD9371_TPL_CORE_ADC_TPL_CORE_BASEADDR
144 #define TX_CORE_BASEADDR XPAR_TX_AD9371_TPL_CORE_DAC_TPL_CORE_BASEADDR
145 #define RX_OS_CORE_BASEADDR XPAR_RX_OS_AD9371_TPL_CORE_ADC_TPL_CORE_BASEADDR
146 #endif
147 
148 #define RX_OBS_DMA_BASEADDR XPAR_AXI_AD9371_RX_OS_DMA_BASEADDR
149 #define RX_DMA_BASEADDR XPAR_AXI_AD9371_RX_DMA_BASEADDR
150 #define TX_DMA_BASEADDR XPAR_AXI_AD9371_TX_DMA_BASEADDR
151 #endif
152 
153 #if defined(DAC_DMA_EXAMPLE) || defined(IIO_SUPPORT)
154 #define DAC_BUFFER_SAMPLES 1024
155 #define ADC_BUFFER_SAMPLES 16384
156 #define ADC_CHANNELS 4
157 #endif
158 
159 #ifdef _XPARAMETERS_PS_H_
160 #define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
161 #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
162 #else /* _XPARAMETERS_PS_H_ */
163 #define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
164 #define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
165 #endif /* _XPARAMETERS_PS_H_ */
166 #define AD9528_CS 1
167 #define AD9371_CS 2
168 
169 #define DAC_GPIO_PLDDR_BYPASS GPIO_OFFSET + 60
170 #define AD9528_RESET_B GPIO_OFFSET + 59
171 #define AD9528_SYSREF_REQ GPIO_OFFSET + 58
172 #define AD9371_RESET_B GPIO_OFFSET + 52
173 
174 #endif