no-OS
ad9523.h
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1 /***************************************************************************/
40 #ifndef _AD9523_H_
41 #define _AD9523_H_
42 
43 /******************************************************************************/
44 /***************************** Include Files **********************************/
45 /******************************************************************************/
46 #include <stdint.h>
47 #include "no_os_delay.h"
48 #include "no_os_spi.h"
49 
50 /******************************************************************************/
51 /****************************** AD9523 ****************************************/
52 /******************************************************************************/
53 /* Registers */
54 
55 #define AD9523_READ (1 << 15)
56 #define AD9523_WRITE (0 << 15)
57 #define AD9523_CNT(x) (((x) - 1) << 13)
58 #define AD9523_ADDR(x) ((x) & 0xFFF)
59 
60 #define AD9523_R1B (1 << 16)
61 #define AD9523_R2B (2 << 16)
62 #define AD9523_R3B (3 << 16)
63 #define AD9523_TRANSF_LEN(x) ((x) >> 16)
64 
65 #define AD9523_SERIAL_PORT_CONFIG (AD9523_R1B | 0x0)
66 #define AD9523_VERSION_REGISTER (AD9523_R1B | 0x2)
67 #define AD9523_PART_REGISTER (AD9523_R1B | 0x3)
68 #define AD9523_READBACK_CTRL (AD9523_R1B | 0x4)
69 
70 #define AD9523_EEPROM_CUSTOMER_VERSION_ID (AD9523_R2B | 0x6)
71 
72 #define AD9523_PLL1_REF_A_DIVIDER (AD9523_R2B | 0x11)
73 #define AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B | 0x13)
74 #define AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B | 0x14)
75 #define AD9523_PLL1_FEEDBACK_DIVIDER (AD9523_R2B | 0x17)
76 #define AD9523_PLL1_CHARGE_PUMP_CTRL (AD9523_R2B | 0x19)
77 #define AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B | 0x1A)
78 #define AD9523_PLL1_REF_CTRL (AD9523_R1B | 0x1B)
79 #define AD9523_PLL1_MISC_CTRL (AD9523_R1B | 0x1C)
80 #define AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B | 0x1D)
81 
82 #define AD9523_PLL2_CHARGE_PUMP (AD9523_R1B | 0xF0)
83 #define AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B | 0xF1)
84 #define AD9523_PLL2_CTRL (AD9523_R1B | 0xF2)
85 #define AD9523_PLL2_VCO_CTRL (AD9523_R1B | 0xF3)
86 #define AD9523_PLL2_VCO_DIVIDER (AD9523_R1B | 0xF4)
87 #define AD9523_PLL2_LOOP_FILTER_CTRL (AD9523_R2B | 0xF6)
88 #define AD9523_PLL2_R2_DIVIDER (AD9523_R1B | 0xF7)
89 
90 #define AD9523_CHANNEL_CLOCK_DIST(ch) (AD9523_R3B | (0x192 + 3 * ch))
91 
92 #define AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B | 0x1BA)
93 #define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB)
94 
95 #define AD9523_READBACK_0 (AD9523_R1B | 0x22C)
96 #define AD9523_READBACK_1 (AD9523_R1B | 0x22D)
97 
98 #define AD9523_STATUS_SIGNALS (AD9523_R3B | 0x232)
99 #define AD9523_POWER_DOWN_CTRL (AD9523_R1B | 0x233)
100 #define AD9523_IO_UPDATE (AD9523_R1B | 0x234)
101 
102 #define AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B | 0xB00)
103 #define AD9523_EEPROM_ERROR_READBACK (AD9523_R1B | 0xB01)
104 #define AD9523_EEPROM_CTRL1 (AD9523_R1B | 0xB02)
105 #define AD9523_EEPROM_CTRL2 (AD9523_R1B | 0xB03)
106 
107 /* AD9523_SERIAL_PORT_CONFIG */
108 
109 #define AD9523_SER_CONF_SDO_ACTIVE ((1 << 7) | (1 << 0))
110 #define AD9523_SER_CONF_SOFT_RESET ((1 << 5) | (1 << 2))
111 
112 /* AD9523_READBACK_CTRL */
113 #define AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0)
114 
115 /* AD9523_PLL1_CHARGE_PUMP_CTRL */
116 #define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x) (((x) / 500) & 0x7F)
117 #define AD9523_PLL1_CHARGE_PUMP_TRISTATE (1 << 7)
118 #define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)
119 #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8)
120 #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8)
121 #define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8)
122 #define AD9523_PLL1_BACKLASH_PW_MIN (0 << 10)
123 #define AD9523_PLL1_BACKLASH_PW_LOW (1 << 10)
124 #define AD9523_PLL1_BACKLASH_PW_HIGH (2 << 10)
125 #define AD9523_PLL1_BACKLASH_PW_MAX (3 << 10)
126 
127 /* AD9523_PLL1_INPUT_RECEIVERS_CTRL */
128 #define AD9523_PLL1_REF_TEST_RCV_EN (1 << 7)
129 #define AD9523_PLL1_REFB_DIFF_RCV_EN (1 << 6)
130 #define AD9523_PLL1_REFA_DIFF_RCV_EN (1 << 5)
131 #define AD9523_PLL1_REFB_RCV_EN (1 << 4)
132 #define AD9523_PLL1_REFA_RCV_EN (1 << 3)
133 #define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2)
134 #define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1)
135 #define AD9523_PLL1_OSC_IN_DIFF_EN (1 << 0)
136 
137 /* AD9523_PLL1_REF_CTRL */
138 #define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN (1 << 7)
139 #define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN (1 << 6)
140 #define AD9523_PLL1_ZERO_DELAY_MODE_INT (1 << 5)
141 #define AD9523_PLL1_ZERO_DELAY_MODE_EXT (0 << 5)
142 #define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN (1 << 4)
143 #define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN (1 << 3)
144 #define AD9523_PLL1_ZD_IN_DIFF_EN (1 << 2)
145 #define AD9523_PLL1_REFB_CMOS_NEG_INP_EN (1 << 1)
146 #define AD9523_PLL1_REFA_CMOS_NEG_INP_EN (1 << 0)
147 
148 /* AD9523_PLL1_MISC_CTRL */
149 #define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN (1 << 7)
150 #define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 6)
151 #define AD9523_PLL1_REF_MODE(x) ((x) << 2)
152 #define AD9523_PLL1_BYPASS_REFB_DIV (1 << 1)
153 #define AD9523_PLL1_BYPASS_REFA_DIV (1 << 0)
154 
155 /* AD9523_PLL1_LOOP_FILTER_CTRL */
156 #define AD9523_PLL1_LOOP_FILTER_RZERO(x) ((x) & 0xF)
157 
158 /* AD9523_PLL2_CHARGE_PUMP */
159 #define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x) ((x) / 3500)
160 
161 /* AD9523_PLL2_FEEDBACK_DIVIDER_AB */
162 #define AD9523_PLL2_FB_NDIV_A_CNT(x) (((x) & 0x3) << 6)
163 #define AD9523_PLL2_FB_NDIV_B_CNT(x) (((x) & 0x3F) << 0)
164 #define AD9523_PLL2_FB_NDIV(a, b) (4 * (b) + (a))
165 
166 /* AD9523_PLL2_CTRL */
167 #define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)
168 #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0)
169 #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0)
170 #define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0)
171 #define AD9523_PLL2_BACKLASH_PW_MIN (0 << 2)
172 #define AD9523_PLL2_BACKLASH_PW_LOW (1 << 2)
173 #define AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2)
174 #define AD9523_PLL2_BACKLASH_PW_MAX (3 << 1)
175 #define AD9523_PLL2_BACKLASH_CTRL_EN (1 << 4)
176 #define AD9523_PLL2_FREQ_DOUBLER_EN (1 << 5)
177 #define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)
178 
179 /* AD9523_PLL2_VCO_CTRL */
180 #define AD9523_PLL2_VCO_CALIBRATE (1 << 1)
181 #define AD9523_PLL2_FORCE_VCO_MIDSCALE (1 << 2)
182 #define AD9523_PLL2_FORCE_REFERENCE_VALID (1 << 3)
183 #define AD9523_PLL2_FORCE_RELEASE_SYNC (1 << 4)
184 
185 /* AD9523_PLL2_VCO_DIVIDER */
186 #define AD9523_PLL2_VCO_DIV_M1(x) ((((x) - 3) & 0x3) << 0)
187 #define AD9523_PLL2_VCO_DIV_M2(x) ((((x) - 3) & 0x3) << 4)
188 #define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 2)
189 #define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN (1 << 6)
190 
191 /* AD9523_PLL2_LOOP_FILTER_CTRL */
192 #define AD9523_PLL2_LOOP_FILTER_CPOLE1(x) (((x) & 0x7) << 0)
193 #define AD9523_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3)
194 #define AD9523_PLL2_LOOP_FILTER_RPOLE2(x) (((x) & 0x7) << 6)
195 #define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)
196 
197 /* AD9523_PLL2_R2_DIVIDER */
198 #define AD9523_PLL2_R2_DIVIDER_VAL(x) (((x) & 0x1F) << 0)
199 
200 /* AD9523_CHANNEL_CLOCK_DIST */
201 #define AD9523_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 18)
202 #define AD9523_CLK_DIST_DIV_PHASE_REV(x) ((ret >> 18) & 0x3F)
203 #define AD9523_CLK_DIST_DIV(x) ((((x) - 1) & 0x3FF) << 8)
204 #define AD9523_CLK_DIST_DIV_REV(x) (((ret >> 8) & 0x3FF) + 1)
205 #define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7)
206 #define AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6)
207 #define AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5)
208 #define AD9523_CLK_DIST_LOW_PWR_MODE_EN (1 << 4)
209 #define AD9523_CLK_DIST_DRIVER_MODE(x) (((x) & 0xF) << 0)
210 
211 /* AD9523_PLL1_OUTPUT_CTRL */
212 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2 (1 << 7)
213 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6)
214 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 (1 << 5)
215 #define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK (1 << 4)
216 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1 (0 << 0)
217 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2 (1 << 0)
218 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4 (2 << 0)
219 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8 (4 << 0)
220 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16 (8 << 0)
221 
222 /* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */
223 #define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7)
224 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6)
225 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5)
226 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4)
227 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3 (1 << 3)
228 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2 (1 << 2)
229 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1 (1 << 1)
230 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 (1 << 0)
231 
232 /* AD9523_READBACK_0 */
233 #define AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7)
234 #define AD9523_READBACK_0_STAT_PLL2_FB_CLK (1 << 6)
235 #define AD9523_READBACK_0_STAT_VCXO (1 << 5)
236 #define AD9523_READBACK_0_STAT_REF_TEST (1 << 4)
237 #define AD9523_READBACK_0_STAT_REFB (1 << 3)
238 #define AD9523_READBACK_0_STAT_REFA (1 << 2)
239 #define AD9523_READBACK_0_STAT_PLL2_LD (1 << 1)
240 #define AD9523_READBACK_0_STAT_PLL1_LD (1 << 0)
241 
242 /* AD9523_READBACK_1 */
243 #define AD9523_READBACK_1_HOLDOVER_ACTIVE (1 << 3)
244 #define AD9523_READBACK_1_AUTOMODE_SEL_REFB (1 << 2)
245 #define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS (1 << 0)
246 
247 /* AD9523_STATUS_SIGNALS */
248 #define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL (1 << 16)
249 #define AD9523_STATUS_MONITOR_01_PLL12_LOCKED (0x302)
250 /* AD9523_POWER_DOWN_CTRL */
251 #define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN (1 << 2)
252 #define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN (1 << 1)
253 #define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN (1 << 0)
254 
255 /* AD9523_IO_UPDATE */
256 #define AD9523_IO_UPDATE_EN (1 << 0)
257 
258 /* AD9523_EEPROM_DATA_XFER_STATUS */
259 #define AD9523_EEPROM_DATA_XFER_IN_PROGRESS (1 << 0)
260 
261 /* AD9523_EEPROM_ERROR_READBACK */
262 #define AD9523_EEPROM_ERROR_READBACK_FAIL (1 << 0)
263 
264 /* AD9523_EEPROM_CTRL1 */
265 #define AD9523_EEPROM_CTRL1_SOFT_EEPROM (1 << 1)
266 #define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS (1 << 0)
267 
268 /* AD9523_EEPROM_CTRL2 */
269 #define AD9523_EEPROM_CTRL2_REG2EEPROM (1 << 0)
270 
271 #define AD9523_NUM_CHAN 14
272 #define AD9523_NUM_CHAN_ALT_CLK_SRC 10
273 
274 /******************************************************************************/
275 /************************ Types Definitions ***********************************/
276 /******************************************************************************/
293 };
294 
301 };
302 
309  uint8_t channel_num;
313  uint8_t sync_ignore_en;
319  uint8_t output_dis;
321  uint8_t driver_mode;
325  uint8_t divider_phase;
327  uint16_t channel_divider;
329  int8_t extended_name[16];
330 };
331 
339 };
340 
346 };
347 
357 };
358 
364  _CPOLE1_24_PF, /* place holder */
368 };
369 
376  uint32_t vcxo_freq;
378  uint8_t spi3wire;
379 
385  uint8_t zd_in_diff_en;
387  uint8_t osc_in_diff_en;
388 
389  /*
390  * Valid if differential input disabled
391  * if not true defaults to pos input
392  */
395  /* REFB single-ended neg./pos. input enable. */
401 
402  /* PLL1 Setting */
404  uint16_t refa_r_div;
406  uint16_t refb_r_div;
417 
419  uint8_t pll1_bypass_en;
422 
424  uint8_t ref_mode;
425 
426  /* PLL2 Setting */
436  uint8_t pll2_r2_div;
441 
442  /* Loop Filter PLL2 */
444  uint8_t rpole2;
446  uint8_t rzero;
448  uint8_t cpole1;
451 
452  /* Output Channel Configuration */
454  int32_t num_channels;
457 
459  int8_t name[16];
460 };
461 
462 struct ad9523_state {
464  uint32_t vcxo_freq;
465  uint32_t vco_freq;
466  uint32_t vco_out_freq[3];
467  uint8_t vco_out_map[14];
468 };
469 
475 };
476 
477 struct ad9523_dev {
478  /* SPI */
480  /* Device Settings */
483 };
484 
486  /* SPI */
488  /* Device Settings */
490 };
491 
492 /******************************************************************************/
493 /************************ Functions Declarations ******************************/
494 /******************************************************************************/
495 /* Reads the value of the selected register. */
496 int32_t ad9523_spi_read(struct ad9523_dev *dev,
497  uint32_t reg_addr,
498  uint32_t *reg_data);
499 
500 /* Writes a value to the selected register. */
501 int32_t ad9523_spi_write(struct ad9523_dev *dev,
502  uint32_t reg_addr,
503  uint32_t reg_data);
504 
505 /* Updates the AD9523 configuration */
506 int32_t ad9523_io_update(struct ad9523_dev *dev);
507 
508 /* Sets the clock provider for selected channel. */
509 int32_t ad9523_vco_out_map(struct ad9523_dev *dev,
510  uint32_t ch,
511  uint32_t out);
512 
513 /* Updates the AD9523 configuration. */
514 int32_t ad9523_sync(struct ad9523_dev *dev);
515 
516 /* Initialize the AD9523 data structure*/
517 int32_t ad9523_init(struct ad9523_init_param *init_param);
518 
519 /* Configure the AD9523. */
520 int32_t ad9523_setup(struct ad9523_dev **device,
521  const struct ad9523_init_param *init_param);
522 
523 /* Free the resources allocated by ad9523_setup(). */
524 int32_t ad9523_remove(struct ad9523_dev *dev);
525 
526 int32_t ad9523_status(struct ad9523_dev *dev);
527 #endif // __AD9523_H__
AD9523_PLL2_LOOP_FILTER_RPOLE2
#define AD9523_PLL2_LOOP_FILTER_RPOLE2(x)
Definition: ad9523.h:194
AD9523_READBACK_CTRL
#define AD9523_READBACK_CTRL
Definition: ad9523.h:68
ad9523_status
int32_t ad9523_status(struct ad9523_dev *dev)
Updates the AD9523 configuration.
Definition: ad9523.c:256
AD9523_PLL2_VCO_CTRL
#define AD9523_PLL2_VCO_CTRL
Definition: ad9523.h:85
ad9523_channel_spec::divider_output_invert_en
uint8_t divider_output_invert_en
Definition: ad9523.h:311
ad9523_platform_data::channels
struct ad9523_channel_spec * channels
Definition: ad9523.h:456
ad9523_platform_data::osc_in_diff_en
uint8_t osc_in_diff_en
Definition: ad9523.h:387
CMOS_CONF9
@ CMOS_CONF9
Definition: ad9523.h:292
RZERO_2750_OHM
@ RZERO_2750_OHM
Definition: ad9523.h:350
AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN
#define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN
Definition: ad9523.h:188
ad9523_channel_spec::use_alt_clock_src
uint8_t use_alt_clock_src
Definition: ad9523.h:317
AD9523_PLL1_OUTPUT_CHANNEL_CTRL
#define AD9523_PLL1_OUTPUT_CHANNEL_CTRL
Definition: ad9523.h:93
AD9523_PLL1_CHARGE_PUMP_CURRENT_nA
#define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x)
Definition: ad9523.h:116
AD9523_PLL1_REFA_CMOS_NEG_INP_EN
#define AD9523_PLL1_REFA_CMOS_NEG_INP_EN
Definition: ad9523.h:146
RZERO_3250_OHM
@ RZERO_3250_OHM
Definition: ad9523.h:349
CPOLE1_40_PF
@ CPOLE1_40_PF
Definition: ad9523.h:366
HSTL1_8mA
@ HSTL1_8mA
Definition: ad9523.h:283
AD9523_CLK_DIST_DIV_PHASE
#define AD9523_CLK_DIST_DIV_PHASE(x)
Definition: ad9523.h:201
AD9523_PLL2_FREQ_DOUBLER_EN
#define AD9523_PLL2_FREQ_DOUBLER_EN
Definition: ad9523.h:176
RPOLE2_225_OHM
@ RPOLE2_225_OHM
Definition: ad9523.h:345
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
RZERO_10_OHM
@ RZERO_10_OHM
Definition: ad9523.h:337
ad9523_platform_data::pll2_vco_diff_m1
uint8_t pll2_vco_diff_m1
Definition: ad9523.h:438
ad9523_channel_spec::channel_num
uint8_t channel_num
Definition: ad9523.h:309
AD9523_CLK_DIST_PWR_DOWN_EN
#define AD9523_CLK_DIST_PWR_DOWN_EN
Definition: ad9523.h:207
AD9523_PLL1_REF_MODE
#define AD9523_PLL1_REF_MODE(x)
Definition: ad9523.h:151
no_os_spi.h
Header file of SPI Interface.
ad9523_sync
int32_t ad9523_sync(struct ad9523_dev *dev)
Updates the AD9523 configuration.
Definition: ad9523.c:310
RPOLE2_900_OHM
@ RPOLE2_900_OHM
Definition: ad9523.h:342
AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2
#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2
Definition: ad9523.h:214
AD9523_STATUS_MONITOR_01_PLL12_LOCKED
#define AD9523_STATUS_MONITOR_01_PLL12_LOCKED
Definition: ad9523.h:249
ad9523_platform_data::refb_diff_rcv_en
uint8_t refb_diff_rcv_en
Definition: ad9523.h:383
AD9523_SER_CONF_SOFT_RESET
#define AD9523_SER_CONF_SOFT_RESET
Definition: ad9523.h:110
AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN
#define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN
Definition: ad9523.h:139
AD9523_PLL2_FB_NDIV_B_CNT
#define AD9523_PLL2_FB_NDIV_B_CNT(x)
Definition: ad9523.h:163
AD9523_PLL1_LOOP_FILTER_RZERO
#define AD9523_PLL1_LOOP_FILTER_RZERO(x)
Definition: ad9523.h:156
AD9523_CLK_DIST_DIV
#define AD9523_CLK_DIST_DIV(x)
Definition: ad9523.h:203
ad9523_dev::spi_desc
no_os_spi_desc * spi_desc
Definition: ad9523.h:479
RPOLE2_450_OHM
@ RPOLE2_450_OHM
Definition: ad9523.h:343
AD9523_PLL2_FB_NDIV
#define AD9523_PLL2_FB_NDIV(a, b)
Definition: ad9523.h:164
AD9523_PLL2_LOOP_FILTER_RZERO
#define AD9523_PLL2_LOOP_FILTER_RZERO(x)
Definition: ad9523.h:193
AD9523_SER_CONF_SDO_ACTIVE
#define AD9523_SER_CONF_SDO_ACTIVE
Definition: ad9523.h:109
no_os_delay.h
Header file of Delay functions.
AD9523_PLL1_REFB_RCV_EN
#define AD9523_PLL1_REFB_RCV_EN
Definition: ad9523.h:131
AD9523_VCXO
@ AD9523_VCXO
Definition: ad9523.h:473
ad9523_setup
int32_t ad9523_setup(struct ad9523_dev **device, const struct ad9523_init_param *init_param)
Setup the AD9523 device.
Definition: ad9523.c:425
AD9523_PLL2_R2_DIVIDER
#define AD9523_PLL2_R2_DIVIDER
Definition: ad9523.h:88
ad9523_platform_data::refb_cmos_neg_inp_en
uint8_t refb_cmos_neg_inp_en
Definition: ad9523.h:396
ad9523_init_param::pdata
struct ad9523_platform_data * pdata
Definition: ad9523.h:489
AD9523_READBACK_0_STAT_PLL2_REF_CLK
#define AD9523_READBACK_0_STAT_PLL2_REF_CLK
Definition: ad9523.h:233
ad9523_channel_spec::sync_ignore_en
uint8_t sync_ignore_en
Definition: ad9523.h:313
AD9523_PLL1_ZD_IN_DIFF_EN
#define AD9523_PLL1_ZD_IN_DIFF_EN
Definition: ad9523.h:144
ad9523_vco_out_map
int32_t ad9523_vco_out_map(struct ad9523_dev *dev, uint32_t ch, uint32_t out)
Sets the clock provider for selected channel.
Definition: ad9523.c:140
CPOLE1_24_PF
@ CPOLE1_24_PF
Definition: ad9523.h:363
CMOS_CONF6
@ CMOS_CONF6
Definition: ad9523.h:289
CMOS_CONF3
@ CMOS_CONF3
Definition: ad9523.h:286
AD9523_VCO1
@ AD9523_VCO1
Definition: ad9523.h:471
device
Definition: ad9361_util.h:75
AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL
#define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL
Definition: ad9523.h:248
RZERO_3000_OHM
@ RZERO_3000_OHM
Definition: ad9523.h:353
AD9523_CLK_DIST_DRIVER_MODE
#define AD9523_CLK_DIST_DRIVER_MODE(x)
Definition: ad9523.h:209
AD9523_READBACK_0_STAT_VCXO
#define AD9523_READBACK_0_STAT_VCXO
Definition: ad9523.h:235
ad9523_platform_data::pll1_bypass_en
uint8_t pll1_bypass_en
Definition: ad9523.h:419
CPOLE1_32_PF
@ CPOLE1_32_PF
Definition: ad9523.h:365
AD9523_PLL1_CHARGE_PUMP_TRISTATE
#define AD9523_PLL1_CHARGE_PUMP_TRISTATE
Definition: ad9523.h:117
_CPOLE1_24_PF
@ _CPOLE1_24_PF
Definition: ad9523.h:364
ad9523_vco_out_map
int32_t ad9523_vco_out_map(struct ad9523_dev *dev, uint32_t ch, uint32_t out)
Sets the clock provider for selected channel.
Definition: ad9523.c:140
AD9523_PLL1_OSC_IN_DIFF_EN
#define AD9523_PLL1_OSC_IN_DIFF_EN
Definition: ad9523.h:135
ad9523_io_update
int32_t ad9523_io_update(struct ad9523_dev *dev)
Updates the AD9523 configuration.
Definition: ad9523.c:124
ad9523_channel_spec
Output channel configuration.
Definition: ad9523.h:307
AD9523_PLL1_REFA_RCV_EN
#define AD9523_PLL1_REFA_RCV_EN
Definition: ad9523.h:132
outp_drv_mode
outp_drv_mode
Definition: ad9523.h:277
AD9523_PLL1_ZERO_DELAY_MODE_INT
#define AD9523_PLL1_ZERO_DELAY_MODE_INT
Definition: ad9523.h:140
AD9523_CLK_DIST_IGNORE_SYNC_EN
#define AD9523_CLK_DIST_IGNORE_SYNC_EN
Definition: ad9523.h:206
CPOLE1_16_PF
@ CPOLE1_16_PF
Definition: ad9523.h:362
AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN
#define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN
Definition: ad9523.h:142
RZERO_883_OHM
@ RZERO_883_OHM
Definition: ad9523.h:333
AD9523_PLL1_CHARGE_PUMP_CTRL
#define AD9523_PLL1_CHARGE_PUMP_CTRL
Definition: ad9523.h:76
ad9523_init_param
Definition: ad9523.h:485
AD9523_PLL1_MISC_CTRL
#define AD9523_PLL1_MISC_CTRL
Definition: ad9523.h:79
AD9523_IO_UPDATE_EN
#define AD9523_IO_UPDATE_EN
Definition: ad9523.h:256
ad9523_io_update
int32_t ad9523_io_update(struct ad9523_dev *dev)
Updates the AD9523 configuration.
Definition: ad9523.c:124
CMOS_CONF1
@ CMOS_CONF1
Definition: ad9523.h:284
ad9523_platform_data::cpole1
uint8_t cpole1
Definition: ad9523.h:448
ad9523_remove
int32_t ad9523_remove(struct ad9523_dev *dev)
Free the resources allocated by ad9523_setup().
Definition: ad9523.c:728
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
AD9523_PLL2_BACKLASH_CTRL_EN
#define AD9523_PLL2_BACKLASH_CTRL_EN
Definition: ad9523.h:175
AD_IF
#define AD_IF(_pde, _a)
Definition: ad9523.c:50
ad9523_platform_data::pll2_freq_doubler_en
uint8_t pll2_freq_doubler_en
Definition: ad9523.h:434
ad9523_spi_read
int32_t ad9523_spi_read(struct ad9523_dev *dev, uint32_t reg_addr, uint32_t *reg_data)
Reads the value of the selected register.
Definition: ad9523.c:61
ad9523_platform_data::rzero
uint8_t rzero
Definition: ad9523.h:446
RPOLE2_300_OHM
@ RPOLE2_300_OHM
Definition: ad9523.h:344
CPOLE1_0_PF
@ CPOLE1_0_PF
Definition: ad9523.h:360
AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN
#define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN
Definition: ad9523.h:134
ad9523_channel_spec::low_power_mode_en
uint8_t low_power_mode_en
Definition: ad9523.h:315
LVDS_4mA
@ LVDS_4mA
Definition: ad9523.h:280
AD9523_PLL1_BACKLASH_PW_MIN
#define AD9523_PLL1_BACKLASH_PW_MIN
Definition: ad9523.h:122
AD9523_PLL2_R2_DIVIDER_VAL
#define AD9523_PLL2_R2_DIVIDER_VAL(x)
Definition: ad9523.h:198
AD9523_READBACK_0_STAT_REFA
#define AD9523_READBACK_0_STAT_REFA
Definition: ad9523.h:238
ad9523_dev
Definition: ad9523.h:477
ad9523.h
Header file of AD9523 Driver.
AD9523_PLL2_VCO_DIV_M2
#define AD9523_PLL2_VCO_DIV_M2(x)
Definition: ad9523.h:187
AD9523_PLL1_FEEDBACK_DIVIDER
#define AD9523_PLL1_FEEDBACK_DIVIDER
Definition: ad9523.h:75
ad9523_platform_data::rzero_bypass_en
uint8_t rzero_bypass_en
Definition: ad9523.h:450
CMOS_CONF2
@ CMOS_CONF2
Definition: ad9523.h:285
SELECT_REFA
@ SELECT_REFA
Definition: ad9523.h:298
ad9523_platform_data::num_channels
int32_t num_channels
Definition: ad9523.h:454
NONEREVERTIVE_STAY_ON_REFB
@ NONEREVERTIVE_STAY_ON_REFB
Definition: ad9523.h:296
AD9523_PLL2_LOOP_FILTER_CPOLE1
#define AD9523_PLL2_LOOP_FILTER_CPOLE1(x)
Definition: ad9523.h:192
ad9523_channel_spec::divider_phase
uint8_t divider_phase
Definition: ad9523.h:325
ad9523_platform_data::ref_mode
uint8_t ref_mode
Definition: ad9523.h:424
ad9523_init
int32_t ad9523_init(struct ad9523_init_param *init_param)
Initialize the AD9523 data structure with the default register values.
Definition: ad9523.c:350
ad9523_state::vcxo_freq
uint32_t vcxo_freq
Definition: ad9523.h:464
ad9523_spi_write
int32_t ad9523_spi_write(struct ad9523_dev *dev, uint32_t reg_addr, uint32_t reg_data)
Writes a value to the selected register.
Definition: ad9523.c:95
AD9523_READBACK_0_STAT_REFB
#define AD9523_READBACK_0_STAT_REFB
Definition: ad9523.h:237
ad9523_platform_data::rpole2
uint8_t rpole2
Definition: ad9523.h:444
ad9523_state::vco_freq
uint32_t vco_freq
Definition: ad9523.h:465
AD9523_NUM_CLK_SRC
@ AD9523_NUM_CLK_SRC
Definition: ad9523.h:474
TRISTATE
@ TRISTATE
Definition: ad9523.h:278
AD9523_STATUS_SIGNALS
#define AD9523_STATUS_SIGNALS
Definition: ad9523.h:98
ad9523_platform_data::pll2_vco_diff_m2
uint8_t pll2_vco_diff_m2
Definition: ad9523.h:440
EXT_REF_SEL
@ EXT_REF_SEL
Definition: ad9523.h:300
ad9523_init_param::spi_init
no_os_spi_init_param spi_init
Definition: ad9523.h:487
ad9523_sync
int32_t ad9523_sync(struct ad9523_dev *dev)
Updates the AD9523 configuration.
Definition: ad9523.c:310
ad9523_platform_data::zd_in_diff_en
uint8_t zd_in_diff_en
Definition: ad9523.h:385
AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL
#define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL
Definition: ad9523.h:118
CPOLE1_8_PF
@ CPOLE1_8_PF
Definition: ad9523.h:361
AD9523_READBACK_0_STAT_PLL1_LD
#define AD9523_READBACK_0_STAT_PLL1_LD
Definition: ad9523.h:240
AD9523_PLL2_FEEDBACK_DIVIDER_AB
#define AD9523_PLL2_FEEDBACK_DIVIDER_AB
Definition: ad9523.h:83
AD9523_SERIAL_PORT_CONFIG
#define AD9523_SERIAL_PORT_CONFIG
Definition: ad9523.h:65
AD9523_POWER_DOWN_CTRL
#define AD9523_POWER_DOWN_CTRL
Definition: ad9523.h:99
AD9523_READBACK_CTRL_READ_BUFFERED
#define AD9523_READBACK_CTRL_READ_BUFFERED
Definition: ad9523.h:113
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
ad9523_platform_data
platform specific information
Definition: ad9523.h:374
ad9523_platform_data::zero_delay_mode_internal_en
uint8_t zero_delay_mode_internal_en
Definition: ad9523.h:412
RZERO_USE_EXT_RES
@ RZERO_USE_EXT_RES
Definition: ad9523.h:338
RZERO_2250_OHM
@ RZERO_2250_OHM
Definition: ad9523.h:351
RZERO_2000_OHM
@ RZERO_2000_OHM
Definition: ad9523.h:355
ad9523_platform_data::vcxo_freq
uint32_t vcxo_freq
Definition: ad9523.h:376
CPOLE1_48_PF
@ CPOLE1_48_PF
Definition: ad9523.h:367
ad9523_platform_data::refa_diff_rcv_en
uint8_t refa_diff_rcv_en
Definition: ad9523.h:381
CMOS_CONF5
@ CMOS_CONF5
Definition: ad9523.h:288
ad9523_spi_read
int32_t ad9523_spi_read(struct ad9523_dev *dev, uint32_t reg_addr, uint32_t *reg_data)
Reads the value of the selected register.
Definition: ad9523.c:61
ad9523_status
int32_t ad9523_status(struct ad9523_dev *dev)
Updates the AD9523 configuration.
Definition: ad9523.c:256
AD9523_PLL2_VCO_DIV_M1
#define AD9523_PLL2_VCO_DIV_M1(x)
Definition: ad9523.h:186
AD9523_PLL1_REFB_CMOS_NEG_INP_EN
#define AD9523_PLL1_REFB_CMOS_NEG_INP_EN
Definition: ad9523.h:145
ad9523_platform_data::name
int8_t name[16]
Definition: ad9523.h:459
CMOS_CONF4
@ CMOS_CONF4
Definition: ad9523.h:287
ad9523_setup
int32_t ad9523_setup(struct ad9523_dev **device, const struct ad9523_init_param *init_param)
Setup the AD9523 device.
Definition: ad9523.c:425
AD9523_IO_UPDATE
#define AD9523_IO_UPDATE
Definition: ad9523.h:100
AD9523_PLL2_CTRL
#define AD9523_PLL2_CTRL
Definition: ad9523.h:84
AD9523_READBACK_0_STAT_PLL2_LD
#define AD9523_READBACK_0_STAT_PLL2_LD
Definition: ad9523.h:239
ad9523_platform_data::refa_cmos_neg_inp_en
uint8_t refa_cmos_neg_inp_en
Definition: ad9523.h:394
AD9523_PLL1_LOOP_FILTER_CTRL
#define AD9523_PLL1_LOOP_FILTER_CTRL
Definition: ad9523.h:80
cpole1_capacitor
cpole1_capacitor
Definition: ad9523.h:359
AD_IFE
#define AD_IFE(_pde, _a, _b)
Definition: ad9523.c:49
ad9523_channel_spec::channel_divider
uint16_t channel_divider
Definition: ad9523.h:327
HSTL0_16mA
@ HSTL0_16mA
Definition: ad9523.h:282
ad9523_platform_data::pll1_charge_pump_current_nA
uint16_t pll1_charge_pump_current_nA
Definition: ad9523.h:410
ad9523_platform_data::pll1_feedback_div
uint16_t pll1_feedback_div
Definition: ad9523.h:408
ad9523_out_frequencies
ad9523_out_frequencies
Definition: ad9523.h:470
RZERO_341_OHM
@ RZERO_341_OHM
Definition: ad9523.h:335
rpole2_resistor
rpole2_resistor
Definition: ad9523.h:341
AD9523_PLL2_LOOP_FILTER_CTRL
#define AD9523_PLL2_LOOP_FILTER_CTRL
Definition: ad9523.h:87
ad9517_lvds_cmos_channel_spec::channel_num
uint8_t channel_num
Definition: ad9517.h:362
LVPECL_8mA
@ LVPECL_8mA
Definition: ad9523.h:279
CMOS_CONF7
@ CMOS_CONF7
Definition: ad9523.h:290
RZERO_677_OHM
@ RZERO_677_OHM
Definition: ad9523.h:334
ad9523_platform_data::refa_r_div
uint16_t refa_r_div
Definition: ad9523.h:404
AD9523_TRANSF_LEN
#define AD9523_TRANSF_LEN(x)
Definition: ad9523.h:63
ad9523_state
Definition: ad9523.h:462
SELECT_REFB
@ SELECT_REFB
Definition: ad9523.h:299
AD9523_PLL2_VCO_CALIBRATE
#define AD9523_PLL2_VCO_CALIBRATE
Definition: ad9523.h:180
ad9523_channel_spec::extended_name
int8_t extended_name[16]
Definition: ad9523.h:329
ref_sel_mode
ref_sel_mode
Definition: ad9523.h:295
AD9523_PLL1_REFB_DIFF_RCV_EN
#define AD9523_PLL1_REFB_DIFF_RCV_EN
Definition: ad9523.h:129
ad9523_init
int32_t ad9523_init(struct ad9523_init_param *init_param)
Initialize the AD9523 data structure with the default register values.
Definition: ad9523.c:350
ad9523_platform_data::spi3wire
uint8_t spi3wire
Definition: ad9523.h:378
ad9523_state::pdata
struct ad9523_platform_data * pdata
Definition: ad9523.h:463
ad9523_platform_data::osc_in_cmos_neg_inp_en
uint8_t osc_in_cmos_neg_inp_en
Definition: ad9523.h:400
AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN
#define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN
Definition: ad9523.h:149
AD9523_PLL1_REFA_DIFF_RCV_EN
#define AD9523_PLL1_REFA_DIFF_RCV_EN
Definition: ad9523.h:130
AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN
#define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN
Definition: ad9523.h:189
AD9523_PLL1_INPUT_RECEIVERS_CTRL
#define AD9523_PLL1_INPUT_RECEIVERS_CTRL
Definition: ad9523.h:77
AD9523_CLK_DIST_INV_DIV_OUTPUT_EN
#define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN
Definition: ad9523.h:205
AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2
#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2
Definition: ad9523.h:226
ad9523_channel_spec::output_dis
uint8_t output_dis
Definition: ad9523.h:319
AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL
#define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL
Definition: ad9523.h:167
ad9523_remove
int32_t ad9523_remove(struct ad9523_dev *dev)
Free the resources allocated by ad9523_setup().
Definition: ad9523.c:728
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
AD9523_READBACK_0_STAT_PLL2_FB_CLK
#define AD9523_READBACK_0_STAT_PLL2_FB_CLK
Definition: ad9523.h:234
ad9523_platform_data::pll2_ndiv_b_cnt
uint8_t pll2_ndiv_b_cnt
Definition: ad9523.h:432
ad9523_platform_data::pll2_ndiv_a_cnt
uint8_t pll2_ndiv_a_cnt
Definition: ad9523.h:430
ad9523_dev::ad9523_st
struct ad9523_state ad9523_st
Definition: ad9523.h:481
AD9523_NUM_CHAN
#define AD9523_NUM_CHAN
Definition: ad9523.h:271
AD9523_PLL1_OUTPUT_CTRL
#define AD9523_PLL1_OUTPUT_CTRL
Definition: ad9523.h:92
AD9523_PLL2_FB_NDIV_A_CNT
#define AD9523_PLL2_FB_NDIV_A_CNT(x)
Definition: ad9523.h:162
RZERO_2100_OHM
@ RZERO_2100_OHM
Definition: ad9523.h:352
REVERT_TO_REFA
@ REVERT_TO_REFA
Definition: ad9523.h:297
AD9523_PLL2_CHARGE_PUMP
#define AD9523_PLL2_CHARGE_PUMP
Definition: ad9523.h:82
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
ad9523_channel_spec::driver_mode
uint8_t driver_mode
Definition: ad9523.h:321
ad9523_platform_data::osc_in_feedback_en
uint8_t osc_in_feedback_en
Definition: ad9523.h:416
AD9523_EEPROM_CUSTOMER_VERSION_ID
#define AD9523_EEPROM_CUSTOMER_VERSION_ID
Definition: ad9523.h:70
AD9523_READBACK_0
#define AD9523_READBACK_0
Definition: ad9523.h:95
AD9523_READBACK_1
#define AD9523_READBACK_1
Definition: ad9523.h:96
AD9523_READBACK_0_STAT_REF_TEST
#define AD9523_READBACK_0_STAT_REF_TEST
Definition: ad9523.h:236
ad9523_dev::pdata
struct ad9523_platform_data * pdata
Definition: ad9523.h:482
ad9523_platform_data::pll2_r2_div
uint8_t pll2_r2_div
Definition: ad9523.h:436
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
AD9523_PLL1_REF_CTRL
#define AD9523_PLL1_REF_CTRL
Definition: ad9523.h:78
ad9523_platform_data::refb_r_div
uint16_t refb_r_div
Definition: ad9523.h:406
ad9523_state::vco_out_map
uint8_t vco_out_map[14]
Definition: ad9523.h:467
LVDS_7mA
@ LVDS_7mA
Definition: ad9523.h:281
AD9523_PLL1_REFA_REFB_PWR_CTRL_EN
#define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN
Definition: ad9523.h:133
RZERO_135_OHM
@ RZERO_135_OHM
Definition: ad9523.h:336
AD9523_PLL2_CHARGE_PUMP_CURRENT_nA
#define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x)
Definition: ad9523.h:159
ad9523_spi_write
int32_t ad9523_spi_write(struct ad9523_dev *dev, uint32_t reg_addr, uint32_t reg_data)
Writes a value to the selected register.
Definition: ad9523.c:95
AD9523_PLL1_REF_B_DIVIDER
#define AD9523_PLL1_REF_B_DIVIDER
Definition: ad9523.h:73
AD9523_PLL1_REF_A_DIVIDER
#define AD9523_PLL1_REF_A_DIVIDER
Definition: ad9523.h:72
rzero_resistor
rzero_resistor
Definition: ad9523.h:348
ad9523_calibrate
int32_t ad9523_calibrate(struct ad9523_dev *dev)
Updates the AD9523 configuration.
Definition: ad9523.c:214
RZERO_2500_OHM
@ RZERO_2500_OHM
Definition: ad9523.h:354
CMOS_CONF8
@ CMOS_CONF8
Definition: ad9523.h:291
AD9523_PLL2_VCO_DIVIDER
#define AD9523_PLL2_VCO_DIVIDER
Definition: ad9523.h:86
ad9523_platform_data::zd_in_cmos_neg_inp_en
uint8_t zd_in_cmos_neg_inp_en
Definition: ad9523.h:398
pll1_rzero_resistor
pll1_rzero_resistor
Definition: ad9523.h:332
AD9523_VCO2
@ AD9523_VCO2
Definition: ad9523.h:472
ad9523_platform_data::pll1_loop_filter_rzero
uint8_t pll1_loop_filter_rzero
Definition: ad9523.h:421
AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN
#define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN
Definition: ad9523.h:143
AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0
#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0
Definition: ad9523.h:230
ad9523_state::vco_out_freq
uint32_t vco_out_freq[3]
Definition: ad9523.h:466
AD9523_CHANNEL_CLOCK_DIST
#define AD9523_CHANNEL_CLOCK_DIST(ch)
Definition: ad9523.h:90
AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN
#define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN
Definition: ad9523.h:195
RZERO_1850_OHM
@ RZERO_1850_OHM
Definition: ad9523.h:356
AD9523_CLK_DIST_LOW_PWR_MODE_EN
#define AD9523_CLK_DIST_LOW_PWR_MODE_EN
Definition: ad9523.h:208
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
ad9523_platform_data::pll2_charge_pump_current_nA
uint32_t pll2_charge_pump_current_nA
Definition: ad9523.h:428