no-OS
adas1000.h
Go to the documentation of this file.
1 /***************************************************************************/
42 #ifndef _ADAS1000_H_
43 #define _ADAS1000_H_
44 
45 /*****************************************************************************/
46 /***************************** Include Files *********************************/
47 /*****************************************************************************/
48 
49 #include <stdint.h>
50 #include <stdbool.h>
51 #include "no_os_spi.h"
52 
53 /******************************************************************************/
54 /* ADAS1000 SPI Registers Memory Map */
55 /******************************************************************************/
56 
57 #define ADAS1000_COMM_WRITE 0x80 /* SPI Write command */
58 #define ADAS1000_RDY_MASK 0x40 /* READY bit mask */
59 #define ADAS1000_ALL_CH_MASK 0x00 /* Word mask for activating all channels */
60 #define ADAS1000_WD_CNT_MASK 0x01 /* Word count mask */
61 
62 #define ADAS1000_NOP 0x00 /* NOP (No operation) */
63 #define ADAS1000_ECGCTL 0x01 /* ECG Setting Register */
64 #define ADAS1000_LOFFCTL 0x02 /* Leads off Control Register */
65 #define ADAS1000_RESPCTL 0x03 /* Respiration Control Register */
66 #define ADAS1000_PACECTL 0x04 /* Pace Detection Control Register */
67 #define ADAS1000_CMREFCTL 0x05 /* Common Mode Reference and Shield Drive Control Register */
68 #define ADAS1000_GPIOCTL 0x06 /* GPIO Control Register */
69 #define ADAS1000_PACEAMPTH 0x07 /* Pace Amplitude Threshold2 */
70 #define ADAS1000_TESTTONE 0x08 /* Test Tone */
71 #define ADAS1000_CALDAC 0x09 /* Calibration DAC */
72 #define ADAS1000_FRMCTL 0x0A /* Frame Control Register */
73 #define ADAS1000_FILTCTL 0x0B /* Filter Control Register */
74 #define ADAS1000_LOFFUTH 0x0C /* Leads off Upper Threshold */
75 #define ADAS1000_LOFFLTH 0x0D /* Leads off Lower Threshold */
76 #define ADAS1000_PACEEDGETH 0x0E /* Pace Edge Threshold */
77 #define ADAS1000_PACELVLTH 0x0F /* Pace Level Threshold */
78 #define ADAS1000_LADATA 0x11 /* LA or LEAD I Data */
79 #define ADAS1000_LLDATA 0x12 /* LL or LEAD II Data */
80 #define ADAS1000_RADATA 0x13 /* RA or LEAD III Data */
81 #define ADAS1000_V1DATA 0x14 /* V1 or V1 Data */
82 #define ADAS1000_V2DATA 0x15 /* V2 or V2 Data */
83 #define ADAS1000_PACEDATA 0x1A /* Read Pace Detection Data */
84 #define ADAS1000_RESPMAG 0x1B /* Read Respiration Data Magnitude */
85 #define ADAS1000_RESPPH 0x1C /* Read Respiration Data Phase */
86 #define ADAS1000_LOFF 0x1D /* Leads Off Status */
87 #define ADAS1000_DCLEADSOFF 0x1E /* DC Leads off Register */
88 #define ADAS1000_EXTENDSW 0x20 /* Extended Switch for respiration inputs */
89 #define ADAS1000_CALLA 0x21 /* User gain calibration LA */
90 #define ADAS1000_CALLL 0x22 /* User gain calibration LL */
91 #define ADAS1000_CALRA 0x23 /* User gain calibration RA */
92 #define ADAS1000_CALV1 0x24 /* User gain calibration V1 */
93 #define ADAS1000_CALV2 0x25 /* User gain calibration V2 */
94 #define ADAS1000_LOAMLA 0x31 /* Leads off Amplitude for LA */
95 #define ADAS1000_LOAMLL 0x32 /* Leads off Amplitude for LL */
96 #define ADAS1000_LOAMRA 0x33 /* Leads off Amplitude for RA */
97 #define ADAS1000_LOAMV1 0x34 /* Leads off Amplitude for V1 */
98 #define ADAS1000_LOAMV2 0x35 /* Leads off Amplitude for V2 */
99 #define ADAS1000_PACE1_DATA 0x3A /* Pace1 Width & Amplitude2 */
100 #define ADAS1000_PACE2_DATA 0x3B /* Pace2 Width & Amplitude2 */
101 #define ADAS1000_PACE3_DATA 0x3C /* Pace3 Width & Amplitude2 */
102 #define ADAS1000_FRAMES 0x40 /* Frame Header - Read Data Frames */
103 #define ADAS1000_CRC 0x41 /* Frame CRC */
104 
105 /******************************************************************************/
106 /* ECG Setting Register */
107 /******************************************************************************/
108 /* ECG Channel Enable, shuts down power to the channel, the input is
109  now HiZ : 1 = enabled, 0 = disabled */
110 #define ADAS1000_ECGCTL_LAEN (1ul << 23)
111 /* ECG Channel Enable, shuts down power to the channel, the input is
112  now HiZ : 1 = enabled, 0 = disabled */
113 #define ADAS1000_ECGCTL_LLEN (1ul << 22)
114 /* ECG Channel Enable, shuts down power to the channel, the input is
115  now HiZ : 1 = enabled, 0 = disabled */
116 #define ADAS1000_ECGCTL_RAEN (1ul << 21)
117 /* ECG Channel Enable, shuts down power to the channel, the input is
118  now HiZ : 1 = enabled, 0 = disabled */
119 #define ADAS1000_ECGCTL_V1EN (1ul << 20)
120 /* ECG Channel Enable, shuts down power to the channel, the input is
121  now HiZ : 1 = enabled, 0 = disabled */
122 #define ADAS1000_ECGCTL_V2EN (1ul << 19)
123 /* Setting this bit selects the differential AFE input:
124  0 = Single Ended Input Digital Lead Mode or Electrode Mode,
125  1 = Differential Input Analog Lead Mode */
126 #define ADAS1000_ECGCTL_CHCONFIG (1ul << 10)
127 /* Pre-Amp & Anti-Aliasing Filter Overall Gain:
128  00 = GAIN 0 = x1.4, 01 = GAIN 1 = x2.1,
129  10 = GAIN 2 = x2.8, 11 = GAIN 3 = x4.2 */
130 #define ADAS1000_ECGCTL_GAIN (1ul << 8)
131 /* VREF Buffer Enable: 0 = Disabled, 1 = Enabled (when using internal
132  VREF, the VREFBUF must be enabled) */
133 #define ADAS1000_ECGCTL_VREFBUF (1ul << 7)
134 /* Use external clock instead of crystal oscillator. The crystal oscillator
135  is automatically disabled if configured as SLAVE in Gang mode and the
136  Slave device should receive the CLK from the Master device:
137  0 = XTAL is CLK source, 1 = CLK_IO is CLK source. */
138 #define ADAS1000_ECGCTL_CLKEXT (1ul << 6)
139 /* In gang mode, this bit selects the master (SYNC_GANG pin is configured
140  as an output). When in Single Channel Mode (GANG = 0), this bit is ignored:
141  0 = Slave, 1 = Master */
142 #define ADAS1000_ECGCTL_MASTER (1ul << 5)
143 /* Enable gang mode. Setting this bit causes the CLK_IO and to be activated:
144  0 = Single Channel mode, 1 = Gang Mode */
145 #define ADAS1000_ECGCTL_GANG (1ul << 4)
146 /* Selects the noise/power performance, this bit controls the ADC sampling
147  frequency. See specifications for further details:
148  0 = 1MSPS - low power, 1 = 2 MSPS - High performance/low noise */
149 #define ADAS1000_ECGCTL_HP (1ul << 3)
150 /* Convert Enable - Setting this bit enables the ADC conversion and filters:
151  0 = Idle, 1 = Conversion Enable */
152 #define ADAS1000_ECGCTL_CNVEN (1ul << 2)
153 /* Power Enable - clearing this bit powers down the device. All analog blocks
154  are powered down and the external crystal is disabled:
155  0 = Power Down, 1 = Power Enable */
156 #define ADAS1000_ECGCTL_PWREN (1ul << 1)
157 /* Software Reset - setting this bit clears all registers to their reset value.
158  This bit automatically clears itself. The software reset requires a NOP
159  command to complete the reset: 0 = NOP, 1 = Reset */
160 
161 #define ADAS1000_ECGCTL_SWRST (1ul << 0)
162 /******************************************************************************/
163 /* Leads off Control Register */
164 /******************************************************************************/
165 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
166 #define ADAS1000_LOFFCTL_LAPH (1ul << 23)
167 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
168 #define ADAS1000_LOFFCTL_LLPH (1ul << 22)
169 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
170 #define ADAS1000_LOFFCTL_RAPH (1ul << 21)
171 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
172 #define ADAS1000_LOFFCTL_V1PH (1ul << 20)
173 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
174 #define ADAS1000_LOFFCTL_V2PH (1ul << 19)
175 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
176 #define ADAS1000_LOFFCTL_CEPH (1ul << 18)
177 /* Individual electrode AC Leads off enable. AC Leads off enables are
178  the OR of ACSEL and the individual AC Leads off Channel enables.
179  0 = AC Leads off disabled, 1 = AC Leads off enabled */
180 #define ADAS1000_LOFFCTL_LAACLOEN (1ul << 17)
181 /* Individual electrode AC Leads off enable. AC Leads off enables are
182  the OR of ACSEL and the individual AC Leads off Channel enables.
183  0 = AC Leads off disabled, 1 = AC Leads off enabled */
184 #define ADAS1000_LOFFCTL_LLACLOEN (1ul << 16)
185 /* Individual electrode AC Leads off enable. AC Leads off enables are
186  the OR of ACSEL and the individual AC Leads off Channel enables.
187  0 = AC Leads off disabled, 1 = AC Leads off enabled */
188 #define ADAS1000_LOFFCTL_RAACLOEN (1ul << 15)
189 /* Individual electrode AC Leads off enable. AC Leads off enables are
190  the OR of ACSEL and the individual AC Leads off Channel enables.
191  0 = AC Leads off disabled, 1 = AC Leads off enabled */
192 #define ADAS1000_LOFFCTL_V1ACLOEN (1ul << 14)
193 /* Individual electrode AC Leads off enable. AC Leads off enables are
194  the OR of ACSEL and the individual AC Leads off Channel enables.
195  0 = AC Leads off disabled, 1 = AC Leads off enabled */
196 #define ADAS1000_LOFFCTL_V2ACLOEN (1ul << 13)
197 /* Individual electrode AC Leads off enable. AC Leads off enables are
198  the OR of ACSEL and the individual AC Leads off Channel enables.
199  0 = AC Leads off disabled, 1 = AC Leads off enabled */
200 #define ADAS1000_LOFFCTL_CEACLOEN (1ul << 12)
201 /* Set Current level for AC leads off (only active for ACSEL = 1).
202  00 = 12.5nA rms, 01 = 25nA rms,
203  10 = 50nA rms, 11 = 100nA rms */
204 #define ADAS1000_LOFFCTL_ACCURREN (1ul << 7)
205 /* Set Current level for DC leads off (only active for ACSEL = 0)
206  000 = 0nA, 001 = 10nA, 010 = 20nA, 011 = 30nA,
207  100 = 40nA, 101 = 50nA, 110 = 60nA, 111 = 70nA */
208 #define ADAS1000_LOFFCTL_DCCURRENT (1ul << 2)
209 /* DC or AC (out of band) Leads Off Detection. If LOFFEN = 0, this bit
210  is don't care. If LOFFEN = 1, 0 = DC Leads Off Detection enabled.
211  (Individual AC leads off may be enabled through bits 12-17),
212  1 = DC Leads off Detection disabled. AC Leads Off Detection enabled
213  (all electrodes except CE electrode). */
214 #define ADAS1000_LOFFCTL_ACSEL (1ul << 1)
215 /* Enable Leads Off Detection:
216  0 = Leads Off Disabled, 1 = Leads Off Enabled */
217 #define ADAS1000_LOFFCTL_LOFFEN (1ul << 0)
218 
219 /******************************************************************************/
220 /* Respiration Control Register */
221 /******************************************************************************/
222 /* Set to one to enable the MSB of the respiration DAC to be driven
223  out onto the GPIO[3] pin. This 64kHz signal can be used to
224  synchronize an external generator to the respiration carrier.
225  0 = normal GPIO3 function, 1 = MSB of RESPDAC driven onto GPIO[3] */
226 #define ADAS1000_RESPCTL_RESPEXTSYNC (1ul << 15)
227 /* For use with external instrumentation amplifier with respiration
228  circuit. Bypasses the on chip amplifier stage and input directly
229  to the ADC. */
230 #define ADAS1000_RESPCTL_RESPEXTAMP (1ul << 14)
231 /* Selects external respiration drive output. RESPDAC_RA is
232  automatically selected when RESPCAP = 1, 0 = RESPDAC _LL, 1 = RESPDAC_LA */
233 #define ADAS1000_RESPCTL_RESPOUT (1ul << 13)
234 /* Selects source of Respiration Capacitors.
235  0 = Use internal capacitors, 1 = Use external capacitors */
236 #define ADAS1000_RESPCTL_RESPCAP (1ul << 12)
237 /* Respiration Inamp Gain (saturates at 10):
238  0000 = x1 gain, 0001 = x2 gain, 0010 = x3 gain,
239  ...
240  1000 = x9 gain, 1001 = x10 gain, 11xx = x10 gain */
241 #define ADAS1000_RESPCTL_RESPGAIN (1ul << 8)
242 /* Selects between EXT_RESP _LA or EXT_RESP_LL paths. Only applies
243  if External Respiration is selected in RESPSEL. EXT_RESP_RA
244  automatically gets enabled. 0 = EXT_RESP_LL, 1 = EXT_RESP _LA */
245 #define ADAS1000_RESPCTL_RESPEXTSEL (1ul << 7)
246 /* Set Leads for Respiration Measurement:
247  00 = Lead I, 01 = Lead II,
248  10 = Lead III, 11 = External Respiration path */
249 #define ADAS1000_RESPCTL_RESPSEL (1ul << 5)
250 /* Set the test tone amplitude for respiration:
251  00 = Amplitude/8, 01 = Amplitude/4,
252  10 = Amplitude/2, 11 = Amplitude */
253 #define ADAS1000_RESPCTL_RESPAMP (1ul << 3)
254 /* Set Frequency for Respiration:
255  00 = 56kHz, 01 = 54kHz, 10 = 52kHz, 11 = 50kHz */
256 #define ADAS1000_RESPCTL_RESPFREQ (1ul << 1)
257 /* Enable Respiration:
258  0 = Respiration Disabled, 1 = Respiration Enabled */
259 #define ADAS1000_RESPCTL_RESPEN (1ul << 0)
260 
261 #define ADAS1000_RESPCTL_RESPGAIN_MASK (0x0000000Ful << 8)
262 #define ADAS1000_RESPCTL_RESPSEL_MASK (0x00000003ul << 5)
263 
264 /******************************************************************************/
265 /* Pace Detection Control Register */
266 /******************************************************************************/
267 /* Pace width Filter:
268  0 = Filter Disabled, 1 = Filter Enabled */
269 #define ADAS1000_PACECTL_PACEFILTW (1ul << 11)
270 /* Pace validation filter 2:
271  0 = Filter Disabled, 1 = Filter Enabled */
272 #define ADAS1000_PACECTL_PACETFILT2 (1ul << 10)
273 /* Pace validation filter 1:
274  0 = Filter Disabled, 1 = Filter Enabled */
275 #define ADAS1000_PACECTL_PACETFILT1 (1ul << 9)
276 /* Set Lead for Pace Detection Measurement:
277  00 = Lead I, 01 = Lead II, 10 = Lead III, 11 = Lead aVF */
278 #define ADAS1000_PACECTL_PACE3SEL (1ul << 7)
279 /* Set Lead for Pace Detection Measurement:
280  00 = Lead I, 01 = Lead II, 10 = Lead III, 11 = Lead aVF */
281 #define ADAS1000_PACECTL_PACE2SEL (1ul << 5)
282 /* Set Lead for Pace Detection Measurement:
283  00 = Lead I, 01 = Lead II, 10 = Lead III, 11 = Lead aVF */
284 #define ADAS1000_PACECTL_PACE1SEL (1ul << 3)
285 /* Enable Pace Detection Algorithm:
286  0 = Pace Detection Disabled, 1 = Pace Detection Enabled */
287 #define ADAS1000_PACECTL_PACE3EN (1ul << 2)
288 /* Enable Pace Detection Algorithm:
289  0 = Pace Detection Disabled, 1 = Pace Detection Enabled */
290 #define ADAS1000_PACECTL_PACE2EN (1ul << 1)
291 /* Enable Pace Detection Algorithm:
292  0 = Pace Detection Disabled, 1 = Pace Detection Enabled */
293 #define ADAS1000_PACECTL_PACE1EN (1ul << 0)
294 #define ADAS1000_PACECTL_PACE3SEL_MASK (0x00000003ul << 7)
295 #define ADAS1000_PACECTL_PACE2SEL_MASK (0x00000003ul << 5)
296 #define ADAS1000_PACECTL_PACE1SEL_MASK (0x00000003ul << 3)
297 
298 /******************************************************************************/
299 /* Common Mode Reference and Shield Drive Control Register */
300 /******************************************************************************/
301 /* Common Mode Electrode Select */
302 #define ADAS1000_CMREFCTL_LACM (1ul << 23)
303 /* Any combination of the 5 input electrodes can be used to create the */
304 #define ADAS1000_CMREFCTL_LLCM (1ul << 22)
305 /* Common Mode signal, or the Common Mode signal can be driven from the */
306 #define ADAS1000_CMREFCTL_RACM (1ul << 21)
307 /* internal reference. Bits 23:19 are ignored when bit 2 is selected. */
308 #define ADAS1000_CMREFCTL_V1CM (1ul << 20)
309 /* The Common Mode is the average of the selected electrodes. When a */
310 /* single electrode is selected, the Common Mode is the signal level of */
311 /* that electrode alone. */
312 /* 0 = does not contribute to the common mode */
313 /* 1 = contributes to the common mode */
314 #define ADAS1000_CMREFCTL_V2CM (1ul << 19)
315 /* RLD Summing Junction
316  0 = does not contribute to RLD input
317  1 = contributes to RLD input */
318 #define ADAS1000_CMREFCTL_LARLD (1ul << 14)
319 /* RLD Summing Junction
320  0 = does not contribute to RLD input
321  1 = contributes to RLD input */
322 #define ADAS1000_CMREFCTL_LLRLD (1ul << 13)
323 /* RLD Summing Junction
324  0 = does not contribute to RLD input
325  1 = contributes to RLD input */
326 #define ADAS1000_CMREFCTL_RARLD (1ul << 12)
327 /* RLD Summing Junction
328  0 = does not contribute to RLD input
329  1 = contributes to RLD input */
330 #define ADAS1000_CMREFCTL_V1RLD (1ul << 11)
331 /* RLD Summing Junction
332  0 = does not contribute to RLD input
333  1 = contributes to RLD input */
334 #define ADAS1000_CMREFCTL_V2RLD (1ul << 10)
335 /* RLD Summing Junction
336  0 = does not contribute to RLD input
337  1 = contributes to RLD input */
338 #define ADAS1000_CMREFCTL_CERLD (1ul << 9)
339 /* Common Electrode Reference
340  0 = Common Electrode disabled
341  1 = Common Electrode enabled */
342 #define ADAS1000_CMREFCTL_CEREFEN (1ul << 8)
343 /* Select electrode for reference drive
344  0000 = RL, 0001 = LA, 0010 = LL,
345  0011 = RA, 0100 = V1, 0101 = V2,
346  0110 to 1111 = Reserved */
347 #define ADAS1000_CMREFCTL_RLDSEL (1ul << 4)
348 /* Common mode output - when set, the internally derived common mode
349  signal is driven out the common mode pin. This bit has no effect
350  if external common mode is selected.
351  0 = common mode is not driven out
352  1 = common mode is driven out the external common mode pin */
353 #define ADAS1000_CMREFCTL_DRVCM (1ul << 3)
354 /* Select the source of Common Mode
355  (use when operating multiple devices together)
356  0 = Internal Common Mode selected
357  1 = External Common Mode selected */
358 #define ADAS1000_CMREFCTL_EXTCM (1ul << 2)
359 /* Enable Right Leg Drive Reference Electrode
360  0 = Disabled
361  1 = Enabled */
362 #define ADAS1000_CMREFCTL_RLD_EN (1ul << 1)
363 /* Enable Shield Drive
364  0 = Shield Drive Disabled
365  1 = Shield Drive Enabled */
366 #define ADAS1000_CMREFCTL_SHLDEN (1ul << 0)
367 
368 #define ADAS1000_CMREFCTL_RLDSEL_MASK (0x0000000Ful << 4)
369 
370 /******************************************************************************/
371 /* GPIO Control Register */
372 /******************************************************************************/
373 /* Frame secondary SPI words with chip select
374  0 = MCS asserted for entire frame
375  1 = MCS asserted for individual word */
376 #define ADAS1000_GPIOCTL_SPIFW (1ul << 18)
377 /* Secondary SPI Enable (ADAS1000 and ADAS1000-2 only) (SPI interface
378  providing ECG data at 128kHz data rate for external digital pace
379  algorithm detection � uses GPIO0, GPIO1, GPIO2 pins)
380  0 = Disabled
381  1 = Enabled. The individual control bits for GPIO0, GPIO1,
382  GPIO2 are ignored. GPIO3 is not affected by SPIEN */
383 #define ADAS1000_GPIOCTL_SPIEN (1ul << 16)
384 /* State of GPIO<3>
385  00 = High Impedance, 01 = Input,
386  10 = Output, 11 = Open Drain */
387 #define ADAS1000_GPIOCTL_G3CTL (1ul << 14)
388 /* Output Value to be written to GPIO<3> when pad is configured as an
389  output or open drain
390  0 = Low Value
391  1 = High Value */
392 #define ADAS1000_GPIOCTL_G3OUT (1ul << 13)
393 /* (Read Only) Input Value read from GPIO<3> when pad is configured as an input
394  0 = Low Value
395  1 = High Value */
396 #define ADAS1000_GPIOCTL_G3IN (1ul << 12)
397 /* State of GPIO<2>
398  00 = High Impedance, 01 = Input,
399  10 = Output, 11 = Open Drain */
400 #define ADAS1000_GPIOCTL_G2CTL (1ul << 10)
401 /* Output Value to be written to GPIO<2> when pad is configured as an
402  output or open drain
403  0 = Low Value
404  1 = High Value */
405 #define ADAS1000_GPIOCTL_G2OUT (1ul << 9)
406 /* (Read Only) Input Value read from GPIO<2> when pad is configured as an input.
407  0 = Low Value
408  1 = High Value */
409 #define ADAS1000_GPIOCTL_G2IN (1ul << 8)
410 /* State of GPIO<1>
411  00 = High Impedance, 01 = Input,
412  10 = Output, 11 = Open Drain */
413 #define ADAS1000_GPIOCTL_G1CTL (1ul << 6)
414 /* Output Value to be written to GPIO<1> when pad is configured as an
415  output or open drain.
416  0 = Low Value
417  1 = High Value */
418 #define ADAS1000_GPIOCTL_G1OUT (1ul << 5)
419 /* (Read Only) Input Value read from GPIO<1> when pad is configured as an input.
420  0 = Low Value
421  1 = High Value */
422 #define ADAS1000_GPIOCTL_G1IN (1ul << 4)
423 /* State of GPIO<0>
424  00 = High Impedance, 01 = Input,
425  10 = Output, 11 = Open Drain */
426 #define ADAS1000_GPIOCTL_G0CTL (1ul << 2)
427 /* Output Value to be written to GPIO<0> when pad is configured as an
428  output or open drain.
429  0 = Low Value
430  1 = High Value */
431 #define ADAS1000_GPIOCTL_G0OUT (1ul << 1)
432 /* (Read Only) Input Value read from GPIO<0> when pad is configured
433  as an input
434  0 = Low Value
435  1 = High Value */
436 #define ADAS1000_GPIOCTL_G0IN (1ul << 0)
437 #define ADAS1000_GPIOCTL_G3CTL_MASK (0x00000003ul << 14)
438 #define ADAS1000_GPIOCTL_G2CTL_MASK (0x00000003ul << 10)
439 #define ADAS1000_GPIOCTL_G1CTL_MASK (0x00000003ul << 6)
440 #define ADAS1000_GPIOCTL_G0CTL_MASK (0x00000003ul << 2)
441 
442 /******************************************************************************/
443 /* Pace Amplitude Threshold2 Register */
444 /******************************************************************************/
445 /* Pace Amplitude Thresold */
446 #define ADAS1000_PACEAMPTH_PACE3AMPTH (1ul << 16)
447 /* Threshold = N - VREF/GAIN/216 */
448 #define ADAS1000_PACEAMPTH_PACE2AMPTH (1ul << 8)
449 #define ADAS1000_PACEAMPTH_PACE1AMPTH (1ul << 0)
450 
451 #define ADAS1000_PACEAMPTH_PACE3AMPTH_MASK (0x000000FFul << 16)
452 #define ADAS1000_PACEAMPTH_PACE2AMPTH_MASK (0x000000FFul << 8)
453 #define ADAS1000_PACEAMPTH_PACE1AMPTH_MASK (0x000000FFul << 0)
454 
455 /******************************************************************************/
456 /* Test Tone Register */
457 /******************************************************************************/
458 /* Tone Select */
459 #define ADAS1000_TESTTONE_TONLA (1ul << 23)
460 /* 0 = 1.3V VCM_REF */
461 #define ADAS1000_TESTTONE_TONLL (1ul << 22)
462 /* 1 = 1mV sinewave or squarewave for toneint, no connect for tonext */
463 #define ADAS1000_TESTTONE_TONRA (1ul << 21)
464 #define ADAS1000_TESTTONE_TONV1 (1ul << 20)
465 #define ADAS1000_TESTTONE_TONV2 (1ul << 19)
466 /* 00 = 10Hz Sine Wave
467  01 = 150Hz Sine Wave
468  1x = 1Hz 1mV Square Wave */
469 #define ADAS1000_TESTTONE_TONTYPE (1ul << 3)
470 /* Test Tone Internal or External
471  0 = External Test Tone
472  1 = Internal Test Tone */
473 #define ADAS1000_TESTTONE_TONINT (1ul << 2)
474 /* Test Tone out Enable
475  0 = disconnects test tone from CAL_DAC_IO during internal mode only
476  1 = Connects CAL_DAC_IO to test tone during internal mode. */
477 #define ADAS1000_TESTTONE_TONOUT (1ul << 1)
478 /* Enables an internal test tone to drive entire signal chain, from
479  pre-amp to SPI interface. This tone comes from the CAL DAC and goes
480  to the pre-amps through the internal mux. When TONEN (CALDAC) is
481  enabled, AC Leads off is disabled.
482  0 = Disable the test tone
483  1 = Enable the CALDAC 1mV SineWave test tone (Cal Mode has priority) */
484 #define ADAS1000_TESTTONE_TONEN (1ul << 0)
485 
486 #define ADAS1000_TESTTONE_TONTYPE_MASK (0x00000003ul << 3)
487 
488 /******************************************************************************/
489 /* Calibration DAC Register */
490 /******************************************************************************/
491 /* Calibration Chop Clock Enable. The CALDAC output can be chopped to
492  lower 1/f noise. Chopping is done at 256kHz.
493  0 = Disabled
494  1 = Enabled. */
495 #define ADAS1000_CALDAC_CALCHPEN (1ul << 13)
496 /* Calibration Mode Enable
497  0 = Disable Calibration mode
498  1 = Enable Calibration mode - connect CAL DAC_IO,
499  begin data acquisition on ECG channels. */
500 #define ADAS1000_CALDAC_CALMODEEN (1ul << 12)
501 /* Calibration Internal or External
502  0 = External Cal - calibration to be performed externally by
503  looping CAL_DAC_IO around into ECG channels.
504  1 = Internal Cal - disconnects external switches for all ECG
505  channels and connects CALDAC internally to all ECG channels. */
506 #define ADAS1000_CALDAC_CALINT (1ul << 11)
507 /* Enable 10-bit calibration DAC for cal mode or external use.
508  0 = Disable CALDAC
509  1 = Enable CALDAC, if a master device and not in calibration
510  mode then also connects CAL_DAC out to its_IO pin for
511  external use, if in Slave mode, the CALDAC will disable to
512  allow master to drive CAL_DAC_IO pin. When CALDAC is enabled,
513  AC Leads off is disabled. */
514 #define ADAS1000_CALDAC_CALDACEN (1ul << 10)
515 /* Set the CAL DAC value */
516 #define ADAS1000_CALDAC_CALDATA (1ul << 0)
517 
518 #define ADAS1000_CALDAC_CALDATA_MASK (0x000003FFul << 0)
519 
520 /******************************************************************************/
521 /* Frame Control Register */
522 /******************************************************************************/
523 /* Include/Exclude word from ECG data frame, if electrode/lead is
524  included in the data word and the electrode falls off, then the
525  data word will be undefined.
526  0 = Included in Frame
527  1 = Exclude from Frame */
528 #define ADAS1000_FRMCTL_LEAD_I_LADIS (1ul << 23)
529 #define ADAS1000_FRMCTL_LEAD_II_LLDIS (1ul << 22)
530 #define ADAS1000_FRMCTL_LEAD_III_RADIS (1ul << 21)
531 #define ADAS1000_FRMCTL_V1DIS (1ul << 20)
532 #define ADAS1000_FRMCTL_V2DIS (1ul << 19)
533 /* Include/Exclude word from ECG data frame
534  0 = Included in Frame
535  1 = Exclude from Frame */
536 #define ADAS1000_FRMCTL_PACEDIS (1ul << 14)
537 /* Respiration Magnitude
538  0 = Included in Frame
539  1 = Exclude from Frame */
540 #define ADAS1000_FRMCTL_RESPMDIS (1ul << 13)
541 /* Respiration Phase
542  0 = Included in Frame
543  1 = Exclude from Frame */
544 #define ADAS1000_FRMCTL_RESPPHDIS (1ul << 12)
545 /* Leads Off Status
546  0 = Included in Frame
547  1 = Exclude from Frame */
548 #define ADAS1000_FRMCTL_LOFFDIS (1ul << 11)
549 /* GPIO Word disable
550  0 = Included in Frame
551  1 = Exclude from Frame */
552 #define ADAS1000_FRMCTL_GPIODIS (1ul << 10)
553 /* CRC Word disable
554  0 = Included in Frame
555  1 = Exclude from Frame */
556 #define ADAS1000_FRMCTL_CRCDIS (1ul << 9)
557 /* In a master device configured for Lead Mode, the ECG data will
558  be signed. When in slave mode (electrode format), the ECG data
559  format is unsigned. Use this bit when using multiple devices to
560  make the slave device signed data.
561  0 = unsigned data (default)
562  1 = signed data */
563 #define ADAS1000_FRMCTL_SIGNEDEN (1ul << 8)
564 /* Automatically disable PACE, RESP, LOFF words if their flags are
565  not set in the header.
566  0 = fixed frame format
567  1 = auto disable words */
568 #define ADAS1000_FRMCTL_ADIS (1ul << 7)
569 /* Ready Repeat � if this bit is set and the frame header indicates
570  data is not ready, the frame header is continuously sent until
571  data is ready.
572  0 = always send entire frame
573  1 = repeat frame header until ready */
574 #define ADAS1000_FRMCTL_RDYRPT (1ul << 6)
575 /* Sets the Output Data Format
576  0 = Lead/Vector Format
577  (only available in 2kHz & 16kHz data rates)
578  1 = Electrode Format */
579 #define ADAS1000_FRMCTL_DATAFMT (1ul << 4)
580 /* Skip interval - this field provides a way to decimate the data
581  00 = output every frame
582  01 = output every other frame
583  1x = output every 4th frame */
584 #define ADAS1000_FRMCTL_SKIP (1ul << 2)
585 /* Sets the Output Data Rate to 2 kHz */
586 #define ADAS1000_FRMCTL_FRMRATE_2KHZ 0x00
587 /* Sets the Output Data Rate to 16 kHz */
588 #define ADAS1000_FRMCTL_FRMRATE_16KHZ 0x01
589 /* Sets the Output Data Rate to 128 kHz */
590 #define ADAS1000_FRMCTL_FRMRATE_128KHZ 0x10
591 /* Sets the Output Data Rate to 31.25 Hz */
592 #define ADAS1000_FRMCTL_FRMRATE_31_25HZ 0x11
593 
594 #define ADAS1000_FRMCTL_WORD_MASK (ADAS1000_FRMCTL_LEAD_I_LADIS | \
595  ADAS1000_FRMCTL_LEAD_II_LLDIS | \
596  ADAS1000_FRMCTL_LEAD_III_RADIS | \
597  ADAS1000_FRMCTL_V1DIS | \
598  ADAS1000_FRMCTL_V2DIS | \
599  ADAS1000_FRMCTL_PACEDIS | \
600  ADAS1000_FRMCTL_RESPMDIS | \
601  ADAS1000_FRMCTL_RESPPHDIS | \
602  ADAS1000_FRMCTL_LOFFDIS | \
603  ADAS1000_FRMCTL_GPIODIS | \
604  ADAS1000_FRMCTL_CRCDIS)
605 #define ADAS1000_FRMCTL_SKIP_MASK (0x00000003ul << 2)
606 #define ADAS1000_FRMCTL_FRMRATE_MASK (0x00000003ul << 0)
607 
608 /******************************************************************************/
609 /* Filter Control Register */
610 /******************************************************************************/
611 /* 2kHz notch bypass for SPI Master
612  0 = notch filter bypassed
613  1 = notch filter present */
614 #define ADAS1000_FILTCTL_MN2K (1ul << 5)
615 /* 2kHz notch bypass
616  0 = notch filter present
617  1 = notch filter bypassed */
618 #define ADAS1000_FILTCTL_N2KBP (1ul << 4)
619 /* 00 = 40Hz
620  01 = 150Hz
621  10 = 250 Hz
622  11 = 450Hz */
623 #define ADAS1000_FILTCTL_LPF (1ul << 2)
624 
625 #define ADAS1000_FILTCTL_LPF_MASK (0x00000003ul << 2)
626 
627 /******************************************************************************/
628 /* Leads off Upper Threshold Register */
629 /******************************************************************************/
630 /* ADC over range threshold. An ADC out-of-range error will be flagged
631  if the ADC output is greater than the over range threshold.
632  The over range threshold is offset from the maximum value.
633  Threshold = max_value � ADCOVER*2^6
634  0000 = max value (disabled)
635  0001 = max_value - 64
636  0010 = max_value - 128
637  ...
638  1111: max_value - 960 */
639 #define ADAS1000_LOFFUTH_ADCOVER (1ul << 16)
640 /* AC Leads off upper Threshold. Leads off will be detected if the DC
641  or AC output is = N * 2 * VREF/GAIN/2^16. 0 = 0V */
642 #define ADAS1000_LOFFUTH_LOFFUTH (1ul << 0)
643 
644 #define ADAS1000_LOFFUTH_ADCOVER_MASK (0x0000000Ful << 16)
645 #define ADAS1000_LOFFUTH_LOFFUTH_MASK (0x0000FFFFul << 0)
646 
647 /******************************************************************************/
648 /* Leads off Lower Threshold Register */
649 /******************************************************************************/
650 /* ADC under range threshold. An ADC out-of-range error will be flagged
651  if the ADC output is less than the under range threshold.
652  Threshold = min_value + ADCUNDR�2^6
653  0000 = min value (disabled)
654  0001 = min_value + 64
655  0010 = min _value + 128
656  ...
657  1111: min _value + 960 */
658 #define ADAS1000_LOFFLTH_ADCUNDR (1ul << 16)
659 /* AC Leads off lower Threshold. Leads off will be detected if the DC
660  or AC output is = N * 2 * VREF/GAIN/2^16. 0 = 0V */
661 #define ADAS1000_LOFFLTH_LOFFLTH (1ul << 0)
662 
663 #define ADAS1000_LOFFLTH_ADCUNDR_MASK (0x0000000Ful << 16)
664 #define ADAS1000_LOFFLTH_LOFFLTH_MASK (0x0000FFFFul << 0)
665 
666 /******************************************************************************/
667 /* Pace Edge Threshold Register */
668 /******************************************************************************/
669 /* Pace edge trigger threshold */
670 #define ADAS1000_PACEEDGETH_PACE3EDGTH (1ul << 16)
671 /* 0 = PACEAMPTH/2 */
672 #define ADAS1000_PACEEDGETH_PACE2EDGTH (1ul << 8)
673 /* 1 = VREF/GAIN/2^16 */
674 #define ADAS1000_PACEEDGETH_PACE1EDGTH (1ul << 0)
675 /* N = N * VREF/GAIN/2^16 */
676 
677 #define ADAS1000_PACEEDGETH_PACE3EDGTH_MASK (0x000000FFul << 16)
678 #define ADAS1000_PACEEDGETH_PACE2EDGTH_MASK (0x000000FFul << 8)
679 #define ADAS1000_PACEEDGETH_PACE1EDGTH_MASK (0x000000FFul << 0)
680 
681 /******************************************************************************/
682 /* Pace Level Threshold Register */
683 /******************************************************************************/
684 /* Pace level threshold. This is a signed value. */
685 #define ADAS1000_PACELVLTH_PACE3LVLTH (1ul << 16)
686 /* -1 = 0xFFF = -VREF/GAIN/2^16 */
687 #define ADAS1000_PACELVLTH_PACE2LVLTH (1ul << 8)
688 /* 0 = 0x0000 = 0V */
689 #define ADAS1000_PACELVLTH_PACE1LVLTH (1ul << 0)
690 /* +1 = 0x001 = +VREF/GAIN/2^16 */
691 /* N = N * VREF/GAIN/2^16 */
692 
693 #define ADAS1000_PACELVLTH_PACE3LVLTH_MASK (0x000000FFul << 16)
694 #define ADAS1000_PACELVLTH_PACE2LVLTH_MASK (0x000000FFul << 8)
695 #define ADAS1000_PACELVLTH_PACE1LVLTH_MASK (0x000000FFul << 0)
696 
697 /***********************************************************************************/
698 /* LA or LEAD I, LL or LEAD II, RA or LEAD III, V1 or V1�, V2 or V2� Data Register */
699 /***********************************************************************************/
700 /* 0x11 : LA or LEAD I
701  0x12 : LL or LEAD II
702  0x13 : RA or LEAD II
703  0x14 : V1 or V1
704  0x15 : V2 or V2 */
705 #define ADAS1000_LADATA_ADDRESS (1ul << 24)
706 /* Channel Data Value. Data left justified (MSB) irrespective of data
707  rate. In electrode format, the value is an unsigned integer.
708  In Vector format, the value is a signed 2�s complement integer format.
709  Vector format had 2x range compared to electrode format since it can
710  swing from +VREF to -VREF, therefore the LSB size is double.
711  Electrode Format:
712  Min value (000...) = 0V
713  Max value (1111...) = VREF/GAIN
714  LSB = (VREF/GAIN)/2N
715  Lead/Vector Format
716  Min value (1000...) = -(VREF/GAIN)
717  Max value (0111...) = +VREF/GAIN
718  LSB = 2^(VREF/GAIN)/2N
719  Where N = # of data bits, 16 for 128kHz data rate or 24 for
720  2kHz/16kHz data rate. */
721 
722 #define ADAS1000_LADATA_ECG_DATA (1ul << 0)
723 #define ADAS1000_LADATA_ADDRESS_MASK (0x000000FFul << 24)
724 #define ADAS1000_LADATA_ECG_DATA_MASK (0x00FFFFFFul << 0)
725 
726 /******************************************************************************/
727 /* Read Pace Detection Data Register */
728 /******************************************************************************/
729 /* 0001 1010 = Pace Detection */
730 #define ADAS1000_PACEDATA_ADDRESS (1ul << 24)
731 /* Pace 3 detected. This bit will be set once a pace pulse is
732  detected. This bit is set on the trailing edge of the pace pulse.
733  0 = Pace pulse not detected in current frame
734  1 = Pace pulse detected in this frame */
735 #define ADAS1000_PACEDATA_PACE3_DETECTED (1ul << 23)
736 /* This is the log2(height) of the pace pulse
737  N: height = 2^N * VREF / GAIN / 2^16 */
738 #define ADAS1000_PACEDATA_PACE_CH3_HEIGHT (1ul << 16)
739 /* This is log2(Width)-1 of the pace pulse.
740  N: Width = 2^(N+1) / 128kHz */
741 #define ADAS1000_PACEDATA_PACE_CH3_WIDTH (1ul << 20)
742 /* Pace 2 detected. This bit will be set once a pace pulse is
743  detected. This bit is set on the trailing edge of the pace pulse.
744  0 = Pace pulse not detected in current frame
745  1 = Pace pulse detected in this frame*/
746 #define ADAS1000_PACEDATA_PACE2_DETECTED (1ul << 15)
747 /* This is log2(Width)-1 of the pace pulse.
748  N: Width = 2^(N+1) / 128kHz */
749 #define ADAS1000_PACEDATA_PACE_CH2_WIDTH (1ul << 12)
750 /* This is the log2(height) of the pace pulse
751  N: height = 2^N * VREF / GAIN / 2^16 */
752 #define ADAS1000_PACEDATA_PACE_CH2_HEIGHT (1ul << 8)
753 /* Pace 1 detected. This bit will be set once a pace pulse is
754  detected. This bit is set on the trailing edge of the pace pulse.
755  0 = Pace pulse not detected in current frame
756  1 = Pace pulse detected in this frame */
757 #define ADAS1000_PACEDATA_PACE1_DETECTED (1ul << 7)
758 /* "This is log2(Width)-1 of the pace pulse.
759  N: Width = 2^(N+1) / 128kHz */
760 #define ADAS1000_PACEDATA_PACE_CH1_WIDTH (1ul << 4)
761 /* This is the log2(height) of the pace pulse
762  N: height = 2^N * VREF / GAIN / 2^16 */
763 #define ADAS1000_PACEDATA_CH1_HEIGHT (1ul << 0)
764 
765 #define ADAS1000_PACEDATA_ADDRESS_MASK (0x000000FFul << 24)
766 #define ADAS1000_PACEDATA_PACE_CH3_WIDTH_MASK (0x00000007ul << 20)
767 #define ADAS1000_PACEDATA_PACE_CH3_HEIGHT_MASK (0x0000000Ful << 16)
768 #define ADAS1000_PACEDATA_PACE_CH2_WIDTH_MASK (0x00000007ul << 12)
769 #define ADAS1000_PACEDATA_PACE_CH2_HEIGHT_MASK (0x0000000Ful << 8)
770 #define ADAS1000_PACEDATA_PACE_CH1_WIDTH_MASK (0x00000007ul << 4)
771 #define ADAS1000_PACEDATA_PACE_CH1_HEIGHT_MASK (0x0000000Ful << 0)
772 
773 /******************************************************************************/
774 /* Read Respiration Data Magnitude Register */
775 /******************************************************************************/
776 /* 0001 1011 = Respiration Magnitude */
777 #define ADAS1000_RESPMAG_ADDRESS (1ul << 24)
778 /* Magnitude of respiration signal. This is an unsigned value. */
779 #define ADAS1000_RESPMAG_MAGNITUDE (1ul << 0)
780 
781 #define ADAS1000_RESPMAG_ADDRESS_MASK (0x000000FFul << 24)
782 #define ADAS1000_RESPMAG_MAGNITUDE_MASK (0x00FFFFFFul << 0)
783 
784 /******************************************************************************/
785 /* Read Respiration Data Phase Register */
786 /******************************************************************************/
787 /* 0001 1100 = Respiration Phase */
788 #define ADAS1000_RESPPH_ADDRESS (1ul << 24)
789 /* Phase of respiration signal. Can be interpreted as either signed or
790  unsigned value. If unsigned, the range is from 0 to 2pi. If as a
791  signed value, the range is from �pi to +pi.
792  0x000000 = 0
793  0x000001 = 2pi / 2^24
794  0x400000 = pi/2
795  0x800000 = +pi = -pi
796  0xC00000 = +3pi/2 = -pi/2
797  0xFFFFFF = +2pi(1 - 2^(-24)) = -2p / 2^24 */
798 #define ADAS1000_RESPPH_PHASE (1ul << 0)
799 
800 #define ADAS1000_RESPPH_ADDRESS_MASK (0x000000FFul << 24)
801 #define ADAS1000_RESPPH_PHASE_MASK (0x00FFFFFFul << 0)
802 
803 /******************************************************************************/
804 /* Leads Off Status Register */
805 /******************************************************************************/
806 /* Address bits define the word data 0001 1101 = Leads Off */
807 #define ADAS1000_LOFF_ADDRESS (1ul << 24)
808 /* Electrode Connection Status. If either DC or AC leads off
809  If both DC and AC leads off are enabled, these bits reflect
810  only the AC leads off status. DC leads off is available in
811  the DCLEADSOFF register. The common electrodes only have DC
812  leads off detection. An AC leads off signal can be injected
813  into the common electrode, but there is no ADC input to measure
814  its amplitude. If the common electrode is off, it will affect
815  the AC leads off amplitude of the other electrodes. These bits
816  accumulate in the frame buffer and are cleared when the frame
817  buffer is loaded into the SPI buffer.
818  0 = Electrode is connected
819  1 = Electrode is disconnected*/
820 #define ADAS1000_LOFF_RL_LEADS_OFF_STATUS (1ul << 23)
821 #define ADAS1000_LOFF_LA_LEADS_OFF_STATUS (1ul << 22)
822 #define ADAS1000_LOFF_LL_LEADS_OFF_STATUS (1ul << 21)
823 #define ADAS1000_LOFF_RA_LEADS_OFF_STATUS (1ul << 20)
824 #define ADAS1000_LOFF_V1_LEADS_OFF_STATUS (1ul << 19)
825 #define ADAS1000_LOFF_V2_LEADS_OFF_STATUS (1ul << 18)
826 #define ADAS1000_LOFF_CELO (1ul << 13)
827 /* ADC out of range error.
828  These status bits indicate the resulting ADC code is out of
829  range. These bits accumulate in the frame buffer and are
830  cleared when the frame buffer is loaded into the SPI buffer. */
831 #define ADAS1000_LOFF_LAADCOR (1ul << 12)
832 #define ADAS1000_LOFF_LLADCOR (1ul << 11)
833 #define ADAS1000_LOFF_RAADCOR (1ul << 10)
834 #define ADAS1000_LOFF_V1ADCOR (1ul << 9)
835 #define ADAS1000_LOFF_V2ADCOR (1ul << 8)
836 
837 #define ADAS1000_LOFF_ADDRESS_MASK (0x000000FFul << 24)
838 
839 /******************************************************************************/
840 /* DC Leads off Register */
841 /******************************************************************************/
842 /* Address bits define the word data 0001 1110 = DC Leads Off */
843 #define ADAS1000_DCLEADSOFF_ADDRESS (1ul << 24)
844 /* The DC leads off detection is comparator based and compares
845  to a fixed level. Per electrode bits flag if the DC leads off
846  comparator threshold level has been exceeded.
847  0 = electrode < overrange threshold, 2.4 V
848  1 = electrode > overrange threshold, 2.4 V */
849 #define ADAS1000_DCLEADSOFF_RL_INPUT_OVERRANGE (1ul << 23)
850 #define ADAS1000_DCLEADSOFF_LA_INPUT_OVERRANGE (1ul << 22)
851 #define ADAS1000_DCLEADSOFF_LL_INPUT_OVERRANGE (1ul << 21)
852 #define ADAS1000_DCLEADSOFF_RA_INPUT_OVERRANGE (1ul << 20)
853 #define ADAS1000_DCLEADSOFF_CE_INPUT_OVERRANGE (1ul << 13)
854 
855 /* The DC leads off detection is comparator based and compares
856  to a fixed level. Per electrode bits flag if the DC leads off
857  comparator threshold level has been exceeded.
858  0 = electrode > underrange threshold, 0.2 V
859  1 = electrode < underrange threshold, 0.2 V */
860 #define ADAS1000_DCLEADSOFF_RL_INPUT_UNDERRANGE (1ul << 12)
861 #define ADAS1000_DCLEADSOFF_LA_INPUT_UNDERRANGE (1ul << 11)
862 #define ADAS1000_DCLEADSOFF_LL_INPUT_UNDERRANGE (1ul << 10)
863 #define ADAS1000_DCLEADSOFF_RA_INPUT_UNDERRANGE (1ul << 9)
864 #define ADAS1000_DCLEADSOFF_CE_INPUT_UNDERRANGE (1ul << 2)
865 
866 #define ADAS1000_DCLEADSOFF_ADDRESS_MASK (0x000000FFul << 24)
867 
868 /******************************************************************************/
869 /* Extended Switch for Respiration Inputs Register */
870 /******************************************************************************/
871 /* External Respiration electrode input switch to channel
872  electrode input.
873  0 = switch open
874  1 = switch closed */
875 #define ADAS1000_EXTENDSW_EXTRESP_RA_LA (1ul << 23)
876 #define ADAS1000_EXTENDSW_EXTRESP_RA_LL (1ul << 22)
877 #define ADAS1000_EXTENDSW_EXTRESP_RA_RA (1ul << 21)
878 #define ADAS1000_EXTENDSW_EXTRESP_RA_V1 (1ul << 20)
879 #define ADAS1000_EXTENDSW_EXTRESP_RA_V2 (1ul << 19)
880 #define ADAS1000_EXTENDSW_EXTRESP_LL_LA (1ul << 18)
881 #define ADAS1000_EXTENDSW_EXTRESP_LL_LL (1ul << 17)
882 #define ADAS1000_EXTENDSW_EXTRESP_LL_RA (1ul << 16)
883 #define ADAS1000_EXTENDSW_EXTRESP_LL_V1 (1ul << 15)
884 #define ADAS1000_EXTENDSW_EXTRESP_LL_V2 (1ul << 14)
885 #define ADAS1000_EXTENDSW_EXTRESP_LA_LA (1ul << 13)
886 #define ADAS1000_EXTENDSW_EXTRESP_LA_LL (1ul << 12)
887 #define ADAS1000_EXTENDSW_EXTRESP_LA_RA (1ul << 11)
888 #define ADAS1000_EXTENDSW_EXTRESP_LA_V1 (1ul << 10)
889 #define ADAS1000_EXTENDSW_EXTRESP_LA_V2 (1ul << 9)
890 
891 /* V1 and V2 electrodes may be used for measurement purposes
892  other than ECG. To achieve this, they need to be disconnected
893  from the patient VCM voltage provided from the internal common
894  mode buffer and instead connected to the internal VCM_REF level
895  of 1.3V. Set FREE_Vx bits high to connect negative input of V1
896  channel will be tied to internal VCM_REF level. This allows user
897  to make alternative measurements on V1 channel relative to the
898  VCM_REF level. If using Digital lead mode, uses these bits in
899  conjunction with NO_MATH_Vx bits [6:5]. */
900 #define ADAS1000_EXTENDSW_FREE_V1 (1ul << 8)
901 #define ADAS1000_EXTENDSW_FREE_V2 (1ul << 7)
902 /* In Digital Lead Mode, the digital core calculates the math on V1
903  and V2 with respect to WCT (LA+LL+RA)/3 providing V1 and V2.
904  Where V1 or V2 are used for measurement of something other than
905  ECG, then the math calculation needs to be disabled. These bits
906  are most likely used in conjunction with bits FREE_Vx [8:7].
907  Set NOMATH_Vx bits high to disable the math calculation in V1
908  and V2 respectively. */
909 #define ADAS1000_EXTENDSW_NOMATH_V1 (1ul << 6)
910 #define ADAS1000_EXTENDSW_NOMATH_V2 (1ul << 5)
911 
912 /******************************************************************************/
913 /* User gain calibration LA, LL, RA, V1, V2 Register */
914 /******************************************************************************/
915 /* 0x21 : CAL LA */
916 /* 0x22 : CAL LL */
917 /* 0x23 : CAL RA */
918 /* 0x24 : CAL V1 */
919 /* 0x25 : CAL V2 */
920 #define ADAS1000_CAL_ADDRESS (1ul << 24)
921 /* User can choose between:
922  0 = default calibration values
923  1 = user calibration values */
924 #define ADAS1000_CAL_USRCAL (1ul << 23)
925 /* Gain Calibration value.
926  Result = data * (1 + GAIN * 2^(-17))
927  The value read from this register is the current gain calibration value.
928  If the USRCAL bit is clear, this register returns the default value for
929  the current gain setting.
930  0x7FF (+2047) = *1.00000011111111111b
931  0x001 (+1) = *1.00000000000000001b
932  0x000 (0) = *1.00000000000000000b
933  0xFFF (-1) = *0.11111111111111111b
934  0x800 (-2048) = *0.11111100000000000b */
935 #define ADAS1000_CAL_CALVALUE (1ul << 0)
936 
937 #define ADAS1000_CAL_ADDRESS_MASK (0x000000FFul << 24)
938 #define ADAS1000_CAL_CALVALUE_MASK (0x00000FFFul << 0)
939 
940 /******************************************************************************/
941 /* Leads off Amplitude for LA, LL, RA, V1, V2 Register */
942 /******************************************************************************/
943 /* 0x31 : LA AC Leads off Magnitude
944  0x32 : LL AC Leads off Magnitude
945  0x33 : RA AC Leads off Magnitude
946  0x34 : V1 AC Leads off Magnitude
947  0x35 : V2 AC Leads off Magnitude */
948 #define ADAS1000_LOAM_ADDRESS (1ul << 24)
949 /* Measured Amplitude.
950  When AC leads off is selected, the data is the average of the rectified
951  2kHz bandpass filter with an update rate of 8Hz and cutoff frequency at
952  2Hz. The output is the amplitude of the 2kHz signal scaled by 2/pi
953  approximately = 0.6 (average of rectified sine wave). To convert to RMS,
954  scale the output by pi / (2*sqrt(2)).
955  Leads off (unsigned):
956  Min 0x0000 = 0V
957  LSB 0x0001= VREF / GAIN / 2^16
958  Max 0xFFFF = VREF / GAIN */
959 #define ADAS1000_LOAM_LOFFAM (1ul << 0)
960 
961 #define ADAS1000_LOAM_ADDRESS_MASK (0x000000FFul << 24)
962 #define ADAS1000_LOAM_LOFFAM_MASK (0x0000FFFFul << 0)
963 
964 /******************************************************************************/
965 /* Pace1, Pace2, Pace3 Width & Amplitude2 Register */
966 /******************************************************************************/
967 /* 0x3A : PACE1DATA
968  0x3B : PACE2DATA
969  0x3C : PACE3DATA */
970 #define ADAS1000_PACE_DATA_ADDRESS (1ul << 24)
971 /* Measured pace height in signed 2�s complement value
972  0 = 0
973  1 = VREF / GAIN / 2^16
974  N = N * VREF / GAIN / 2^16 */
975 #define ADAS1000_PACE_DATA_HEIGHT (1ul << 8)
976 /* Measured pace width in 128kHz samples
977  N: N / 128kHz = width
978  12: 12 / 128kHz = 93us
979  255: 255 / 128kHz = 2.0ms */
980 #define ADAS1000_PACE_DATA_WIDTH (1ul << 0)
981 
982 #define ADAS1000_PACE_DATA_ADDRESS_MASK (0x000000FFul << 24)
983 #define ADAS1000_PACE_DATA_HEIGHT_MASK (0x0000FFFFul << 8)
984 #define ADAS1000_PACE_DATA_WIDTH_MASK (0x000000FFul << 0)
985 
986 /******************************************************************************/
987 /* Frame Header - Read Data Frames Register */
988 /******************************************************************************/
989 /* Header marker, set to 1 for the header */
990 #define ADAS1000_FRAMES_MARKER (1ul << 31)
991 /* Ready bit indicates if ECG frame data is calculated and
992  ready for reading.
993  0 = Ready, data frame follows
994  1 = Busy */
995 #define ADAS1000_FRAMES_READY_BIT (1ul << 30)
996 /* Overflow bits indicate that since the last frame read,
997  a number of frames have been missed. This field saturates
998  at the maximum count. The data in the frame including
999  this header word is valid but old if the overflow bits
1000  are > 0. When using Skip mode (FRMCTL register (0x0A)[3:2]),
1001  the Overflow bit acts as a flag, where a non-zero value
1002  indicates an overflow.
1003  00 = 0 missed
1004  01 = 1 frame missed
1005  10 = 2 frames missed
1006  11 = 3 or more frames missed */
1007 #define ADAS1000_FRAMES_OVERFLOW (1ul << 28)
1008 /* Internal device error detected.
1009  0 = normal operation
1010  1 = error condition */
1011 #define ADAS1000_FRAMES_FAULT (1ul << 27)
1012 /* PACE 3 Indicates Pacing Artifact was qualified at most
1013  recent point.
1014  0 = No Pacing Artifact
1015  1 = Pacing Artifact Present */
1016 #define ADAS1000_FRAMES_PACE3_DETECTED (1ul << 26)
1017 /* PACE 2 Indicates Pacing Artifact was qualified at most
1018  recent point.
1019  0 = No Pacing Artifact
1020  1 = Pacing Artifact Present */
1021 #define ADAS1000_FRAMES_PACE2_DETECTED (1ul << 25)
1022 /* PACE 1 Indicates Pacing Artifact was qualified at most
1023  recent point.
1024  0 = No Pacing Artifact
1025  1 = Pacing Artifact Present */
1026 #define ADAS1000_FRAMES_PACE1_DETECTED (1ul << 24)
1027 /* 0 = no new respiration data
1028  1 = respiration data updated */
1029 #define ADAS1000_FRAMES_RESPIRATION (1ul << 23)
1030 /* If both DC & AC leads off are enabled, this bit is the
1031  OR of all the AC leads off detect flags. If only AC or
1032  DC leads off is enabled (but not both, this bit reflects
1033  the OR of all DC & AC leads off flags.
1034  0 = all leads connected
1035  1 = one or more leads off detected */
1036 #define ADAS1000_FRAMES_LEADS_OFF_DETECTED (1ul << 22)
1037 /* 0 = all leads connected
1038  1 = one or more leads off detected */
1039 #define ADAS1000_FRAMES_DC_LEADS_OFF_DETECTED (1ul << 21)
1040 /* 0 = ADC within range
1041  1 = ADC out of range */
1042 #define ADAS1000_FRAMES_ADC_OUT_OF_RANGE (1ul << 20)
1043 /******************************************************************************/
1044 /* Frame CRC Register */
1045 /******************************************************************************/
1046 /* Cyclic Redundancy Check */
1047 #define ADAS1000_CRC_MASK (0x00FFFFFF << 0)
1048 
1049 /******************************************************************************/
1050 /* ADAS1000 data rates, word sizes and frame size */
1051 /******************************************************************************/
1052 #define ADAS1000_31_25HZ_FRAME_RATE 3125
1053 #define ADAS1000_2KHZ_FRAME_RATE 2000
1054 #define ADAS1000_16KHZ_FRAME_RATE 16000
1055 #define ADAS1000_128KHZ_FRAME_RATE 128000
1056 
1057 #define ADAS1000_31_25HZ_WORD_SIZE 32
1058 #define ADAS1000_2KHZ_WORD_SIZE 32
1059 #define ADAS1000_16KHZ_WORD_SIZE 32
1060 #define ADAS1000_128KHZ_WORD_SIZE 16
1061 
1062 #define ADAS1000_31_25HZ_FRAME_SIZE 12
1063 #define ADAS1000_2KHZ_FRAME_SIZE 12
1064 #define ADAS1000_16KHZ_FRAME_SIZE 12
1065 #define ADAS1000_128KHZ_FRAME_SIZE 15
1066 
1067 /******************************************************************************/
1068 /* ADAS1000 CRC constants */
1069 /******************************************************************************/
1070 #define CRC_POLY_2KHZ_16KHZ 0x005D6DCBul
1071 #define CRC_CHECK_CONST_2KHZ_16KHZ 0x0015A0BAul
1072 
1073 #define CRC_POLY_128KHZ 0x00001021ul
1074 #define CRC_CHECK_CONST_128KHz 0x00001D0Ful
1075 
1080  uint32_t frame_size;
1082  uint32_t frame_rate;
1085 };
1086 
1091  uint32_t frame_rate;
1092 };
1093 
1094 struct read_param {
1106 };
1107 
1108 
1109 /******************************************************************************/
1110 /* Functions Prototypes */
1111 /******************************************************************************/
1114  uint32_t *spi_freq);
1115 
1116 /* Initializes the communication with ADAS1000 and checks if the device is present.*/
1117 int32_t adas1000_init(struct adas1000_dev **device,
1118  const struct adas1000_init_param *init_param);
1119 
1120 /* Reads the value of a ADAS1000 register */
1121 int32_t adas1000_read(struct adas1000_dev *device, uint8_t reg_addr,
1122  uint32_t *reg_data);
1123 
1124 /* Writes a value into a ADAS1000 register */
1125 int32_t adas1000_write(struct adas1000_dev *device, uint8_t reg_addr,
1126  uint32_t reg_data);
1127 
1128 /* Performs a software reset of the ADAS1000 */
1129 int32_t adas1000_soft_reset(struct adas1000_dev *device);
1130 
1131 /* Compute frame size. */
1133 
1134 /* Selects which words are not included in a data frame */
1136  uint32_t words_mask);
1137 
1138 /* Sets the frame rate */
1139 int32_t adas1000_set_frame_rate(struct adas1000_dev *device, uint32_t rate);
1140 
1141 /* Reads the specified number of frames */
1142 int32_t adas1000_read_data(struct adas1000_dev *device, uint8_t *data_buff,
1143  uint32_t frame_cnt, struct read_param *read_data_param);
1144 
1145 /* Computes the CRC for a frame */
1147  uint8_t *buff);
1148 
1149 #endif /* _ADAS1000_H_ */
adas1000_init
int32_t adas1000_init(struct adas1000_dev **device, const struct adas1000_init_param *init_param)
Initializes the SPI communication with ADAS1000. The ADAS1000 is configured with the specified frame ...
Definition: adas1000.c:99
ADAS1000_31_25HZ_FRAME_SIZE
#define ADAS1000_31_25HZ_FRAME_SIZE
Definition: adas1000.h:1062
adas1000_read_data
int32_t adas1000_read_data(struct adas1000_dev *device, uint8_t *data_buff, uint32_t frame_cnt, struct read_param *read_data_param)
Reads the specified number of frames.
Definition: adas1000.c:330
adas1000_soft_reset
int32_t adas1000_soft_reset(struct adas1000_dev *device)
Software reset of the device.
Definition: adas1000.c:194
adas1000_dev::inactive_words_no
uint32_t inactive_words_no
Definition: adas1000.h:1084
ADAS1000_ALL_CH_MASK
#define ADAS1000_ALL_CH_MASK
Definition: adas1000.h:59
adas1000_write
int32_t adas1000_write(struct adas1000_dev *device, uint8_t reg_addr, uint32_t reg_data)
Write device register.
Definition: adas1000.c:175
NO_OS_DECLARE_CRC16_TABLE
NO_OS_DECLARE_CRC16_TABLE(ad7606_crc16)
ADAS1000_128KHZ_WORD_SIZE
#define ADAS1000_128KHZ_WORD_SIZE
Definition: adas1000.h:1060
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
no_os_spi.h
Header file of SPI Interface.
CRC_POLY_128KHZ
#define CRC_POLY_128KHZ
Definition: adas1000.h:1073
ADAS1000_2KHZ_FRAME_RATE
#define ADAS1000_2KHZ_FRAME_RATE
Definition: adas1000.h:1053
ADAS1000_31_25HZ_FRAME_RATE
#define ADAS1000_31_25HZ_FRAME_RATE
Definition: adas1000.h:1052
adas1000_read_data
int32_t adas1000_read_data(struct adas1000_dev *device, uint8_t *data_buff, uint32_t frame_cnt, struct read_param *read_data_param)
Reads the specified number of frames.
Definition: adas1000.c:330
read_param::start_read
bool start_read
Definition: adas1000.h:1096
ADAS1000_NOP
#define ADAS1000_NOP
Definition: adas1000.h:62
no_os_crc24_populate_msb
void no_os_crc24_populate_msb(uint32_t *table, const uint32_t polynomial)
adas1000_init_param
Definition: adas1000.h:1087
ADAS1000_WD_CNT_MASK
#define ADAS1000_WD_CNT_MASK
Definition: adas1000.h:60
adas1000_init_param::frame_rate
uint32_t frame_rate
Definition: adas1000.h:1091
ADAS1000_128KHZ_FRAME_SIZE
#define ADAS1000_128KHZ_FRAME_SIZE
Definition: adas1000.h:1065
device
Definition: ad9361_util.h:75
ADAS1000_FRMCTL_FRMRATE_2KHZ
#define ADAS1000_FRMCTL_FRMRATE_2KHZ
Definition: adas1000.h:586
adas1000_init_param::spi_init
struct no_os_spi_init_param spi_init
Definition: adas1000.h:1089
ADAS1000_FRMCTL_FRMRATE_31_25HZ
#define ADAS1000_FRMCTL_FRMRATE_31_25HZ
Definition: adas1000.h:592
ADAS1000_FRMCTL_FRMRATE_MASK
#define ADAS1000_FRMCTL_FRMRATE_MASK
Definition: adas1000.h:606
ADAS1000_16KHZ_WORD_SIZE
#define ADAS1000_16KHZ_WORD_SIZE
Definition: adas1000.h:1059
ADAS1000_16KHZ_FRAME_SIZE
#define ADAS1000_16KHZ_FRAME_SIZE
Definition: adas1000.h:1064
ADAS1000_ECGCTL_SWRST
#define ADAS1000_ECGCTL_SWRST
Definition: adas1000.h:161
adas1000_dev::frame_size
uint32_t frame_size
Definition: adas1000.h:1080
no_os_error.h
Error codes definition.
adas1000_compute_frame_crc
uint32_t adas1000_compute_frame_crc(struct adas1000_dev *device, uint8_t *buff)
Computes the CRC for a frame.
Definition: adas1000.c:407
ADAS1000_FRMCTL_WORD_MASK
#define ADAS1000_FRMCTL_WORD_MASK
Definition: adas1000.h:594
adas1000_compute_frame_size
int32_t adas1000_compute_frame_size(struct adas1000_dev *device)
Compute frame size.
Definition: adas1000.c:211
ADAS1000_16KHZ_FRAME_RATE
#define ADAS1000_16KHZ_FRAME_RATE
Definition: adas1000.h:1054
read_param::ready_repeat
bool ready_repeat
Definition: adas1000.h:1105
adas1000_set_inactive_framewords
int32_t adas1000_set_inactive_framewords(struct adas1000_dev *device, uint32_t words_mask)
Selects which words are not included in a data frame.
Definition: adas1000.c:244
adas1000_compute_frame_size
int32_t adas1000_compute_frame_size(struct adas1000_dev *device)
Compute frame size.
Definition: adas1000.c:211
ADAS1000_ECGCTL
#define ADAS1000_ECGCTL
Definition: adas1000.h:63
read_param::stop_read
bool stop_read
Definition: adas1000.h:1099
ADAS1000_2KHZ_FRAME_SIZE
#define ADAS1000_2KHZ_FRAME_SIZE
Definition: adas1000.h:1063
ADAS1000_FRMCTL
#define ADAS1000_FRMCTL
Definition: adas1000.h:72
adas1000_set_frame_rate
int32_t adas1000_set_frame_rate(struct adas1000_dev *device, uint32_t rate)
Sets the frame rate.
Definition: adas1000.c:282
adas1000_read
int32_t adas1000_read(struct adas1000_dev *device, uint8_t reg_addr, uint32_t *reg_data)
Read device register.
Definition: adas1000.c:146
adas1000_set_frame_rate
int32_t adas1000_set_frame_rate(struct adas1000_dev *device, uint32_t rate)
Sets the frame rate.
Definition: adas1000.c:282
read_param::wait_for_ready
bool wait_for_ready
Definition: adas1000.h:1102
adas1000_init
int32_t adas1000_init(struct adas1000_dev **device, const struct adas1000_init_param *init_param)
Initializes the SPI communication with ADAS1000. The ADAS1000 is configured with the specified frame ...
Definition: adas1000.c:99
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
adas1000_write
int32_t adas1000_write(struct adas1000_dev *device, uint8_t reg_addr, uint32_t reg_data)
Write device register.
Definition: adas1000.c:175
no_os_crc.h
Generic header file for all CRC computation algorithms.
ADAS1000_128KHZ_FRAME_RATE
#define ADAS1000_128KHZ_FRAME_RATE
Definition: adas1000.h:1055
ADAS1000_FRAMES
#define ADAS1000_FRAMES
Definition: adas1000.h:102
adas1000_dev
Definition: adas1000.h:1076
adas1000_set_inactive_framewords
int32_t adas1000_set_inactive_framewords(struct adas1000_dev *device, uint32_t words_mask)
Selects which words are not included in a data frame.
Definition: adas1000.c:244
adas1000_read
int32_t adas1000_read(struct adas1000_dev *device, uint8_t reg_addr, uint32_t *reg_data)
Read device register.
Definition: adas1000.c:146
no_os_crc24
uint32_t no_os_crc24(const uint32_t *table, const uint8_t *pdata, size_t nbytes, uint32_t crc)
no_os_crc16
uint16_t no_os_crc16(const uint16_t *table, const uint8_t *pdata, size_t nbytes, uint16_t crc)
adas1000_dev::spi_desc
struct no_os_spi_desc * spi_desc
Definition: adas1000.h:1078
ADAS1000_FRMCTL_FRMRATE_16KHZ
#define ADAS1000_FRMCTL_FRMRATE_16KHZ
Definition: adas1000.h:588
ADAS1000_COMM_WRITE
#define ADAS1000_COMM_WRITE
Definition: adas1000.h:57
read_param
Definition: adas1000.h:1094
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
adas1000_compute_frame_crc
uint32_t adas1000_compute_frame_crc(struct adas1000_dev *device, uint8_t *buff)
Computes the CRC for a frame.
Definition: adas1000.c:407
ADAS1000_31_25HZ_WORD_SIZE
#define ADAS1000_31_25HZ_WORD_SIZE
Definition: adas1000.h:1057
NO_OS_DECLARE_CRC24_TABLE
#define NO_OS_DECLARE_CRC24_TABLE(_table)
Definition: no_os_crc24.h:47
adas1000_compute_spi_freq
int32_t adas1000_compute_spi_freq(struct adas1000_init_param *init_param, uint32_t *spi_freq)
Preliminary function which computes the spi frequency based on the frame rate value passed input para...
Definition: adas1000.c:61
ADAS1000_RDY_MASK
#define ADAS1000_RDY_MASK
Definition: adas1000.h:58
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
no_os_crc16_populate_msb
void no_os_crc16_populate_msb(uint16_t *table, const uint16_t polynomial)
adas1000.h
Header file of ADAS1000 Driver.
ADAS1000_2KHZ_WORD_SIZE
#define ADAS1000_2KHZ_WORD_SIZE
Definition: adas1000.h:1058
CRC_POLY_2KHZ_16KHZ
#define CRC_POLY_2KHZ_16KHZ
Definition: adas1000.h:1070
ADAS1000_FRMCTL_FRMRATE_128KHZ
#define ADAS1000_FRMCTL_FRMRATE_128KHZ
Definition: adas1000.h:590
adas1000_dev::frame_rate
uint32_t frame_rate
Definition: adas1000.h:1082
adas1000_compute_spi_freq
int32_t adas1000_compute_spi_freq(struct adas1000_init_param *init_param, uint32_t *spi_freq)
Preliminary function which computes the spi frequency based on the frame rate value passed input para...
Definition: adas1000.c:61
adas1000_soft_reset
int32_t adas1000_soft_reset(struct adas1000_dev *device)
Software reset of the device.
Definition: adas1000.c:194
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112