no-OS
adf7023.h
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1 /***************************************************************************/
39 #ifndef __ADF7023_H__
40 #define __ADF7023_H__
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include <stdint.h>
46 #include "no_os_spi.h"
47 #include "no_os_gpio.h"
48 
49 /* Status Word */
50 #define STATUS_SPI_READY (0x1 << 7)
51 #define STATUS_IRQ_STATUS (0x1 << 6)
52 #define STATUS_CMD_READY (0x1 << 5)
53 #define STATUS_FW_STATE (0x1F << 0)
54 
55 /* FW_STATE Description */
56 #define FW_STATE_INIT 0x0F
57 #define FW_STATE_BUSY 0x00
58 #define FW_STATE_PHY_OFF 0x11
59 #define FW_STATE_PHY_ON 0x12
60 #define FW_STATE_PHY_RX 0x13
61 #define FW_STATE_PHY_TX 0x14
62 #define FW_STATE_PHY_SLEEP 0x06
63 #define FW_STATE_GET_RSSI 0x05
64 #define FW_STATE_IR_CAL 0x07
65 #define FW_STATE_AES_DECRYPT_INIT 0x08
66 #define FW_STATE_AES_DECRYPT 0x09
67 #define FW_STATE_AES_ENCRYPT 0x0A
68 
69 /* SPI Memory Access Commands */
70 #define SPI_MEM_WR 0x18 // Write data to packet RAM sequentially.
71 #define SPI_MEM_RD 0x38 // Read data from packet RAM sequentially.
72 #define SPI_MEMR_WR 0x08 // Write data to packet RAM nonsequentially.
73 #define SPI_MEMR_RD 0x28 // Read data from packet RAM nonsequentially.
74 #define SPI_NOP 0xFF // No operation.
75 
76 /* Radio Controller Commands */
77 #define CMD_SYNC 0xA2 // This is an optional command. It is not necessary to use it during device initialization
78 #define CMD_PHY_OFF 0xB0 // Performs a transition of the device into the PHY_OFF state.
79 #define CMD_PHY_ON 0xB1 // Performs a transition of the device into the PHY_ON state.
80 #define CMD_PHY_RX 0xB2 // Performs a transition of the device into the PHY_RX state.
81 #define CMD_PHY_TX 0xB5 // Performs a transition of the device into the PHY_TX state.
82 #define CMD_PHY_SLEEP 0xBA // Performs a transition of the device into the PHY_SLEEP state.
83 #define CMD_CONFIG_DEV 0xBB // Configures the radio parameters based on the BBRAM values.
84 #define CMD_GET_RSSI 0xBC // Performs an RSSI measurement.
85 #define CMD_BB_CAL 0xBE // Performs a calibration of the IF filter.
86 #define CMD_HW_RESET 0xC8 // Performs a full hardware reset. The device enters the PHY_SLEEP state.
87 #define CMD_RAM_LOAD_INIT 0xBF // Prepares the program RAM for a firmware module download.
88 #define CMD_RAM_LOAD_DONE 0xC7 // Performs a reset of the communications processor after download of a firmware module to program RAM.
89 #define CMD_IR_CAL 0xBD // Initiates an image rejection calibration routine.
90 #define CMD_AES_ENCRYPT 0xD0 // Performs an AES encryption on the transmit payload data stored in packet RAM.
91 #define CMD_AES_DECRYPT 0xD2 // Performs an AES decryption on the received payload data stored in packet RAM.
92 #define CMD_AES_DECRYPT_INIT 0xD1 // Initializes the internal variables required for AES decryption.
93 #define CMD_RS_ENCODE_INIT 0xD1 // Initializes the internal variables required for the Reed Solomon encoding.
94 #define CMD_RS_ENCODE 0xD0 // Calculates and appends the Reed Solomon check bytes to the transmit payload data stored in packet RAM.
95 #define CMD_RS_DECODE 0xD2 // Performs a Reed Solomon error correction on the received payload data stored in packet RAM.
96 
97 /* Battery Backup Memory (BBRAM) */
98 #define BBRAM_REG_INTERRUPT_MASK_0 0x100
99 #define BBRAM_REG_INTERRUPT_MASK_1 0x101
100 #define BBRAM_REG_NUMBER_OF_WAKEUPS_0 0x102
101 #define BBRAM_REG_NUMBER_OF_WAKEUPS_1 0x103
102 #define BBRAM_REG_NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_0 0x104
103 #define BBRAM_REG_NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_1 0x105
104 #define BBRAM_REG_RX_DWELL_TIME 0x106
105 #define BBRAM_REG_PARMTIME_DIVIDER 0x107
106 #define BBRAM_REG_SWM_RSSI_THRESH 0x108
107 #define BBRAM_REG_CHANNEL_FREQ_0 0x109
108 #define BBRAM_REG_CHANNEL_FREQ_1 0x10A
109 #define BBRAM_REG_CHANNEL_FREQ_2 0x10B
110 #define BBRAM_REG_RADIO_CFG_0 0x10C
111 #define BBRAM_REG_RADIO_CFG_1 0x10D
112 #define BBRAM_REG_RADIO_CFG_2 0x10E
113 #define BBRAM_REG_RADIO_CFG_3 0x10F
114 #define BBRAM_REG_RADIO_CFG_4 0x110
115 #define BBRAM_REG_RADIO_CFG_5 0x111
116 #define BBRAM_REG_RADIO_CFG_6 0x112
117 #define BBRAM_REG_RADIO_CFG_7 0x113
118 #define BBRAM_REG_RADIO_CFG_8 0x114
119 #define BBRAM_REG_RADIO_CFG_9 0x115
120 #define BBRAM_REG_RADIO_CFG_10 0x116
121 #define BBRAM_REG_RADIO_CFG_11 0x117
122 #define BBRAM_REG_IMAGE_REJECT_CAL_PHASE 0x118
123 #define BBRAM_REG_IMAGE_REJECT_CAL_AMPLITUDE 0x119
124 #define BBRAM_REG_MODE_CONTROL 0x11A
125 #define BBRAM_REG_PREAMBLE_MATCH 0x11B
126 #define BBRAM_REG_SYMBOL_MODE 0x11C
127 #define BBRAM_REG_PREAMBLE_LEN 0x11D
128 #define BBRAM_REG_CRC_POLY_0 0x11E
129 #define BBRAM_REG_CRC_POLY_1 0x11F
130 #define BBRAM_REG_SYNC_CONTROL 0x120
131 #define BBRAM_REG_SYNC_BYTE_0 0x121
132 #define BBRAM_REG_SYNC_BYTE_1 0x122
133 #define BBRAM_REG_SYNC_BYTE_2 0x123
134 #define BBRAM_REG_TX_BASE_ADR 0x124
135 #define BBRAM_REG_RX_BASE_ADR 0x125
136 #define BBRAM_REG_PACKET_LENGTH_CONTROL 0x126
137 #define BBRAM_REG_PACKET_LENGTH_MAX 0x127
138 #define BBRAM_REG_STATIC_REG_FIX 0x128
139 #define BBRAM_REG_ADDRESS_MATCH_OFFSET 0x129
140 #define BBRAM_REG_ADDRESS_LENGTH 0x12A
141 #define BBRAM_REG_ADDRESS_FILTERING_0 0x12B
142 #define BBRAM_REG_ADDRESS_FILTERING_1 0x12C
143 #define BBRAM_REG_ADDRESS_FILTERING_2 0x12D
144 #define BBRAM_REG_ADDRESS_FILTERING_3 0x12E
145 #define BBRAM_REG_ADDRESS_FILTERING_4 0x12F
146 #define BBRAM_REG_ADDRESS_FILTERING_5 0x130
147 #define BBRAM_REG_ADDRESS_FILTERING_6 0x131
148 #define BBRAM_REG_ADDRESS_FILTERING_7 0x132
149 #define BBRAM_REG_ADDRESS_FILTERING_8 0x133
150 #define BBRAM_REG_ADDRESS_FILTERING_9 0x134
151 #define BBRAM_REG_ADDRESS_FILTERING_10 0x135
152 #define BBRAM_REG_ADDRESS_FILTERING_11 0x136
153 #define BBRAM_REG_ADDRESS_FILTERING_12 0x137
154 #define BBRAM_REG_RSSI_WAIT_TIME 0x138
155 #define BBRAM_REG_TESTMODES 0x139
156 #define BBRAM_REG_TRANSITION_CLOCK_DIV 0x13A
157 #define BBRAM_REG_RESERVED_0 0x13B
158 #define BBRAM_REG_RESERVED_1 0x13C
159 #define BBRAM_REG_RESERVED_2 0x13D
160 #define BBRAM_REG_RX_SYNTH_LOCK_TIME 0x13E
161 #define BBRAM_REG_TX_SYNTH_LOCK_TIME 0x13F
162 
163 /* BBRAM_REG_INTERRUPT_MASK_0 - 0x100 */
164 #define BBRAM_INTERRUPT_MASK_0_INTERRUPT_NUM_WAKEUPS (0x1 << 7)
165 #define BBRAM_INTERRUPT_MASK_0_INTERRUPT_SWM_RSSI_DET (0x1 << 6)
166 #define BBRAM_INTERRUPT_MASK_0_INTERRUPT_AES_DONE (0x1 << 5)
167 #define BBRAM_INTERRUPT_MASK_0_INTERRUPT_TX_EOF (0x1 << 4)
168 #define BBRAM_INTERRUPT_MASK_0_INTERRUPT_ADDRESS_MATCH (0x1 << 3)
169 #define BBRAM_INTERRUPT_MASK_0_INTERRUPT_CRC_CORRECT (0x1 << 2)
170 #define BBRAM_INTERRUPT_MASK_0_INTERRUPT_SYNC_DETECT (0x1 << 1)
171 #define BBRAM_INTERRUPT_MASK_0_INTERRUPT_PREMABLE_DETECT (0x1 << 0)
172 
173 /* BBRAM_REG_INTERRUPT_MASK_1 - 0x101*/
174 #define BBRAM_INTERRUPT_MASK_1_BATTERY_ALARM (0x1 << 7)
175 #define BBRAM_INTERRUPT_MASK_1_CMD_READY (0x1 << 6)
176 #define BBRAM_INTERRUPT_MASK_1_WUC_TIMEOUT (0x1 << 4)
177 #define BBRAM_INTERRUPT_MASK_1_SPI_READY (0x1 << 1)
178 #define BBRAM_INTERRUPT_MASK_1_CMD_FINISHED (0x1 << 0)
179 
180 /* BBRAM_REG_RADIO_CFG_0 - 0x10C */
181 #define BBRAM_RADIO_CFG_0_DATA_RATE_7_0(x) ((x & 0xFF) << 0)
182 
183 /* BBRAM_REG_RADIO_CFG_1 - 0x10D */
184 #define BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8(x) ((x & 0xF) << 4)
185 #define BBRAM_RADIO_CFG_1_DATA_RATE_11_8(x) ((x & 0xF) << 0)
186 
187 /* BBRAM_REG_RADIO_CFG_2 - 0x10E */
188 #define BBRAM_RADIO_CFG_2_FREQ_DEVIATION_7_0(x) ((x & 0xFF) << 0)
189 
190 /* BBRAM_REG_RADIO_CFG_6 - 0x112 */
191 #define BBRAM_RADIO_CFG_6_SYNTH_LUT_CONFIG_0(x) ((x & 0x3F) << 2)
192 #define BBRAM_RADIO_CFG_6_DISCRIM_PHASE(x) ((x & 0x3) << 0)
193 
194 /* BBRAM_REG_RADIO_CFG_7 - 0x113 */
195 #define BBRAM_RADIO_CFG_7_AGC_LOCK_MODE(x) ((x & 0x3) << 6)
196 #define BBRAM_RADIO_CFG_7_SYNTH_LUT_CONTROL(x) ((x & 0x3) << 4)
197 #define BBRAM_RADIO_CFG_7_SYNTH_LUT_CONFIG_1(x) ((x & 0xF) << 0)
198 
199 /* BBRAM_REG_RADIO_CFG_8 - 0x114 */
200 #define BBRAM_RADIO_CFG_8_PA_SINGLE_DIFF_SEL (0x1 << 7)
201 #define BBRAM_RADIO_CFG_8_PA_LEVEL(x) ((x & 0xF) << 3)
202 #define BBRAM_RADIO_CFG_8_PA_RAMP(x) ((x & 0x7) << 0)
203 
204 /* BBRAM_REG_RADIO_CFG_9 - 0x115 */
205 #define BBRAM_RADIO_CFG_9_IFBW(x) ((x & 0x3) << 6)
206 #define BBRAM_RADIO_CFG_9_MOD_SCHEME(x) ((x & 0x7) << 3)
207 #define BBRAM_RADIO_CFG_9_DEMOD_SCHEME(x) ((x & 0x7) << 0)
208 
209 /* BBRAM_REG_RADIO_CFG_10 - 0x116 */
210 #define BBRAM_RADIO_CFG_10_AFC_POLARITY (0x0 << 4)
211 #define BBRAM_RADIO_CFG_10_AFC_SCHEME(x) ((x & 0x3) << 2)
212 #define BBRAM_RADIO_CFG_10_AFC_LOCK_MODE(x) ((x & 0x3) << 0)
213 
214 /* BBRAM_REG_RADIO_CFG_11 - 0x117 */
215 #define BBRAM_RADIO_CFG_11_AFC_KP(x) ((x & 0xF) << 4)
216 #define BBRAM_RADIO_CFG_11_AFC_KI(x) ((x & 0xF) << 0)
217 
218 /* BBRAM_REG_MODE_CONTROL - 0x11A */
219 #define BBRAM_MODE_CONTROL_SWM_EN (0x1 << 7)
220 #define BBRAM_MODE_CONTROL_BB_CAL (0x1 << 6)
221 #define BBRAM_MODE_CONTROL_SWM_RSSI_QUAL (0x1 << 5)
222 #define BBRAM_MODE_CONTROL_TX_TO_RX_AUTO_TURNAROUND (0x1 << 4)
223 #define BBRAM_MODE_CONTROL_RX_TO_TX_AUTO_TURNAROUND (0x1 << 3)
224 #define BBRAM_MODE_CONTROL_CUSTOM_TRX_SYNTH_LOCK_TIME_EN (0x1 << 2)
225 #define BBRAM_MODE_CONTROL_EXT_LNA_EN (0x1 << 1)
226 #define BBRAM_MODE_CONTROL_EXT_PA_EN (0x1 << 0)
227 
228 /* BBRAM_REG_SYMBOL_MODE - 0x11C */
229 #define BBRAM_SYMBOL_MODE_MANCHESTER_ENC (0x1 << 6)
230 #define BBRAM_SYMBOL_MODE_PROG_CRC_EN (0x1 << 5)
231 #define BBRAM_SYMBOL_MODE_EIGHT_TEN_ENC (0x1 << 4)
232 #define BBRAM_SYMBOL_MODE_DATA_WHITENING (0x1 << 3)
233 #define BBRAM_SYMBOL_MODE_SYMBOL_LENGTH(x) ((x & 0x7) << 0)
234 
235 /* BBRAM_REG_SYNC_CONTROL - 0x120 */
236 #define BBRAM_SYNC_CONTROL_SYNC_ERROR_TOL(x) ((x & 0x3) << 6)
237 #define BBRAM_SYNC_CONTROL_SYNC_WORD_LENGTH(x) ((x & 0x1F) << 0)
238 
239 /* BBRAM_REG_PACKET_LENGTH_CONTROL - 0x126 */
240 #define BBRAM_PACKET_LENGTH_CONTROL_DATA_BYTE (0x1 << 7)
241 #define BBRAM_PACKET_LENGTH_CONTROL_PACKET_LEN (0x1 << 6)
242 #define BBRAM_PACKET_LENGTH_CONTROL_CRC_EN (0x1 << 5)
243 #define BBRAM_PACKET_LENGTH_CONTROL_DATA_MODE(x) ((x & 0x3) << 3)
244 #define BBRAM_PACKET_LENGTH_CONTROL_LENGTH_OFFSET(x) ((x & 0x7) << 0)
245 
246 /* BBRAM_REG_TESTMODES - 0x139 */
247 #define BBRAM_TESTMODES_EXT_PA_LNA_ATB_CONFIG (0x1 << 7)
248 #define BBRAM_TESTMODES_PER_IRQ_SELF_CLEAR (0x1 << 3)
249 #define BBRAM_TESTMODES_PER_ENABLE (0x1 << 2)
250 #define BBRAM_TESTMODES_CONTINUOUS_TX (0x1 << 1)
251 #define BBRAM_TESTMODES_CONTINUOUS_RX (0x1 << 0)
252 
253 /* Modem Configuration Memory (MCR) */
254 #define MCR_REG_PA_LEVEL_MCR 0x307
255 #define MCR_REG_WUC_CONFIG_HIGH 0x30C
256 #define MCR_REG_WUC_CONFIG_LOW 0x30D
257 #define MCR_REG_WUC_VALUE_HIGH 0x30E
258 #define MCR_REG_WUC_VALUE_LOW 0x30F
259 #define MCR_REG_WUC_FLAG_RESET 0x310
260 #define MCR_REG_WUC_STATUS 0x311
261 #define MCR_REG_RSSI_READBACK 0x312
262 #define MCR_REG_MAX_AFC_RANGE 0x315
263 #define MCR_REG_IMAGE_REJECT_CAL_CONFIG 0x319
264 #define MCR_REG_CHIP_SHUTDOWN 0x322
265 #define MCR_REG_POWERDOWN_RX 0x324
266 #define MCR_REG_POWERDOWN_AUX 0x325
267 #define MCR_REG_ADC_READBACK_HIGH 0x327
268 #define MCR_REG_ADC_READBACK_LOW 0x328
269 #define MCR_REG_BATTERY_MONITOR_THRESHOLD_VOLTAGE 0x32D
270 #define MCR_REG_EXT_UC_CLK_DIVIDE 0x32E
271 #define MCR_REG_AGC_CLK_DIVIDE 0x32F
272 #define MCR_REG_INTERRUPT_SOURCE_0 0x336
273 #define MCR_REG_INTERRUPT_SOURCE_1 0x337
274 #define MCR_REG_CALIBRATION_CONTROL 0x338
275 #define MCR_REG_CALIBRATION_STATUS 0x339
276 #define MCR_REG_RXBB_CAL_CALWRD_READBACK 0x345
277 #define MCR_REG_RXBB_CAL_CALWRD_OVERWRITE 0x346
278 #define MCR_REG_RCOSC_CAL_READBACK_HIGH 0x34F
279 #define MCR_REG_RCOSC_CAL_READBACK_LOW 0x350
280 #define MCR_REG_ADC_CONFIG_LOW 0x359
281 #define MCR_REG_ADC_CONFIG_HIGH 0x35A
282 #define MCR_REG_AGC_OOK_CONTROL 0x35B
283 #define MCR_REG_AGC_CONFIG 0x35C
284 #define MCR_REG_AGC_MODE 0x35D
285 #define MCR_REG_AGC_LOW_THRESHOLD 0x35E
286 #define MCR_REG_AGC_HIGH_THRESHOLD 0x35F
287 #define MCR_REG_AGC_GAIN_STATUS 0x360
288 #define MCR_REG_AGC_ADC_WORD 0x361
289 #define MCR_REG_FREQUENCY_ERROR_READBACK 0x372
290 #define MCR_REG_VCO_BAND_OVRW_VAL 0x3CB
291 #define MCR_REG_VCO_AMPL_OVRW_VAL 0x3CC
292 #define MCR_REG_VCO_OVRW_EN 0x3CD
293 #define MCR_REG_VCO_CAL_CFG 0x3D0
294 #define MCR_REG_OSC_CONFIG 0x3D2
295 #define MCR_REG_VCO_BAND_READBACK 0x3DA
296 #define MCR_REG_VCO_AMPL_READBACK 0x3DB
297 #define MCR_REG_ANALOG_TEST_BUS 0x3F8
298 #define MCR_REG_RSSI_TSTMUX_SEL 0x3F9
299 #define MCR_REG_GPIO_CONFIGURE 0x3FA
300 #define MCR_REG_TEST_DAC_GAIN 0x3FD
301 
303  uint8_t interrupt_mask0; // 0x100
304  uint8_t interrupt_mask1; // 0x101
305  uint8_t number_of_wakeups0; // 0x102
306  uint8_t number_of_wakeups1; // 0x103
309  uint8_t rx_dwell_time; // 0x106
310  uint8_t parmtime_divider; // 0x107
311  uint8_t swm_rssi_thresh; // 0x108
312  uint8_t channel_freq0; // 0x109
313  uint8_t channel_freq1; // 0x10A
314  uint8_t channel_freq2; // 0x10B
315  uint8_t radio_cfg0; // 0x10C
316  uint8_t radio_cfg1; // 0x10D
317  uint8_t radio_cfg2; // 0x10E
318  uint8_t radio_cfg3; // 0x10F
319  uint8_t radio_cfg4; // 0x110
320  uint8_t radio_cfg5; // 0x111
321  uint8_t radio_cfg6; // 0x112
322  uint8_t radio_cfg7; // 0x113
323  uint8_t radio_cfg8; // 0x114
324  uint8_t radio_cfg9; // 0x115
325  uint8_t radio_cfg10; // 0x116
326  uint8_t radio_cfg11; // 0x117
327  uint8_t image_reject_cal_phase; // 0x118
328  uint8_t image_reject_cal_amplitude; // 0x119
329  uint8_t mode_control; // 0x11A
330  uint8_t preamble_match; // 0x11B
331  uint8_t symbol_mode; // 0x11C
332  uint8_t preamble_len; // 0x11D
333  uint8_t crc_poly0; // 0x11E
334  uint8_t crc_poly1; // 0x11F
335  uint8_t syncControl; // 0x120
336  uint8_t sync_byte0; // 0x121
337  uint8_t sync_byte1; // 0x122
338  uint8_t sync_byte2; // 0x123
339  uint8_t tx_base_adr; // 0x124
340  uint8_t rx_base_adr; // 0x125
341  uint8_t packet_length_control; // 0x126
342  uint8_t packet_length_max; // 0x127
343  uint8_t static_reg_fix; // 0x128
344  uint8_t address_match_offset; // 0x129
345  uint8_t address_length; // 0x12A
346  uint8_t address_filtering0; // 0x12B
347  uint8_t address_filtering1; // 0x12C
348  uint8_t address_filtering2; // 0x12D
349  uint8_t address_filtering3; // 0x12E
350  uint8_t address_filtering4; // 0x12F
351  uint8_t address_filtering5; // 0x130
352  uint8_t address_filtering6; // 0x131
353  uint8_t address_filtering7; // 0x132
354  uint8_t address_filtering8; // 0x133
355  uint8_t address_filtering9; // 0x134
356  uint8_t address_filtering10; // 0x135
357  uint8_t address_filtering11; // 0x136
358  uint8_t address_filtering12; // 0x137
359  uint8_t rssi_wait_time; // 0x138
360  uint8_t testmodes; // 0x139
361  uint8_t transition_clock_div; // 0x13A
362  uint8_t reserved0; // 0x13B
363  uint8_t reserved1; // 0x13C
364  uint8_t reserved2; // 0x13D
365  uint8_t rx_synth_lock_time; // 0x13E
366  uint8_t tx_synth_lock_time; // 0x13F
367 };
368 
369 #define ADF7023_TX_BASE_ADR 0x10
370 #define ADF7023_RX_BASE_ADR 0x10
371 
372 /******************************************************************************/
373 /*************************** Types Declarations *******************************/
374 /******************************************************************************/
375 
376 struct adf7023_dev {
377  /* SPI */
379  /* GPIO */
382  /* Device Settings */
384 };
385 
387  /* SPI */
389  /* GPIO */
392 };
393 
394 /******************************************************************************/
395 /************************ Functions Declarations ******************************/
396 /******************************************************************************/
397 
398 /* Initializes the ADF7023. */
399 int32_t adf7023_init(struct adf7023_dev **device,
401 
402 /* Free the resources allocated by adf7023_init(). */
403 int32_t adf7023_remove(struct adf7023_dev *dev);
404 
405 /* Reads the status word of the ADF7023. */
406 void adf7023_get_status(struct adf7023_dev *dev,
407  uint8_t* status);
408 
409 /* Initiates a command. */
410 void adf7023_set_command(struct adf7023_dev *dev,
411  uint8_t command);
412 
413 /* Sets a FW state and waits until the device enters in that state. */
414 void adf7023_set_fw_state(struct adf7023_dev *dev,
415  uint8_t fw_state);
416 
417 /* Reads data from the RAM. */
418 void adf7023_get_ram(struct adf7023_dev *dev,
419  uint32_t address,
420  uint32_t length,
421  uint8_t* data);
422 
423 /* Writes data to RAM. */
424 void adf7023_set_ram(struct adf7023_dev *dev,
425  uint32_t address,
426  uint32_t length,
427  uint8_t* data);
428 
429 /* Receives one packet. */
430 void adf7023_receive_packet(struct adf7023_dev *dev,
431  uint8_t* packet,
432  uint8_t* length);
433 
434 /* Transmits one packet. */
435 void adf7023_transmit_packet(struct adf7023_dev *dev,
436  uint8_t* packet,
437  uint8_t length);
438 
439 /* Sets the channel frequency. */
441  uint32_t ch_freq);
442 
443 /* Sets the data rate. */
444 void adf7023_set_data_rate(struct adf7023_dev *dev,
445  uint32_t data_rate);
446 
447 /* Sets the frequency deviation. */
449  uint32_t freq_dev);
450 
451 #endif // __ADF7023_H__
adf7023_transmit_packet
void adf7023_transmit_packet(struct adf7023_dev *dev, uint8_t *packet, uint8_t length)
Transmits one packet.
Definition: adf7023.c:313
adf7023_dev::adf7023_bbram_current
struct adf7023_bbram adf7023_bbram_current
Definition: adf7023.h:383
adf7023_bbram::reserved2
uint8_t reserved2
Definition: adf7023.h:364
SPI_MEM_RD
#define SPI_MEM_RD
Definition: adf7023.h:71
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
adf7023_bbram::address_filtering10
uint8_t address_filtering10
Definition: adf7023.h:356
adf7023_bbram::radio_cfg5
uint8_t radio_cfg5
Definition: adf7023.h:320
FW_STATE_PHY_OFF
#define FW_STATE_PHY_OFF
Definition: adf7023.h:58
adf7023_bbram::mode_control
uint8_t mode_control
Definition: adf7023.h:329
adf7023_bbram::radio_cfg4
uint8_t radio_cfg4
Definition: adf7023.h:319
ADF7023_CS_DEASSERT
#define ADF7023_CS_DEASSERT
Definition: adf7023.c:52
adf7023_init_param
Definition: adf7023.h:386
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
adf7023_set_command
void adf7023_set_command(struct adf7023_dev *dev, uint8_t command)
Initiates a command.
Definition: adf7023.c:184
adf7023_bbram::number_of_wakeups0
uint8_t number_of_wakeups0
Definition: adf7023.h:305
adf7023_set_fw_state
void adf7023_set_fw_state(struct adf7023_dev *dev, uint8_t fw_state)
Sets a FW state and waits until the device enters in that state.
Definition: adf7023.c:200
adf7023_write_read_byte
void adf7023_write_read_byte(struct adf7023_dev *dev, uint8_t write_byte, uint8_t *read_byte)
Transfers one byte of data.
Definition: adf7023.c:69
no_os_spi.h
Header file of SPI Interface.
CMD_PHY_RX
#define CMD_PHY_RX
Definition: adf7023.h:80
CMD_PHY_TX
#define CMD_PHY_TX
Definition: adf7023.h:81
no_os_gpio_get_value
int32_t no_os_gpio_get_value(struct no_os_gpio_desc *desc, uint8_t *value)
Get the value of the specified GPIO.
Definition: no_os_gpio.c:177
adf7023_bbram::radio_cfg6
uint8_t radio_cfg6
Definition: adf7023.h:321
ADF7023_CS_ASSERT
#define ADF7023_CS_ASSERT
Definition: adf7023.c:50
adf7023_bbram::syncControl
uint8_t syncControl
Definition: adf7023.h:335
adf7023_bbram::packet_length_max
uint8_t packet_length_max
Definition: adf7023.h:342
adf7023_bbram::image_reject_cal_phase
uint8_t image_reject_cal_phase
Definition: adf7023.h:327
adf7023_bbram::address_filtering4
uint8_t address_filtering4
Definition: adf7023.h:350
BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8
#define BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8(x)
Definition: adf7023.h:184
adf7023_bbram::rx_base_adr
uint8_t rx_base_adr
Definition: adf7023.h:340
adf7023_remove
int32_t adf7023_remove(struct adf7023_dev *dev)
Free the resources allocated by adf7023_init().
Definition: adf7023.c:145
adf7023_bbram::crc_poly0
uint8_t crc_poly0
Definition: adf7023.h:333
adf7023_init_param::gpio_miso
struct no_os_gpio_init_param gpio_miso
Definition: adf7023.h:391
device
Definition: ad9361_util.h:75
adf7023_config.h
Configuration file of ADF7023 Driver.
NO_OS_GPIO_HIGH
@ NO_OS_GPIO_HIGH
Definition: no_os_gpio.h:123
adf7023_bbram::tx_synth_lock_time
uint8_t tx_synth_lock_time
Definition: adf7023.h:366
BBRAM_RADIO_CFG_2_FREQ_DEVIATION_7_0
#define BBRAM_RADIO_CFG_2_FREQ_DEVIATION_7_0(x)
Definition: adf7023.h:188
adf7023_bbram::rx_synth_lock_time
uint8_t rx_synth_lock_time
Definition: adf7023.h:365
adf7023_set_channel_frequency
void adf7023_set_channel_frequency(struct adf7023_dev *dev, uint32_t ch_freq)
Sets the channel frequency.
Definition: adf7023.c:341
FW_STATE_PHY_RX
#define FW_STATE_PHY_RX
Definition: adf7023.h:60
BBRAM_RADIO_CFG_0_DATA_RATE_7_0
#define BBRAM_RADIO_CFG_0_DATA_RATE_7_0(x)
Definition: adf7023.h:181
adf7023_set_frequency_deviation
void adf7023_set_frequency_deviation(struct adf7023_dev *dev, uint32_t freq_dev)
Sets the frequency deviation.
Definition: adf7023.c:381
adf7023.h
Header file of ADF7023 Driver.
FW_STATE_PHY_ON
#define FW_STATE_PHY_ON
Definition: adf7023.h:59
adf7023_get_status
void adf7023_get_status(struct adf7023_dev *dev, uint8_t *status)
Reads the status word of the ADF7023.
Definition: adf7023.c:167
adf7023_bbram::address_filtering1
uint8_t address_filtering1
Definition: adf7023.h:347
adf7023_bbram::sync_byte0
uint8_t sync_byte0
Definition: adf7023.h:336
adf7023_bbram::reserved1
uint8_t reserved1
Definition: adf7023.h:363
adf7023_bbram::address_filtering9
uint8_t address_filtering9
Definition: adf7023.h:355
adf7023_bbram::preamble_match
uint8_t preamble_match
Definition: adf7023.h:330
adf7023_bbram::parmtime_divider
uint8_t parmtime_divider
Definition: adf7023.h:310
adf7023_bbram::address_filtering12
uint8_t address_filtering12
Definition: adf7023.h:358
adf7023_set_fw_state
void adf7023_set_fw_state(struct adf7023_dev *dev, uint8_t fw_state)
Sets a FW state and waits until the device enters in that state.
Definition: adf7023.c:200
adf7023_bbram::swm_rssi_thresh
uint8_t swm_rssi_thresh
Definition: adf7023.h:311
adf7023_set_data_rate
void adf7023_set_data_rate(struct adf7023_dev *dev, uint32_t data_rate)
Sets the data rate.
Definition: adf7023.c:359
BBRAM_INTERRUPT_MASK_0_INTERRUPT_CRC_CORRECT
#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_CRC_CORRECT
Definition: adf7023.h:169
BBRAM_INTERRUPT_MASK_0_INTERRUPT_TX_EOF
#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_TX_EOF
Definition: adf7023.h:167
adf7023_bbram::channel_freq2
uint8_t channel_freq2
Definition: adf7023.h:314
adf7023_bbram::address_match_offset
uint8_t address_match_offset
Definition: adf7023.h:344
adf7023_bbram::radio_cfg11
uint8_t radio_cfg11
Definition: adf7023.h:326
MCR_REG_INTERRUPT_SOURCE_0
#define MCR_REG_INTERRUPT_SOURCE_0
Definition: adf7023.h:272
adf7023_transmit_packet
void adf7023_transmit_packet(struct adf7023_dev *dev, uint8_t *packet, uint8_t length)
Transmits one packet.
Definition: adf7023.c:313
adf7023_bbram::testmodes
uint8_t testmodes
Definition: adf7023.h:360
adf7023_bbram::interrupt_mask1
uint8_t interrupt_mask1
Definition: adf7023.h:304
adf7023_get_ram
void adf7023_get_ram(struct adf7023_dev *dev, uint32_t address, uint32_t length, uint8_t *data)
Reads data from the RAM.
Definition: adf7023.c:236
adf7023_bbram::address_filtering8
uint8_t address_filtering8
Definition: adf7023.h:354
no_os_gpio_remove
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:95
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
adf7023_bbram::radio_cfg0
uint8_t radio_cfg0
Definition: adf7023.h:315
adf7023_bbram::channel_freq1
uint8_t channel_freq1
Definition: adf7023.h:313
CMD_PHY_SLEEP
#define CMD_PHY_SLEEP
Definition: adf7023.h:82
adf7023_bbram::number_of_wakeups_irq_threshold1
uint8_t number_of_wakeups_irq_threshold1
Definition: adf7023.h:308
adf7023_bbram::rx_dwell_time
uint8_t rx_dwell_time
Definition: adf7023.h:309
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
adf7023_dev
Definition: adf7023.h:376
adf7023_bbram::address_filtering0
uint8_t address_filtering0
Definition: adf7023.h:346
adf7023_bbram::transition_clock_div
uint8_t transition_clock_div
Definition: adf7023.h:361
adf7023_dev::spi_desc
no_os_spi_desc * spi_desc
Definition: adf7023.h:378
no_os_gpio_get
int32_t no_os_gpio_get(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Obtain the GPIO decriptor.
Definition: no_os_gpio.c:55
adf7023_bbram::number_of_wakeups1
uint8_t number_of_wakeups1
Definition: adf7023.h:306
adf7023_bbram::static_reg_fix
uint8_t static_reg_fix
Definition: adf7023.h:343
adf7023_get_ram
void adf7023_get_ram(struct adf7023_dev *dev, uint32_t address, uint32_t length, uint8_t *data)
Reads data from the RAM.
Definition: adf7023.c:236
adf7023_bbram_default
struct adf7023_bbram adf7023_bbram_default
Definition: adf7023_config.h:51
adf7023_bbram::radio_cfg10
uint8_t radio_cfg10
Definition: adf7023.h:325
adf7023_bbram::reserved0
uint8_t reserved0
Definition: adf7023.h:362
adf7023_dev::gpio_cs
struct no_os_gpio_desc * gpio_cs
Definition: adf7023.h:380
adf7023_receive_packet
void adf7023_receive_packet(struct adf7023_dev *dev, uint8_t *packet, uint8_t *length)
Receives one packet.
Definition: adf7023.c:284
adf7023_bbram::radio_cfg9
uint8_t radio_cfg9
Definition: adf7023.h:324
adf7023_bbram::sync_byte2
uint8_t sync_byte2
Definition: adf7023.h:338
adf7023_bbram::radio_cfg3
uint8_t radio_cfg3
Definition: adf7023.h:318
CMD_PHY_OFF
#define CMD_PHY_OFF
Definition: adf7023.h:78
adf7023_set_ram
void adf7023_set_ram(struct adf7023_dev *dev, uint32_t address, uint32_t length, uint8_t *data)
Writes data to RAM.
Definition: adf7023.c:261
adf7023_get_status
void adf7023_get_status(struct adf7023_dev *dev, uint8_t *status)
Reads the status word of the ADF7023.
Definition: adf7023.c:167
adf7023_bbram::channel_freq0
uint8_t channel_freq0
Definition: adf7023.h:312
adf7023_bbram::address_filtering5
uint8_t address_filtering5
Definition: adf7023.h:351
adf7023_remove
int32_t adf7023_remove(struct adf7023_dev *dev)
Free the resources allocated by adf7023_init().
Definition: adf7023.c:145
adf7023_init_param::spi_init
no_os_spi_init_param spi_init
Definition: adf7023.h:388
adf7023_init_param::gpio_cs
struct no_os_gpio_init_param gpio_cs
Definition: adf7023.h:390
adf7023_bbram::number_of_wakeups_irq_threshold0
uint8_t number_of_wakeups_irq_threshold0
Definition: adf7023.h:307
adf7023_set_ram
void adf7023_set_ram(struct adf7023_dev *dev, uint32_t address, uint32_t length, uint8_t *data)
Writes data to RAM.
Definition: adf7023.c:261
STATUS_FW_STATE
#define STATUS_FW_STATE
Definition: adf7023.h:53
adf7023_bbram::tx_base_adr
uint8_t tx_base_adr
Definition: adf7023.h:339
adf7023_bbram::interrupt_mask0
uint8_t interrupt_mask0
Definition: adf7023.h:303
adf7023_set_channel_frequency
void adf7023_set_channel_frequency(struct adf7023_dev *dev, uint32_t ch_freq)
Sets the channel frequency.
Definition: adf7023.c:341
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
adf7023_set_data_rate
void adf7023_set_data_rate(struct adf7023_dev *dev, uint32_t data_rate)
Sets the data rate.
Definition: adf7023.c:359
adf7023_bbram::radio_cfg8
uint8_t radio_cfg8
Definition: adf7023.h:323
FW_STATE_PHY_TX
#define FW_STATE_PHY_TX
Definition: adf7023.h:61
adf7023_bbram::symbol_mode
uint8_t symbol_mode
Definition: adf7023.h:331
adf7023_bbram::address_filtering11
uint8_t address_filtering11
Definition: adf7023.h:357
adf7023_bbram::address_filtering3
uint8_t address_filtering3
Definition: adf7023.h:349
adf7023_bbram::rssi_wait_time
uint8_t rssi_wait_time
Definition: adf7023.h:359
CMD_CONFIG_DEV
#define CMD_CONFIG_DEV
Definition: adf7023.h:83
adf7023_bbram::address_filtering7
uint8_t address_filtering7
Definition: adf7023.h:353
adf7023_receive_packet
void adf7023_receive_packet(struct adf7023_dev *dev, uint8_t *packet, uint8_t *length)
Receives one packet.
Definition: adf7023.c:284
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
adf7023_bbram
Definition: adf7023.h:302
adf7023_bbram::address_filtering6
uint8_t address_filtering6
Definition: adf7023.h:352
no_os_gpio.h
Header file of GPIO Interface.
adf7023_bbram::radio_cfg7
uint8_t radio_cfg7
Definition: adf7023.h:322
adf7023_bbram::address_length
uint8_t address_length
Definition: adf7023.h:345
adf7023_init
int32_t adf7023_init(struct adf7023_dev **device, struct adf7023_init_param init_param)
Initializes the ADF7023.
Definition: adf7023.c:94
BBRAM_RADIO_CFG_1_DATA_RATE_11_8
#define BBRAM_RADIO_CFG_1_DATA_RATE_11_8(x)
Definition: adf7023.h:185
adf7023_dev::gpio_miso
struct no_os_gpio_desc * gpio_miso
Definition: adf7023.h:381
SPI_MEM_WR
#define SPI_MEM_WR
Definition: adf7023.h:70
adf7023_bbram::crc_poly1
uint8_t crc_poly1
Definition: adf7023.h:334
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
CMD_PHY_ON
#define CMD_PHY_ON
Definition: adf7023.h:79
adf7023_bbram::radio_cfg2
uint8_t radio_cfg2
Definition: adf7023.h:317
adf7023_init
int32_t adf7023_init(struct adf7023_dev **device, struct adf7023_init_param init_param)
Initializes the ADF7023.
Definition: adf7023.c:94
STATUS_CMD_READY
#define STATUS_CMD_READY
Definition: adf7023.h:52
SPI_NOP
#define SPI_NOP
Definition: adf7023.h:74
no_os_gpio_direction_output
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:124
adf7023_bbram::packet_length_control
uint8_t packet_length_control
Definition: adf7023.h:341
adf7023_bbram::radio_cfg1
uint8_t radio_cfg1
Definition: adf7023.h:316
adf7023_set_command
void adf7023_set_command(struct adf7023_dev *dev, uint8_t command)
Initiates a command.
Definition: adf7023.c:184
adf7023_bbram::address_filtering2
uint8_t address_filtering2
Definition: adf7023.h:348
adf7023_bbram::image_reject_cal_amplitude
uint8_t image_reject_cal_amplitude
Definition: adf7023.h:328
adf7023_set_frequency_deviation
void adf7023_set_frequency_deviation(struct adf7023_dev *dev, uint32_t freq_dev)
Sets the frequency deviation.
Definition: adf7023.c:381
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
adf7023_bbram::preamble_len
uint8_t preamble_len
Definition: adf7023.h:332
adf7023_bbram::sync_byte1
uint8_t sync_byte1
Definition: adf7023.h:337