no-OS
adpd188.h
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1 /***************************************************************************/
40 #ifndef ADPD188_H_
41 #define ADPD188_H_
42 
43 /******************************************************************************/
44 /***************************** Include Files **********************************/
45 /******************************************************************************/
46 
47 #include <stdint.h>
48 #include <stdbool.h>
49 #include "no_os_i2c.h"
50 #include "no_os_spi.h"
51 #include "no_os_gpio.h"
52 
53 /******************************************************************************/
54 /********************** Macros and Constants Definitions **********************/
55 /******************************************************************************/
56 
57 #define ADPD188_REG_STATUS 0x00
58 #define ADPD188_REG_INT_MASK 0x01
59 #define ADPD188_REG_GPIO_DRV 0x02
60 #define ADPD188_REG_BG_STATUS 0x04
61 #define ADPD188_REG_FIFO_THRESH 0x06
62 #define ADPD188_REG_DEVID 0x08
63 #define ADPD188_REG_I2CS_ID 0x09
64 #define ADPD188_REG_CLK_RATIO 0x0A
65 #define ADPD188_REG_GPIO_CTRL 0x0B
66 #define ADPD188_REG_SLAVE_ADDR_KEY 0x0D
67 #define ADPD188_REG_SW_RESET 0x0F
68 #define ADPD188_REG_MODE 0x10
69 #define ADPD188_REG_SLOT_EN 0x11
70 #define ADPD188_REG_FSAMPLE 0x12
71 #define ADPD188_REG_PD_LED_SELECT 0x14
72 #define ADPD188_REG_NUM_AVG 0x15
73 #define ADPD188_REG_BG_MEAS_A 0x16
74 #define ADPD188_REG_INT_SEQ_A 0x17
75 #define ADPD188_REG_SLOTA_CH1_OFFSET 0x18
76 #define ADPD188_REG_SLOTA_CH2_OFFSET 0x19
77 #define ADPD188_REG_SLOTA_CH3_OFFSET 0x1A
78 #define ADPD188_REG_SLOTA_CH4_OFFSET 0x1B
79 #define ADPD188_REG_BG_MEAS_B 0x1C
80 #define ADPD188_REG_INT_SEQ_B 0x1D
81 #define ADPD188_REG_SLOTB_CH1_OFFSET 0x1E
82 #define ADPD188_REG_SLOTB_CH2_OFFSET 0x1F
83 #define ADPD188_REG_SLOTB_CH3_OFFSET 0x20
84 #define ADPD188_REG_SLOTB_CH4_OFFSET 0x21
85 #define ADPD188_REG_ILED3_COARSE 0x22
86 #define ADPD188_REG_ILED1_COARSE 0x23
87 #define ADPD188_REG_ILED2_COARSE 0x24
88 #define ADPD188_REG_ILED_FINE 0x25
89 #define ADPD188_REG_SLOTA_LED_PULSE 0x30
90 #define ADPD188_REG_SLOTA_NUMPULSES 0x31
91 #define ADPD188_REG_LED_DISABLE 0x34
92 #define ADPD188_REG_SLOTB_LED_PULSE 0x35
93 #define ADPD188_REG_SLOTB_NUMPULSES 0x36
94 #define ADPD188_REG_ALT_PWR_DN 0x37
95 #define ADPD188_REG_EXT_SYNC_STARTUP 0x38
96 #define ADPD188_REG_SLOTA_AFE_WINDOW 0x39
97 #define ADPD188_REG_SLOTB_AFE_WINDOW 0x3B
98 #define ADPD188_REG_AFE_PWR_CFG1 0x3C
99 #define ADPD188_REG_SLOTA_FLOAT_LED 0x3E
100 #define ADPD188_REG_SLOTB_FLOAT_LED 0x3F
101 #define ADPD188_REG_SLOTA_TIA_CFG 0x42
102 #define ADPD188_REG_SLOTA_AFE_CFG 0x43
103 #define ADPD188_REG_SLOTB_TIA_CFG 0x44
104 #define ADPD188_REG_SLOTB_AFE_CFG 0x45
105 #define ADPD188_REG_SAMPLE_CLK 0x4B
106 #define ADPD188_REG_CLK32M_ADJUST 0x4D
107 #define ADPD188_REG_EXT_SYNC_SEL 0x4F
108 #define ADPD188_REG_CLK32M_CAL_EN 0x50
109 #define ADPD188_REG_AFE_PWR_CFG2 0x54
110 #define ADPD188_REG_TIA_INDEP_GAIN 0x55
111 #define ADPD188_REG_MATH 0x58
112 #define ADPD188_REG_FLT_CONFIG_B 0x59
113 #define ADPD188_REG_FLT_LED_FIRE 0x5A
114 #define ADPD188_REG_FLT_CONFIG_A 0x5E
115 #define ADPD188_REG_DATA_ACCESS_CTL 0x5F
116 #define ADPD188_REG_FIFO_ACCESS 0x60
117 #define ADPD188_REG_SLOTA_PD1_16BIT 0x64
118 #define ADPD188_REG_SLOTA_PD2_16BIT 0x65
119 #define ADPD188_REG_SLOTA_PD3_16BIT 0x66
120 #define ADPD188_REG_SLOTA_PD4_16BIT 0x67
121 #define ADPD188_REG_SLOTB_PD1_16BIT 0x68
122 #define ADPD188_REG_SLOTB_PD2_16BIT 0x69
123 #define ADPD188_REG_SLOTB_PD3_16BIT 0x6A
124 #define ADPD188_REG_SLOTB_PD4_16BIT 0x6B
125 #define ADPD188_REG_A_PD1_LOW 0x70
126 #define ADPD188_REG_A_PD2_LOW 0x71
127 #define ADPD188_REG_A_PD3_LOW 0x72
128 #define ADPD188_REG_A_PD4_LOW 0x73
129 #define ADPD188_REG_A_PD1_HIGH 0x74
130 #define ADPD188_REG_A_PD2_HIGH 0x75
131 #define ADPD188_REG_A_PD3_HIGH 0x76
132 #define ADPD188_REG_A_PD4_HIGH 0x77
133 #define ADPD188_REG_B_PD1_LOW 0x78
134 #define ADPD188_REG_B_PD2_LOW 0x79
135 #define ADPD188_REG_B_PD3_LOW 0x7A
136 #define ADPD188_REG_B_PD4_LOW 0x7B
137 #define ADPD188_REG_B_PD1_HIGH 0x7C
138 #define ADPD188_REG_B_PD2_HIGH 0x7D
139 #define ADPD188_REG_B_PD3_HIGH 0x7E
140 #define ADPD188_REG_B_PD4_HIGH 0x7F
141 
142 /* ADPD188_REG_STATUS */
143 #define ADPD188_STATUS_FIFO_SAMPLES_MASK 0xFF00
144 #define ADPD188_STATUS_SLOTB_INT_MASK 0x0040
145 #define ADPD188_STATUS_SLOTA_INT_MASK 0x0020
146 #define ADPD188_STATUS_FIFO_SAMPLES_POS 8
147 #define ADPD188_STATUS_SLOTB_INT_POS 6
148 #define ADPD188_STATUS_SLOTA_INT_POS 5
149 
150 /* ADPD188_REG_INT_MASK */
151 #define ADPD188_INT_MASK_FIFO_INT_MASK_MASK 0x0100
152 #define ADPD188_INT_MASK_SLOTB_INT_MASK_MASK 0x0040
153 #define ADPD188_INT_MASK_SLOTA_INT_MASK_MASK 0x0020
154 #define ADPD188_INT_MASK_FIFO_INT_MASK_POS 8
155 #define ADPD188_INT_MASK_SLOTB_INT_MASK_POS 6
156 #define ADPD188_INT_MASK_SLOTA_INT_MASK_POS 5
157 
158 /* ADPD188_REG_GPIO_DRV */
159 #define ADPD188_GPIO_DRV_GPIO1_DRV_MASK 0x0200
160 #define ADPD188_GPIO_DRV_GPIO1_POL_MASK 0x0100
161 #define ADPD188_GPIO_DRV_GPIO0_ENA_MASK 0x0004
162 #define ADPD188_GPIO_DRV_GPIO0_DRV_MASK 0x0002
163 #define ADPD188_GPIO_DRV_GPIO0_POL_MASK 0x0001
164 #define ADPD188_GPIO_DRV_GPIO1_DRV_POS 9
165 #define ADPD188_GPIO_DRV_GPIO1_POL_POS 8
166 #define ADPD188_GPIO_DRV_GPIO0_ENA_POS 2
167 #define ADPD188_GPIO_DRV_GPIO0_DRV_POS 1
168 #define ADPD188_GPIO_DRV_GPIO0_POL_POS 0
169 
170 /* ADPD188_REG_BG_STATUS */
171 #define ADPD188_BG_STATUS_BG_STATUS_B_MASK 0x00F0
172 #define ADPD188_BG_STATUS_BG_STATUS_A_MASK 0x000F
173 #define ADPD188_BG_STATUS_BG_STATUS_B_POS 4
174 #define ADPD188_BG_STATUS_BG_STATUS_A_POS 0
175 
176 /* ADPD188_REG_FIFO_THRESH */
177 #define ADPD188_FIFO_THRESH_FIFO_THRESH_MASK 0x3F00
178 #define ADPD188_FIFO_THRESH_FIFO_THRESH_POS 8
179 #define ADPD188_FIFO_THRESH_MAX_THRESHOLD 63
180 
181 /* ADPD188_REG_DEVID */
182 #define ADPD188_DEVID_REV_NUM_MASK 0xFF00
183 #define ADPD188_DEVID_DEV_ID_MASK 0x00FF
184 #define ADPD188_DEVID_REV_NUM_POS 8
185 #define ADPD188_DEVID_DEV_ID_POS 0
186 /* ADPD188BI specific */
187 #define ADPD188_DEVICE_ID 0x0916
188 /* ADPD108X specific */
189 #define ADPD108X_DEVICE_ID 0x0A16
190 
191 /* ADPD188_REG_I2CS_ID */
192 #define ADPD188_I2CS_ID_ADDRESS_WRITE_KEY_MASK 0xFF00
193 #define ADPD188_I2CS_ID_SLAVE_ADDRESS_MASK 0x00FE
194 #define ADPD188_I2CS_ID_ADDRESS_WRITE_KEY_POS 8
195 #define ADPD188_I2CS_ID_SLAVE_ADDRESS_POS 1
196 
197 /* ADPD188_REG_CLK_RATIO */
198 #define ADPD188_CLK_RATIO_CLK_RATIO_MASK 0x0FFF
199 #define ADPD188_CLK_RATIO_CLK_RATIO_POS 0
200 
201 /* ADPD188_REG_GPIO_CTRL */
202 #define ADPD188_GPIO_CTRL_GPIO1_ALT_CFG_MASK 0x1F00
203 #define ADPD188_GPIO_CTRL_GPIO0_ALT_CFG_MASK 0x001F
204 #define ADPD188_GPIO_CTRL_GPIO1_ALT_CFG_POS 8
205 #define ADPD188_GPIO_CTRL_GPIO0_ALT_CFG_POS 0
206 
207 /* ADPD188_REG_SW_RESET */
208 #define ADPD188_SW_RESET_SW_RESET_MASK 0x0001
209 #define ADPD188_SW_RESET_SW_RESET_POS 0
210 
211 /* ADPD188_REG_MODE */
212 #define ADPD188_MODE_MODE_MASK 0x0003
213 #define ADPD188_MODE_MODE_POS 0
214 
215 /* ADPD188_REG_SLOT_EN */
216 #define ADPD188_SLOT_EN_RDOUT_MODE_MASK 0x2000
217 #define ADPD188_SLOT_EN_FIFO_OVRN_PREVENT_MASK 0x1000
218 #define ADPD188_SLOT_EN_SLOTB_FIFO_MODE_MASK 0x01C0
219 #define ADPD188_SLOT_EN_SLOTB_EN_MASK 0x0020
220 #define ADPD188_SLOT_EN_SLOTA_FIFO_MODE_MASK 0x001C
221 #define ADPD188_SLOT_EN_SLOTA_EN_MASK 0x0001
222 #define ADPD188_SLOT_EN_RDOUT_MODE_POS 13
223 #define ADPD188_SLOT_EN_FIFO_OVRN_PREVENT_POS 12
224 #define ADPD188_SLOT_EN_SLOTB_FIFO_MODE_POS 6
225 #define ADPD188_SLOT_EN_SLOTB_EN_POS 5
226 #define ADPD188_SLOT_EN_SLOTA_FIFO_MODE_POS 2
227 #define ADPD188_SLOT_EN_SLOTA_EN_POS 0
228 
229 /* ADPD188_REG_PD_LED_SELECT */
230 #define ADPD188_PD_LED_SELECT_SLOTB_PD_SEL_MASK 0x0F00
231 #define ADPD188_PD_LED_SELECT_SLOTA_PD_SEL_MASK 0x00F0
232 #define ADPD188_PD_LED_SELECT_SLOTB_LED_SEL_MASK 0x000C
233 #define ADPD188_PD_LED_SELECT_SLOTA_LED_SEL_MASK 0x0003
234 #define ADPD188_PD_LED_SELECT_SLOTB_PD_SEL_POS 8
235 #define ADPD188_PD_LED_SELECT_SLOTA_PD_SEL_POS 4
236 #define ADPD188_PD_LED_SELECT_SLOTB_LED_SEL_POS 2
237 #define ADPD188_PD_LED_SELECT_SLOTA_LED_SEL_POS 0
238 
239 /* ADPD188_REG_NUM_AVG */
240 #define ADPD188_NUM_AVG_SLOTB_NUM_AVG_MASK 0x0700
241 #define ADPD188_NUM_AVG_SLOTA_NUM_AVG_MASK 0x0070
242 #define ADPD188_NUM_AVG_SLOTB_NUM_AVG_POS 8
243 #define ADPD188_NUM_AVG_SLOTA_NUM_AVG_POS 4
244 
245 /* ADPD188_REG_BG_MEAS_A */
246 #define ADPD188_BG_MEAS_A_BG_COUNT_A_MASK 0xC000
247 #define ADPD188_BG_MEAS_A_BG_THRESH_A_MASK 0x3FFF
248 #define ADPD188_BG_MEAS_A_BG_COUNT_A_POS 14
249 #define ADPD188_BG_MEAS_A_BG_THRESH_A_POS 0
250 
251 /* ADPD188_REG_INT_SEQ_A */
252 #define ADPD188_INT_SEQ_A_INTEG_ORDER_A_MASK 0x000F
253 #define ADPD188_INT_SEQ_A_INTEG_ORDER_A_POS 0
254 
255 /* ADPD188_REG_BG_MEAS_B */
256 #define ADPD188_BG_MEAS_B_BG_COUNT_B_MASK 0xC000
257 #define ADPD188_BG_MEAS_B_BG_THRESH_B_MASK 0x3FFF
258 #define ADPD188_BG_MEAS_B_BG_COUNT_B_POS 14
259 #define ADPD188_BG_MEAS_B_BG_THRESH_B_POS 0
260 
261 /* ADPD188_REG_INT_SEQ_B */
262 #define ADPD188_INT_SEQ_B_INTEG_ORDER_B_MASK 0x000F
263 #define ADPD188_INT_SEQ_B_INTEG_ORDER_B_POS 0
264 
265 /* ADPD188_REG_ILED3_COARSE */
266 #define ADPD188_ILED3_COARSE_ILED3_SCALE_MASK 0x2000
267 #define ADPD188_ILED3_COARSE_ILED3_SLEW_MASK 0x0070
268 #define ADPD188_ILED3_COARSE_ILED3_COARSE_MASK 0x000F
269 #define ADPD188_ILED3_COARSE_ILED3_SCALE_POS 13
270 #define ADPD188_ILED3_COARSE_ILED3_SLEW_POS 4
271 #define ADPD188_ILED3_COARSE_ILED3_COARSE_POS 0
272 
273 /* ADPD188_REG_ILED1_COARSE */
274 #define ADPD188_ILED1_COARSE_ILED1_SCALE_MASK 0x2000
275 #define ADPD188_ILED1_COARSE_ILED1_SLEW_MASK 0x0070
276 #define ADPD188_ILED1_COARSE_ILED1_COARSE_MASK 0x000F
277 #define ADPD188_ILED1_COARSE_ILED1_SCALE_POS 13
278 #define ADPD188_ILED1_COARSE_ILED1_SLEW_POS 4
279 #define ADPD188_ILED1_COARSE_ILED1_COARSE_POS 0
280 
281 /* ADPD188_REG_ILED2_COARSE */
282 #define ADPD188_ILED2_COARSE_ILED2_SCALE_MASK 0x2000
283 #define ADPD188_ILED2_COARSE_ILED2_SLEW_MASK 0x0070
284 #define ADPD188_ILED2_COARSE_ILED2_COARSE_MASK 0x000F
285 #define ADPD188_ILED2_COARSE_ILED2_SCALE_POS 13
286 #define ADPD188_ILED2_COARSE_ILED2_SLEW_POS 4
287 #define ADPD188_ILED2_COARSE_ILED2_COARSE_POS 0
288 
289 /* ADPD188_REG_ILED_FINE */
290 #define ADPD188_ILED_FINE_ILED3_FINE_MASK 0xF800
291 #define ADPD188_ILED_FINE_ILED2_FINE_MASK 0x07C0
292 #define ADPD188_ILED_FINE_ILED1_FINE_MASK 0x001F
293 #define ADPD188_ILED_FINE_ILED3_FINE_POS 11
294 #define ADPD188_ILED_FINE_ILED2_FINE_POS 6
295 #define ADPD188_ILED_FINE_ILED1_FINE_POS 0
296 
297 /* ADPD188_REG_SLOTA_LED_PULSE */
298 #define ADPD188_SLOTA_LED_PULSE_SLOTA_LED_WIDTH_MASK 0x1F00
299 #define ADPD188_SLOTA_LED_PULSE_SLOTA_LED_OFFSET_MASK 0x00FF
300 #define ADPD188_SLOTA_LED_PULSE_SLOTA_LED_WIDTH_POS 8
301 #define ADPD188_SLOTA_LED_PULSE_SLOTA_LED_OFFSET_POS 0
302 
303 /* ADPD188_REG_SLOTA_NUMPULSES */
304 #define ADPD188_SLOTA_NUMPULSES_SLOTA_PULSES_MASK 0xFF00
305 #define ADPD188_SLOTA_NUMPULSES_SLOTA_PERIOD_MASK 0x00FF
306 #define ADPD188_SLOTA_NUMPULSES_SLOTA_PULSES_POS 8
307 #define ADPD188_SLOTA_NUMPULSES_SLOTA_PERIOD_POS 0
308 
309 /* ADPD188_REG_LED_DISABLE */
310 #define ADPD188_LED_DISABLE_SLOTB_LED_DIS_MASK 0x0200
311 #define ADPD188_LED_DISABLE_SLOTA_LED_DIS_MASK 0x0100
312 #define ADPD188_LED_DISABLE_SLOTB_LED_DIS_POS 9
313 #define ADPD188_LED_DISABLE_SLOTA_LED_DIS_POS 8
314 
315 /* ADPD188_REG_SLOTB_LED_PULSE */
316 #define ADPD188_SLOTB_LED_PULSE_SLOTB_LED_WIDTH_MASK 0x1F00
317 #define ADPD188_SLOTB_LED_PULSE_SLOTB_LED_OFFSET_MASK 0x00FF
318 #define ADPD188_SLOTB_LED_PULSE_SLOTB_LED_WIDTH_POS 8
319 #define ADPD188_SLOTB_LED_PULSE_SLOTB_LED_OFFSET_POS 0
320 
321 /* ADPD188_REG_SLOTB_NUMPULSES */
322 #define ADPD188_SLOTB_NUMPULSES_SLOTB_PULSES_MASK 0xFF00
323 #define ADPD188_SLOTB_NUMPULSES_SLOTB_PERIOD_MASK 0x00FF
324 #define ADPD188_SLOTB_NUMPULSES_SLOTB_PULSES_POS 8
325 #define ADPD188_SLOTB_NUMPULSES_SLOTB_PERIOD_POS 0
326 
327 /* ADPD188_REG_ALT_PWR_DN */
328 #define ADPD188_ALT_PWR_DN_CH34_DISABLE_MASK 0xE000
329 #define ADPD188_ALT_PWR_DN_CH2_DISABLE_MASK 0x1C00
330 #define ADPD188_ALT_PWR_DN_SLOTB_PERIOD_MASK 0x0300
331 #define ADPD188_ALT_PWR_DN_SLOTA_PERIOD_MASK 0x0003
332 #define ADPD188_ALT_PWR_DN_CH34_DISABLE_POS 13
333 #define ADPD188_ALT_PWR_DN_CH2_DISABLE_POS 10
334 #define ADPD188_ALT_PWR_DN_SLOTB_PERIOD_POS 8
335 #define ADPD188_ALT_PWR_DN_SLOTA_PERIOD_POS 0
336 
337 /* ADPD188_REG_SLOTA_AFE_WINDOW */
338 #define ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_WIDTH_MASK 0xF800
339 #define ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_OFFSET_MASK 0x07FF
340 #define ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_WIDTH_POS 11
341 #define ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_OFFSET_POS 0
342 
343 /* ADPD188_REG_SLOTB_AFE_WINDOW */
344 #define ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_WIDTH_MASK 0xF800
345 #define ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_OFFSET_MASK 0x07FF
346 #define ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_WIDTH_POS 11
347 #define ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_OFFSET_POS 0
348 
349 /* ADPD188_REG_AFE_PWR_CFG1 */
350 #define ADPD188_AFE_PWR_CFG1_V_CATHODE_MASK 0x0200
351 #define ADPD188_AFE_PWR_CFG1_AFE_POWERDOWN_MASK 0x01F8
352 #define ADPD188_AFE_PWR_CFG1_V_CATHODE_POS 9
353 #define ADPD188_AFE_PWR_CFG1_AFE_POWERDOWN_POS 3
354 
355 /* ADPD188_REG_SLOTA_FLOAT_LED */
356 #define ADPD188_SLOTA_FLOAT_LED_FLT_LED_SELECT_A_MASK 0xC000
357 #define ADPD188_SLOTA_FLOAT_LED_FLT_LED_WIDTH_A_MASK 0x1F00
358 #define ADPD188_SLOTA_FLOAT_LED_FLT_LED_OFFSET_A_MASK 0x00FF
359 #define ADPD188_SLOTA_FLOAT_LED_FLT_LED_SELECT_A_POS 14
360 #define ADPD188_SLOTA_FLOAT_LED_FLT_LED_WIDTH_A_POS 8
361 #define ADPD188_SLOTA_FLOAT_LED_FLT_LED_OFFSET_A_POS 0
362 
363 /* ADPD188_REG_SLOTB_FLOAT_LED */
364 #define ADPD188_SLOTB_FLOAT_LED_FLT_LED_SELECT_B_MASK 0xC000
365 #define ADPD188_SLOTB_FLOAT_LED_FLT_LED_WIDTH_B_MASK 0x1F00
366 #define ADPD188_SLOTB_FLOAT_LED_FLT_LED_OFFSET_B_MASK 0x00FF
367 #define ADPD188_SLOTB_FLOAT_LED_FLT_LED_SELECT_B_POS 14
368 #define ADPD188_SLOTB_FLOAT_LED_FLT_LED_WIDTH_B_POS 8
369 #define ADPD188_SLOTB_FLOAT_LED_FLT_LED_OFFSET_B_POS 0
370 
371 /* ADPD188_REG_SLOTA_TIA_CFG */
372 /* ADPD188BI specific registers */
373 #define ADPD188_SLOTA_TIA_CFG_SLOTA_BUF_GAIN_MASK 0x0200
374 #define ADPD188_SLOTA_TIA_CFG_SLOTA_BUF_GAIN_POS 9
375 /* ADPD108X specific registers */
376 #define ADPD108X_SLOTA_TIA_CFG_SLOTA_BUF_GAIN_MASK 0x0300
377 #define ADPD108X_SLOTA_TIA_CFG_SLOTA_INT_GAIN_POS 8
378 /* ADPD188_REG_SLOTA_TIA_CFG common registers */
379 #define ADPD188_SLOTA_TIA_CFG_SLOTA_AFE_MODE_MASK 0xFC00
380 #define ADPD188_SLOTA_TIA_CFG_SLOTA_INT_AS_BUF_MASK 0x0080
381 #define ADPD188_SLOTA_TIA_CFG_SLOTA_TIA_IND_EN_MASK 0x0040
382 #define ADPD188_SLOTA_TIA_CFG_SLOTA_TIA_VREF_MASK 0x0030
383 #define ADPD188_SLOTA_TIA_CFG_SLOTA_TIA_GAIN_MASK 0x0003
384 #define ADPD188_SLOTA_TIA_CFG_SLOTA_AFE_MODE_POS 10
385 #define ADPD188_SLOTA_TIA_CFG_SLOTA_INT_AS_BUF_POS 7
386 #define ADPD188_SLOTA_TIA_CFG_SLOTA_TIA_IND_EN_POS 6
387 #define ADPD188_SLOTA_TIA_CFG_SLOTA_TIA_VREF_POS 4
388 #define ADPD188_SLOTA_TIA_CFG_SLOTA_TIA_GAIN_POS 0
389 
390 /* ADPD188_REG_SLOTB_TIA_CFG */
391 /* ADPD188BI specific registers */
392 #define ADPD188_SLOTB_TIA_CFG_SLOTA_BUF_GAIN_MASK 0x0200
393 #define ADPD188_SLOTB_TIA_CFG_SLOTA_BUF_GAIN_POS 9
394 /* ADPD108X specific registers */
395 #define ADPD108X_SLOTB_TIA_CFG_SLOTA_BUF_GAIN_MASK 0x0300
396 #define ADPD108X_SLOTB_TIA_CFG_SLOTA_INT_GAIN_POS 8
397 /* ADPD188_REG_SLOTA_TIA_CFG common registers */
398 #define ADPD188_SLOTB_TIA_CFG_SLOTB_AFE_MODE_MASK 0xFC00
399 #define ADPD188_SLOTB_TIA_CFG_SLOTB_INT_AS_BUF_MASK 0x0080
400 #define ADPD188_SLOTB_TIA_CFG_SLOTB_TIA_IND_EN_MASK 0x0040
401 #define ADPD188_SLOTB_TIA_CFG_SLOTB_TIA_VREF_MASK 0x0030
402 #define ADPD188_SLOTB_TIA_CFG_SLOTB_TIA_GAIN_MASK 0x0003
403 #define ADPD188_SLOTB_TIA_CFG_SLOTB_AFE_MODE_POS 10
404 #define ADPD188_SLOTB_TIA_CFG_SLOTB_INT_AS_BUF_POS 7
405 #define ADPD188_SLOTB_TIA_CFG_SLOTB_TIA_IND_EN_POS 6
406 #define ADPD188_SLOTB_TIA_CFG_SLOTB_TIA_VREF_POS 4
407 #define ADPD188_SLOTB_TIA_CFG_SLOTB_TIA_GAIN_POS 0
408 
409 /* ADPD188_REG_SAMPLE_CLK */
410 #define ADPD188_SAMPLE_CLK_CLK32K_BYP_MASK 0x0100
411 #define ADPD188_SAMPLE_CLK_CLK32K_EN_MASK 0x0080
412 #define ADPD188_SAMPLE_CLK_CLK32K_ADJUST_MASK 0x003F
413 #define ADPD188_SAMPLE_CLK_CLK32K_BYP_POS 8
414 #define ADPD188_SAMPLE_CLK_CLK32K_EN_POS 7
415 #define ADPD188_SAMPLE_CLK_CLK32K_ADJUST_POS 0
416 
417 /* ADPD188_REG_CLK32M_ADJUST */
418 #define ADPD188_CLK32M_ADJUST_CLK32M_ADJUST_MASK 0x00FF
419 #define ADPD188_CLK32M_ADJUST_CLK32M_ADJUST_POS 0
420 
421 /* ADPD188_REG_EXT_SYNC_SEL */
422 #define ADPD188_EXT_SYNC_SEL_GPIO1_OE_MASK 0x0040
423 #define ADPD188_EXT_SYNC_SEL_GPIO1_IE_MASK 0x0020
424 #define ADPD188_EXT_SYNC_SEL_EXT_SYNC_SEL_MASK 0x000C
425 #define ADPD188_EXT_SYNC_SEL_GPIO0_IE_MASK 0x0002
426 #define ADPD188_EXT_SYNC_SEL_GPIO1_OE_POS 6
427 #define ADPD188_EXT_SYNC_SEL_GPIO1_IE_POS 5
428 #define ADPD188_EXT_SYNC_SEL_EXT_SYNC_SEL_POS 2
429 #define ADPD188_EXT_SYNC_SEL_GPIO0_IE_POS 1
430 
431 /* ADPD188_REG_CLK32M_CAL_EN */
432 #define ADPD188_CLK32M_CAL_EN_GPIO1_CTRL_MASK 0x0040
433 #define ADPD188_CLK32M_CAL_EN_CLK32M_CAL_EN_MASK 0x0020
434 #define ADPD188_CLK32M_CAL_EN_GPIO1_CTRL_POS 6
435 #define ADPD188_CLK32M_CAL_EN_CLK32M_CAL_EN_POS 5
436 
437 /* ADPD188_REG_AFE_PWR_CFG2 */
438 #define ADPD188_AFE_PWR_CFG2_SLEEP_V_CATHODE_MASK 0x3000
439 #define ADPD188_AFE_PWR_CFG2_SLOTB_V_CATHODE_MASK 0x0C00
440 #define ADPD188_AFE_PWR_CFG2_SLOTA_V_CATHODE_MASK 0x0300
441 #define ADPD188_AFE_PWR_CFG2_REG54_VCAT_ENABLE_MASK 0x0080
442 #define ADPD188_AFE_PWR_CFG2_SLEEP_V_CATHODE_POS 12
443 #define ADPD188_AFE_PWR_CFG2_SLOTB_V_CATHODE_POS 10
444 #define ADPD188_AFE_PWR_CFG2_SLOTA_V_CATHODE_POS 8
445 #define ADPD188_AFE_PWR_CFG2_REG54_VCAT_ENABLE_POS 7
446 
447 /* ADPD188_REG_TIA_INDEP_GAIN */
448 #define ADPD188_TIA_INDEP_GAIN_SLOTB_TIA_GAIN_4_MASK 0x0C00
449 #define ADPD188_TIA_INDEP_GAIN_SLOTB_TIA_GAIN_3_MASK 0x0300
450 #define ADPD188_TIA_INDEP_GAIN_SLOTB_TIA_GAIN_2_MASK 0x00C0
451 #define ADPD188_TIA_INDEP_GAIN_SLOTA_TIA_GAIN_4_MASK 0x0030
452 #define ADPD188_TIA_INDEP_GAIN_SLOTA_TIA_GAIN_3_MASK 0x000C
453 #define ADPD188_TIA_INDEP_GAIN_SLOTA_TIA_GAIN_2_MASK 0x0003
454 #define ADPD188_TIA_INDEP_GAIN_SLOTB_TIA_GAIN_4_POS 10
455 #define ADPD188_TIA_INDEP_GAIN_SLOTB_TIA_GAIN_3_POS 8
456 #define ADPD188_TIA_INDEP_GAIN_SLOTB_TIA_GAIN_2_POS 6
457 #define ADPD188_TIA_INDEP_GAIN_SLOTA_TIA_GAIN_4_POS 4
458 #define ADPD188_TIA_INDEP_GAIN_SLOTA_TIA_GAIN_3_POS 2
459 #define ADPD188_TIA_INDEP_GAIN_SLOTA_TIA_GAIN_2_POS 0
460 
461 /* ADPD188_REG_MATH */
462 #define ADPD188_MATH_FLT_MATH34_B_MASK 0x0C00
463 #define ADPD188_MATH_FLT_MATH34_A_MASK 0x0300
464 #define ADPD188_MATH_ENA_INT_AS_BUF_MASK 0x0080
465 #define ADPD188_MATH_FLT_MATH12_B_MASK 0x0060
466 #define ADPD188_MATH_FLT_MATH12_A_MASK 0x0006
467 #define ADPD188_MATH_FLT_MATH34_B_POS 10
468 #define ADPD188_MATH_FLT_MATH34_A_POS 8
469 #define ADPD188_MATH_ENA_INT_AS_BUF_POS 7
470 #define ADPD188_MATH_FLT_MATH12_B_POS 5
471 #define ADPD188_MATH_FLT_MATH12_A_POS 1
472 
473 /* ADPD188_REG_FLT_CONFIG_B */
474 #define ADPD188_FLT_CONFIG_B_FLT_EN_B_MASK 0x6000
475 #define ADPD188_FLT_CONFIG_B_FLT_PRECON_B_MASK 0x1F00
476 #define ADPD188_FLT_CONFIG_B_FLT_EN_B_POS 13
477 #define ADPD188_FLT_CONFIG_B_FLT_PRECON_B_POS 8
478 
479 /* ADPD188_REG_FLT_LED_FIRE */
480 #define ADPD188_FLT_LED_FIRE_FLT_LED_FIRE_B_MASK 0xF000
481 #define ADPD188_FLT_LED_FIRE_FLT_LED_FIRE_A_MASK 0x0F00
482 #define ADPD188_FLT_LED_FIRE_FLT_LED_FIRE_B_POS 12
483 #define ADPD188_FLT_LED_FIRE_FLT_LED_FIRE_A_POS 8
484 
485 /* ADPD188_REG_FLT_CONFIG_A */
486 #define ADPD188_FLT_CONFIG_A_FLT_EN_A_MASK 0x6000
487 #define ADPD188_FLT_CONFIG_A_FLT_PRECON_A_MASK 0x1F00
488 #define ADPD188_FLT_CONFIG_A_FLT_EN_A_POS 13
489 #define ADPD188_FLT_CONFIG_A_FLT_PRECON_A_POS 8
490 
491 /* ADPD188_REG_DATA_ACCESS_CTL */
492 #define ADPD188_DATA_ACCESS_CTL_SLOTB_DATA_HOLD_MASK 0x0004
493 #define ADPD188_DATA_ACCESS_CTL_SLOTA_DATA_HOLD_MASK 0x0002
494 #define ADPD188_DATA_ACCESS_CTL_DIGITAL_CLOCK_ENA_MASK 0x0001
495 #define ADPD188_DATA_ACCESS_CTL_SLOTB_DATA_HOLD_POS 2
496 #define ADPD188_DATA_ACCESS_CTL_SLOTA_DATA_HOLD_POS 1
497 #define ADPD188_DATA_ACCESS_CTL_DIGITAL_CLOCK_ENA_POS 0
498 
499 /******************************************************************************/
500 /*************************** Types Declarations *******************************/
501 /******************************************************************************/
502 
511 };
512 
523 };
524 
534 };
535 
547 };
548 
560 };
561 
568  uint8_t gpio_id;
570  uint8_t gpio_pol;
572  uint8_t gpio_drv;
574  uint8_t gpio_en;
575 };
576 
614 };
615 
625 };
626 
642 };
643 
652  bool slot_en;
655 };
656 
661 struct adpd188_dev {
667  void *phy_desc;
672 };
673 
689 };
690 
691 /******************************************************************************/
692 /************************ Functions Declarations ******************************/
693 /******************************************************************************/
694 
695 /* Initialize the ADPD188 driver. */
696 int32_t adpd188_init(struct adpd188_dev **device,
698 
699 /* Free resources allocated by adpd188_init(). */
700 int32_t adpd188_remove(struct adpd188_dev *dev);
701 
702 /* Read one 16 bit register of the ADPD188. */
703 int32_t adpd188_reg_read(struct adpd188_dev *dev, uint8_t reg_addr,
704  uint16_t *reg_val);
705 
706 /* Write one 16 bit register of the ADPD188. */
707 int32_t adpd188_reg_write(struct adpd188_dev *dev, uint8_t reg_addr,
708  uint16_t reg_val);
709 
710 /* Get the mode of operation of the ADPD188. */
711 int32_t adpd188_mode_get(struct adpd188_dev *dev, enum adpd188_mode *mode);
712 
713 /* Set the mode of operation of the ADPD188. */
714 int32_t adpd188_mode_set(struct adpd188_dev *dev, enum adpd188_mode new_mode);
715 
716 /* Get the number of bytes currently present in FIFO. */
717 int32_t adpd188_fifo_status_get(struct adpd188_dev *dev, uint8_t *bytes_no);
718 
719 /* Empty the FIFO. */
720 int32_t adpd188_fifo_clear(struct adpd188_dev *dev);
721 
722 /*
723  * Set the number of 16 bit words that need to be in the FIFO to trigger an
724  * interrupt.
725  */
726 int32_t adpd188_fifo_thresh_set(struct adpd188_dev *dev, uint8_t word_no);
727 
728 /* Get the slot and FIFO interrupt flags. */
729 int32_t adpd188_interrupt_get(struct adpd188_dev *dev, uint8_t *flags);
730 
731 /* Clear the slot and FIFO interrupt flags. */
732 int32_t adpd188_interrupt_clear(struct adpd188_dev *dev, uint8_t flags);
733 
734 /* Enable the slot and FIFO interrupt flags. */
735 int32_t adpd188_interrupt_en(struct adpd188_dev *dev, uint8_t flags);
736 
737 /* Setup drive and polarity of the GPIOs. */
738 int32_t adpd188_gpio_setup(struct adpd188_dev *dev,
739  struct adpd188_gpio_config config);
740 
741 /* Setup the GPIO source. */
742 int32_t adpd188_gpio_alt_setup(struct adpd188_dev *dev, uint8_t gpio_id,
743  enum adpd188_gpio_alt_config config);
744 
745 /* Do software reset of the device. */
746 int32_t adpd188_sw_reset(struct adpd188_dev *dev);
747 
748 /* Do internal 32MHz clock calibration. */
749 int32_t adpd188_clk32mhz_cal(struct adpd188_dev *dev);
750 
751 /* Enable slot and setup its FIFO interaction. */
752 int32_t adpd188_slot_setup(struct adpd188_dev *dev,
753  struct adpd188_slot_config config);
754 
755 /* Set sample frequency of the ADC. */
756 int32_t adpd188_adc_fsample_set(struct adpd188_dev *dev, uint16_t freq_hz);
757 
758 /* Get sample frequency of the ADC. */
759 int32_t adpd188_adc_fsample_get(struct adpd188_dev *dev, uint16_t *freq_hz);
760 
761 /* Do initial configuration of the device to use as a smoke detector. */
762 int32_t adpd188_smoke_detect_setup(struct adpd188_dev *dev);
763 
764 #endif /* ADPD188_H_ */
adpd188_interrupt
adpd188_interrupt
Interrupt flags of the ADPD188.
Definition: adpd188.h:553
ADPD188_SPI
@ ADPD188_SPI
Definition: adpd188.h:531
ADPD188_DEVICE_ID
#define ADPD188_DEVICE_ID
Definition: adpd188.h:187
ADPD188_OUT_LOW
@ ADPD188_OUT_LOW
Definition: adpd188.h:609
adpd188_dev::gpio0
struct no_os_gpio_desc * gpio0
Definition: adpd188.h:669
ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_WIDTH_MASK
#define ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_WIDTH_MASK
Definition: adpd188.h:338
ADPD188_PD_LED_SELECT_SLOTB_PD_SEL_MASK
#define ADPD188_PD_LED_SELECT_SLOTB_PD_SEL_MASK
Definition: adpd188.h:230
adpd188_adc_fsample_set
int32_t adpd188_adc_fsample_set(struct adpd188_dev *dev, uint16_t freq_hz)
Set sample frequency of the ADC.
Definition: adpd188.c:630
ADPD188_REG_DATA_ACCESS_CTL
#define ADPD188_REG_DATA_ACCESS_CTL
Definition: adpd188.h:115
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
ADPD188_FIFO_THRESH_FIFO_THRESH_POS
#define ADPD188_FIFO_THRESH_FIFO_THRESH_POS
Definition: adpd188.h:178
ADPD188_INT_MASK_FIFO_INT_MASK_MASK
#define ADPD188_INT_MASK_FIFO_INT_MASK_MASK
Definition: adpd188.h:151
ADPD188_REG_NUM_AVG
#define ADPD188_REG_NUM_AVG
Definition: adpd188.h:72
adpd188_gpio_alt_setup
int32_t adpd188_gpio_alt_setup(struct adpd188_dev *dev, uint8_t gpio_id, enum adpd188_gpio_alt_config config)
Setup the GPIO source.
Definition: adpd188.c:490
adpd188_mode
adpd188_mode
ADPD188 operation modes.
Definition: adpd188.h:540
ADPD188_STATUS_FIFO_SAMPLES_MASK
#define ADPD188_STATUS_FIFO_SAMPLES_MASK
Definition: adpd188.h:143
no_os_i2c_write
int32_t no_os_i2c_write(struct no_os_i2c_desc *desc, uint8_t *data, uint8_t bytes_number, uint8_t stop_bit)
I2C Write data to slave device.
Definition: no_os_i2c.c:85
adpd188_adc_fsample_set
int32_t adpd188_adc_fsample_set(struct adpd188_dev *dev, uint16_t freq_hz)
Set sample frequency of the ADC.
Definition: adpd188.c:630
ADPD188_SLOTB_NUMPULSES_SLOTB_PULSES_MASK
#define ADPD188_SLOTB_NUMPULSES_SLOTB_PULSES_MASK
Definition: adpd188.h:322
no_os_i2c_init
int32_t no_os_i2c_init(struct no_os_i2c_desc **desc, const struct no_os_i2c_init_param *param)
Initialize the I2C communication peripheral.
Definition: no_os_i2c.c:51
ADPD188_SLOTA_PULSE
@ ADPD188_SLOTA_PULSE
Definition: adpd188.h:592
adpd188_interrupt_clear
int32_t adpd188_interrupt_clear(struct adpd188_dev *dev, uint8_t flags)
Clear the slot and FIFO interrupt flags.
Definition: adpd188.c:383
adpd188_fifo_clear
int32_t adpd188_fifo_clear(struct adpd188_dev *dev)
Empty the FIFO.
Definition: adpd188.c:301
ADPD188_GPIO_CTRL_GPIO0_ALT_CFG_POS
#define ADPD188_GPIO_CTRL_GPIO0_ALT_CFG_POS
Definition: adpd188.h:205
ADPD188_ILED3_COARSE_ILED3_COARSE_POS
#define ADPD188_ILED3_COARSE_ILED3_COARSE_POS
Definition: adpd188.h:271
ADPD188_REG_FSAMPLE
#define ADPD188_REG_FSAMPLE
Definition: adpd188.h:70
adpd188_mode_get
int32_t adpd188_mode_get(struct adpd188_dev *dev, enum adpd188_mode *mode)
Get the mode of operation of the ADPD188.
Definition: adpd188.c:243
ADPD188_FIFO_INT
@ ADPD188_FIFO_INT
Definition: adpd188.h:559
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:83
adpd188_interrupt_en
int32_t adpd188_interrupt_en(struct adpd188_dev *dev, uint8_t flags)
Enable the slot and FIFO interrupt flags.
Definition: adpd188.c:423
ADPD188_ANYSLOT_PULSE
@ ADPD188_ANYSLOT_PULSE
Definition: adpd188.h:596
ADPD188_REG_ILED3_COARSE
#define ADPD188_REG_ILED3_COARSE
Definition: adpd188.h:85
ADPD188_PD_LED_SELECT_SLOTA_LED_SEL_MASK
#define ADPD188_PD_LED_SELECT_SLOTA_LED_SEL_MASK
Definition: adpd188.h:233
adpd188_mode_set
int32_t adpd188_mode_set(struct adpd188_dev *dev, enum adpd188_mode new_mode)
Set the mode of operation of the ADPD188.
Definition: adpd188.c:266
adpd188_init
int32_t adpd188_init(struct adpd188_dev **device, struct adpd188_init_param *init_param)
Initialize the ADPD188 driver.
Definition: adpd188.c:60
ADPD188_NORMAL
@ ADPD188_NORMAL
Definition: adpd188.h:546
ADPD188_ANYSLOT_OUT
@ ADPD188_ANYSLOT_OUT
Definition: adpd188.h:602
adpd188_slot_setup
int32_t adpd188_slot_setup(struct adpd188_dev *dev, struct adpd188_slot_config config)
Enable slot and setup its FIFO interaction.
Definition: adpd188.c:593
no_os_spi.h
Header file of SPI Interface.
ADPD188_REG_MATH
#define ADPD188_REG_MATH
Definition: adpd188.h:111
ADPD188_GPIO_CTRL_GPIO1_ALT_CFG_POS
#define ADPD188_GPIO_CTRL_GPIO1_ALT_CFG_POS
Definition: adpd188.h:204
adpd188_dev::device
enum adpd_supported_devices device
Definition: adpd188.h:663
adpd188.h
ADPD188 driver header file.
ADPD188_FIFO_THRESH_FIFO_THRESH_MASK
#define ADPD188_FIFO_THRESH_FIFO_THRESH_MASK
Definition: adpd188.h:177
no_os_i2c_remove
int32_t no_os_i2c_remove(struct no_os_i2c_desc *desc)
Free the resources allocated by no_os_i2c_init().
Definition: no_os_i2c.c:70
ADPD188_SLOTB_OUT
@ ADPD188_SLOTB_OUT
Definition: adpd188.h:600
adpd188_fifo_thresh_set
int32_t adpd188_fifo_thresh_set(struct adpd188_dev *dev, uint8_t word_no)
Set the number of 16 bit words that need to be in the FIFO to trigger an interrupt.
Definition: adpd188.c:324
ADPD188_MATH_FLT_MATH12_A_POS
#define ADPD188_MATH_FLT_MATH12_A_POS
Definition: adpd188.h:471
ADPD188_32BIT_4CHAN
@ ADPD188_32BIT_4CHAN
Definition: adpd188.h:641
ADPD188_REG_INT_MASK
#define ADPD188_REG_INT_MASK
Definition: adpd188.h:58
ADPD188_REG_DEVID
#define ADPD188_REG_DEVID
Definition: adpd188.h:62
adpd_supported_devices
adpd_supported_devices
Devices supported by the driver.
Definition: adpd188.h:507
adpd188_gpio_config::gpio_pol
uint8_t gpio_pol
Definition: adpd188.h:570
ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_WIDTH_MASK
#define ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_WIDTH_MASK
Definition: adpd188.h:344
no_os_delay.h
Header file of Delay functions.
ADPD188_MODE_MODE_MASK
#define ADPD188_MODE_MODE_MASK
Definition: adpd188.h:212
ADPD188_PROGRAM
@ ADPD188_PROGRAM
Definition: adpd188.h:544
adpd188_init_param::phy_init
union adpd188_phy_init phy_init
Definition: adpd188.h:684
ADPD188_MATH_FLT_MATH12_A_MASK
#define ADPD188_MATH_FLT_MATH12_A_MASK
Definition: adpd188.h:466
ADPD188_AFE_PWR_CFG1_AFE_POWERDOWN_POS
#define ADPD188_AFE_PWR_CFG1_AFE_POWERDOWN_POS
Definition: adpd188.h:353
adpd188_smoke_detect_setup
int32_t adpd188_smoke_detect_setup(struct adpd188_dev *dev)
Do initial configuration of the device to use as a smoke detector. The configuration is described in ...
Definition: adpd188.c:667
ADPD188_SLOTB_INT
@ ADPD188_SLOTB_INT
Definition: adpd188.h:557
device
Definition: ad9361_util.h:75
adpd188_init_param::phy_opt
enum adpd188_phy_opt phy_opt
Definition: adpd188.h:682
ADPD188_SLOT_EN_SLOTB_EN_POS
#define ADPD188_SLOT_EN_SLOTB_EN_POS
Definition: adpd188.h:225
ADPD188_REG_INT_SEQ_B
#define ADPD188_REG_INT_SEQ_B
Definition: adpd188.h:80
adpd188_slot_config::slot_id
enum adpd188_slots slot_id
Definition: adpd188.h:650
ADPD188_ILED3_COARSE_ILED3_COARSE_MASK
#define ADPD188_ILED3_COARSE_ILED3_COARSE_MASK
Definition: adpd188.h:268
ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_OFFSET_MASK
#define ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_OFFSET_MASK
Definition: adpd188.h:345
ADPD188_MATH_FLT_MATH34_A_POS
#define ADPD188_MATH_FLT_MATH34_A_POS
Definition: adpd188.h:468
adpd188_reg_write
int32_t adpd188_reg_write(struct adpd188_dev *dev, uint8_t reg_addr, uint16_t reg_val)
Write one 16 bit register of the ADPD188.
Definition: adpd188.c:210
ADPD188_CLK32M_CAL_EN_CLK32M_CAL_EN_MASK
#define ADPD188_CLK32M_CAL_EN_CLK32M_CAL_EN_MASK
Definition: adpd188.h:433
adpd188_sw_reset
int32_t adpd188_sw_reset(struct adpd188_dev *dev)
Do software reset of the device.
Definition: adpd188.c:520
no_os_gpio_direction_input
int32_t no_os_gpio_direction_input(struct no_os_gpio_desc *desc)
Enable the input direction of the specified GPIO.
Definition: no_os_gpio.c:108
ADPD188_REG_SW_RESET
#define ADPD188_REG_SW_RESET
Definition: adpd188.h:67
adpd188_init_param::device
enum adpd_supported_devices device
Definition: adpd188.h:680
ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_WIDTH_POS
#define ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_WIDTH_POS
Definition: adpd188.h:340
ADPD188_SLOTA_INT
@ ADPD188_SLOTA_INT
Definition: adpd188.h:555
ADPD188_REG_GPIO_DRV
#define ADPD188_REG_GPIO_DRV
Definition: adpd188.h:59
adpd188_adc_fsample_get
int32_t adpd188_adc_fsample_get(struct adpd188_dev *dev, uint16_t *freq_hz)
Get sample frequency of the ADC.
Definition: adpd188.c:648
ADPD188_GPIO_CTRL_GPIO1_ALT_CFG_MASK
#define ADPD188_GPIO_CTRL_GPIO1_ALT_CFG_MASK
Definition: adpd188.h:202
adpd188_interrupt_get
int32_t adpd188_interrupt_get(struct adpd188_dev *dev, uint8_t *flags)
Get the slot and FIFO interrupt flags.
Definition: adpd188.c:353
ADPD188_GPIO_DRV_GPIO1_DRV_MASK
#define ADPD188_GPIO_DRV_GPIO1_DRV_MASK
Definition: adpd188.h:159
ADPD188_SLOT_EN_SLOTB_EN_MASK
#define ADPD188_SLOT_EN_SLOTB_EN_MASK
Definition: adpd188.h:219
ADPD188_NO_FIFO
@ ADPD188_NO_FIFO
Definition: adpd188.h:633
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
ADPD188_SLOT_EN_FIFO_OVRN_PREVENT_MASK
#define ADPD188_SLOT_EN_FIFO_OVRN_PREVENT_MASK
Definition: adpd188.h:217
ADPD188_REG_SLOTA_CH3_OFFSET
#define ADPD188_REG_SLOTA_CH3_OFFSET
Definition: adpd188.h:77
ADPD188_REG_AFE_PWR_CFG1
#define ADPD188_REG_AFE_PWR_CFG1
Definition: adpd188.h:98
ADPD188_I2C
@ ADPD188_I2C
Definition: adpd188.h:533
ADPD188_REG_PD_LED_SELECT
#define ADPD188_REG_PD_LED_SELECT
Definition: adpd188.h:71
no_os_error.h
Error codes definition.
ADPD188_STATUS_SLOTB_INT_MASK
#define ADPD188_STATUS_SLOTB_INT_MASK
Definition: adpd188.h:144
ADPD188_PD_LED_SELECT_SLOTA_LED_SEL_POS
#define ADPD188_PD_LED_SELECT_SLOTA_LED_SEL_POS
Definition: adpd188.h:237
adpd188_init_param::gpio0_init
struct no_os_gpio_init_param gpio0_init
Definition: adpd188.h:686
ADPD188_AFE_PWR_CFG1_AFE_POWERDOWN_MASK
#define ADPD188_AFE_PWR_CFG1_AFE_POWERDOWN_MASK
Definition: adpd188.h:351
adpd188_slot_config::sot_fifo_mode
enum adpd188_slot_fifo_mode sot_fifo_mode
Definition: adpd188.h:654
adpd188_mode_get
int32_t adpd188_mode_get(struct adpd188_dev *dev, enum adpd188_mode *mode)
Get the mode of operation of the ADPD188.
Definition: adpd188.c:243
ADPD188_32BIT_SUM
@ ADPD188_32BIT_SUM
Definition: adpd188.h:637
adpd188_reg_write
int32_t adpd188_reg_write(struct adpd188_dev *dev, uint8_t reg_addr, uint16_t reg_val)
Write one 16 bit register of the ADPD188.
Definition: adpd188.c:210
ADPD188_REG_SLOTB_NUMPULSES
#define ADPD188_REG_SLOTB_NUMPULSES
Definition: adpd188.h:93
ADPD188_SLOT_EN_SLOTA_EN_POS
#define ADPD188_SLOT_EN_SLOTA_EN_POS
Definition: adpd188.h:227
ADPD188_PD_LED_SELECT_SLOTA_PD_SEL_POS
#define ADPD188_PD_LED_SELECT_SLOTA_PD_SEL_POS
Definition: adpd188.h:235
ADPD188_REG_GPIO_CTRL
#define ADPD188_REG_GPIO_CTRL
Definition: adpd188.h:65
ADPD188_OUT_HIGH
@ ADPD188_OUT_HIGH
Definition: adpd188.h:611
ADPD1081
@ ADPD1081
Definition: adpd188.h:510
ADPD188_STANDBY
@ ADPD188_STANDBY
Definition: adpd188.h:542
adpd188_slot_fifo_mode
adpd188_slot_fifo_mode
The way a time slot stores data in the FIFO.
Definition: adpd188.h:631
ADPD188_REG_FIFO_THRESH
#define ADPD188_REG_FIFO_THRESH
Definition: adpd188.h:61
ADPD188_SLOTA_NUMPULSES_SLOTA_PERIOD_POS
#define ADPD188_SLOTA_NUMPULSES_SLOTA_PERIOD_POS
Definition: adpd188.h:307
ADPD188_ILED3_COARSE_ILED3_SCALE_MASK
#define ADPD188_ILED3_COARSE_ILED3_SCALE_MASK
Definition: adpd188.h:266
ADPD188_REG_SLOTA_CH4_OFFSET
#define ADPD188_REG_SLOTA_CH4_OFFSET
Definition: adpd188.h:78
ADPD188_32KHZ_OSC
@ ADPD188_32KHZ_OSC
Definition: adpd188.h:613
ADPD188_SLOTB_PULSE
@ ADPD188_SLOTB_PULSE
Definition: adpd188.h:594
adpd188_reg_read
int32_t adpd188_reg_read(struct adpd188_dev *dev, uint8_t reg_addr, uint16_t *reg_val)
Read one 16 bit register of the ADPD188.
Definition: adpd188.c:172
ADPD188_SLOTB_NUMPULSES_SLOTB_PULSES_POS
#define ADPD188_SLOTB_NUMPULSES_SLOTB_PULSES_POS
Definition: adpd188.h:324
ADPD188_ACTIVE_PULSE
@ ADPD188_ACTIVE_PULSE
Definition: adpd188.h:590
ADPD188_16BIT_SUM
@ ADPD188_16BIT_SUM
Definition: adpd188.h:635
ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_OFFSET_POS
#define ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_OFFSET_POS
Definition: adpd188.h:347
ADPD188_REG_SLOTA_NUMPULSES
#define ADPD188_REG_SLOTA_NUMPULSES
Definition: adpd188.h:90
adpd188_slot_config
Slot configuration initialization structure.
Definition: adpd188.h:648
adpd188_slot_config::slot_en
bool slot_en
Definition: adpd188.h:652
adpd188_reg_read
int32_t adpd188_reg_read(struct adpd188_dev *dev, uint8_t reg_addr, uint16_t *reg_val)
Read one 16 bit register of the ADPD188.
Definition: adpd188.c:172
ADPD188_GPIO_DRV_GPIO0_POL_MASK
#define ADPD188_GPIO_DRV_GPIO0_POL_MASK
Definition: adpd188.h:163
ADPD188_STATUS_FIFO_SAMPLES_POS
#define ADPD188_STATUS_FIFO_SAMPLES_POS
Definition: adpd188.h:146
adpd188_mode_set
int32_t adpd188_mode_set(struct adpd188_dev *dev, enum adpd188_mode new_mode)
Set the mode of operation of the ADPD188.
Definition: adpd188.c:266
ADPD188_PD_LED_SELECT_SLOTB_LED_SEL_MASK
#define ADPD188_PD_LED_SELECT_SLOTB_LED_SEL_MASK
Definition: adpd188.h:232
ADPD188_GPIO_DRV_GPIO0_ENA_MASK
#define ADPD188_GPIO_DRV_GPIO0_ENA_MASK
Definition: adpd188.h:161
ADPD188_REG_CLK32M_ADJUST
#define ADPD188_REG_CLK32M_ADJUST
Definition: adpd188.h:106
no_os_gpio_remove
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:95
adpd188_smoke_detect_setup
int32_t adpd188_smoke_detect_setup(struct adpd188_dev *dev)
Do initial configuration of the device to use as a smoke detector. The configuration is described in ...
Definition: adpd188.c:667
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:143
adpd188_fifo_thresh_set
int32_t adpd188_fifo_thresh_set(struct adpd188_dev *dev, uint8_t word_no)
Set the number of 16 bit words that need to be in the FIFO to trigger an interrupt.
Definition: adpd188.c:324
adpd188_fifo_clear
int32_t adpd188_fifo_clear(struct adpd188_dev *dev)
Empty the FIFO.
Definition: adpd188.c:301
adpd188_phy_opt
adpd188_phy_opt
Types of physical communication protocol.
Definition: adpd188.h:529
ADPD188_SLOTB
@ ADPD188_SLOTB
Definition: adpd188.h:624
adpd188_phy_init::i2c_phy
struct no_os_i2c_init_param i2c_phy
Definition: adpd188.h:520
adpd188_remove
int32_t adpd188_remove(struct adpd188_dev *dev)
Free resources allocated by adpd188_init().
Definition: adpd188.c:140
adpd188_clk32mhz_cal
int32_t adpd188_clk32mhz_cal(struct adpd188_dev *dev)
Do internal 32MHz clock calibration. This calibration requires the 32kHz clock to be calibrated first...
Definition: adpd188.c:532
ADPD188_INT_MASK_SLOTA_INT_MASK_MASK
#define ADPD188_INT_MASK_SLOTA_INT_MASK_MASK
Definition: adpd188.h:153
ADPD188_REG_SLOTB_CH4_OFFSET
#define ADPD188_REG_SLOTB_CH4_OFFSET
Definition: adpd188.h:84
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
ADPD188_FIFO_THRESH_MAX_THRESHOLD
#define ADPD188_FIFO_THRESH_MAX_THRESHOLD
Definition: adpd188.h:179
adpd188_sw_reset
int32_t adpd188_sw_reset(struct adpd188_dev *dev)
Do software reset of the device.
Definition: adpd188.c:520
adpd188_phy_init::spi_phy
struct no_os_spi_init_param spi_phy
Definition: adpd188.h:522
ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_WIDTH_POS
#define ADPD188_SLOTB_AFE_WINDOW_SLOTB_AFE_WIDTH_POS
Definition: adpd188.h:346
ADPD188_SLOT_EN_SLOTA_FIFO_MODE_POS
#define ADPD188_SLOT_EN_SLOTA_FIFO_MODE_POS
Definition: adpd188.h:226
adpd188_remove
int32_t adpd188_remove(struct adpd188_dev *dev)
Free resources allocated by adpd188_init().
Definition: adpd188.c:140
adpd188_interrupt_en
int32_t adpd188_interrupt_en(struct adpd188_dev *dev, uint8_t flags)
Enable the slot and FIFO interrupt flags.
Definition: adpd188.c:423
adpd188_gpio_setup
int32_t adpd188_gpio_setup(struct adpd188_dev *dev, struct adpd188_gpio_config config)
Setup drive and polarity of the GPIOs. Also enable GPIO if necessary.
Definition: adpd188.c:447
ADPD188_GPIO_DRV_GPIO0_DRV_MASK
#define ADPD188_GPIO_DRV_GPIO0_DRV_MASK
Definition: adpd188.h:162
ADPD188_ILED1_COARSE_ILED1_SLEW_POS
#define ADPD188_ILED1_COARSE_ILED1_SLEW_POS
Definition: adpd188.h:278
adpd188_phy_init
Communication physical protocol initialization structure. Can be I2C or SPI.
Definition: adpd188.h:518
ADPD188_REG_SLOTA_CH2_OFFSET
#define ADPD188_REG_SLOTA_CH2_OFFSET
Definition: adpd188.h:76
adpd188_adc_fsample_get
int32_t adpd188_adc_fsample_get(struct adpd188_dev *dev, uint16_t *freq_hz)
Get sample frequency of the ADC.
Definition: adpd188.c:648
ADPD188_CLK_RATIO_CLK_RATIO_MASK
#define ADPD188_CLK_RATIO_CLK_RATIO_MASK
Definition: adpd188.h:198
adpd188_clk32mhz_cal
int32_t adpd188_clk32mhz_cal(struct adpd188_dev *dev)
Do internal 32MHz clock calibration. This calibration requires the 32kHz clock to be calibrated first...
Definition: adpd188.c:532
no_os_i2c_desc
Structure holding I2C descriptor.
Definition: no_os_i2c.h:81
ADPD188_CLK32M_ADJUST_CLK32M_ADJUST_MASK
#define ADPD188_CLK32M_ADJUST_CLK32M_ADJUST_MASK
Definition: adpd188.h:418
no_os_gpio_get
int32_t no_os_gpio_get(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Obtain the GPIO decriptor.
Definition: no_os_gpio.c:55
no_os_i2c_read
int32_t no_os_i2c_read(struct no_os_i2c_desc *desc, uint8_t *data, uint8_t bytes_number, uint8_t stop_bit)
I2C Read data from slave device.
Definition: no_os_i2c.c:104
adpd188_gpio_alt_setup
int32_t adpd188_gpio_alt_setup(struct adpd188_dev *dev, uint8_t gpio_id, enum adpd188_gpio_alt_config config)
Setup the GPIO source.
Definition: adpd188.c:490
ADPD188_MATH_FLT_MATH12_B_MASK
#define ADPD188_MATH_FLT_MATH12_B_MASK
Definition: adpd188.h:465
adpd188_fifo_status_get
int32_t adpd188_fifo_status_get(struct adpd188_dev *dev, uint8_t *bytes_no)
Get the number of bytes currently present in FIFO.
Definition: adpd188.c:281
no_os_i2c.h
Header file of I2C Interface.
adpd188_slots
adpd188_slots
ADPD188 time slots.
Definition: adpd188.h:620
ADPD188_REG_STATUS
#define ADPD188_REG_STATUS
Definition: adpd188.h:57
adpd188_init_param
Driver initialization structure.
Definition: adpd188.h:678
ADPD188_SLOTA_OUT
@ ADPD188_SLOTA_OUT
Definition: adpd188.h:598
ADPD188_REG_MODE
#define ADPD188_REG_MODE
Definition: adpd188.h:68
ADPD188BI
@ ADPD188BI
Definition: adpd188.h:508
adpd188_gpio_config
GPIO level configuration.
Definition: adpd188.h:566
ADPD188_SLOTA_NUMPULSES_SLOTA_PULSES_POS
#define ADPD188_SLOTA_NUMPULSES_SLOTA_PULSES_POS
Definition: adpd188.h:306
ADPD188_REG_SLOTB_CH1_OFFSET
#define ADPD188_REG_SLOTB_CH1_OFFSET
Definition: adpd188.h:81
ADPD188_SLOT_EN_SLOTA_FIFO_MODE_MASK
#define ADPD188_SLOT_EN_SLOTA_FIFO_MODE_MASK
Definition: adpd188.h:220
adpd188_fifo_status_get
int32_t adpd188_fifo_status_get(struct adpd188_dev *dev, uint8_t *bytes_no)
Get the number of bytes currently present in FIFO.
Definition: adpd188.c:281
adpd188_slot_setup
int32_t adpd188_slot_setup(struct adpd188_dev *dev, struct adpd188_slot_config config)
Enable slot and setup its FIFO interaction.
Definition: adpd188.c:593
ADPD188_MATH_FLT_MATH34_B_MASK
#define ADPD188_MATH_FLT_MATH34_B_MASK
Definition: adpd188.h:462
ADPD188_INT_FUNC
@ ADPD188_INT_FUNC
Definition: adpd188.h:585
ADPD188_GPIO_CTRL_GPIO0_ALT_CFG_MASK
#define ADPD188_GPIO_CTRL_GPIO0_ALT_CFG_MASK
Definition: adpd188.h:203
ADPD188_SLOTB_NUMPULSES_SLOTB_PERIOD_MASK
#define ADPD188_SLOTB_NUMPULSES_SLOTB_PERIOD_MASK
Definition: adpd188.h:323
ADPD188_PD_LED_SELECT_SLOTB_PD_SEL_POS
#define ADPD188_PD_LED_SELECT_SLOTB_PD_SEL_POS
Definition: adpd188.h:234
adpd188_dev::phy_desc
void * phy_desc
Definition: adpd188.h:667
adpd188_interrupt_get
int32_t adpd188_interrupt_get(struct adpd188_dev *dev, uint8_t *flags)
Get the slot and FIFO interrupt flags.
Definition: adpd188.c:353
ADPD188_REG_SLOTB_AFE_WINDOW
#define ADPD188_REG_SLOTB_AFE_WINDOW
Definition: adpd188.h:97
ADPD188_SLOT_EN_SLOTA_EN_MASK
#define ADPD188_SLOT_EN_SLOTA_EN_MASK
Definition: adpd188.h:221
adpd188_init_param::gpio1_init
struct no_os_gpio_init_param gpio1_init
Definition: adpd188.h:688
no_os_i2c_init_param
Structure holding the parameters for I2C initialization.
Definition: no_os_i2c.h:64
ADPD188_INT_MASK_SLOTB_INT_MASK_MASK
#define ADPD188_INT_MASK_SLOTB_INT_MASK_MASK
Definition: adpd188.h:152
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
ADPD188_REG_SLOT_EN
#define ADPD188_REG_SLOT_EN
Definition: adpd188.h:69
ADPD188_MATH_FLT_MATH34_A_MASK
#define ADPD188_MATH_FLT_MATH34_A_MASK
Definition: adpd188.h:463
adpd188_gpio_config::gpio_drv
uint8_t gpio_drv
Definition: adpd188.h:572
ADPD188_ILED3_COARSE_ILED3_SLEW_MASK
#define ADPD188_ILED3_COARSE_ILED3_SLEW_MASK
Definition: adpd188.h:267
ADPD188_DATA_ACCESS_CTL_DIGITAL_CLOCK_ENA_MASK
#define ADPD188_DATA_ACCESS_CTL_DIGITAL_CLOCK_ENA_MASK
Definition: adpd188.h:494
ADPD188_ILED1_COARSE_ILED1_SLEW_MASK
#define ADPD188_ILED1_COARSE_ILED1_SLEW_MASK
Definition: adpd188.h:275
ADPD188_HALF_SAMPLING
@ ADPD188_HALF_SAMPLING
Definition: adpd188.h:607
ADPD188_REG_INT_SEQ_A
#define ADPD188_REG_INT_SEQ_A
Definition: adpd188.h:74
APDP1080
@ APDP1080
Definition: adpd188.h:509
ADPD188_MATH_FLT_MATH34_B_POS
#define ADPD188_MATH_FLT_MATH34_B_POS
Definition: adpd188.h:467
ADPD188_REG_SLOTA_AFE_WINDOW
#define ADPD188_REG_SLOTA_AFE_WINDOW
Definition: adpd188.h:96
adpd188_gpio_alt_config
adpd188_gpio_alt_config
GPIO source configuration.
Definition: adpd188.h:581
ADPD188_16BIT_4CHAN
@ ADPD188_16BIT_4CHAN
Definition: adpd188.h:639
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:71
ADPD188_INT_SEQ_A_INTEG_ORDER_A_MASK
#define ADPD188_INT_SEQ_A_INTEG_ORDER_A_MASK
Definition: adpd188.h:252
ADPD188_GPIO_DRV_GPIO1_POL_MASK
#define ADPD188_GPIO_DRV_GPIO1_POL_MASK
Definition: adpd188.h:160
ADPD188_SLOT_EN_SLOTB_FIFO_MODE_POS
#define ADPD188_SLOT_EN_SLOTB_FIFO_MODE_POS
Definition: adpd188.h:224
no_os_gpio.h
Header file of GPIO Interface.
ADPD108X_DEVICE_ID
#define ADPD108X_DEVICE_ID
Definition: adpd188.h:189
adpd188_gpio_config::gpio_id
uint8_t gpio_id
Definition: adpd188.h:568
ADPD188_ILED1_COARSE_ILED1_COARSE_MASK
#define ADPD188_ILED1_COARSE_ILED1_COARSE_MASK
Definition: adpd188.h:276
ADPD188_ILED1_COARSE_ILED1_SCALE_MASK
#define ADPD188_ILED1_COARSE_ILED1_SCALE_MASK
Definition: adpd188.h:274
ADPD188_REG_CLK_RATIO
#define ADPD188_REG_CLK_RATIO
Definition: adpd188.h:64
ADPD188_PD_LED_SELECT_SLOTB_LED_SEL_POS
#define ADPD188_PD_LED_SELECT_SLOTB_LED_SEL_POS
Definition: adpd188.h:236
ADPD188_REG_ILED1_COARSE
#define ADPD188_REG_ILED1_COARSE
Definition: adpd188.h:86
adpd188_gpio_config::gpio_en
uint8_t gpio_en
Definition: adpd188.h:574
ADPD188_STATUS_SLOTA_INT_MASK
#define ADPD188_STATUS_SLOTA_INT_MASK
Definition: adpd188.h:145
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
adpd188_dev
Driver descriptor structure.
Definition: adpd188.h:661
adpd188_dev::gpio1
struct no_os_gpio_desc * gpio1
Definition: adpd188.h:671
ADPD188_REG_CLK32M_CAL_EN
#define ADPD188_REG_CLK32M_CAL_EN
Definition: adpd188.h:108
ADPD188_SLOTA
@ ADPD188_SLOTA
Definition: adpd188.h:622
ADPD188_REG_SLOTB_CH2_OFFSET
#define ADPD188_REG_SLOTB_CH2_OFFSET
Definition: adpd188.h:82
ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_OFFSET_POS
#define ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_OFFSET_POS
Definition: adpd188.h:341
ADPD188_REG_SLOTA_CH1_OFFSET
#define ADPD188_REG_SLOTA_CH1_OFFSET
Definition: adpd188.h:75
ADPD188_ILED1_COARSE_ILED1_COARSE_POS
#define ADPD188_ILED1_COARSE_ILED1_COARSE_POS
Definition: adpd188.h:279
ADPD188_PD_LED_SELECT_SLOTA_PD_SEL_MASK
#define ADPD188_PD_LED_SELECT_SLOTA_PD_SEL_MASK
Definition: adpd188.h:231
ADPD188_SLOT_EN_SLOTB_FIFO_MODE_MASK
#define ADPD188_SLOT_EN_SLOTB_FIFO_MODE_MASK
Definition: adpd188.h:218
adpd188_interrupt_clear
int32_t adpd188_interrupt_clear(struct adpd188_dev *dev, uint8_t flags)
Clear the slot and FIFO interrupt flags.
Definition: adpd188.c:383
ADPD188_INT_SEQ_B_INTEG_ORDER_B_MASK
#define ADPD188_INT_SEQ_B_INTEG_ORDER_B_MASK
Definition: adpd188.h:262
ADPD188_ADPD103
@ ADPD188_ADPD103
Definition: adpd188.h:583
ADPD188_SLOT_EN_RDOUT_MODE_MASK
#define ADPD188_SLOT_EN_RDOUT_MODE_MASK
Definition: adpd188.h:216
adpd188_gpio_setup
int32_t adpd188_gpio_setup(struct adpd188_dev *dev, struct adpd188_gpio_config config)
Setup drive and polarity of the GPIOs. Also enable GPIO if necessary.
Definition: adpd188.c:447
ADPD188_ILED3_COARSE_ILED3_SLEW_POS
#define ADPD188_ILED3_COARSE_ILED3_SLEW_POS
Definition: adpd188.h:270
ADPD188_SLOTA_NUMPULSES_SLOTA_PERIOD_MASK
#define ADPD188_SLOTA_NUMPULSES_SLOTA_PERIOD_MASK
Definition: adpd188.h:305
ADPD188_SLOTB_NUMPULSES_SLOTB_PERIOD_POS
#define ADPD188_SLOTB_NUMPULSES_SLOTB_PERIOD_POS
Definition: adpd188.h:325
ADPD188_REG_SLOTB_CH3_OFFSET
#define ADPD188_REG_SLOTB_CH3_OFFSET
Definition: adpd188.h:83
ADPD188_MATH_FLT_MATH12_B_POS
#define ADPD188_MATH_FLT_MATH12_B_POS
Definition: adpd188.h:470
ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_OFFSET_MASK
#define ADPD188_SLOTA_AFE_WINDOW_SLOTA_AFE_OFFSET_MASK
Definition: adpd188.h:339
adpd188_init
int32_t adpd188_init(struct adpd188_dev **device, struct adpd188_init_param *init_param)
Initialize the ADPD188 driver.
Definition: adpd188.c:60
ADPD188_SLOTA_NUMPULSES_SLOTA_PULSES_MASK
#define ADPD188_SLOTA_NUMPULSES_SLOTA_PULSES_MASK
Definition: adpd188.h:304
adpd188_dev::phy_opt
enum adpd188_phy_opt phy_opt
Definition: adpd188.h:665
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:121