no-OS
adpd410x.h
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1 /***************************************************************************/
39 #ifndef ADPD410X_H_
40 #define ADPD410X_H_
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 
46 #include <stdbool.h>
47 #include "no_os_spi.h"
48 #include "no_os_i2c.h"
49 #include "no_os_gpio.h"
50 
51 /******************************************************************************/
52 /********************** Macros and Constants Definitions **********************/
53 /******************************************************************************/
54 
55 #define ADPD410X_REG_FIFO_STATUS 0x0000
56 #define ADPD410X_REG_INT_STATUS_DATA 0x0001
57 #define ADPD410X_REG_INT_STATUS_LEV0 0x0002
58 #define ADPD410X_REG_INT_STATUS_LEV1 0x0003
59 #define ADPD410X_REG_FIFO_TH 0x0006
60 #define ADPD410X_REG_INT_ACLEAR 0x0007
61 #define ADPD410X_REG_CHIP_ID 0x0008
62 #define ADPD410X_REG_OSC32M 0x0009
63 #define ADPD410X_REG_OSC32M_CAL 0x000A
64 #define ADPD410X_REG_OSC1M 0x000B
65 #define ADPD410X_REG_OSC32K 0x000C
66 #define ADPD410X_REG_TS_FREQ 0x000D
67 #define ADPD410X_REG_TS_FREQH 0x000E
68 #define ADPD410X_REG_SYS_CTL 0x000F
69 #define ADPD410X_REG_OPMODE 0x0010
70 #define ADPD410X_REG_STAMP_L 0x0011
71 #define ADPD410X_REG_STAMP_H 0x0012
72 #define ADPD410X_REG_STAMPDELTA 0x0013
73 #define ADPD410X_REG_INT_ENABLE_XD 0x0014
74 #define ADPD410X_REG_INT_ENABLE_YD 0x0015
75 #define ADPD410X_REG_INT_ENABLE_XL0 0x0016
76 #define ADPD410X_REG_INT_ENABLE_XL1 0x0017
77 #define ADPD410X_REG_INT_ENABLE_YL0 0x001a
78 #define ADPD410X_REG_INT_ENABLE_YL1 0x001b
79 #define ADPD410X_REG_FIFO_STATUS_BYTES 0x001e
80 #define ADPD410X_REG_INPUT_SLEEP 0x0020
81 #define ADPD410X_REG_INPUT_CFG 0x0021
82 #define ADPD410X_REG_GPIO_CFG 0x0022
83 #define ADPD410X_REG_GPIO01 0x0023
84 #define ADPD410X_REG_GPIO23 0x0024
85 #define ADPD410X_REG_GPIO_IN 0x0025
86 #define ADPD410X_REG_GPIO_EXT 0x0026
87 #define ADPD410X_REG_DATA_HOLD_FLAG 0x002E
88 #define ADPD410X_REG_FIFO_DATA 0x002F
89 #define ADPD410X_REG_SIGNAL1_L(ts) (0x0030 + (ts) * 0x08)
90 #define ADPD410X_REG_SIGNAL1_H(ts) (0x0031 + (ts) * 0x08)
91 #define ADPD410X_REG_SIGNAL2_L(ts) (0x0032 + (ts) * 0x08)
92 #define ADPD410X_REG_SIGNAL2_H(ts) (0x0033 + (ts) * 0x08)
93 #define ADPD410X_REG_DARK1_L(ts) (0x0034 + (ts) * 0x08)
94 #define ADPD410X_REG_DARK1_H(ts) (0x0035 + (ts) * 0x08)
95 #define ADPD410X_REG_DARK2_L(ts) (0x0036 + (ts) * 0x08)
96 #define ADPD410X_REG_DARK2_H(ts) (0x0037 + (ts) * 0x08)
97 #define ADPD410X_REG_IO_ADJUST 0x00B4
98 #define ADPD410X_REG_I2C_KEY 0x00B6
99 #define ADPD410X_REG_I2C_ADDR 0x00B7
100 #define ADPD410X_REG_TS_CTRL(ts) (0x0100 + (ts) * 0x20)
101 #define ADPD410X_REG_TS_PATH(ts) (0x0101 + (ts) * 0x20)
102 #define ADPD410X_REG_INPUTS(ts) (0x0102 + (ts) * 0x20)
103 #define ADPD410X_REG_CATHODE(ts) (0x0103 + (ts) * 0x20)
104 #define ADPD410X_REG_AFE_TRIM(ts) (0x0104 + (ts) * 0x20)
105 #define ADPD410X_REG_LED_POW12(ts) (0x0105 + (ts) * 0x20)
106 #define ADPD410X_REG_LED_POW34(ts) (0x0106 + (ts) * 0x20)
107 #define ADPD410X_REG_COUNTS(ts) (0x0107 + (ts) * 0x20)
108 #define ADPD410X_REG_PERIOD(ts) (0x0108 + (ts) * 0x20)
109 #define ADPD410X_REG_LED_PULSE(ts) (0x0109 + (ts) * 0x20)
110 #define ADPD410X_REG_INTEG_WIDTH(ts) (0x010A + (ts) * 0x20)
111 #define ADPD410X_REG_INTEG_OFFSET(ts) (0x010B + (ts) * 0x20)
112 #define ADPD410X_REG_MOD_PULSE(ts) (0x010C + (ts) * 0x20)
113 #define ADPD410X_REG_PATTERN(ts) (0x010D + (ts) * 0x20)
114 #define ADPD410X_REG_ADC_OFF1(ts) (0x010E + (ts) * 0x20)
115 #define ADPD410X_REG_ADC_OFF2(ts) (0x010F + (ts) * 0x20)
116 #define ADPD410X_REG_DATA1(ts) (0x0110 + (ts) * 0x20)
117 #define ADPD410X_REG_DATA2(ts) (0x0111 + (ts) * 0x20)
118 #define ADPD410X_REG_DECIMATE(ts) (0x0112 + (ts) * 0x20)
119 #define ADPD410X_REG_DIGINT_LIT(ts) (0x0113 + (ts) * 0x20)
120 #define ADPD410X_REG_DIGINT_DARK(ts) (0x0114 + (ts) * 0x20)
121 #define ADPD410X_REG_THRESH_CFG(ts) (0x0115 + (ts) * 0x20)
122 #define ADPD410X_REG_THRESH0(ts) (0x0116 + (ts) * 0x20)
123 #define ADPD410X_REG_THRESH1(ts) (0x0117 + (ts) * 0x20)
124 
125 
126 /* ADPD410X_REG_FIFO_STATUS */
127 #define BITP_INT_STATUS_FIFO_FIFO_BYTE_COUNT 0
128 #define BITP_INT_STATUS_FIFO_INT_FIFO_OFLOW 13
129 #define BITP_INT_STATUS_FIFO_INT_FIFO_UFLOW 14
130 #define BITP_INT_STATUS_FIFO_CLEAR_FIFO 15
131 #define BITM_INT_STATUS_FIFO_FIFO_BYTE_COUNT 0x07ff
132 #define BITM_INT_STATUS_FIFO_INT_FIFO_OFLOW 0x2000
133 #define BITM_INT_STATUS_FIFO_INT_FIFO_UFLOW 0x4000
134 #define BITM_INT_STATUS_FIFO_CLEAR_FIFO 0x8000
135 
136 
137 /* ADPD410X_REG_INT_STATUS_DATA */
138 #define BITP_INT_STATUS_DATA_INT_DATA_A 0
139 #define BITP_INT_STATUS_DATA_INT_DATA_B 1
140 #define BITP_INT_STATUS_DATA_INT_DATA_C 2
141 #define BITP_INT_STATUS_DATA_INT_DATA_D 3
142 #define BITP_INT_STATUS_DATA_INT_DATA_E 4
143 #define BITP_INT_STATUS_DATA_INT_DATA_F 5
144 #define BITP_INT_STATUS_DATA_INT_DATA_G 6
145 #define BITP_INT_STATUS_DATA_INT_DATA_H 7
146 #define BITP_INT_STATUS_DATA_INT_DATA_I 8
147 #define BITP_INT_STATUS_DATA_INT_DATA_J 9
148 #define BITP_INT_STATUS_DATA_INT_DATA_K 10
149 #define BITP_INT_STATUS_DATA_INT_DATA_L 11
150 #define BITP_INT_STATUS_DATA_INT_FIFO_TH 15
151 #define BITM_INT_STATUS_DATA_INT_DATA_A 0x0001
152 #define BITM_INT_STATUS_DATA_INT_DATA_B 0x0002
153 #define BITM_INT_STATUS_DATA_INT_DATA_C 0x0004
154 #define BITM_INT_STATUS_DATA_INT_DATA_D 0x0008
155 #define BITM_INT_STATUS_DATA_INT_DATA_E 0x0010
156 #define BITM_INT_STATUS_DATA_INT_DATA_F 0x0020
157 #define BITM_INT_STATUS_DATA_INT_DATA_G 0x0040
158 #define BITM_INT_STATUS_DATA_INT_DATA_H 0x0080
159 #define BITM_INT_STATUS_DATA_INT_DATA_I 0x0100
160 #define BITM_INT_STATUS_DATA_INT_DATA_J 0x0200
161 #define BITM_INT_STATUS_DATA_INT_DATA_K 0x0400
162 #define BITM_INT_STATUS_DATA_INT_DATA_L 0x0800
163 #define BITM_INT_STATUS_DATA_INT_FIFO_TH 0x8000
164 
165 /* ADPD410X_REG_INT_STATUS_LEV0 */
166 #define BITP_INT_STATUS_LEV0_INT_LEV0_A 0
167 #define BITP_INT_STATUS_LEV0_INT_LEV0_B 1
168 #define BITP_INT_STATUS_LEV0_INT_LEV0_C 2
169 #define BITP_INT_STATUS_LEV0_INT_LEV0_D 3
170 #define BITP_INT_STATUS_LEV0_INT_LEV0_E 4
171 #define BITP_INT_STATUS_LEV0_INT_LEV0_F 5
172 #define BITP_INT_STATUS_LEV0_INT_LEV0_G 6
173 #define BITP_INT_STATUS_LEV0_INT_LEV0_H 7
174 #define BITP_INT_STATUS_LEV0_INT_LEV0_I 8
175 #define BITP_INT_STATUS_LEV0_INT_LEV0_J 9
176 #define BITP_INT_STATUS_LEV0_INT_LEV0_K 10
177 #define BITP_INT_STATUS_LEV0_INT_LEV0_L 11
178 #define BITM_INT_STATUS_LEV0_INT_LEV0_A 0x0001
179 #define BITM_INT_STATUS_LEV0_INT_LEV0_B 0x0002
180 #define BITM_INT_STATUS_LEV0_INT_LEV0_C 0x0004
181 #define BITM_INT_STATUS_LEV0_INT_LEV0_D 0x0008
182 #define BITM_INT_STATUS_LEV0_INT_LEV0_E 0x0010
183 #define BITM_INT_STATUS_LEV0_INT_LEV0_F 0x0020
184 #define BITM_INT_STATUS_LEV0_INT_LEV0_G 0x0040
185 #define BITM_INT_STATUS_LEV0_INT_LEV0_H 0x0080
186 #define BITM_INT_STATUS_LEV0_INT_LEV0_I 0x0100
187 #define BITM_INT_STATUS_LEV0_INT_LEV0_J 0x0200
188 #define BITM_INT_STATUS_LEV0_INT_LEV0_K 0x0400
189 #define BITM_INT_STATUS_LEV0_INT_LEV0_L 0x0800
190 
191 /* ADPD410X_REG_INT_STATUS_LEV1 */
192 #define BITP_INT_STATUS_LEV1_INT_LEV1_A 0
193 #define BITP_INT_STATUS_LEV1_INT_LEV1_B 1
194 #define BITP_INT_STATUS_LEV1_INT_LEV1_C 2
195 #define BITP_INT_STATUS_LEV1_INT_LEV1_D 3
196 #define BITP_INT_STATUS_LEV1_INT_LEV1_E 4
197 #define BITP_INT_STATUS_LEV1_INT_LEV1_F 5
198 #define BITP_INT_STATUS_LEV1_INT_LEV1_G 6
199 #define BITP_INT_STATUS_LEV1_INT_LEV1_H 7
200 #define BITP_INT_STATUS_LEV1_INT_LEV1_I 8
201 #define BITP_INT_STATUS_LEV1_INT_LEV1_J 9
202 #define BITP_INT_STATUS_LEV1_INT_LEV1_K 10
203 #define BITP_INT_STATUS_LEV1_INT_LEV1_L 11
204 #define BITM_INT_STATUS_LEV1_INT_LEV1_A 0x0001
205 #define BITM_INT_STATUS_LEV1_INT_LEV1_B 0x0002
206 #define BITM_INT_STATUS_LEV1_INT_LEV1_C 0x0004
207 #define BITM_INT_STATUS_LEV1_INT_LEV1_D 0x0008
208 #define BITM_INT_STATUS_LEV1_INT_LEV1_E 0x0010
209 #define BITM_INT_STATUS_LEV1_INT_LEV1_F 0x0020
210 #define BITM_INT_STATUS_LEV1_INT_LEV1_G 0x0040
211 #define BITM_INT_STATUS_LEV1_INT_LEV1_H 0x0080
212 #define BITM_INT_STATUS_LEV1_INT_LEV1_I 0x0100
213 #define BITM_INT_STATUS_LEV1_INT_LEV1_J 0x0200
214 #define BITM_INT_STATUS_LEV1_INT_LEV1_K 0x0400
215 #define BITM_INT_STATUS_LEV1_INT_LEV1_L 0x0800
216 
217 
218 /* ADPD410X_REG_FIFO_TH */
219 #define BITP_FIFO_CTL_FIFO_TH 0
220 #define BITM_FIFO_CTL_FIFO_TH 0x03ff
221 
222 /* ADPD410X_REG_INT_ACLEAR */
223 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_A 0
224 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_B 1
225 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_C 2
226 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_D 3
227 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_E 4
228 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_F 5
229 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_G 6
230 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_H 7
231 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_I 8
232 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_J 9
233 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_K 10
234 #define BITP_INT_ACLEAR_INT_ACLEAR_DATA_L 11
235 #define BITP_INT_ACLEAR_INT_ACLEAR_FIFO 15
236 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_A 0x0001
237 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_B 0x0002
238 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_C 0x0004
239 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_D 0x0008
240 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_E 0x0010
241 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_F 0x0020
242 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_G 0x0040
243 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_H 0x0080
244 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_I 0x0100
245 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_J 0x0200
246 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_K 0x0400
247 #define BITM_INT_ACLEAR_INT_ACLEAR_DATA_L 0x0800
248 #define BITM_INT_ACLEAR_INT_ACLEAR_FIFO 0x8000
249 
250 /* ADPD410X_REG_CHIP_ID */
251 #define BITP_CHIP_ID 0
252 #define BITP_CHIP_VERSION 8
253 #define BITM_CHIP_ID 0x00ff
254 #define BITM_CHIP_VERSION 0xff00
255 #define ADPD410X_CHIP_ID 0xC2
256 
257 /* ADPD410X_REG_OSC32M */
258 #define BITP_OSC32M_OSC_32M_FREQ_ADJ 0
259 #define BITM_OSC32M_OSC_32M_FREQ_ADJ 0x00ff
260 
261 /* ADPD410X_REG_OSC32M_CAL */
262 #define BITP_OSC32M_CAL_OSC_32M_CAL_COUNT 0
263 #define BITP_OSC32M_CAL_OSC_32M_CAL_START 15
264 #define BITM_OSC32M_CAL_OSC_32M_CAL_COUNT 0x7fff
265 #define BITM_OSC32M_CAL_OSC_32M_CAL_START 0x8000
266 
267 /* ADPD410X_REG_OSC1M */
268 #define BITP_OSC1M_OSC_1M_FREQ_ADJ 0
269 #define BITP_OSC1M_OSC_CLK_CAL_ENA 10
270 #define BITM_OSC1M_OSC_1M_FREQ_ADJ 0x03ff
271 #define BITM_OSC1M_OSC_CLK_CAL_ENA 0x0400
272 
273 /* ADPD410X_REG_OSC32K */
274 #define BITP_OSC32K_OSC_32K_ADJUST 0
275 #define BITP_OSC32K_CAPTURE_TIMESTAMP 15
276 #define BITM_OSC32K_OSC_32K_ADJUST 0x003f
277 #define BITM_OSC32K_CAPTURE_TIMESTAMP 0x8000
278 
279 /* ADPD410X_REG_TS_FREQ */
280 #define BITP_TS_FREQ_TIMESLOT_PERIOD_L 0
281 #define BITM_TS_FREQ_TIMESLOT_PERIOD_L 0xffff
282 
283 /* ADPD410X_REG_TS_FREQH */
284 #define BITP_TS_FREQH_TIMESLOT_PERIOD_H 0
285 #define BITM_TS_FREQH_TIMESLOT_PERIOD_H 0x007f
286 
287 /* ADPD410X_REG_SYS_CTL */
288 #define BITP_SYS_CTL_OSC_32K_EN 0
289 #define BITP_SYS_CTL_OSC_1M_EN 1
290 #define BITP_SYS_CTL_LFOSC_SEL 2
291 #define BITP_SYS_CTL_RANDOM_SLEEP 3
292 #define BITP_SYS_CTL_GO_SLEEP 4
293 #define BITP_SYS_CTL_ALT_CLK_GPIO 6
294 #define BITP_SYS_CTL_ALT_CLOCKS 8
295 #define BITP_SYS_CTL_SW_RESET 15
296 #define BITM_SYS_CTL_OSC_32K_EN 0x0001
297 #define BITM_SYS_CTL_OSC_1M_EN 0x0002
298 #define BITM_SYS_CTL_LFOSC_SEL 0x0004
299 #define BITM_SYS_CTL_RANDOM_SLEEP 0x0008
300 #define BITM_SYS_CTL_GO_SLEEP 0x0010
301 #define BITM_SYS_CTL_ALT_CLK_GPIO 0x00c0
302 #define BITM_SYS_CTL_ALT_CLOCKS 0x0300
303 #define BITM_SYS_CTL_SW_RESET 0x8000
304 
305 /* ADPD410X_REG_OPMODE */
306 #define BITP_OPMODE_OP_MODE 0
307 #define BITP_OPMODE_TIMESLOT_EN 8
308 #define BITM_OPMODE_OP_MODE 0x0001
309 #define BITM_OPMODE_TIMESLOT_EN 0x0f00
310 
311 /* ADPD410X_REG_STAMP_L */
312 #define BITP_STAMP_L_TIMESTAMP_COUNT_L 0
313 #define BITM_STAMP_L_TIMESTAMP_COUNT_L 0xffff
314 
315 /* ADPD410X_REG_STAMP_H */
316 #define BITP_STAMP_H_TIMESTAMP_COUNT_H 0
317 #define BITM_STAMP_H_TIMESTAMP_COUNT_H 0xffff
318 
319 /* ADPD410X_REG_STAMPDELTA */
320 #define BITP_STAMPDELTA_TIMESTAMP_SLOT_DELTA 0
321 #define BITM_STAMPDELTA_TIMESTAMP_SLOT_DELTA 0xffff
322 
323 /* ADPD410X_REG_INT_ENABLE_XD */
324 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_A 0
325 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_B 1
326 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_C 2
327 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_D 3
328 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_E 4
329 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_F 5
330 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_G 6
331 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_H 7
332 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_I 8
333 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_J 9
334 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_K 10
335 #define BITP_INT_ENABLE_XD_INTX_EN_DATA_L 11
336 #define BITP_INT_ENABLE_XD_INTX_EN_FIFO_OFLOW 13
337 #define BITP_INT_ENABLE_XD_INTX_EN_FIFO_UFLOW 14
338 #define BITP_INT_ENABLE_XD_INTX_EN_FIFO_TH 15
339 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_A 0x0001
340 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_B 0x0002
341 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_C 0x0004
342 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_D 0x0008
343 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_E 0x0010
344 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_F 0x0020
345 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_G 0x0040
346 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_H 0x0080
347 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_I 0x0100
348 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_J 0x0200
349 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_K 0x0400
350 #define BITM_INT_ENABLE_XD_INTX_EN_DATA_L 0x0800
351 #define BITM_INT_ENABLE_XD_INTX_EN_FIFO_OFLOW 0x2000
352 #define BITM_INT_ENABLE_XD_INTX_EN_FIFO_UFLOW 0x4000
353 #define BITM_INT_ENABLE_XD_INTX_EN_FIFO_TH 0x8000
354 
355 /* ADPD410X_REG_INT_ENABLE_YD */
356 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_A 0
357 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_B 1
358 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_C 2
359 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_D 3
360 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_E 4
361 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_F 5
362 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_G 6
363 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_H 7
364 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_I 8
365 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_J 9
366 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_K 10
367 #define BITP_INT_ENABLE_YD_INTY_EN_DATA_L 11
368 #define BITP_INT_ENABLE_YD_INTY_EN_FIFO_OFLOW 13
369 #define BITP_INT_ENABLE_YD_INTY_EN_FIFO_UFLOW 14
370 #define BITP_INT_ENABLE_YD_INTY_EN_FIFO_TH 15
371 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_A 0x0001
372 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_B 0x0002
373 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_C 0x0004
374 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_D 0x0008
375 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_E 0x0010
376 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_F 0x0020
377 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_G 0x0040
378 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_H 0x0080
379 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_I 0x0100
380 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_J 0x0200
381 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_K 0x0400
382 #define BITM_INT_ENABLE_YD_INTY_EN_DATA_L 0x0800
383 #define BITM_INT_ENABLE_YD_INTY_EN_FIFO_OFLOW 0x2000
384 #define BITM_INT_ENABLE_YD_INTY_EN_FIFO_UFLOW 0x4000
385 #define BITM_INT_ENABLE_YD_INTY_EN_FIFO_TH 0x8000
386 
387 /* ADPD410X_REG_INT_ENABLE_XL0 */
388 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_A 0
389 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_B 1
390 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_C 2
391 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_D 3
392 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_E 4
393 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_F 5
394 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_G 6
395 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_H 7
396 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_I 8
397 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_J 9
398 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_K 10
399 #define BITP_INT_ENABLE_XL0_INTX_EN_LEV0_L 11
400 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_A 0x0001
401 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_B 0x0002
402 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_C 0x0004
403 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_D 0x0008
404 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_E 0x0010
405 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_F 0x0020
406 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_G 0x0040
407 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_H 0x0080
408 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_I 0x0100
409 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_J 0x0200
410 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_K 0x0400
411 #define BITM_INT_ENABLE_XL0_INTX_EN_LEV0_L 0x0800
412 
413 /* ADPD410X_REG_INT_ENABLE_XL1 */
414 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_A 0
415 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_B 1
416 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_C 2
417 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_D 3
418 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_E 4
419 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_F 5
420 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_G 6
421 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_H 7
422 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_I 8
423 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_J 9
424 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_K 10
425 #define BITP_INT_ENABLE_XL1_INTX_EN_LEV1_L 11
426 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_A 0x0001
427 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_B 0x0002
428 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_C 0x0004
429 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_D 0x0008
430 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_E 0x0010
431 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_F 0x0020
432 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_G 0x0040
433 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_H 0x0080
434 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_I 0x0100
435 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_J 0x0200
436 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_K 0x0400
437 #define BITM_INT_ENABLE_XL1_INTX_EN_LEV1_L 0x0800
438 
439 /* ADPD410X_REG_INT_ENABLE_YL0 */
440 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_A 0
441 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_B 1
442 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_C 2
443 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_D 3
444 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_E 4
445 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_F 5
446 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_G 6
447 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_H 7
448 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_I 8
449 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_J 9
450 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_K 10
451 #define BITP_INT_ENABLE_YL0_INTY_EN_LEV0_L 11
452 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_A 0x0001
453 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_B 0x0002
454 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_C 0x0004
455 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_D 0x0008
456 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_E 0x0010
457 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_F 0x0020
458 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_G 0x0040
459 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_H 0x0080
460 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_I 0x0100
461 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_J 0x0200
462 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_K 0x0400
463 #define BITM_INT_ENABLE_YL0_INTY_EN_LEV0_L 0x0800
464 
465 /* ADPD410X_REG_INT_ENABLE_YL1 */
466 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_A 0
467 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_B 1
468 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_C 2
469 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_D 3
470 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_E 4
471 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_F 5
472 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_G 6
473 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_H 7
474 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_I 8
475 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_J 9
476 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_K 10
477 #define BITP_INT_ENABLE_YL1_INTY_EN_LEV1_L 11
478 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_A 0x0001
479 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_B 0x0002
480 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_C 0x0004
481 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_D 0x0008
482 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_E 0x0010
483 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_F 0x0020
484 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_G 0x0040
485 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_H 0x0080
486 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_I 0x0100
487 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_J 0x0200
488 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_K 0x0400
489 #define BITM_INT_ENABLE_YL1_INTY_EN_LEV1_L 0x0800
490 
491 /* ADPD410X_REG_FIFO_STATUS_BYTES */
492 #define BITP_FIFO_STATUS_BYTES_ENA_STAT_SUM 0
493 #define BITP_FIFO_STATUS_BYTES_ENA_STAT_D1 1
494 #define BITP_FIFO_STATUS_BYTES_ENA_STAT_D2 2
495 #define BITP_FIFO_STATUS_BYTES_ENA_STAT_L0 3
496 #define BITP_FIFO_STATUS_BYTES_ENA_STAT_L1 4
497 #define BITP_FIFO_STATUS_BYTES_ENA_STAT_LX 5
498 #define BITP_FIFO_STATUS_BYTES_ENA_STAT_TS1 6
499 #define BITP_FIFO_STATUS_BYTES_ENA_STAT_TS2 7
500 #define BITP_FIFO_STATUS_BYTES_ENA_STAT_TSX 8
501 #define BITM_FIFO_STATUS_BYTES_ENA_STAT_SUM 0x0001
502 #define BITM_FIFO_STATUS_BYTES_ENA_STAT_D1 0x0002
503 #define BITM_FIFO_STATUS_BYTES_ENA_STAT_D2 0x0004
504 #define BITM_FIFO_STATUS_BYTES_ENA_STAT_L0 0x0008
505 #define BITM_FIFO_STATUS_BYTES_ENA_STAT_L1 0x0010
506 #define BITM_FIFO_STATUS_BYTES_ENA_STAT_LX 0x0020
507 #define BITM_FIFO_STATUS_BYTES_ENA_STAT_TS1 0x0040
508 #define BITM_FIFO_STATUS_BYTES_ENA_STAT_TS2 0x0080
509 #define BITM_FIFO_STATUS_BYTES_ENA_STAT_TSX 0x0100
510 
511 /* ADPD410X_REG_INPUT_SLEEP */
512 #define BITP_INPUT_SLEEP_INP_SLEEP_12 0
513 #define BITP_INPUT_SLEEP_INP_SLEEP_34 4
514 #define BITP_INPUT_SLEEP_INP_SLEEP_56 8
515 #define BITP_INPUT_SLEEP_INP_SLEEP_78 12
516 #define BITM_INPUT_SLEEP_INP_SLEEP_12 0x000f
517 #define BITM_INPUT_SLEEP_INP_SLEEP_34 0x00f0
518 #define BITM_INPUT_SLEEP_INP_SLEEP_56 0x0f00
519 #define BITM_INPUT_SLEEP_INP_SLEEP_78 0xf000
520 
521 /* ADPD410X_REG_INPUT_CFG */
522 #define BITP_INPUT_CFG_PAIR12 0
523 #define BITP_INPUT_CFG_PAIR34 1
524 #define BITP_INPUT_CFG_PAIR56 2
525 #define BITP_INPUT_CFG_PAIR78 3
526 #define BITP_INPUT_CFG_VC1_SLEEP 4
527 #define BITP_INPUT_CFG_VC2_SLEEP 6
528 #define BITM_INPUT_CFG_PAIR12 0
529 #define BITM_INPUT_CFG_PAIR34 0x0002
530 #define BITM_INPUT_CFG_PAIR56 0x0004
531 #define BITM_INPUT_CFG_PAIR78 0x0008
532 #define BITM_INPUT_CFG_VC1_SLEEP 0x0030
533 #define BITM_INPUT_CFG_VC2_SLEEP 0x00c0
534 
535 /* ADPD410X_REG_GPIO_CFG */
536 #define BITP_GPIO_CFG_GPIO_PIN_CFG0 0
537 #define BITP_GPIO_CFG_GPIO_PIN_CFG1 3
538 #define BITP_GPIO_CFG_GPIO_PIN_CFG2 6
539 #define BITP_GPIO_CFG_GPIO_PIN_CFG3 9
540 #define BITP_GPIO_CFG_GPIO_DRV 12
541 #define BITP_GPIO_CFG_GPIO_SLEW 14
542 #define BITM_GPIO_CFG_GPIO_PIN_CFG0 0x0007
543 #define BITM_GPIO_CFG_GPIO_PIN_CFG1 0x0038
544 #define BITM_GPIO_CFG_GPIO_PIN_CFG2 0x01c0
545 #define BITM_GPIO_CFG_GPIO_PIN_CFG3 0x0e00
546 #define BITM_GPIO_CFG_GPIO_DRV 0x3000
547 #define BITM_GPIO_CFG_GPIO_SLEW 0xc000
548 
549 /* ADPD410X_REG_GPIO01 */
550 #define BITP_GPIO01_GPIOOUT0 0
551 #define BITP_GPIO01_GPIOOUT1 8
552 #define BITP_GPIO01_TIMESTAMP_INV 14
553 #define BITP_GPIO01_TIMESTAMP_ALWAYS_EN 15
554 #define BITM_GPIO01_GPIOOUT0 0x001f
555 #define BITM_GPIO01_GPIOOUT1 0x1f00
556 #define BITM_GPIO01_TIMESTAMP_INV 0x4000
557 #define BITM_GPIO01_TIMESTAMP_ALWAYS_EN 0x8000
558 
559 /* ADPD410X_REG_GPIO23 */
560 #define BITP_GPIO23_GPIOOUT2 0
561 #define BITP_GPIO23_GPIOOUT3 8
562 #define BITP_GPIO23_EXT_SYNC_EN 14
563 #define BITM_GPIO23_GPIOOUT2 0x001f
564 #define BITM_GPIO23_GPIOOUT3 0x1f00
565 #define BITM_GPIO23_EXT_SYNC_EN 0x4000
566 
567 /* ADPD410X_REG_GPIO_IN */
568 #define BITP_GPIO_IN_GPIO_INPUT 0
569 #define BITM_GPIO_IN_GPIO_INPUT 0x000f
570 
571 /* ADPD410X_REG_GPIO_EXT */
572 #define BITP_GPIO_EXT_EXT_SYNC_GPIO 0
573 #define BITP_GPIO_EXT_EXT_SYNC_EN 2
574 #define BITP_GPIO_EXT_TIMESTAMP_GPIO 4
575 #define BITP_GPIO_EXT_TIMESTAMP_ALWAYS_EN 6
576 #define BITP_GPIO_EXT_TIMESTAMP_INV 7
577 #define BITP_GPIO_EXT_TS_GPIO_SLEEP 8
578 #define BITM_GPIO_EXT_EXT_SYNC_GPIO 0x0003
579 #define BITM_GPIO_EXT_EXT_SYNC_EN 0x0004
580 #define BITM_GPIO_EXT_TIMESTAMP_GPIO 0x0030
581 #define BITM_GPIO_EXT_TIMESTAMP_ALWAYS_EN 0x0040
582 #define BITM_GPIO_EXT_TIMESTAMP_INV 0x0080
583 #define BITM_GPIO_EXT_TS_GPIO_SLEEP 0x0100
584 
585 /* ADPD410X_REG_DATA_HOLD_FLAG */
586 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_A 0
587 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_B 1
588 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_C 2
589 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_D 3
590 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_E 4
591 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_F 5
592 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_G 6
593 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_H 7
594 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_I 8
595 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_J 9
596 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_K 10
597 #define BITP_DATA_HOLD_FLAG_HOLD_REGS_L 11
598 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_A 0x0001
599 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_B 0x0002
600 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_C 0x0004
601 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_D 0x0008
602 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_E 0x0010
603 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_F 0x0020
604 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_G 0x0040
605 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_H 0x0080
606 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_I 0x0100
607 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_J 0x0200
608 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_K 0x0400
609 #define BITM_DATA_HOLD_FLAG_HOLD_REGS_L 0x0800
610 
611 /* ADPD410X_REG_FIFO_DATA */
612 #define BITP_FIFO_DATA_FIFO_DATA 0
613 #define BITM_FIFO_DATA_FIFO_DATA 0xffff
614 
615 /* ADPD410X_REG_SIGNAL1_L */
616 #define BITP_SIGNAL1_L_A_SIGNAL1_L 0
617 #define BITM_SIGNAL1_L_A_SIGNAL1_L 0xffff
618 
619 /* ADPD410X_REG_SIGNAL1_H */
620 #define BITP_SIGNAL1_H_A_SIGNAL1_H 0
621 #define BITM_SIGNAL1_H_A_SIGNAL1_H 0xffff
622 
623 /* ADPD410X_REG_SIGNAL2_L */
624 #define BITP_SIGNAL2_L_A_SIGNAL2_L 0
625 #define BITM_SIGNAL2_L_A_SIGNAL2_L 0xffff
626 
627 /* ADPD410X_REG_SIGNAL2_H */
628 #define BITP_SIGNAL2_H_A_SIGNAL2_H 0
629 #define BITM_SIGNAL2_H_A_SIGNAL2_H 0xffff
630 
631 /* ADPD410X_REG_DARK1_L */
632 #define BITP_DARK1_L_A_DARK1_L 0
633 #define BITM_DARK1_L_A_DARK1_L 0xffff
634 
635 /* ADPD410X_REG_DARK1_H */
636 #define BITP_DARK1_H_A_DARK1_H 0
637 #define BITM_DARK1_H_A_DARK1_H 0xffff
638 
639 /* ADPD410X_REG_DARK2_L */
640 #define BITP_DARK2_L_A_DARK2_L 0
641 #define BITM_DARK2_L_A_DARK2_L 0xffff
642 
643 /* ADPD410X_REG_DARK2_H */
644 #define BITP_DARK2_H_A_DARK2_H 0
645 #define BITM_DARK2_H_A_DARK2_H 0xffff
646 
647 /* ADPD410X_REG_IO_ADJUST */
648 #define BITP_IO_ADJUST_SPI_DRV 0
649 #define BITP_IO_ADJUST_SPI_SLEW 2
650 #define BITM_IO_ADJUST_SPI_DRV 0x0003
651 #define BITM_IO_ADJUST_SPI_SLEW 0x000c
652 
653 /* ADPD410X_REG_I2C_KEY */
654 #define BITP_I2C_KEY_I2C_KEY 0
655 #define BITP_I2C_KEY_I2C_KEY_MATCH 12
656 #define BITM_I2C_KEY_I2C_KEY 0x0fff
657 #define BITM_I2C_KEY_I2C_KEY_MATCH 0xf000
658 
659 /* ADPD410X_REG_I2C_ADDR */
660 #define BITP_I2C_ADDR_I2C_SLAVE_ADDR 1
661 #define BITP_I2C_ADDR_I2C_SLAVE_KEY2 8
662 #define BITM_I2C_ADDR_I2C_SLAVE_ADDR 0x00fe
663 #define BITM_I2C_ADDR_I2C_SLAVE_KEY2 0xff00
664 
665 /* ADPD410X_REG_TS_CTRL */
666 #define BITP_TS_CTRL_A_TIMESLOT_OFFSET 0
667 #define BITP_TS_CTRL_A_INPUT_R_SELECT 10
668 #define BITP_TS_CTRL_A_SAMPLE_TYPE 12
669 #define BITP_TS_CTRL_A_CH2_EN 14
670 #define BITP_TS_CTRL_A_SUBSAMPLE 15
671 #define BITM_TS_CTRL_A_TIMESLOT_OFFSET 0x03ff
672 #define BITM_TS_CTRL_A_INPUT_R_SELECT 0x0c00
673 #define BITM_TS_CTRL_A_SAMPLE_TYPE 0x3000
674 #define BITM_TS_CTRL_A_CH2_EN 0x4000
675 #define BITM_TS_CTRL_A_SUBSAMPLE 0x8000
676 
677 /* ADPD410X_REG_TS_PATH */
678 #define BITP_TS_PATH_A_AFE_PATH_CFG 0
679 #define BITP_TS_PATH_A_PRE_WIDTH 12
680 #define BITM_TS_PATH_A_AFE_PATH_CFG 0x01ff
681 #define BITM_TS_PATH_A_PRE_WIDTH 0xf000
682 
683 /* ADPD410X_REG_INPUTS */
684 #define BITP_INPUTS_A_INP12 0
685 #define BITP_INPUTS_A_INP34 4
686 #define BITP_INPUTS_A_INP56 8
687 #define BITP_INPUTS_A_INP78 12
688 #define BITM_INPUTS_A_INP12 0x000f
689 #define BITM_INPUTS_A_INP34 0x00f0
690 #define BITM_INPUTS_A_INP56 0x0f00
691 #define BITM_INPUTS_A_INP78 0xf000
692 
693 /* ADPD410X_REG_CATHODE */
694 #define BITP_CATHODE_A_VC1_SEL 0
695 #define BITP_CATHODE_A_VC1_ALT 2
696 #define BITP_CATHODE_A_VC1_PULSE 4
697 #define BITP_CATHODE_A_VC2_SEL 6
698 #define BITP_CATHODE_A_VC2_ALT 8
699 #define BITP_CATHODE_A_VC2_PULSE 10
700 #define BITP_CATHODE_A_PRECON 12
701 #define BITM_CATHODE_A_VC1_SEL 0x0003
702 #define BITM_CATHODE_A_VC1_ALT 0x000c
703 #define BITM_CATHODE_A_VC1_PULSE 0x0030
704 #define BITM_CATHODE_A_VC2_SEL 0x00c0
705 #define BITM_CATHODE_A_VC2_ALT 0x0300
706 #define BITM_CATHODE_A_VC2_PULSE 0x0c00
707 #define BITM_CATHODE_A_PRECON 0x7000
708 
709 /* ADPD410X_REG_AFE_TRIM */
710 #define BITP_AFE_TRIM_A_TIA_GAIN_CH1 0
711 #define BITP_AFE_TRIM_A_TIA_GAIN_CH2 3
712 #define BITP_AFE_TRIM_A_VREF_PULSE_VAL 6
713 #define BITP_AFE_TRIM_A_AFE_TRIM_VREF 8
714 #define BITP_AFE_TRIM_A_VREF_PULSE 10
715 #define BITP_AFE_TRIM_A_CH1_TRIM_INT 11
716 #define BITP_AFE_TRIM_A_CH2_TRIM_INT 13
717 #define BITP_AFE_TRIM_A_TIA_CEIL_DETECT_EN 15
718 #define BITM_AFE_TRIM_A_TIA_GAIN_CH1 0x0007
719 #define BITM_AFE_TRIM_A_TIA_GAIN_CH2 0x0038
720 #define BITM_AFE_TRIM_A_VREF_PULSE_VAL 0x00c0
721 #define BITM_AFE_TRIM_A_AFE_TRIM_VREF 0x0300
722 #define BITM_AFE_TRIM_A_VREF_PULSE 0x0400
723 #define BITM_AFE_TRIM_A_CH1_TRIM_INT 0x1800
724 #define BITM_AFE_TRIM_A_CH2_TRIM_INT 0x6000
725 #define BITM_AFE_TRIM_A_TIA_CEIL_DETECT_EN 0x8000
726 
727 /* ADPD410X_REG_LED_POW12 */
728 #define BITP_LED_POW12_A_LED_CURRENT1 0
729 #define BITP_LED_POW12_A_LED_DRIVESIDE1 7
730 #define BITP_LED_POW12_A_LED_CURRENT2 8
731 #define BITP_LED_POW12_A_LED_DRIVESIDE2 15
732 #define BITM_LED_POW12_A_LED_CURRENT1 0x007f
733 #define BITM_LED_POW12_A_LED_DRIVESIDE1 0x0080
734 #define BITM_LED_POW12_A_LED_CURRENT2 0x7f00
735 #define BITM_LED_POW12_A_LED_DRIVESIDE2 0x8000
736 
737 /* ADPD410X_REG_LED_POW34 */
738 #define BITP_LED_POW34_A_LED_CURRENT3 0
739 #define BITP_LED_POW34_A_LED_DRIVESIDE3 7
740 #define BITP_LED_POW34_A_LED_CURRENT4 8
741 #define BITP_LED_POW34_A_LED_DRIVESIDE4 15
742 #define BITM_LED_POW34_A_LED_CURRENT3 0x007f
743 #define BITM_LED_POW34_A_LED_DRIVESIDE3 0x0080
744 #define BITM_LED_POW34_A_LED_CURRENT4 0x7f00
745 #define BITM_LED_POW34_A_LED_DRIVESIDE4 0x8000
746 
747 /* ADPD410X_REG_COUNTS */
748 #define BITP_COUNTS_A_NUM_REPEAT 0
749 #define BITP_COUNTS_A_NUM_INT 8
750 #define BITM_COUNTS_A_NUM_REPEAT 0x00ff
751 #define BITM_COUNTS_A_NUM_INT 0xff00
752 
753 /* ADPD410X_REG_PERIOD */
754 #define BITP_PERIOD_A_MIN_PERIOD 0
755 #define BITP_PERIOD_A_MOD_TYPE 12
756 #define BITM_PERIOD_A_MIN_PERIOD 0x03ff
757 #define BITM_PERIOD_A_MOD_TYPE 0x3000
758 
759 /* ADPD410X_REG_LED_PULSE */
760 #define BITP_LED_PULSE_A_LED_OFFSET 0
761 #define BITP_LED_PULSE_A_LED_WIDTH 8
762 #define BITM_LED_PULSE_A_LED_OFFSET 0x00ff
763 #define BITM_LED_PULSE_A_LED_WIDTH 0xff00
764 
765 /* ADPD410X_REG_INTEG_WIDTH */
766 #define BITP_INTEG_WIDTH_A_INTEG_WIDTH 0
767 #define BITP_INTEG_WIDTH_A_ADC_COUNT 6
768 #define BITP_INTEG_WIDTH_A_CH1_AMP_DISABLE 8
769 #define BITP_INTEG_WIDTH_A_AFE_INT_C_BUF 11
770 #define BITP_INTEG_WIDTH_A_CH2_AMP_DISABLE 12
771 #define BITP_INTEG_WIDTH_A_SINGLE_INTEG 15
772 #define BITM_INTEG_WIDTH_A_INTEG_WIDTH 0x001f
773 #define BITM_INTEG_WIDTH_A_ADC_COUNT 0x00c0
774 #define BITM_INTEG_WIDTH_A_CH1_AMP_DISABLE 0x0700
775 #define BITM_INTEG_WIDTH_A_AFE_INT_C_BUF 0x0800
776 #define BITM_INTEG_WIDTH_A_CH2_AMP_DISABLE 0x7000
777 #define BITM_INTEG_WIDTH_A_SINGLE_INTEG 0x8000
778 
779 /* ADPD410X_REG_INTEG_OFFSET */
780 #define BITP_INTEG_OFFSET_A_INTEG_OFFSET 0
781 #define BITM_INTEG_OFFSET_A_INTEG_OFFSET 0x1fff
782 #define BITP_INTEG_OFFSET_A_INTEG_OFFSET_UPPER 5
783 #define BITM_INTEG_OFFSET_A_INTEG_OFFSET_UPPER 0xff
784 
785 /* ADPD410X_REG_MOD_PULSE */
786 #define BITP_MOD_PULSE_A_MOD_OFFSET 0
787 #define BITP_MOD_PULSE_A_MOD_WIDTH 8
788 #define BITM_MOD_PULSE_A_MOD_OFFSET 0x00ff
789 #define BITM_MOD_PULSE_A_MOD_WIDTH 0xff00
790 
791 /* ADPD410X_REG_PATTERN */
792 #define BITP_PATTERN_A_REVERSE_INTEG 0
793 #define BITP_PATTERN_A_SUBTRACT 4
794 #define BITP_PATTERN_A_MOD_DISABLE 8
795 #define BITP_PATTERN_A_LED_DISABLE 12
796 #define BITM_PATTERN_A_REVERSE_INTEG 0x000f
797 #define BITM_PATTERN_A_SUBTRACT 0x00f0
798 #define BITM_PATTERN_A_MOD_DISABLE 0x0f00
799 #define BITM_PATTERN_A_LED_DISABLE 0xf000
800 
801 /* ADPD410X_REG_ADC_OFF1 */
802 #define BITP_ADC_OFF1_A_CH1_ADC_ADJUST 0
803 #define BITM_ADC_OFF1_A_CH1_ADC_ADJUST 0x3fff
804 
805 /* ADPD410X_REG_ADC_OFF2 */
806 #define BITP_ADC_OFF2_A_CH2_ADC_ADJUST 0
807 #define BITP_ADC_OFF2_A_ZERO_ADJUST 15
808 #define BITM_ADC_OFF2_A_CH2_ADC_ADJUST 0x3fff
809 #define BITM_ADC_OFF2_A_ZERO_ADJUST 0x8000
810 
811 /* ADPD410X_REG_DATA1 */
812 #define BITP_DATA1_A_SIGNAL_SIZE 0
813 #define BITP_DATA1_A_SIGNAL_SHIFT 3
814 #define BITP_DATA1_A_DARK_SIZE 8
815 #define BITP_DATA1_A_DARK_SHIFT 11
816 #define BITM_DATA1_A_SIGNAL_SIZE 0x0007
817 #define BITM_DATA1_A_SIGNAL_SHIFT 0x00f8
818 #define BITM_DATA1_A_DARK_SIZE 0x0700
819 #define BITM_DATA1_A_DARK_SHIFT 0xf800
820 
821 /* ADPD410X_REG_DATA2 */
822 #define BITP_DATA2_A_LIT_SIZE 0
823 #define BITP_DATA2_A_LIT_SHIFT 3
824 #define BITM_DATA2_A_LIT_SIZE 0x0007
825 #define BITM_DATA2_A_LIT_SHIFT 0x00f8
826 
827 /* ADPD410X_REG_DECIMATE */
828 #define BITP_DECIMATE_A_DECIMATE_TYPE 0
829 #define BITP_DECIMATE_A_DECIMATE_FACTOR 4
830 #define BITM_DECIMATE_A_DECIMATE_TYPE 0x000f
831 #define BITM_DECIMATE_A_DECIMATE_FACTOR 0x07f0
832 
833 /* ADPD410X_REG_DIGINT_LIT */
834 #define BITP_DIGINT_LIT_A_LIT_OFFSET 0
835 #define BITM_DIGINT_LIT_A_LIT_OFFSET 0x01ff
836 
837 /* ADPD410X_REG_DIGINT_DARK */
838 #define BITP_DIGINT_DARK_A_DARK1_OFFSET 0
839 #define BITP_DIGINT_DARK_A_DARK2_OFFSET 7
840 #define BITM_DIGINT_DARK_A_DARK1_OFFSET 0x007f
841 #define BITM_DIGINT_DARK_A_DARK2_OFFSET 0xff80
842 
843 /* ADPD410X_REG_THRESH_CFG */
844 #define BITP_THRESH_CFG_A_THRESH0_TYPE 0
845 #define BITP_THRESH_CFG_A_THRESH0_DIR 2
846 #define BITP_THRESH_CFG_A_THRESH0_CHAN 3
847 #define BITP_THRESH_CFG_A_THRESH1_TYPE 4
848 #define BITP_THRESH_CFG_A_THRESH1_DIR 6
849 #define BITP_THRESH_CFG_A_THRESH1_CHAN 7
850 #define BITM_THRESH_CFG_A_THRESH0_TYPE 0x0003
851 #define BITM_THRESH_CFG_A_THRESH0_DIR 0x0004
852 #define BITM_THRESH_CFG_A_THRESH0_CHAN 0x0008
853 #define BITM_THRESH_CFG_A_THRESH1_TYPE 0x0030
854 #define BITM_THRESH_CFG_A_THRESH1_DIR 0x0040
855 #define BITM_THRESH_CFG_A_THRESH1_CHAN 0x0080
856 
857 /* ADPD410X_REG_THRESH0 */
858 #define BITP_THRESH0_A_THRESH0_VALUE 0
859 #define BITP_THRESH0_A_THRESH0_SHIFT 8
860 #define BITM_THRESH0_A_THRESH0_VALUE 0x00ff
861 #define BITM_THRESH0_A_THRESH0_SHIFT 0x1f00
862 
863 /* ADPD410X_REG_THRESH1 */
864 #define BITP_THRESH1_A_THRESH1_VALUE 0
865 #define BITP_THRESH1_A_THRESH1_SHIFT 8
866 #define BITM_THRESH1_A_THRESH1_VALUE 0x00ff
867 #define BITM_THRESH1_A_THRESH1_SHIFT 0x1f00
868 
869 #define ADPD410X_LOW_FREQ_OSCILLATOR_FREQ1 1000000
870 #define ADPD410X_LOW_FREQ_OSCILLATOR_FREQ2 32768
871 #define ADPD410X_HIGH_FREQ_OSCILLATOR_FREQ 32000000
872 
873 #define ADPD410X_MAX_SLOT_NUMBER 12
874 #define ADPD410X_LED_CURR_LSB 1.333
875 #define ADPD410X_MAX_NUM_INT 255
876 #define ADPD410X_MAX_PULSE_LENGTH 255
877 #define ADPD410X_MAX_INTEG_OS 255
878 #define ADPD410X_FIFO_DEPTH 512
879 #define ADPD410X_MAX_SAMPLING_FREQ 9000
880 
881 #define ADPD410X_UPPDER_BYTE_SPI_MASK 0x7f80
882 #define ADPD410X_LOWER_BYTE_SPI_MASK 0xfe
883 #define ADPD410X_UPPDER_BYTE_I2C_MASK 0x7f00
884 #define ADPD410X_LOWER_BYTE_I2C_MASK 0xff
885 
886 /******************************************************************************/
887 /*************************** Types Declarations *******************************/
888 /******************************************************************************/
889 
899 };
900 
910 };
911 
919 };
920 
930 };
931 
945 };
946 
970 };
971 
981 };
982 
1002 };
1003 
1017 };
1018 
1034 };
1035 
1045 };
1046 
1053  uint8_t let_current_select : 7;
1056 };
1057 
1066  uint8_t value;
1067 };
1068 
1098 };
1099 
1124  uint8_t byte_no;
1126  uint8_t dec_factor;
1136  uint8_t adc_cycles;
1138  uint8_t repeats_no;
1139 };
1140 
1155 };
1156 
1177  uint32_t ext_lfo_freq;
1178 };
1179 
1200  uint32_t ext_lfo_freq;
1201 };
1202 
1203 /******************************************************************************/
1204 /************************ Functions Declarations ******************************/
1205 /******************************************************************************/
1206 
1208 int32_t adpd410x_reg_read(struct adpd410x_dev *dev, uint16_t address,
1209  uint16_t *data);
1210 
1212 int32_t adpd410x_reg_read_bytes(struct adpd410x_dev *dev, uint16_t address,
1213  uint8_t *data, uint16_t num_bytes);
1214 
1216 int32_t adpd410x_reg_write(struct adpd410x_dev *dev, uint16_t address,
1217  uint16_t data);
1218 
1220 int32_t adpd410x_reg_write_mask(struct adpd410x_dev *dev, uint16_t address,
1221  uint16_t data, uint16_t mask);
1222 
1224 int32_t adpd410x_reset(struct adpd410x_dev *dev);
1225 
1227 int32_t adpd410x_set_opmode(struct adpd410x_dev *dev,
1228  enum adpd410x_opmode mode);
1229 
1231 int32_t adpd410x_get_opmode(struct adpd410x_dev *dev,
1232  enum adpd410x_opmode *mode);
1233 
1235 int32_t adpd410x_set_last_timeslot(struct adpd410x_dev *dev,
1236  uint8_t timeslot_no);
1237 
1239 int32_t adpd410x_get_last_timeslot(struct adpd410x_dev *dev,
1240  enum adpd410x_timeslots *timeslot_no);
1241 
1243 int32_t adpd410x_set_sampling_freq(struct adpd410x_dev *dev,
1244  uint32_t sampling_freq);
1245 
1247 int32_t adpd410x_get_sampling_freq(struct adpd410x_dev *dev,
1248  uint32_t *sampling_freq);
1249 
1251 int32_t adpd410x_timeslot_setup(struct adpd410x_dev *dev,
1252  enum adpd410x_timeslots timeslot_no,
1253  struct adpd410x_timeslot_init *init);
1254 
1256 int32_t adpd410x_get_fifo_bytecount(struct adpd410x_dev *dev, uint16_t *bytes);
1257 
1259 int32_t adpd410x_read_fifo(struct adpd410x_dev *dev, uint32_t *data,
1260  uint16_t num_samples,
1261  uint8_t datawidth);
1262 
1265 int32_t adpd410x_get_data(struct adpd410x_dev *dev, uint32_t *data);
1266 
1268 int32_t adpd410x_setup(struct adpd410x_dev **device,
1270 
1272 int32_t adpd410x_remove(struct adpd410x_dev *dev);
1273 
1274 #endif /* ADPD410X_H_ */
ADPD410X_INP34
@ ADPD410X_INP34
Definition: adpd410x.h:940
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
phy_comm_dev::i2c_phy_dev
struct no_os_i2c_desc * i2c_phy_dev
Definition: adpd410x.h:898
adpd410x_timeslot_init::pulse4_reverse
uint8_t pulse4_reverse
Definition: adpd410x.h:1120
ADPD410X_SHORT_INS
@ ADPD410X_SHORT_INS
Definition: adpd410x.h:1001
BITM_INT_STATUS_FIFO_FIFO_BYTE_COUNT
#define BITM_INT_STATUS_FIFO_FIFO_BYTE_COUNT
Definition: adpd410x.h:131
ADPD410X_INaCH2_INbCH1
@ ADPD410X_INaCH2_INbCH1
Definition: adpd410x.h:965
_adpd410x_led_control::led_output_select
enum adpd410x_led_output_opt led_output_select
Definition: adpd410x.h:1055
BITM_SYS_CTL_ALT_CLOCKS
#define BITM_SYS_CTL_ALT_CLOCKS
Definition: adpd410x.h:302
ADPD410X_GENLFO_EXTHFO
@ ADPD410X_GENLFO_EXTHFO
Definition: adpd410x.h:1154
no_os_i2c_write
int32_t no_os_i2c_write(struct no_os_i2c_desc *desc, uint8_t *data, uint8_t bytes_number, uint8_t stop_bit)
I2C Write data to slave device.
Definition: no_os_i2c.c:85
ADPD410X_INP78
@ ADPD410X_INP78
Definition: adpd410x.h:944
ADPD410X_FLOAT_INS
@ ADPD410X_FLOAT_INS
Definition: adpd410x.h:989
no_os_i2c_init
int32_t no_os_i2c_init(struct no_os_i2c_desc **desc, const struct no_os_i2c_init_param *param)
Initialize the I2C communication peripheral.
Definition: no_os_i2c.c:51
phy_comm_dev::spi_phy_dev
struct no_os_spi_desc * spi_phy_dev
Definition: adpd410x.h:896
ADPD410X_TS_E
@ ADPD410X_TS_E
Definition: adpd410x.h:1083
ADPD410X_INaDIS_INbCH1
@ ADPD410X_INaDIS_INbCH1
Definition: adpd410x.h:959
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
ADPD410X_TS_D
@ ADPD410X_TS_D
Definition: adpd410x.h:1081
ADPD410X_INP56
@ ADPD410X_INP56
Definition: adpd410x.h:942
sampling_freq
uint64_t sampling_freq
Definition: headless.c:78
adpd410x_led_control::value
uint8_t value
Definition: adpd410x.h:1066
ADPD410X_TIA_VREF_100K
@ ADPD410X_TIA_VREF_100K
Definition: adpd410x.h:1027
ADPD410X_INaCH1_INbCH1
@ ADPD410X_INaCH1_INbCH1
Definition: adpd410x.h:967
NO_OS_GPIO_HIGH_Z
@ NO_OS_GPIO_HIGH_Z
Definition: no_os_gpio.h:125
ADPD410X_TIA_VREF_1V256
@ ADPD410X_TIA_VREF_1V256
Definition: adpd410x.h:1016
adpd410x_dev::gpio1
struct no_os_gpio_desc * gpio1
Definition: adpd410x.h:1194
adpd410x_timeslot_init::dec_factor
uint8_t dec_factor
Definition: adpd410x.h:1126
no_os_spi.h
Header file of SPI Interface.
adpd410x_timeslot_init::byte_no
uint8_t byte_no
Definition: adpd410x.h:1124
BITP_LED_POW34_A_LED_CURRENT4
#define BITP_LED_POW34_A_LED_CURRENT4
Definition: adpd410x.h:740
ADPD410X_REG_TS_FREQH
#define ADPD410X_REG_TS_FREQH
Definition: adpd410x.h:67
adpd410x_get_opmode
int32_t adpd410x_get_opmode(struct adpd410x_dev *dev, enum adpd410x_opmode *mode)
Get operation mode.
Definition: adpd410x.c:249
adpd410x_timeslot_init::ts_inputs
struct adpd410x_ts_inputs ts_inputs
Definition: adpd410x.h:1108
ADPD410X_TS_L
@ ADPD410X_TS_L
Definition: adpd410x.h:1097
ADPD410X_VC2
@ ADPD410X_VC2
Definition: adpd410x.h:993
no_os_i2c_remove
int32_t no_os_i2c_remove(struct no_os_i2c_desc *desc)
Free the resources allocated by no_os_i2c_init().
Definition: no_os_i2c.c:70
adpd410x_init_param::dev_ops_init
union phy_comm_init_param dev_ops_init
Definition: adpd410x.h:1163
adpd410x_timeslot_init::led4
union adpd410x_led_control led4
Definition: adpd410x.h:1132
BITM_TS_CTRL_A_CH2_EN
#define BITM_TS_CTRL_A_CH2_EN
Definition: adpd410x.h:674
ADPD410X_REG_TS_FREQ
#define ADPD410X_REG_TS_FREQ
Definition: adpd410x.h:66
BITP_AFE_TRIM_A_TIA_GAIN_CH1
#define BITP_AFE_TRIM_A_TIA_GAIN_CH1
Definition: adpd410x.h:710
adpd410x_timeslot_init
Initialization structure for time slots.
Definition: adpd410x.h:1104
adpd410x_ts_inputs::pair
enum adpd410x_ts_input_pair pair
Definition: adpd410x.h:978
adpd410x_timeslot_init::led1
union adpd410x_led_control led1
Definition: adpd410x.h:1130
ADPD410X_TS_J
@ ADPD410X_TS_J
Definition: adpd410x.h:1093
ADPD410X_TS_A
@ ADPD410X_TS_A
Definition: adpd410x.h:1075
ADPD410X_TIA_VREF_12K5
@ ADPD410X_TIA_VREF_12K5
Definition: adpd410x.h:1033
ADPD410X_REG_FIFO_DATA
#define ADPD410X_REG_FIFO_DATA
Definition: adpd410x.h:88
phy_comm_init_param::i2c_phy_init
struct no_os_i2c_init_param i2c_phy_init
Definition: adpd410x.h:909
adpd410x_set_opmode
int32_t adpd410x_set_opmode(struct adpd410x_dev *dev, enum adpd410x_opmode mode)
Set operation mode.
Definition: adpd410x.c:236
adpd410x_init_param::gpio2
struct no_os_gpio_init_param gpio2
Definition: adpd410x.h:1173
ADPD410X_GOMODE
@ ADPD410X_GOMODE
Definition: adpd410x.h:929
phy_comm_init_param
Contains physical communication initialization structure.
Definition: adpd410x.h:905
adpd410x_ts_inputs
Structure holding time slot input configuration.
Definition: adpd410x.h:976
device
Definition: ad9361_util.h:75
adpd410x_dev::gpio0
struct no_os_gpio_desc * gpio0
Definition: adpd410x.h:1192
ADPD410X_UPPDER_BYTE_SPI_MASK
#define ADPD410X_UPPDER_BYTE_SPI_MASK
Definition: adpd410x.h:881
NO_OS_GPIO_HIGH
@ NO_OS_GPIO_HIGH
Definition: no_os_gpio.h:123
adpd410x_timeslot_init::chan1
enum adpd410x_tia_vref_ref chan1
Definition: adpd410x.h:1116
adpd410x_remove
int32_t adpd410x_remove(struct adpd410x_dev *dev)
Free memory allocated by adpd410x_setup().
Definition: adpd410x.c:772
adpd410x_setup
int32_t adpd410x_setup(struct adpd410x_dev **device, struct adpd410x_init_param *init_param)
Setup the device and the driver.
Definition: adpd410x.c:661
ADPD410X_TIA_VREF_200K
@ ADPD410X_TIA_VREF_200K
Definition: adpd410x.h:1025
ADPD410X_TS_I
@ ADPD410X_TS_I
Definition: adpd410x.h:1091
adpd410x_led_control::fields
struct _adpd410x_led_control fields
Definition: adpd410x.h:1064
adpd410x_init_param::gpio0
struct no_os_gpio_init_param gpio0
Definition: adpd410x.h:1169
adpd410x_init_param::gpio3
struct no_os_gpio_init_param gpio3
Definition: adpd410x.h:1175
adpd410x_timeslot_init::chan2
enum adpd410x_tia_vref_ref chan2
Definition: adpd410x.h:1118
_adpd410x_led_control::let_current_select
uint8_t let_current_select
Definition: adpd410x.h:1053
BITM_SYS_CTL_OSC_1M_EN
#define BITM_SYS_CTL_OSC_1M_EN
Definition: adpd410x.h:297
ADPD410X_TIA_VREF_25K
@ ADPD410X_TIA_VREF_25K
Definition: adpd410x.h:1031
ADPD410X_TIA_VREF
@ ADPD410X_TIA_VREF
Definition: adpd410x.h:999
adpd410x_timeslot_setup
int32_t adpd410x_timeslot_setup(struct adpd410x_dev *dev, enum adpd410x_timeslots timeslot_no, struct adpd410x_timeslot_init *init)
Setup an active time slot.
Definition: adpd410x.c:382
adpd410x_supported_dev
adpd410x_supported_dev
Devices supported by the driver.
Definition: adpd410x.h:916
adpd410x_tia_vref_volt
adpd410x_tia_vref_volt
TIA reference voltage options.
Definition: adpd410x.h:1008
ADPD410X_OUTPUT_B
@ ADPD410X_OUTPUT_B
Definition: adpd410x.h:1044
ADPD410X_LOWER_BYTE_I2C_MASK
#define ADPD410X_LOWER_BYTE_I2C_MASK
Definition: adpd410x.h:884
ADPD410X_TIA_VREF_0V8855
@ ADPD410X_TIA_VREF_0V8855
Definition: adpd410x.h:1014
adpd410x_precon_opt
adpd410x_precon_opt
Time slot input precondition options.
Definition: adpd410x.h:987
ADPD410X_FIFO_DEPTH
#define ADPD410X_FIFO_DEPTH
Definition: adpd410x.h:878
ADPD410X_REG_DATA1
#define ADPD410X_REG_DATA1(ts)
Definition: adpd410x.h:116
adpd410x_read_fifo
int32_t adpd410x_read_fifo(struct adpd410x_dev *dev, uint32_t *data, uint16_t num_samples, uint8_t datawidth)
Reads a certain number of bytes from the fifo and stores in data Used to read a large amount of data ...
Definition: adpd410x.c:563
adpd410x_set_last_timeslot
int32_t adpd410x_set_last_timeslot(struct adpd410x_dev *dev, enum adpd410x_timeslots timeslot_no)
Set number of active time slots.
Definition: adpd410x.c:270
adpd410x_led_output_opt
adpd410x_led_output_opt
LED output option.
Definition: adpd410x.h:1040
adpd410x_timeslot_init::enable_ch2
bool enable_ch2
Definition: adpd410x.h:1106
adpd410x_dev::clk_opt
enum adpd410x_clk_opt clk_opt
Definition: adpd410x.h:1190
ADPD410X_VICM
@ ADPD410X_VICM
Definition: adpd410x.h:995
BITP_DECIMATE_A_DECIMATE_FACTOR
#define BITP_DECIMATE_A_DECIMATE_FACTOR
Definition: adpd410x.h:829
no_os_error.h
Error codes definition.
adpd410x_setup
int32_t adpd410x_setup(struct adpd410x_dev **device, struct adpd410x_init_param *init_param)
Setup the device and the driver.
Definition: adpd410x.c:661
adpd410x_reg_write
int32_t adpd410x_reg_write(struct adpd410x_dev *dev, uint16_t address, uint16_t data)
Write device register.
Definition: adpd410x.c:143
ADPD410X_TS_G
@ ADPD410X_TS_G
Definition: adpd410x.h:1087
ADPD410X_INaCH2_INbDIS
@ ADPD410X_INaCH2_INbDIS
Definition: adpd410x.h:957
adpd410x_dev
Device driver handler.
Definition: adpd410x.h:1184
ADPD410X_INaDIS_INbCH2
@ ADPD410X_INaDIS_INbCH2
Definition: adpd410x.h:961
ADPD410X_TIA_VREF_1V1385
@ ADPD410X_TIA_VREF_1V1385
Definition: adpd410x.h:1010
BITM_SYS_CTL_LFOSC_SEL
#define BITM_SYS_CTL_LFOSC_SEL
Definition: adpd410x.h:298
adpd410x_get_fifo_bytecount
int32_t adpd410x_get_fifo_bytecount(struct adpd410x_dev *dev, uint16_t *bytes)
Get number of bytes in the device FIFO.
Definition: adpd410x.c:484
ADPD410X_REG_CHIP_ID
#define ADPD410X_REG_CHIP_ID
Definition: adpd410x.h:61
adpd410x_get_last_timeslot
int32_t adpd410x_get_last_timeslot(struct adpd410x_dev *dev, enum adpd410x_timeslots *timeslot_no)
Get number of active time slots.
Definition: adpd410x.c:283
adpd410x_timeslot_init::led2
union adpd410x_led_control led2
Definition: adpd410x.h:1128
ADPD410X_INaCH2_INbCH2
@ ADPD410X_INaCH2_INbCH2
Definition: adpd410x.h:969
ADPD410X_TIA_VREF_1V012
@ ADPD410X_TIA_VREF_1V012
Definition: adpd410x.h:1012
adpd410x_ts_inputs::option
enum adpd410x_ts_input_opt option
Definition: adpd410x.h:980
ADPD410X_OUTPUT_A
@ ADPD410X_OUTPUT_A
Definition: adpd410x.h:1042
adpd410x_remove
int32_t adpd410x_remove(struct adpd410x_dev *dev)
Free memory allocated by adpd410x_setup().
Definition: adpd410x.c:772
adpd410x_read_fifo
int32_t adpd410x_read_fifo(struct adpd410x_dev *dev, uint32_t *data, uint16_t num_samples, uint8_t datawidth)
Reads a certain number of bytes from the fifo and stores in data Used to read a large amount of data ...
Definition: adpd410x.c:563
adpd410x_get_last_timeslot
int32_t adpd410x_get_last_timeslot(struct adpd410x_dev *dev, enum adpd410x_timeslots *timeslot_no)
Get number of active time slots.
Definition: adpd410x.c:283
adpd410x_timeslots
adpd410x_timeslots
Available Time slots.
Definition: adpd410x.h:1073
BITP_AFE_TRIM_A_AFE_TRIM_VREF
#define BITP_AFE_TRIM_A_AFE_TRIM_VREF
Definition: adpd410x.h:713
adpd410x_timeslot_init::repeats_no
uint8_t repeats_no
Definition: adpd410x.h:1138
BITP_PATTERN_A_SUBTRACT
#define BITP_PATTERN_A_SUBTRACT
Definition: adpd410x.h:793
adpd410x_dev::dev_type
enum adpd410x_supported_dev dev_type
Definition: adpd410x.h:1188
BITP_OPMODE_TIMESLOT_EN
#define BITP_OPMODE_TIMESLOT_EN
Definition: adpd410x.h:307
BITP_SYS_CTL_LFOSC_SEL
#define BITP_SYS_CTL_LFOSC_SEL
Definition: adpd410x.h:290
adpd410x_timeslot_init::adc_cycles
uint8_t adc_cycles
Definition: adpd410x.h:1136
ADPD410X_TIA_IN
@ ADPD410X_TIA_IN
Definition: adpd410x.h:997
ADPD410X_INTLFO_INTHFO
@ ADPD410X_INTLFO_INTHFO
Definition: adpd410x.h:1147
adpd410x_set_sampling_freq
int32_t adpd410x_set_sampling_freq(struct adpd410x_dev *dev, uint32_t sampling_freq)
Set device sampling frequency.
Definition: adpd410x.c:304
adpd410x_set_last_timeslot
int32_t adpd410x_set_last_timeslot(struct adpd410x_dev *dev, uint8_t timeslot_no)
no_os_gpio_remove
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:95
adpd410x_reset
int32_t adpd410x_reset(struct adpd410x_dev *dev)
Do a software reset.
Definition: adpd410x.c:218
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
ADPD410X_REG_PATTERN
#define ADPD410X_REG_PATTERN(ts)
Definition: adpd410x.h:113
adpd410x_dev::ext_lfo_freq
uint32_t ext_lfo_freq
Definition: adpd410x.h:1200
BITP_AFE_TRIM_A_VREF_PULSE_VAL
#define BITP_AFE_TRIM_A_VREF_PULSE_VAL
Definition: adpd410x.h:712
ADPD410X_STANDBY
@ ADPD410X_STANDBY
Definition: adpd410x.h:927
ADPD410X_INP12
@ ADPD410X_INP12
Definition: adpd410x.h:938
ADPD410X_REG_LED_POW34
#define ADPD410X_REG_LED_POW34(ts)
Definition: adpd410x.h:106
adpd410x_get_fifo_bytecount
int32_t adpd410x_get_fifo_bytecount(struct adpd410x_dev *dev, uint16_t *bytes)
Get number of bytes in the device FIFO.
Definition: adpd410x.c:484
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
ADPD410X_INTLFO_EXTHFO
@ ADPD410X_INTLFO_EXTHFO
Definition: adpd410x.h:1151
ADPD410X_TIA_VREF_50K
@ ADPD410X_TIA_VREF_50K
Definition: adpd410x.h:1029
ADPD410X_REG_COUNTS
#define ADPD410X_REG_COUNTS(ts)
Definition: adpd410x.h:107
BITP_COUNTS_A_NUM_INT
#define BITP_COUNTS_A_NUM_INT
Definition: adpd410x.h:749
ADPD410X_CHIP_ID
#define ADPD410X_CHIP_ID
Definition: adpd410x.h:255
ADPD410X_REG_TS_CTRL
#define ADPD410X_REG_TS_CTRL(ts)
Definition: adpd410x.h:100
adpd410x_timeslot_init::pulse4_subtract
uint8_t pulse4_subtract
Definition: adpd410x.h:1122
adpd410x_led_control
Union of the LED mapping and value so they can be accessed both ways.
Definition: adpd410x.h:1062
ADPD4101
@ ADPD4101
Definition: adpd410x.h:918
adpd410x_opmode
adpd410x_opmode
Operation modes of the device.
Definition: adpd410x.h:925
adpd410x_reg_read_bytes
int32_t adpd410x_reg_read_bytes(struct adpd410x_dev *dev, uint16_t address, uint8_t *data, uint16_t num_bytes)
Read a specified number of bytes from device register.
Definition: adpd410x.c:86
ADPD410X_LOW_FREQ_OSCILLATOR_FREQ2
#define ADPD410X_LOW_FREQ_OSCILLATOR_FREQ2
Definition: adpd410x.h:870
no_os_i2c_desc
Structure holding I2C descriptor.
Definition: no_os_i2c.h:81
no_os_gpio_get
int32_t no_os_gpio_get(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Obtain the GPIO decriptor.
Definition: no_os_gpio.c:55
BITM_OPMODE_TIMESLOT_EN
#define BITM_OPMODE_TIMESLOT_EN
Definition: adpd410x.h:309
ADPD410X_UPPDER_BYTE_I2C_MASK
#define ADPD410X_UPPDER_BYTE_I2C_MASK
Definition: adpd410x.h:883
no_os_i2c_read
int32_t no_os_i2c_read(struct no_os_i2c_desc *desc, uint8_t *data, uint8_t bytes_number, uint8_t stop_bit)
I2C Read data from slave device.
Definition: no_os_i2c.c:104
adpd410x_init_param::gpio1
struct no_os_gpio_init_param gpio1
Definition: adpd410x.h:1171
no_os_i2c.h
Header file of I2C Interface.
adpd410x_init_param::ext_lfo_freq
uint32_t ext_lfo_freq
Definition: adpd410x.h:1177
adpd410x_tia_vref_ref
adpd410x_tia_vref_ref
TIA resistor gain setting.
Definition: adpd410x.h:1023
BITM_SYS_CTL_SW_RESET
#define BITM_SYS_CTL_SW_RESET
Definition: adpd410x.h:303
ADPD4100
@ ADPD4100
Definition: adpd410x.h:917
adpd410x_get_sampling_freq
int32_t adpd410x_get_sampling_freq(struct adpd410x_dev *dev, uint32_t *sampling_freq)
Get device sampling frequency.
Definition: adpd410x.c:339
no_os_field_get
uint32_t no_os_field_get(uint32_t mask, uint32_t word)
ADPD410X_VC1
@ ADPD410X_VC1
Definition: adpd410x.h:991
ADPD410X_REG_OPMODE
#define ADPD410X_REG_OPMODE
Definition: adpd410x.h:69
BITP_SYS_CTL_ALT_CLOCKS
#define BITP_SYS_CTL_ALT_CLOCKS
Definition: adpd410x.h:294
_adpd410x_led_control
Structure mapping LED output option and LED strength to one byte.
Definition: adpd410x.h:1051
BITM_CHIP_ID
#define BITM_CHIP_ID
Definition: adpd410x.h:253
ADPD410X_TS_B
@ ADPD410X_TS_B
Definition: adpd410x.h:1077
adpd410x_timeslot_init::led3
union adpd410x_led_control led3
Definition: adpd410x.h:1134
adpd410x_get_opmode
int32_t adpd410x_get_opmode(struct adpd410x_dev *dev, enum adpd410x_opmode *mode)
Get operation mode.
Definition: adpd410x.c:249
adpd410x_timeslot_setup
int32_t adpd410x_timeslot_setup(struct adpd410x_dev *dev, enum adpd410x_timeslots timeslot_no, struct adpd410x_timeslot_init *init)
Setup an active time slot.
Definition: adpd410x.c:382
ADPD410X_REG_DECIMATE
#define ADPD410X_REG_DECIMATE(ts)
Definition: adpd410x.h:118
adpd410x_timeslot_init::afe_trim_opt
enum adpd410x_tia_vref_volt afe_trim_opt
Definition: adpd410x.h:1112
no_os_i2c_init_param
Structure holding the parameters for I2C initialization.
Definition: no_os_i2c.h:64
NULL
#define NULL
Definition: wrapper.h:64
ADPD410X_LOW_FREQ_OSCILLATOR_FREQ1
#define ADPD410X_LOW_FREQ_OSCILLATOR_FREQ1
Definition: adpd410x.h:869
adpd410x_set_sampling_freq
int32_t adpd410x_set_sampling_freq(struct adpd410x_dev *dev, uint32_t sampling_freq)
Set device sampling frequency.
Definition: adpd410x.c:304
BITM_OPMODE_OP_MODE
#define BITM_OPMODE_OP_MODE
Definition: adpd410x.h:308
no_os_gpio_set_value
int32_t no_os_gpio_set_value(struct no_os_gpio_desc *desc, uint8_t value)
Set the value of the specified GPIO.
Definition: no_os_gpio.c:160
adpd410x_reg_read_bytes
int32_t adpd410x_reg_read_bytes(struct adpd410x_dev *dev, uint16_t address, uint8_t *data, uint16_t num_bytes)
Read a specified number of bytes from device register.
Definition: adpd410x.c:86
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
adpd410x_timeslot_init::vref_pulse_opt
enum adpd410x_tia_vref_volt vref_pulse_opt
Definition: adpd410x.h:1114
BITP_PATTERN_A_REVERSE_INTEG
#define BITP_PATTERN_A_REVERSE_INTEG
Definition: adpd410x.h:792
adpd410x_ts_input_opt
adpd410x_ts_input_opt
List of input configurations for time slot.
Definition: adpd410x.h:951
phy_comm_dev
Contains physical communication handler.
Definition: adpd410x.h:894
ADPD410X_TS_C
@ ADPD410X_TS_C
Definition: adpd410x.h:1079
adpd410x_dev::dev_ops
union phy_comm_dev dev_ops
Definition: adpd410x.h:1186
adpd410x_get_data
int32_t adpd410x_get_data(struct adpd410x_dev *dev, uint32_t *data)
Get a full data packet from the device containing data from all active time slots.
Definition: adpd410x.c:630
adpd410x_init_param::clk_opt
enum adpd410x_clk_opt clk_opt
Definition: adpd410x.h:1167
adpd410x_reg_read
int32_t adpd410x_reg_read(struct adpd410x_dev *dev, uint16_t address, uint16_t *data)
Read device register.
Definition: adpd410x.c:61
ADPD410X_INaDIS_INbDIS
@ ADPD410X_INaDIS_INbDIS
Definition: adpd410x.h:953
ADPD410X_TS_F
@ ADPD410X_TS_F
Definition: adpd410x.h:1085
ADPD410X_REG_CATHODE
#define ADPD410X_REG_CATHODE(ts)
Definition: adpd410x.h:103
phy_comm_init_param::spi_phy_init
struct no_os_spi_init_param spi_phy_init
Definition: adpd410x.h:907
BITM_DECIMATE_A_DECIMATE_FACTOR
#define BITM_DECIMATE_A_DECIMATE_FACTOR
Definition: adpd410x.h:831
BITP_DATA1_A_SIGNAL_SIZE
#define BITP_DATA1_A_SIGNAL_SIZE
Definition: adpd410x.h:812
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
no_os_gpio.h
Header file of GPIO Interface.
adpd410x_reg_read
int32_t adpd410x_reg_read(struct adpd410x_dev *dev, uint16_t address, uint16_t *data)
Read device register.
Definition: adpd410x.c:61
adpd410x_dev::gpio3
struct no_os_gpio_desc * gpio3
Definition: adpd410x.h:1198
adpd410x_init_param
Device driver initialization structure.
Definition: adpd410x.h:1161
ADPD410X_TS_K
@ ADPD410X_TS_K
Definition: adpd410x.h:1095
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
adpd410x_ts_input_pair
adpd410x_ts_input_pair
List of input pairs options for time slots.
Definition: adpd410x.h:936
ADPD410X_REG_AFE_TRIM
#define ADPD410X_REG_AFE_TRIM(ts)
Definition: adpd410x.h:104
no_os_util.h
Implementation of utility functions.
no_os_find_first_set_bit
uint32_t no_os_find_first_set_bit(uint32_t word)
adpd410x_reg_write_mask
int32_t adpd410x_reg_write_mask(struct adpd410x_dev *dev, uint16_t address, uint16_t data, uint16_t mask)
Do a read and write of a register to update only part of a register.
Definition: adpd410x.c:177
adpd410x_get_sampling_freq
int32_t adpd410x_get_sampling_freq(struct adpd410x_dev *dev, uint32_t *sampling_freq)
Get device sampling frequency.
Definition: adpd410x.c:339
ADPD410X_EXTLFO_INTHFO
@ ADPD410X_EXTLFO_INTHFO
Definition: adpd410x.h:1149
BITM_DATA1_A_SIGNAL_SIZE
#define BITM_DATA1_A_SIGNAL_SIZE
Definition: adpd410x.h:816
ADPD410X_REG_SYS_CTL
#define ADPD410X_REG_SYS_CTL
Definition: adpd410x.h:68
ADPD410X_REG_LED_POW12
#define ADPD410X_REG_LED_POW12(ts)
Definition: adpd410x.h:105
adpd410x_get_data
int32_t adpd410x_get_data(struct adpd410x_dev *dev, uint32_t *data)
Get a full data packet from the device containing data from all active time slots.
Definition: adpd410x.c:630
no_os_gpio_direction_output
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:124
adpd410x_init_param::dev_type
enum adpd410x_supported_dev dev_type
Definition: adpd410x.h:1165
adpd410x.h
BITP_AFE_TRIM_A_TIA_GAIN_CH2
#define BITP_AFE_TRIM_A_TIA_GAIN_CH2
Definition: adpd410x.h:711
adpd410x_reg_write_mask
int32_t adpd410x_reg_write_mask(struct adpd410x_dev *dev, uint16_t address, uint16_t data, uint16_t mask)
Do a read and write of a register to update only part of a register.
Definition: adpd410x.c:177
BITP_LED_POW12_A_LED_CURRENT2
#define BITP_LED_POW12_A_LED_CURRENT2
Definition: adpd410x.h:730
adpd410x_timeslot_init::precon_option
enum adpd410x_precon_opt precon_option
Definition: adpd410x.h:1110
ADPD410X_REG_FIFO_STATUS
#define ADPD410X_REG_FIFO_STATUS
Definition: adpd410x.h:55
ADPD410X_INaCH1_INbCH2
@ ADPD410X_INaCH1_INbCH2
Definition: adpd410x.h:963
adpd410x_reset
int32_t adpd410x_reset(struct adpd410x_dev *dev)
Do a software reset.
Definition: adpd410x.c:218
adpd410x_dev::gpio2
struct no_os_gpio_desc * gpio2
Definition: adpd410x.h:1196
ADPD410X_LOWER_BYTE_SPI_MASK
#define ADPD410X_LOWER_BYTE_SPI_MASK
Definition: adpd410x.h:882
ADPD410X_INaCH1_INbDIS
@ ADPD410X_INaCH1_INbDIS
Definition: adpd410x.h:955
ADPD410X_REG_INPUTS
#define ADPD410X_REG_INPUTS(ts)
Definition: adpd410x.h:102
adpd410x_clk_opt
adpd410x_clk_opt
External clock options.
Definition: adpd410x.h:1145
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
BITM_CATHODE_A_PRECON
#define BITM_CATHODE_A_PRECON
Definition: adpd410x.h:707
adpd410x_reg_write
int32_t adpd410x_reg_write(struct adpd410x_dev *dev, uint16_t address, uint16_t data)
Write device register.
Definition: adpd410x.c:143
ADPD410X_TS_H
@ ADPD410X_TS_H
Definition: adpd410x.h:1089
adpd410x_set_opmode
int32_t adpd410x_set_opmode(struct adpd410x_dev *dev, enum adpd410x_opmode mode)
Set operation mode.
Definition: adpd410x.c:236