no-OS
parameters.h
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1 /***************************************************************************/
39 #ifndef _PARAMETERS_H_
40 #define _PARAMETERS_H_
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include "app_config.h"
46 #ifdef ALTERA_PLATFORM
47 #include "system.h"
48 #else
49 #include "xparameters.h"
50 #endif
51 
52 /******************************************************************************/
53 /********************** Macros and Constants Definitions **********************/
54 /******************************************************************************/
55 #ifdef ALTERA_PLATFORM
56 #define GPIO_OFFSET 0
57 
58 #define ADRV_RESETB GPIO_OFFSET + 52
59 #define ADRV_SYSREF_REQ GPIO_OFFSET + 58
60 #define CLK_RESETB GPIO_OFFSET + 59
61 
62 #define RX_A10_FPLL_BASEADDR ADRV9009_RX_JESD204_LINK_PLL_RECONFIG_BASE
63 #define TX_A10_FPLL_BASEADDR ADRV9009_TX_JESD204_LINK_PLL_RECONFIG_BASE
64 #define RX_OS_A10_FPLL_BASEADDR ADRV9009_RX_OS_JESD204_LINK_PLL_RECONFIG_BASE
65 
66 #define RX_JESD_BASEADDR ADRV9009_RX_JESD204_LINK_RECONFIG_BASE
67 #define TX_JESD_BASEADDR ADRV9009_TX_JESD204_LINK_RECONFIG_BASE
68 #define RX_OS_JESD_BASEADDR ADRV9009_RX_OS_JESD204_LINK_RECONFIG_BASE
69 
70 #define RX_XCVR_BASEADDR ADRV9009_RX_JESD204_LINK_MANAGEMENT_BASE
71 #define TX_XCVR_BASEADDR ADRV9009_TX_JESD204_LINK_MANAGEMENT_BASE
72 #define RX_OS_XCVR_BASEADDR ADRV9009_RX_OS_JESD204_LINK_MANAGEMENT_BASE
73 
74 #define RX_ADXCFG_0_BASEADDR AVL_ADXCFG_0_RCFG_S1_BASE
75 #define RX_ADXCFG_1_BASEADDR AVL_ADXCFG_1_RCFG_S1_BASE
76 #define TX_ADXCFG_0_BASEADDR AVL_ADXCFG_0_RCFG_S0_BASE
77 #define TX_ADXCFG_1_BASEADDR AVL_ADXCFG_1_RCFG_S0_BASE
78 #define TX_ADXCFG_2_BASEADDR AVL_ADXCFG_2_RCFG_S0_BASE
79 #define TX_ADXCFG_3_BASEADDR AVL_ADXCFG_3_RCFG_S0_BASE
80 #define RX_OS_ADXCFG_0_BASEADDR AVL_ADXCFG_2_RCFG_S1_BASE
81 #define RX_OS_ADXCFG_1_BASEADDR AVL_ADXCFG_3_RCFG_S1_BASE
82 
83 #define TX_PLL_BASEADDR ADRV9009_TX_JESD204_LANE_PLL_RECONFIG_BASE
84 
85 #define RX_CORE_BASEADDR AXI_ADRV9009_BASE
86 #define TX_CORE_BASEADDR AXI_ADRV9009_BASE + 0x4000
87 #define RX_OS_CORE_BASEADDR AXI_ADRV9009_BASE + 0x8000
88 
89 #define RX_DMA_BASEADDR AXI_ADRV9009_RX_DMA_BASE
90 #define TX_DMA_BASEADDR AXI_ADRV9009_TX_DMA_BASE
91 
92 #define DDR_MEM_BASEADDR SYS_DDR3_CNTRL_ARCH_BASE
93 #define ADC_DDR_BASEADDR SYS_DDR3_CNTRL_ARCH_BASE + 0x800000
94 #define DAC_DDR_BASEADDR SYS_DDR3_CNTRL_ARCH_BASE + 0xA000000
95 
96 #define GPIO_BASEADDR SYS_GPIO_OUT_BASE
97 
98 #define SPI_BASEADDR SYS_SPI_BASE
99 #else
100 #ifdef PLATFORM_ZYNQMP
101 #define GPIO_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
102 #else
103 #define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
104 #endif
105 
106 #if defined(ZU11EG) // ZU11EG
107 #define ADRV_CS 0 // Talise A
108 #define ADRV_B_CS 1 // Talise B
109 #define CLK_CS 2 // Clock chip placed on the som
110 #define CAR_CLK_CS 3 // Clock chip placed on the carrier
111 
112 // Transceiver A
113 #define TRX_A_RESETB_GPIO 130
114 #define TRX_A_TEST_GPIO 131
115 #define TRX_A_RX1_ENABLE_GPIO 132
116 #define TRX_A_RX2_ENABLE_GPIO 133
117 #define TRX_A_TX1_ENABLE_GPIO 134
118 #define TRX_A_TX2_ENABLE_GPIO 135
119 
120 // Transceiver B
121 #define TRX_B_RESETB_GPIO 156
122 #define TRX_B_TEST_GPIO 157
123 #define TRX_B_RX1_ENABLE_GPIO 158
124 #define TRX_B_RX2_ENABLE_GPIO 159
125 #define TRX_B_TX1_ENABLE_GPIO 160
126 #define TRX_B_TX2_ENABLE_GPIO 161
127 
128 #define SYSREF_REQ_GPIO 167
129 #define CLK_RESETB_GPIO 162
130 #define DAC_FIFO_BYPASS_GPIO 168
131 #define CAR_CLK_RESETB_GPIO 101
132 
133 #elif defined(FMCOMMS8_ZCU102)
134 
135 #define ADRV_CS 0 // Talise A
136 #define ADRV_B_CS 1 // Talise B
137 #define CLK_CS 2 // Clock chip placed on the som
138 #define CAR_CLK_CS 3 // Clock chip placed on the carrier
139 
140 // Transceiver A
141 #define TRX_A_RESETB_GPIO 120
142 #define TRX_A_TEST_GPIO 131
143 #define TRX_A_RX1_ENABLE_GPIO 121
144 #define TRX_A_RX2_ENABLE_GPIO 122
145 #define TRX_A_TX1_ENABLE_GPIO 123
146 #define TRX_A_TX2_ENABLE_GPIO 124
147 
148 // Transceiver B
149 #define TRX_B_RESETB_GPIO 135
150 #define TRX_B_TEST_GPIO 157
151 #define TRX_B_RX1_ENABLE_GPIO 136
152 #define TRX_B_RX2_ENABLE_GPIO 137
153 #define TRX_B_TX1_ENABLE_GPIO 138
154 #define TRX_B_TX2_ENABLE_GPIO 139
155 
156 #define SYSREF_REQ_GPIO 167
157 #define CLK_RESETB_GPIO 162
158 #define DAC_FIFO_BYPASS_GPIO 168
159 #define CAR_CLK_RESETB_GPIO 101
160 
161 #else
162 
163 #define CLK_CS 0
164 #define ADRV_CS 1
165 
166 #ifdef XPS_BOARD_ZCU102 // ZCU102
167 #define TRX_A_RESETB_GPIO 130
168 #define SYSREF_REQ_GPIO 136
169 #define CLK_RESETB_GPIO 137
170 #define DAC_FIFO_BYPASS_GPIO 138
171 #else // ZC706
172 #define TRX_A_RESETB_GPIO 106
173 #define SYSREF_REQ_GPIO 112
174 #define CLK_RESETB_GPIO 113
175 #define DAC_FIFO_BYPASS_GPIO 114
176 #endif
177 #endif
178 
179 #if defined(ZU11EG)
180 // axi_clkgen is not used with the adrv9009 som.
181 #elif defined(FMCOMMS8_ZCU102)
182 // axi_clkgen is not used with the fmcomms8.
183 #else
184 #define RX_CLKGEN_BASEADDR XPAR_AXI_ADRV9009_RX_CLKGEN_BASEADDR
185 #define TX_CLKGEN_BASEADDR XPAR_AXI_ADRV9009_TX_CLKGEN_BASEADDR
186 #define RX_OS_CLKGEN_BASEADDR XPAR_AXI_ADRV9009_RX_OS_CLKGEN_BASEADDR
187 #endif
188 
189 #if defined(ZU11EG)
190 #define RX_JESD_BASEADDR XPAR_AXI_ADRV9009_SOM_RX_JESD_RX_AXI_BASEADDR
191 #define TX_JESD_BASEADDR XPAR_AXI_ADRV9009_SOM_TX_JESD_TX_AXI_BASEADDR
192 #define RX_OS_JESD_BASEADDR XPAR_AXI_ADRV9009_SOM_OBS_JESD_RX_AXI_BASEADDR
193 #elif defined(FMCOMMS8_ZCU102)
194 #define RX_JESD_BASEADDR XPAR_AXI_ADRV9009_FMC_RX_JESD_RX_AXI_BASEADDR
195 #define TX_JESD_BASEADDR XPAR_AXI_ADRV9009_FMC_TX_JESD_TX_AXI_BASEADDR
196 #define RX_OS_JESD_BASEADDR XPAR_AXI_ADRV9009_FMC_OBS_JESD_RX_AXI_BASEADDR
197 #else
198 #define RX_JESD_BASEADDR XPAR_AXI_ADRV9009_RX_JESD_RX_AXI_BASEADDR
199 #define TX_JESD_BASEADDR XPAR_AXI_ADRV9009_TX_JESD_TX_AXI_BASEADDR
200 #define RX_OS_JESD_BASEADDR XPAR_AXI_ADRV9009_RX_OS_JESD_RX_AXI_BASEADDR
201 #endif
202 
203 #if defined(ZU11EG)
204 #define RX_XCVR_BASEADDR XPAR_AXI_ADRV9009_SOM_RX_XCVR_BASEADDR
205 #define TX_XCVR_BASEADDR XPAR_AXI_ADRV9009_SOM_TX_XCVR_BASEADDR
206 #define RX_OS_XCVR_BASEADDR XPAR_AXI_ADRV9009_SOM_OBS_XCVR_BASEADDR
207 #elif defined(FMCOMMS8_ZCU102)
208 #define RX_XCVR_BASEADDR XPAR_AXI_ADRV9009_FMC_RX_XCVR_BASEADDR
209 #define TX_XCVR_BASEADDR XPAR_AXI_ADRV9009_FMC_TX_XCVR_BASEADDR
210 #define RX_OS_XCVR_BASEADDR XPAR_AXI_ADRV9009_FMC_OBS_XCVR_BASEADDR
211 #else
212 #define RX_XCVR_BASEADDR XPAR_AXI_ADRV9009_RX_XCVR_BASEADDR
213 #define TX_XCVR_BASEADDR XPAR_AXI_ADRV9009_TX_XCVR_BASEADDR
214 #define RX_OS_XCVR_BASEADDR XPAR_AXI_ADRV9009_RX_OS_XCVR_BASEADDR
215 #endif
216 
217 #ifdef XPAR_AXI_ADRV9009_CORE_BASEADDR
218 #define RX_CORE_BASEADDR XPAR_AXI_ADRV9009_CORE_BASEADDR
219 #define TX_CORE_BASEADDR XPAR_AXI_ADRV9009_CORE_BASEADDR + 0x4000
220 #define RX_OS_CORE_BASEADDR XPAR_AXI_ADRV9009_CORE_BASEADDR + 0x8000
221 #else
222 #if defined(ZU11EG)
223 #define RX_CORE_BASEADDR XPAR_RX_ADRV9009_SOM_TPL_CORE_ADC_TPL_CORE_BASEADDR
224 #define TX_CORE_BASEADDR XPAR_TX_ADRV9009_SOM_TPL_CORE_DAC_TPL_CORE_BASEADDR
225 #define RX_OS_CORE_BASEADDR XPAR_OBS_ADRV9009_SOM_TPL_CORE_ADC_TPL_CORE_BASEADDR
226 #elif defined(FMCOMMS8_ZCU102)
227 #define RX_CORE_BASEADDR XPAR_RX_ADRV9009_FMC_TPL_CORE_ADC_TPL_CORE_BASEADDR
228 #define TX_CORE_BASEADDR XPAR_TX_ADRV9009_FMC_TPL_CORE_DAC_TPL_CORE_BASEADDR
229 #define RX_OS_CORE_BASEADDR XPAR_OBS_ADRV9009_FMC_TPL_CORE_ADC_TPL_CORE_BASEADDR
230 #else
231 #define RX_CORE_BASEADDR XPAR_RX_ADRV9009_TPL_CORE_ADC_TPL_CORE_BASEADDR
232 #define TX_CORE_BASEADDR XPAR_TX_ADRV9009_TPL_CORE_DAC_TPL_CORE_BASEADDR
233 #define RX_OS_CORE_BASEADDR XPAR_RX_OS_ADRV9009_TPL_CORE_ADC_TPL_CORE_BASEADDR
234 #endif // #if defined(ZU11EG)
235 #endif // #ifdef XPAR_AXI_ADRV9009_CORE_BASEADDR
236 
237 #if defined(ZU11EG)
238 #define RX_DMA_BASEADDR XPAR_AXI_ADRV9009_SOM_RX_DMA_BASEADDR
239 #define TX_DMA_BASEADDR XPAR_AXI_ADRV9009_SOM_TX_DMA_BASEADDR
240 #elif defined(FMCOMMS8_ZCU102)
241 #define RX_DMA_BASEADDR XPAR_AXI_ADRV9009_FMC_RX_DMA_BASEADDR
242 #define TX_DMA_BASEADDR XPAR_AXI_ADRV9009_FMC_TX_DMA_BASEADDR
243 #else
244 #define RX_DMA_BASEADDR XPAR_AXI_ADRV9009_RX_DMA_BASEADDR
245 #define TX_DMA_BASEADDR XPAR_AXI_ADRV9009_TX_DMA_BASEADDR
246 #endif
247 
248 #define DDR_MEM_BASEADDR XPAR_DDR_MEM_BASEADDR
249 #define ADC_DDR_BASEADDR XPAR_DDR_MEM_BASEADDR + 0x800000
250 #define DAC_DDR_BASEADDR XPAR_DDR_MEM_BASEADDR + 0xA000000
251 
252 #define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
253 #define UART_BAUDRATE 921600
254 #ifdef XPS_BOARD_ZCU102
255 #define UART_IRQ_ID XPAR_XUARTPS_0_INTR
256 #else
257 #define UART_IRQ_ID XPAR_XUARTPS_1_INTR
258 #endif
259 #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
260 #endif
261 
262 #endif
263