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54 #define ADXCVR_SYS_CLK_CPLL 0x00
55 #define ADXCVR_SYS_CLK_QPLL1 0x02
56 #define ADXCVR_SYS_CLK_QPLL0 0x03
59 #define ADXCVR_OUTCLK_PCS 1
60 #define ADXCVR_OUTCLK_PMA 2
61 #define ADXCVR_REFCLK 3
62 #define ADXCVR_REFCLK_DIV2 4
63 #define ADXCVR_PROGDIV_CLK 5
131 unsigned int drp_port,
136 unsigned int drp_port,
153 unsigned long parent_rate);
int adxcvr_clk_enable(struct adxcvr *xcvr)
AXI ADXCVR Clock Enable.
Definition: axi_adxcvr.c:498
enum axi_fpga_speed_grade speed_grade
Definition: xilinx_transceiver.h:180
#define AXI_INFO_FPGA_DEV_PACKAGE(info)
Definition: clk_axi_clkgen.c:72
uint32_t timeout
Definition: ad413x.c:54
uint32_t lane_rate_khz
Definition: altera_adxcvr.h:103
Driver for the Xilinx High-speed transceiver dynamic reconfiguration.
int32_t adxcvr_remove(struct adxcvr *xcvr)
adxcvr_remove
Definition: altera_adxcvr.c:494
const char * name
Definition: altera_adxcvr.h:96
int xilinx_xcvr_calc_qpll_config(struct xilinx_xcvr *xcvr, uint32_t sys_clk_sel, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_qpll_config *conf, uint32_t *out_div)
Definition: xilinx_transceiver.c:674
bool qpll_enable
Definition: axi_adxcvr.h:77
int adxcvr_clk_set_rate(struct adxcvr *xcvr, unsigned long rate, unsigned long parent_rate)
AXI ADXCVR Clock Set Rate.
Definition: axi_adxcvr.c:328
int32_t adxcvr_status_error(struct adxcvr *xcvr)
AXI ADXCVR Status Read.
Definition: axi_adxcvr.c:452
enum axi_fpga_family family
Definition: xilinx_transceiver.h:179
#define ADXCVR_DRP_PORT_ADDR_COMMON
Definition: axi_adxcvr.c:85
ADI JESD204B/C AXI_ADXCVR Highspeed Transceiver Device structure.
Definition: altera_adxcvr.h:95
int adxcvr_drp_write(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int val)
AXI ADXCVR DPR Port Write.
Definition: axi_adxcvr.c:200
uint32_t ref_rate_khz
Definition: axi_adxcvr.h:87
#define ADXCVR_PROGDIV_CLK
Definition: axi_adxcvr.h:63
#define pr_err(fmt, args...)
Definition: no_os_print_log.h:94
Header file of Delay functions.
#define ADXCVR_REG_DRP_SEL(x)
Definition: axi_adxcvr.c:74
#define ADXCVR_BUFSTATUS_RST
Definition: axi_adxcvr.c:59
@ XILINX_XCVR_LEGACY_TYPE_S7_GTX2
Definition: xilinx_transceiver.h:87
#define pr_info(fmt, args...)
Definition: no_os_print_log.h:121
uint32_t base
Definition: altera_adxcvr.h:97
enum xilinx_xcvr_type type
Definition: xilinx_transceiver.h:173
int adxcvr_clk_disable(struct adxcvr *xcvr)
AXI ADXCVR Clock Disable.
Definition: axi_adxcvr.c:548
struct adxcvr * ad_xcvr
Definition: xilinx_transceiver.h:176
#define ADXCVR_BUFSTATUS_UNDERFLOW
Definition: axi_adxcvr.c:63
@ XILINX_XCVR_TYPE_US_GTY4
Definition: xilinx_transceiver.h:79
int xilinx_xcvr_calc_cpll_config(struct xilinx_xcvr *xcvr, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_cpll_config *conf, uint32_t *out_div)
Definition: xilinx_transceiver.c:545
@ PM_200
Definition: xilinx_transceiver.h:98
uint32_t version
Definition: xilinx_transceiver.h:177
int xilinx_xcvr_configure_cdr(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t lane_rate, uint32_t out_div, bool lpm_enable)
Definition: xilinx_transceiver.c:363
bool lpm_enable
Definition: axi_adxcvr.h:119
#define ADXCVR_OUTCLK_SEL(x)
Definition: axi_adxcvr.c:70
int xilinx_xcvr_write_prog_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_prog_div, int32_t tx_prog_div)
Definition: xilinx_transceiver.c:1860
Definition: xilinx_transceiver.h:191
int32_t adxcvr_init(struct adxcvr **ad_xcvr, const struct adxcvr_init *init)
AXI ADXCVR Device Initialization.
Definition: axi_adxcvr.c:581
int32_t adxcvr_status_error(struct adxcvr *xcvr)
AXI ADXCVR Status Read.
Definition: axi_adxcvr.c:452
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
enum xilinx_xcvr_refclk_ppm refclk_ppm
Definition: xilinx_transceiver.h:174
enum axi_fgpa_technology tech
Definition: xilinx_transceiver.h:178
#define AXI_REG_FPGA_INFO
Definition: clk_axi_clkgen.c:66
Driver for the ADI AXI-ADXCVR Module.
int xilinx_xcvr_qpll_calc_lane_rate(struct xilinx_xcvr *xcvr, uint32_t refclk_hz, const struct xilinx_xcvr_qpll_config *conf, uint32_t out_div)
Definition: xilinx_transceiver.c:1467
#define ADXCVR_DRP_CTRL_ADDR(x)
Definition: axi_adxcvr.c:78
#define pr_debug(fmt, args...)
Definition: no_os_print_log.h:135
uint32_t sys_clk_sel
Definition: axi_adxcvr.h:91
uint32_t num_lanes
Definition: axi_adxcvr.h:83
#define ADXCVR_DRP_STATUS_BUSY
Definition: axi_adxcvr.c:82
int xilinx_xcvr_read_out_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t *rx_out_div, uint32_t *tx_out_div)
Definition: xilinx_transceiver.c:1557
@ XILINX_XCVR_LEGACY_TYPE_US_GTH3
Definition: xilinx_transceiver.h:88
int32_t adxcvr_write(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t reg_val)
adxcvr_write
Definition: altera_adxcvr.c:87
int32_t adxcvr_remove(struct adxcvr *xcvr)
Free resoulces allocated for AXI_ADXCVR.
Definition: axi_adxcvr.c:693
#define ADXCVR_REG_DRP_CTRL(x)
Definition: axi_adxcvr.c:76
#define AXI_REG_VERSION
Definition: clk_axi_clkgen.c:61
enum axi_fpga_dev_pack dev_package
Definition: xilinx_transceiver.h:181
Definition: altera_adxcvr.h:108
int xilinx_xcvr_qpll_write_config(struct xilinx_xcvr *xcvr, uint32_t sys_clk_sel, uint32_t drp_port, const struct xilinx_xcvr_qpll_config *conf)
Definition: xilinx_transceiver.c:1439
#define ADXCVR_DRP_CTRL_WDATA(x)
Definition: axi_adxcvr.c:79
const char * name
Definition: altera_adxcvr.h:109
int32_t adxcvr_read(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t *reg_val)
adxcvr_read
Definition: altera_adxcvr.c:99
int32_t no_os_axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
AXI IO Altera specific read function.
Definition: altera_axi_io.c:59
uint32_t out_clk_sel
Definition: axi_adxcvr.h:117
#define ADXCVR_SYSCLK_SEL(x)
Definition: axi_adxcvr.c:69
int32_t adxcvr_init(struct adxcvr **ad_xcvr, const struct adxcvr_init *init)
adxcvr_init
Definition: altera_adxcvr.c:443
uint32_t base
Definition: altera_adxcvr.h:110
int adxcvr_clk_enable(struct adxcvr *xcvr)
AXI ADXCVR Clock Enable.
Definition: axi_adxcvr.c:498
int adxcvr_drp_read(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int *val)
AXI ADXCVR DPR Port Read.
Definition: axi_adxcvr.c:165
#define ADXCVR_DRP_PORT_ADDR_CHANNEL
Definition: axi_adxcvr.c:86
uint32_t encoding
Definition: xilinx_transceiver.h:175
#define AXI_REG_FPGA_VOLTAGE
Definition: clk_axi_clkgen.c:67
#define ADXCVR_REG_CONTROL
Definition: axi_adxcvr.c:66
struct xilinx_xcvr xlx_xcvr
Definition: axi_adxcvr.h:97
#define ADXCVR_REG_SYNTH
Definition: axi_adxcvr.c:72
int(* read)(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int *val)
Definition: xilinx_transceiver.h:194
int adxcvr_clk_disable(struct adxcvr *xcvr)
AXI ADXCVR Clock Disable.
Definition: axi_adxcvr.c:548
#define ADXCVR_REG_RESETN
Definition: axi_adxcvr.c:57
#define ENC_66B64B
Definition: xilinx_transceiver.h:274
@ XILINX_XCVR_TYPE_US_GTH3
Definition: xilinx_transceiver.h:77
int xilinx_xcvr_qpll_read_config(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t sys_clk_sel, struct xilinx_xcvr_qpll_config *conf)
Definition: xilinx_transceiver.c:1257
uint32_t ref_rate_khz
Definition: axi_adxcvr.h:123
Structure holding CPLL configuration.
Definition: xilinx_transceiver.h:255
int xilinx_xcvr_write_rx_clk25_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
Definition: xilinx_transceiver.c:2010
uint32_t lane_rate_khz
Definition: altera_adxcvr.h:113
int xilinx_xcvr_write_out_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_out_div, int32_t tx_out_div)
Definition: xilinx_transceiver.c:1670
int32_t adxcvr_read(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t *reg_val)
AXI ADXCVR Read.
Definition: axi_adxcvr.c:123
#define ADXCVR_SYS_CLK_CPLL
Definition: axi_adxcvr.h:54
int adxcvr_clk_set_rate(struct adxcvr *xcvr, unsigned long rate, unsigned long parent_rate)
AXI ADXCVR Clock Set Rate.
Definition: axi_adxcvr.c:328
uint32_t voltage
Definition: xilinx_transceiver.h:182
int xilinx_xcvr_cpll_calc_lane_rate(struct xilinx_xcvr *xcvr, uint32_t refclk_hz, const struct xilinx_xcvr_cpll_config *conf, uint32_t out_div)
Definition: xilinx_transceiver.c:1093
#define ADXCVR_STATUS
Definition: axi_adxcvr.c:62
int xilinx_xcvr_write_prog_div_rate(struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_rate, int32_t tx_rate)
Definition: xilinx_transceiver.c:1939
void no_os_udelay(uint32_t usecs)
Wait until usecs microseconds passed.
Definition: aducm3029_delay.c:120
int adxcvr_drp_read(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int *val)
AXI ADXCVR DPR Port Read.
Definition: axi_adxcvr.c:165
#define NULL
Definition: wrapper.h:64
uint32_t out_clk_sel
Definition: axi_adxcvr.h:95
xilinx_xcvr parameters structure.
Definition: xilinx_transceiver.h:172
#define ADXCVR_REG_STATUS
Definition: axi_adxcvr.c:61
#define AXI_PCORE_VER_MAJOR(version)
Definition: clk_axi_clkgen.c:57
#define ADXCVR_BUFSTATUS_OVERFLOW
Definition: axi_adxcvr.c:64
int xilinx_xcvr_configure_lpm_dfe_mode(struct xilinx_xcvr *xcvr, uint32_t drp_port, bool lpm)
Definition: xilinx_transceiver.c:390
#define ADXCVR_DRP_PORT_COMMON(x)
Definition: axi_adxcvr.c:88
int32_t no_os_axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
AXI IO Altera specific write function.
Definition: altera_axi_io.c:73
Structure holding QPLL configuration.
Definition: xilinx_transceiver.h:265
#define ADXCVR_REG_DRP_STATUS(x)
Definition: axi_adxcvr.c:81
#define AXI_INFO_FPGA_TECH(info)
Definition: clk_axi_clkgen.c:69
uint32_t sys_clk_sel
Definition: axi_adxcvr.h:113
unsigned long(* recalc_rate)(struct adxcvr *xcvr, unsigned long parent_rate)
Definition: xilinx_transceiver.h:241
bool tx_enable
Definition: axi_adxcvr.h:79
Definition: xilinx_transceiver.h:238
int32_t adxcvr_write(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t reg_val)
AXI ADXCVR Write.
Definition: axi_adxcvr.c:107
#define ADXCVR_DRP_STATUS_RDATA(x)
Definition: axi_adxcvr.c:83
Header file of utility functions.
@ XILINX_XCVR_LEGACY_TYPE_US_GTY4
Definition: xilinx_transceiver.h:90
int32_t adxcvr_drp_wait_idle(struct adxcvr *xcvr, uint32_t drp_addr)
Read AXI ADXCVR DRP status.
Definition: axi_adxcvr.c:138
#define ADI_AXI_PCORE_VER(major, minor, patch)
Definition: axi_adxcvr.c:93
#define ADXCVR_DRP_PORT_CHANNEL(x)
Definition: axi_adxcvr.c:89
@ XILINX_XCVR_TYPE_US_GTH4
Definition: xilinx_transceiver.h:78
bool cpll_enable
Definition: axi_adxcvr.h:75
@ XILINX_XCVR_LEGACY_TYPE_US_GTH4
Definition: xilinx_transceiver.h:89
int xilinx_xcvr_write_tx_clk25_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
Definition: xilinx_transceiver.c:2052
#define ADXCVR_LPM_DFE_N
Definition: axi_adxcvr.c:67
int adxcvr_drp_write(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int val)
AXI ADXCVR DPR Port Write.
Definition: axi_adxcvr.c:200
#define ENC_8B10B
Definition: xilinx_transceiver.h:273
#define AXI_INFO_FPGA_FAMILY(info)
Definition: clk_axi_clkgen.c:70
int xilinx_xcvr_cpll_write_config(struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_cpll_config *conf)
Definition: xilinx_transceiver.c:1067
#define NO_OS_DIV_ROUND_CLOSEST(x, y)
Definition: no_os_util.h:58
#define AXI_INFO_FPGA_VOLTAGE(val)
Definition: clk_axi_clkgen.c:73
int xilinx_xcvr_cpll_read_config(struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_cpll_config *conf)
Definition: xilinx_transceiver.c:912
#define AXI_INFO_FPGA_SPEED_GRADE(info)
Definition: clk_axi_clkgen.c:71
bool lpm_enable
Definition: axi_adxcvr.h:81
#define ADXCVR_RESETN
Definition: axi_adxcvr.c:58
@ XILINX_XCVR_TYPE_S7_GTX2
Definition: xilinx_transceiver.h:76
#define ADXCVR_DRP_CTRL_WR
Definition: axi_adxcvr.c:77