no-OS
axi_adxcvr.h
Go to the documentation of this file.
1 /***************************************************************************/
39 #ifndef AXI_ADXCVR_H_
40 #define AXI_ADXCVR_H_
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include <stdint.h>
46 #include <stdbool.h>
47 #include "xilinx_transceiver.h"
48 
49 /******************************************************************************/
50 /********************** Macros and Types Declarations *************************/
51 /******************************************************************************/
52 
53 // Selection of PLL reference clock source to drive the RXOUTCLK
54 #define ADXCVR_SYS_CLK_CPLL 0x00
55 #define ADXCVR_SYS_CLK_QPLL1 0x02
56 #define ADXCVR_SYS_CLK_QPLL0 0x03
57 
58 // adi,out-clk-select
59 #define ADXCVR_OUTCLK_PCS 1
60 #define ADXCVR_OUTCLK_PMA 2
61 #define ADXCVR_REFCLK 3
62 #define ADXCVR_REFCLK_DIV2 4
63 #define ADXCVR_PROGDIV_CLK 5 /* GTHE3, GTHE4, GTYE4 only */
64 
69 struct adxcvr {
71  const char *name;
73  uint32_t base;
79  bool tx_enable;
81  bool lpm_enable;
83  uint32_t num_lanes;
85  uint32_t lane_rate_khz;
87  uint32_t ref_rate_khz;
91  uint32_t sys_clk_sel;
95  uint32_t out_clk_sel;
98 };
99 
105 struct adxcvr_init {
107  const char *name;
109  uint32_t base;
113  uint32_t sys_clk_sel;
117  uint32_t out_clk_sel;
121  uint32_t lane_rate_khz;
123  uint32_t ref_rate_khz;
124 };
125 
126 /******************************************************************************/
127 /************************ Functions Declarations ******************************/
128 /******************************************************************************/
130 int adxcvr_drp_read(struct adxcvr *xcvr,
131  unsigned int drp_port,
132  unsigned int reg,
133  unsigned int *val);
135 int adxcvr_drp_write(struct adxcvr *xcvr,
136  unsigned int drp_port,
137  unsigned int reg,
138  unsigned int val);
140 int32_t adxcvr_status_error(struct adxcvr *xcvr);
142 int adxcvr_clk_enable(struct adxcvr *xcvr);
144 int adxcvr_clk_disable(struct adxcvr *xcvr);
146 int32_t adxcvr_init(struct adxcvr **ad_xcvr,
147  const struct adxcvr_init *init);
149 int32_t adxcvr_remove(struct adxcvr *xcvr);
151 int adxcvr_clk_set_rate(struct adxcvr *xcvr,
152  unsigned long rate,
153  unsigned long parent_rate);
155 int32_t adxcvr_write(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t reg_val);
157 int32_t adxcvr_read(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t *reg_val);
158 #endif
adxcvr_clk_enable
int adxcvr_clk_enable(struct adxcvr *xcvr)
AXI ADXCVR Clock Enable.
Definition: axi_adxcvr.c:498
xilinx_xcvr::speed_grade
enum axi_fpga_speed_grade speed_grade
Definition: xilinx_transceiver.h:180
AXI_INFO_FPGA_DEV_PACKAGE
#define AXI_INFO_FPGA_DEV_PACKAGE(info)
Definition: clk_axi_clkgen.c:72
timeout
uint32_t timeout
Definition: ad413x.c:54
adxcvr::lane_rate_khz
uint32_t lane_rate_khz
Definition: altera_adxcvr.h:103
xilinx_transceiver.h
Driver for the Xilinx High-speed transceiver dynamic reconfiguration.
adxcvr_remove
int32_t adxcvr_remove(struct adxcvr *xcvr)
adxcvr_remove
Definition: altera_adxcvr.c:494
adxcvr::name
const char * name
Definition: altera_adxcvr.h:96
xilinx_xcvr_calc_qpll_config
int xilinx_xcvr_calc_qpll_config(struct xilinx_xcvr *xcvr, uint32_t sys_clk_sel, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_qpll_config *conf, uint32_t *out_div)
Definition: xilinx_transceiver.c:674
adxcvr::qpll_enable
bool qpll_enable
Definition: axi_adxcvr.h:77
adxcvr_clk_set_rate
int adxcvr_clk_set_rate(struct adxcvr *xcvr, unsigned long rate, unsigned long parent_rate)
AXI ADXCVR Clock Set Rate.
Definition: axi_adxcvr.c:328
adxcvr_status_error
int32_t adxcvr_status_error(struct adxcvr *xcvr)
AXI ADXCVR Status Read.
Definition: axi_adxcvr.c:452
xilinx_xcvr::family
enum axi_fpga_family family
Definition: xilinx_transceiver.h:179
ADXCVR_DRP_PORT_ADDR_COMMON
#define ADXCVR_DRP_PORT_ADDR_COMMON
Definition: axi_adxcvr.c:85
adxcvr
ADI JESD204B/C AXI_ADXCVR Highspeed Transceiver Device structure.
Definition: altera_adxcvr.h:95
adxcvr_drp_write
int adxcvr_drp_write(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int val)
AXI ADXCVR DPR Port Write.
Definition: axi_adxcvr.c:200
adxcvr::ref_rate_khz
uint32_t ref_rate_khz
Definition: axi_adxcvr.h:87
ADXCVR_PROGDIV_CLK
#define ADXCVR_PROGDIV_CLK
Definition: axi_adxcvr.h:63
pr_err
#define pr_err(fmt, args...)
Definition: no_os_print_log.h:94
no_os_delay.h
Header file of Delay functions.
ADXCVR_REG_DRP_SEL
#define ADXCVR_REG_DRP_SEL(x)
Definition: axi_adxcvr.c:74
ADXCVR_BUFSTATUS_RST
#define ADXCVR_BUFSTATUS_RST
Definition: axi_adxcvr.c:59
XILINX_XCVR_LEGACY_TYPE_S7_GTX2
@ XILINX_XCVR_LEGACY_TYPE_S7_GTX2
Definition: xilinx_transceiver.h:87
pr_info
#define pr_info(fmt, args...)
Definition: no_os_print_log.h:121
adxcvr::base
uint32_t base
Definition: altera_adxcvr.h:97
xilinx_xcvr::type
enum xilinx_xcvr_type type
Definition: xilinx_transceiver.h:173
adxcvr_clk_disable
int adxcvr_clk_disable(struct adxcvr *xcvr)
AXI ADXCVR Clock Disable.
Definition: axi_adxcvr.c:548
xilinx_xcvr::ad_xcvr
struct adxcvr * ad_xcvr
Definition: xilinx_transceiver.h:176
ADXCVR_BUFSTATUS_UNDERFLOW
#define ADXCVR_BUFSTATUS_UNDERFLOW
Definition: axi_adxcvr.c:63
XILINX_XCVR_TYPE_US_GTY4
@ XILINX_XCVR_TYPE_US_GTY4
Definition: xilinx_transceiver.h:79
no_os_print_log.h
Print messages helpers.
xilinx_xcvr_calc_cpll_config
int xilinx_xcvr_calc_cpll_config(struct xilinx_xcvr *xcvr, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_cpll_config *conf, uint32_t *out_div)
Definition: xilinx_transceiver.c:545
PM_200
@ PM_200
Definition: xilinx_transceiver.h:98
xilinx_xcvr::version
uint32_t version
Definition: xilinx_transceiver.h:177
xilinx_xcvr_configure_cdr
int xilinx_xcvr_configure_cdr(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t lane_rate, uint32_t out_div, bool lpm_enable)
Definition: xilinx_transceiver.c:363
no_os_axi_io.h
Header file of AXI IO.
adxcvr_init::lpm_enable
bool lpm_enable
Definition: axi_adxcvr.h:119
ADXCVR_OUTCLK_SEL
#define ADXCVR_OUTCLK_SEL(x)
Definition: axi_adxcvr.c:70
xilinx_xcvr_write_prog_div
int xilinx_xcvr_write_prog_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_prog_div, int32_t tx_prog_div)
Definition: xilinx_transceiver.c:1860
xilinx_xcvr_drp_ops
Definition: xilinx_transceiver.h:191
adxcvr_init
int32_t adxcvr_init(struct adxcvr **ad_xcvr, const struct adxcvr_init *init)
AXI ADXCVR Device Initialization.
Definition: axi_adxcvr.c:581
adxcvr_status_error
int32_t adxcvr_status_error(struct adxcvr *xcvr)
AXI ADXCVR Status Read.
Definition: axi_adxcvr.c:452
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
xilinx_xcvr::refclk_ppm
enum xilinx_xcvr_refclk_ppm refclk_ppm
Definition: xilinx_transceiver.h:174
xilinx_xcvr::tech
enum axi_fgpa_technology tech
Definition: xilinx_transceiver.h:178
AXI_REG_FPGA_INFO
#define AXI_REG_FPGA_INFO
Definition: clk_axi_clkgen.c:66
axi_adxcvr.h
Driver for the ADI AXI-ADXCVR Module.
xilinx_xcvr_qpll_calc_lane_rate
int xilinx_xcvr_qpll_calc_lane_rate(struct xilinx_xcvr *xcvr, uint32_t refclk_hz, const struct xilinx_xcvr_qpll_config *conf, uint32_t out_div)
Definition: xilinx_transceiver.c:1467
no_os_error.h
Error codes definition.
ADXCVR_DRP_CTRL_ADDR
#define ADXCVR_DRP_CTRL_ADDR(x)
Definition: axi_adxcvr.c:78
pr_debug
#define pr_debug(fmt, args...)
Definition: no_os_print_log.h:135
adxcvr::sys_clk_sel
uint32_t sys_clk_sel
Definition: axi_adxcvr.h:91
adxcvr::num_lanes
uint32_t num_lanes
Definition: axi_adxcvr.h:83
ADXCVR_DRP_STATUS_BUSY
#define ADXCVR_DRP_STATUS_BUSY
Definition: axi_adxcvr.c:82
xilinx_xcvr_read_out_div
int xilinx_xcvr_read_out_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t *rx_out_div, uint32_t *tx_out_div)
Definition: xilinx_transceiver.c:1557
XILINX_XCVR_LEGACY_TYPE_US_GTH3
@ XILINX_XCVR_LEGACY_TYPE_US_GTH3
Definition: xilinx_transceiver.h:88
adxcvr_write
int32_t adxcvr_write(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t reg_val)
adxcvr_write
Definition: altera_adxcvr.c:87
adxcvr_remove
int32_t adxcvr_remove(struct adxcvr *xcvr)
Free resoulces allocated for AXI_ADXCVR.
Definition: axi_adxcvr.c:693
ADXCVR_REG_DRP_CTRL
#define ADXCVR_REG_DRP_CTRL(x)
Definition: axi_adxcvr.c:76
AXI_REG_VERSION
#define AXI_REG_VERSION
Definition: clk_axi_clkgen.c:61
xilinx_xcvr::dev_package
enum axi_fpga_dev_pack dev_package
Definition: xilinx_transceiver.h:181
adxcvr_init
Definition: altera_adxcvr.h:108
xilinx_xcvr_qpll_write_config
int xilinx_xcvr_qpll_write_config(struct xilinx_xcvr *xcvr, uint32_t sys_clk_sel, uint32_t drp_port, const struct xilinx_xcvr_qpll_config *conf)
Definition: xilinx_transceiver.c:1439
ADXCVR_DRP_CTRL_WDATA
#define ADXCVR_DRP_CTRL_WDATA(x)
Definition: axi_adxcvr.c:79
adxcvr_init::name
const char * name
Definition: altera_adxcvr.h:109
adxcvr_read
int32_t adxcvr_read(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t *reg_val)
adxcvr_read
Definition: altera_adxcvr.c:99
no_os_axi_io_read
int32_t no_os_axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
AXI IO Altera specific read function.
Definition: altera_axi_io.c:59
adxcvr_init::out_clk_sel
uint32_t out_clk_sel
Definition: axi_adxcvr.h:117
ADXCVR_SYSCLK_SEL
#define ADXCVR_SYSCLK_SEL(x)
Definition: axi_adxcvr.c:69
adxcvr_init
int32_t adxcvr_init(struct adxcvr **ad_xcvr, const struct adxcvr_init *init)
adxcvr_init
Definition: altera_adxcvr.c:443
adxcvr_init::base
uint32_t base
Definition: altera_adxcvr.h:110
adxcvr_clk_enable
int adxcvr_clk_enable(struct adxcvr *xcvr)
AXI ADXCVR Clock Enable.
Definition: axi_adxcvr.c:498
adxcvr_drp_read
int adxcvr_drp_read(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int *val)
AXI ADXCVR DPR Port Read.
Definition: axi_adxcvr.c:165
ADXCVR_DRP_PORT_ADDR_CHANNEL
#define ADXCVR_DRP_PORT_ADDR_CHANNEL
Definition: axi_adxcvr.c:86
xilinx_xcvr::encoding
uint32_t encoding
Definition: xilinx_transceiver.h:175
AXI_REG_FPGA_VOLTAGE
#define AXI_REG_FPGA_VOLTAGE
Definition: clk_axi_clkgen.c:67
ADXCVR_REG_CONTROL
#define ADXCVR_REG_CONTROL
Definition: axi_adxcvr.c:66
adxcvr::xlx_xcvr
struct xilinx_xcvr xlx_xcvr
Definition: axi_adxcvr.h:97
ADXCVR_REG_SYNTH
#define ADXCVR_REG_SYNTH
Definition: axi_adxcvr.c:72
xilinx_xcvr_drp_ops::read
int(* read)(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int *val)
Definition: xilinx_transceiver.h:194
adxcvr_clk_disable
int adxcvr_clk_disable(struct adxcvr *xcvr)
AXI ADXCVR Clock Disable.
Definition: axi_adxcvr.c:548
ADXCVR_REG_RESETN
#define ADXCVR_REG_RESETN
Definition: axi_adxcvr.c:57
ENC_66B64B
#define ENC_66B64B
Definition: xilinx_transceiver.h:274
XILINX_XCVR_TYPE_US_GTH3
@ XILINX_XCVR_TYPE_US_GTH3
Definition: xilinx_transceiver.h:77
xilinx_xcvr_qpll_read_config
int xilinx_xcvr_qpll_read_config(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t sys_clk_sel, struct xilinx_xcvr_qpll_config *conf)
Definition: xilinx_transceiver.c:1257
adxcvr_init::ref_rate_khz
uint32_t ref_rate_khz
Definition: axi_adxcvr.h:123
xilinx_xcvr_cpll_config
Structure holding CPLL configuration.
Definition: xilinx_transceiver.h:255
xilinx_xcvr_write_rx_clk25_div
int xilinx_xcvr_write_rx_clk25_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
Definition: xilinx_transceiver.c:2010
adxcvr_init::lane_rate_khz
uint32_t lane_rate_khz
Definition: altera_adxcvr.h:113
xilinx_xcvr_write_out_div
int xilinx_xcvr_write_out_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_out_div, int32_t tx_out_div)
Definition: xilinx_transceiver.c:1670
adxcvr_read
int32_t adxcvr_read(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t *reg_val)
AXI ADXCVR Read.
Definition: axi_adxcvr.c:123
ADXCVR_SYS_CLK_CPLL
#define ADXCVR_SYS_CLK_CPLL
Definition: axi_adxcvr.h:54
adxcvr_clk_set_rate
int adxcvr_clk_set_rate(struct adxcvr *xcvr, unsigned long rate, unsigned long parent_rate)
AXI ADXCVR Clock Set Rate.
Definition: axi_adxcvr.c:328
xilinx_xcvr::voltage
uint32_t voltage
Definition: xilinx_transceiver.h:182
xilinx_xcvr_cpll_calc_lane_rate
int xilinx_xcvr_cpll_calc_lane_rate(struct xilinx_xcvr *xcvr, uint32_t refclk_hz, const struct xilinx_xcvr_cpll_config *conf, uint32_t out_div)
Definition: xilinx_transceiver.c:1093
ADXCVR_STATUS
#define ADXCVR_STATUS
Definition: axi_adxcvr.c:62
xilinx_xcvr_write_prog_div_rate
int xilinx_xcvr_write_prog_div_rate(struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_rate, int32_t tx_rate)
Definition: xilinx_transceiver.c:1939
no_os_udelay
void no_os_udelay(uint32_t usecs)
Wait until usecs microseconds passed.
Definition: aducm3029_delay.c:120
adxcvr_drp_read
int adxcvr_drp_read(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int *val)
AXI ADXCVR DPR Port Read.
Definition: axi_adxcvr.c:165
NULL
#define NULL
Definition: wrapper.h:64
adxcvr::out_clk_sel
uint32_t out_clk_sel
Definition: axi_adxcvr.h:95
xilinx_xcvr
xilinx_xcvr parameters structure.
Definition: xilinx_transceiver.h:172
ADXCVR_REG_STATUS
#define ADXCVR_REG_STATUS
Definition: axi_adxcvr.c:61
AXI_PCORE_VER_MAJOR
#define AXI_PCORE_VER_MAJOR(version)
Definition: clk_axi_clkgen.c:57
ADXCVR_BUFSTATUS_OVERFLOW
#define ADXCVR_BUFSTATUS_OVERFLOW
Definition: axi_adxcvr.c:64
xilinx_xcvr_configure_lpm_dfe_mode
int xilinx_xcvr_configure_lpm_dfe_mode(struct xilinx_xcvr *xcvr, uint32_t drp_port, bool lpm)
Definition: xilinx_transceiver.c:390
ADXCVR_DRP_PORT_COMMON
#define ADXCVR_DRP_PORT_COMMON(x)
Definition: axi_adxcvr.c:88
no_os_axi_io_write
int32_t no_os_axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
AXI IO Altera specific write function.
Definition: altera_axi_io.c:73
xilinx_xcvr_qpll_config
Structure holding QPLL configuration.
Definition: xilinx_transceiver.h:265
ADXCVR_REG_DRP_STATUS
#define ADXCVR_REG_DRP_STATUS(x)
Definition: axi_adxcvr.c:81
AXI_INFO_FPGA_TECH
#define AXI_INFO_FPGA_TECH(info)
Definition: clk_axi_clkgen.c:69
adxcvr_init::sys_clk_sel
uint32_t sys_clk_sel
Definition: axi_adxcvr.h:113
clk_ops::recalc_rate
unsigned long(* recalc_rate)(struct adxcvr *xcvr, unsigned long parent_rate)
Definition: xilinx_transceiver.h:241
adxcvr::tx_enable
bool tx_enable
Definition: axi_adxcvr.h:79
clk_ops
Definition: xilinx_transceiver.h:238
adxcvr_write
int32_t adxcvr_write(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t reg_val)
AXI ADXCVR Write.
Definition: axi_adxcvr.c:107
ADXCVR_DRP_STATUS_RDATA
#define ADXCVR_DRP_STATUS_RDATA(x)
Definition: axi_adxcvr.c:83
no_os_util.h
Header file of utility functions.
XILINX_XCVR_LEGACY_TYPE_US_GTY4
@ XILINX_XCVR_LEGACY_TYPE_US_GTY4
Definition: xilinx_transceiver.h:90
adxcvr_drp_wait_idle
int32_t adxcvr_drp_wait_idle(struct adxcvr *xcvr, uint32_t drp_addr)
Read AXI ADXCVR DRP status.
Definition: axi_adxcvr.c:138
ADI_AXI_PCORE_VER
#define ADI_AXI_PCORE_VER(major, minor, patch)
Definition: axi_adxcvr.c:93
ADXCVR_DRP_PORT_CHANNEL
#define ADXCVR_DRP_PORT_CHANNEL(x)
Definition: axi_adxcvr.c:89
XILINX_XCVR_TYPE_US_GTH4
@ XILINX_XCVR_TYPE_US_GTH4
Definition: xilinx_transceiver.h:78
adxcvr::cpll_enable
bool cpll_enable
Definition: axi_adxcvr.h:75
XILINX_XCVR_LEGACY_TYPE_US_GTH4
@ XILINX_XCVR_LEGACY_TYPE_US_GTH4
Definition: xilinx_transceiver.h:89
xilinx_xcvr_write_tx_clk25_div
int xilinx_xcvr_write_tx_clk25_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
Definition: xilinx_transceiver.c:2052
ADXCVR_LPM_DFE_N
#define ADXCVR_LPM_DFE_N
Definition: axi_adxcvr.c:67
adxcvr_drp_write
int adxcvr_drp_write(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int val)
AXI ADXCVR DPR Port Write.
Definition: axi_adxcvr.c:200
ENC_8B10B
#define ENC_8B10B
Definition: xilinx_transceiver.h:273
AXI_INFO_FPGA_FAMILY
#define AXI_INFO_FPGA_FAMILY(info)
Definition: clk_axi_clkgen.c:70
xilinx_xcvr_cpll_write_config
int xilinx_xcvr_cpll_write_config(struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_cpll_config *conf)
Definition: xilinx_transceiver.c:1067
NO_OS_DIV_ROUND_CLOSEST
#define NO_OS_DIV_ROUND_CLOSEST(x, y)
Definition: no_os_util.h:58
AXI_INFO_FPGA_VOLTAGE
#define AXI_INFO_FPGA_VOLTAGE(val)
Definition: clk_axi_clkgen.c:73
xilinx_xcvr_cpll_read_config
int xilinx_xcvr_cpll_read_config(struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_cpll_config *conf)
Definition: xilinx_transceiver.c:912
AXI_INFO_FPGA_SPEED_GRADE
#define AXI_INFO_FPGA_SPEED_GRADE(info)
Definition: clk_axi_clkgen.c:71
adxcvr::lpm_enable
bool lpm_enable
Definition: axi_adxcvr.h:81
ADXCVR_RESETN
#define ADXCVR_RESETN
Definition: axi_adxcvr.c:58
XILINX_XCVR_TYPE_S7_GTX2
@ XILINX_XCVR_TYPE_S7_GTX2
Definition: xilinx_transceiver.h:76
ADXCVR_DRP_CTRL_WR
#define ADXCVR_DRP_CTRL_WR
Definition: axi_adxcvr.c:77