no-OS
axi_adxcvr.h
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1 /***************************************************************************/
39 #ifndef AXI_ADXCVR_H_
40 #define AXI_ADXCVR_H_
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include <stdint.h>
46 #include <stdbool.h>
47 #include "xilinx_transceiver.h"
48 
49 /******************************************************************************/
50 /*************************** Types Declarations *******************************/
51 /******************************************************************************/
56 struct adxcvr {
58  const char *name;
60  uint32_t base;
64  bool tx_enable;
66  bool lpm_enable;
68  uint32_t num_lanes;
70  uint32_t lane_rate_khz;
72  uint32_t ref_rate_khz;
76  uint32_t sys_clk_sel;
80  uint32_t out_clk_sel;
83 };
84 
90 struct adxcvr_init {
92  const char *name;
94  uint32_t base;
98  uint32_t sys_clk_sel;
102  uint32_t out_clk_sel;
108  uint32_t lane_rate_khz;
110  uint32_t ref_rate_khz;
111 };
112 
113 /******************************************************************************/
114 /************************ Functions Declarations ******************************/
115 /******************************************************************************/
117 int32_t adxcvr_drp_read(struct adxcvr *xcvr,
118  uint32_t drp_port,
119  uint32_t reg,
120  uint32_t *val);
122 int32_t adxcvr_drp_write(struct adxcvr *xcvr,
123  uint32_t drp_port,
124  uint32_t reg,
125  uint32_t val);
127 int32_t adxcvr_status_error(struct adxcvr *xcvr);
129 int32_t adxcvr_clk_enable(struct adxcvr *xcvr);
131 int32_t adxcvr_clk_disable(struct adxcvr *xcvr);
133 int32_t adxcvr_init(struct adxcvr **ad_xcvr,
134  const struct adxcvr_init *init);
136 int32_t adxcvr_remove(struct adxcvr *xcvr);
138 int32_t adxcvr_clk_set_rate(struct adxcvr *xcvr,
139  uint32_t rate,
140  uint32_t parent_rate);
142 int32_t adxcvr_write(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t reg_val);
144 int32_t adxcvr_read(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t *reg_val);
145 #endif
xilinx_xcvr_write_out_div
int32_t xilinx_xcvr_write_out_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_out_div, int32_t tx_out_div)
xilinx_xcvr_write_out_div
Definition: xilinx_transceiver.c:1295
xilinx_xcvr::speed_grade
enum axi_fpga_speed_grade speed_grade
Definition: xilinx_transceiver.h:148
AXI_INFO_FPGA_DEV_PACKAGE
#define AXI_INFO_FPGA_DEV_PACKAGE(info)
Definition: clk_axi_clkgen.c:72
adxcvr::lane_rate_khz
uint32_t lane_rate_khz
Definition: altera_adxcvr.h:103
xilinx_transceiver.h
Driver for the Xilinx High-speed transceiver dynamic reconfiguration.
adxcvr_remove
int32_t adxcvr_remove(struct adxcvr *xcvr)
adxcvr_remove
Definition: altera_adxcvr.c:494
adxcvr::name
const char * name
Definition: altera_adxcvr.h:96
adxcvr_clk_enable
int32_t adxcvr_clk_enable(struct adxcvr *xcvr)
AXI ADXCVR Clock Enable.
Definition: axi_adxcvr.c:322
adxcvr_status_error
int32_t adxcvr_status_error(struct adxcvr *xcvr)
AXI ADXCVR Status Read.
Definition: axi_adxcvr.c:299
xilinx_xcvr::family
enum axi_fpga_family family
Definition: xilinx_transceiver.h:147
ADXCVR_DRP_PORT_ADDR_COMMON
#define ADXCVR_DRP_PORT_ADDR_COMMON
Definition: axi_adxcvr.c:81
adxcvr
ADI JESD204B/C AXI_ADXCVR Highspeed Transceiver Device structure.
Definition: altera_adxcvr.h:95
adxcvr::ref_rate_khz
uint32_t ref_rate_khz
Definition: axi_adxcvr.h:72
no_os_delay.h
Header file of Delay functions.
ADXCVR_REG_DRP_SEL
#define ADXCVR_REG_DRP_SEL(x)
Definition: axi_adxcvr.c:70
XILINX_XCVR_LEGACY_TYPE_S7_GTX2
@ XILINX_XCVR_LEGACY_TYPE_S7_GTX2
Definition: xilinx_transceiver.h:79
adxcvr_drp_read
int32_t adxcvr_drp_read(struct adxcvr *xcvr, uint32_t drp_port, uint32_t reg, uint32_t *val)
AXI ADXCVR DPR Port Read.
Definition: axi_adxcvr.c:154
adxcvr::base
uint32_t base
Definition: altera_adxcvr.h:97
xilinx_xcvr::type
enum xilinx_xcvr_type type
Definition: xilinx_transceiver.h:141
xilinx_xcvr::ad_xcvr
struct adxcvr * ad_xcvr
Definition: xilinx_transceiver.h:144
XILINX_XCVR_TYPE_US_GTY4
@ XILINX_XCVR_TYPE_US_GTY4
Definition: xilinx_transceiver.h:75
PM_200
@ PM_200
Definition: xilinx_transceiver.h:86
xilinx_xcvr::version
uint32_t version
Definition: xilinx_transceiver.h:145
no_os_axi_io.h
Header file of AXI IO.
adxcvr_init::lpm_enable
bool lpm_enable
Definition: axi_adxcvr.h:106
ADXCVR_OUTCLK_SEL
#define ADXCVR_OUTCLK_SEL(x)
Definition: axi_adxcvr.c:66
adxcvr_init::cpll_enable
bool cpll_enable
Definition: axi_adxcvr.h:104
adxcvr_clk_disable
int32_t adxcvr_clk_disable(struct adxcvr *xcvr)
AXI ADXCVR Clock Disable.
Definition: axi_adxcvr.c:335
adxcvr_init
int32_t adxcvr_init(struct adxcvr **ad_xcvr, const struct adxcvr_init *init)
AXI ADXCVR Device Initialization.
Definition: axi_adxcvr.c:366
adxcvr_status_error
int32_t adxcvr_status_error(struct adxcvr *xcvr)
AXI ADXCVR Status Read.
Definition: axi_adxcvr.c:299
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
adxcvr_drp_write
int32_t adxcvr_drp_write(struct adxcvr *xcvr, uint32_t drp_port, uint32_t reg, uint32_t val)
AXI ADXCVR DPR Port Write.
Definition: axi_adxcvr.c:189
xilinx_xcvr::refclk_ppm
enum xilinx_xcvr_refclk_ppm refclk_ppm
Definition: xilinx_transceiver.h:142
xilinx_xcvr_configure_cdr
int32_t xilinx_xcvr_configure_cdr(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t lane_rate, uint32_t out_div, bool lpm_enable)
xilinx_xcvr_configure_cdr
Definition: xilinx_transceiver.c:306
xilinx_xcvr::tech
enum axi_fgpa_technology tech
Definition: xilinx_transceiver.h:146
AXI_REG_FPGA_INFO
#define AXI_REG_FPGA_INFO
Definition: clk_axi_clkgen.c:66
axi_adxcvr.h
Driver for the ADI AXI-ADXCVR Module.
no_os_error.h
Error codes definition.
ADXCVR_DRP_CTRL_ADDR
#define ADXCVR_DRP_CTRL_ADDR(x)
Definition: axi_adxcvr.c:74
adxcvr::sys_clk_sel
uint32_t sys_clk_sel
Definition: axi_adxcvr.h:76
adxcvr_clk_set_rate
int32_t adxcvr_clk_set_rate(struct adxcvr *xcvr, uint32_t rate, uint32_t parent_rate)
AXI ADXCVR Clock Set Rate.
Definition: axi_adxcvr.c:222
adxcvr_drp_write
int32_t adxcvr_drp_write(struct adxcvr *xcvr, uint32_t drp_port, uint32_t reg, uint32_t val)
AXI ADXCVR DPR Port Write.
Definition: axi_adxcvr.c:189
adxcvr::num_lanes
uint32_t num_lanes
Definition: axi_adxcvr.h:68
ADXCVR_DRP_STATUS_BUSY
#define ADXCVR_DRP_STATUS_BUSY
Definition: axi_adxcvr.c:78
xilinx_xcvr_cpll_write_config
int32_t xilinx_xcvr_cpll_write_config(struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_cpll_config *conf)
xilinx_xcvr_cpll_write_config
Definition: xilinx_transceiver.c:825
XILINX_XCVR_LEGACY_TYPE_US_GTH3
@ XILINX_XCVR_LEGACY_TYPE_US_GTH3
Definition: xilinx_transceiver.h:80
adxcvr_write
int32_t adxcvr_write(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t reg_val)
adxcvr_write
Definition: altera_adxcvr.c:87
adxcvr_remove
int32_t adxcvr_remove(struct adxcvr *xcvr)
Free resoulces allocated for AXI_ADXCVR.
Definition: axi_adxcvr.c:471
xilinx_xcvr_write_rx_clk25_div
int32_t xilinx_xcvr_write_rx_clk25_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
xilinx_xcvr_write_rx_clk25_div
Definition: xilinx_transceiver.c:1315
ADXCVR_REG_DRP_CTRL
#define ADXCVR_REG_DRP_CTRL(x)
Definition: axi_adxcvr.c:72
AXI_REG_VERSION
#define AXI_REG_VERSION
Definition: clk_axi_clkgen.c:61
xilinx_xcvr::dev_package
enum axi_fpga_dev_pack dev_package
Definition: xilinx_transceiver.h:149
adxcvr_init
Definition: altera_adxcvr.h:108
adxcvr_clk_set_rate
int32_t adxcvr_clk_set_rate(struct adxcvr *xcvr, uint32_t rate, uint32_t parent_rate)
AXI ADXCVR Clock Set Rate.
Definition: axi_adxcvr.c:222
ADXCVR_DRP_CTRL_WDATA
#define ADXCVR_DRP_CTRL_WDATA(x)
Definition: axi_adxcvr.c:75
adxcvr_init::name
const char * name
Definition: altera_adxcvr.h:109
adxcvr_read
int32_t adxcvr_read(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t *reg_val)
adxcvr_read
Definition: altera_adxcvr.c:99
no_os_axi_io_read
int32_t no_os_axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
AXI IO Altera specific read function.
Definition: axi_io.c:59
adxcvr_init::out_clk_sel
uint32_t out_clk_sel
Definition: axi_adxcvr.h:102
ADXCVR_SYSCLK_SEL
#define ADXCVR_SYSCLK_SEL(x)
Definition: axi_adxcvr.c:65
adxcvr_init
int32_t adxcvr_init(struct adxcvr **ad_xcvr, const struct adxcvr_init *init)
adxcvr_init
Definition: altera_adxcvr.c:443
adxcvr_init::base
uint32_t base
Definition: altera_adxcvr.h:110
xilinx_xcvr_qpll_write_config
int32_t xilinx_xcvr_qpll_write_config(struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_qpll_config *conf)
xilinx_xcvr_qpll_write_config
Definition: xilinx_transceiver.c:1130
ADXCVR_DRP_PORT_ADDR_CHANNEL
#define ADXCVR_DRP_PORT_ADDR_CHANNEL
Definition: axi_adxcvr.c:82
xilinx_xcvr::encoding
uint32_t encoding
Definition: xilinx_transceiver.h:143
AXI_REG_FPGA_VOLTAGE
#define AXI_REG_FPGA_VOLTAGE
Definition: clk_axi_clkgen.c:67
ADXCVR_REG_CONTROL
#define ADXCVR_REG_CONTROL
Definition: axi_adxcvr.c:62
adxcvr::xlx_xcvr
struct xilinx_xcvr xlx_xcvr
Definition: axi_adxcvr.h:82
ADXCVR_REG_SYNTH
#define ADXCVR_REG_SYNTH
Definition: axi_adxcvr.c:68
ADXCVR_REG_RESETN
#define ADXCVR_REG_RESETN
Definition: axi_adxcvr.c:56
XILINX_XCVR_TYPE_US_GTH3
@ XILINX_XCVR_TYPE_US_GTH3
Definition: xilinx_transceiver.h:73
adxcvr_init::ref_rate_khz
uint32_t ref_rate_khz
Definition: axi_adxcvr.h:110
xilinx_xcvr_cpll_config
Definition: xilinx_transceiver.h:153
adxcvr_init::lane_rate_khz
uint32_t lane_rate_khz
Definition: altera_adxcvr.h:113
xilinx_xcvr_write_tx_clk25_div
int32_t xilinx_xcvr_write_tx_clk25_div(struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
xilinx_xcvr_write_tx_clk25_div
Definition: xilinx_transceiver.c:1348
xilinx_xcvr_check_lane_rate
int32_t xilinx_xcvr_check_lane_rate(struct xilinx_xcvr *xcvr, uint32_t lane_rate_khz)
xilinx_xcvr_check_lane_rate
Definition: xilinx_transceiver.c:326
adxcvr_read
int32_t adxcvr_read(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t *reg_val)
AXI ADXCVR Read.
Definition: axi_adxcvr.c:112
xilinx_xcvr::voltage
uint32_t voltage
Definition: xilinx_transceiver.h:150
xilinx_xcvr_configure_lpm_dfe_mode
int32_t xilinx_xcvr_configure_lpm_dfe_mode(struct xilinx_xcvr *xcvr, uint32_t drp_port, bool lpm)
xilinx_xcvr_configure_lpm_dfe_mode
Definition: xilinx_transceiver.c:419
adxcvr_clk_disable
int32_t adxcvr_clk_disable(struct adxcvr *xcvr)
AXI ADXCVR Clock Disable.
Definition: axi_adxcvr.c:335
adxcvr::out_clk_sel
uint32_t out_clk_sel
Definition: axi_adxcvr.h:80
xilinx_xcvr
Definition: xilinx_transceiver.h:140
ADXCVR_REG_STATUS
#define ADXCVR_REG_STATUS
Definition: axi_adxcvr.c:59
adxcvr_drp_read
int32_t adxcvr_drp_read(struct adxcvr *xcvr, uint32_t drp_port, uint32_t reg, uint32_t *val)
AXI ADXCVR DPR Port Read.
Definition: axi_adxcvr.c:154
AXI_PCORE_VER_MAJOR
#define AXI_PCORE_VER_MAJOR(version)
Definition: clk_axi_clkgen.c:57
ADXCVR_DRP_PORT_COMMON
#define ADXCVR_DRP_PORT_COMMON(x)
Definition: axi_adxcvr.c:84
no_os_axi_io_write
int32_t no_os_axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
AXI IO Altera specific write function.
Definition: axi_io.c:73
xilinx_xcvr_qpll_config
Definition: xilinx_transceiver.h:159
ADXCVR_REG_DRP_STATUS
#define ADXCVR_REG_DRP_STATUS(x)
Definition: axi_adxcvr.c:77
AXI_INFO_FPGA_TECH
#define AXI_INFO_FPGA_TECH(info)
Definition: clk_axi_clkgen.c:69
adxcvr_init::sys_clk_sel
uint32_t sys_clk_sel
Definition: axi_adxcvr.h:98
adxcvr::tx_enable
bool tx_enable
Definition: axi_adxcvr.h:64
adxcvr_write
int32_t adxcvr_write(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t reg_val)
AXI ADXCVR Write.
Definition: axi_adxcvr.c:96
ADXCVR_DRP_STATUS_RDATA
#define ADXCVR_DRP_STATUS_RDATA(x)
Definition: axi_adxcvr.c:79
no_os_util.h
Implementation of utility functions.
XILINX_XCVR_LEGACY_TYPE_US_GTY4
@ XILINX_XCVR_LEGACY_TYPE_US_GTY4
Definition: xilinx_transceiver.h:82
adxcvr_drp_wait_idle
int32_t adxcvr_drp_wait_idle(struct adxcvr *xcvr, uint32_t drp_addr)
Read AXI ADXCVR DRP status.
Definition: axi_adxcvr.c:127
ADXCVR_DRP_PORT_CHANNEL
#define ADXCVR_DRP_PORT_CHANNEL(x)
Definition: axi_adxcvr.c:85
xilinx_xcvr_calc_cpll_config
int32_t xilinx_xcvr_calc_cpll_config(struct xilinx_xcvr *xcvr, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_cpll_config *conf, uint32_t *out_div)
xilinx_xcvr_calc_cpll_config
Definition: xilinx_transceiver.c:445
XILINX_XCVR_TYPE_US_GTH4
@ XILINX_XCVR_TYPE_US_GTH4
Definition: xilinx_transceiver.h:74
adxcvr::cpll_enable
bool cpll_enable
Definition: axi_adxcvr.h:62
XILINX_XCVR_LEGACY_TYPE_US_GTH4
@ XILINX_XCVR_LEGACY_TYPE_US_GTH4
Definition: xilinx_transceiver.h:81
ADXCVR_LPM_DFE_N
#define ADXCVR_LPM_DFE_N
Definition: axi_adxcvr.c:63
ENC_8B10B
#define ENC_8B10B
Definition: xilinx_transceiver.h:165
xilinx_xcvr_calc_qpll_config
int32_t xilinx_xcvr_calc_qpll_config(struct xilinx_xcvr *xcvr, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_qpll_config *conf, uint32_t *out_div)
xilinx_xcvr_calc_qpll_config
Definition: xilinx_transceiver.c:517
adxcvr_clk_enable
int32_t adxcvr_clk_enable(struct adxcvr *xcvr)
AXI ADXCVR Clock Enable.
Definition: axi_adxcvr.c:322
AXI_INFO_FPGA_FAMILY
#define AXI_INFO_FPGA_FAMILY(info)
Definition: clk_axi_clkgen.c:70
NO_OS_DIV_ROUND_CLOSEST
#define NO_OS_DIV_ROUND_CLOSEST(x, y)
Definition: no_os_util.h:58
AXI_INFO_FPGA_VOLTAGE
#define AXI_INFO_FPGA_VOLTAGE(val)
Definition: clk_axi_clkgen.c:73
AXI_INFO_FPGA_SPEED_GRADE
#define AXI_INFO_FPGA_SPEED_GRADE(info)
Definition: clk_axi_clkgen.c:71
adxcvr::lpm_enable
bool lpm_enable
Definition: axi_adxcvr.h:66
ADXCVR_RESETN
#define ADXCVR_RESETN
Definition: axi_adxcvr.c:57
XILINX_XCVR_TYPE_S7_GTX2
@ XILINX_XCVR_TYPE_S7_GTX2
Definition: xilinx_transceiver.h:72
ADXCVR_DRP_CTRL_WR
#define ADXCVR_DRP_CTRL_WR
Definition: axi_adxcvr.c:73