no-OS
axi_fmcadc5_sync.h
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1 /*
2  * axi_fmcadc5_sync.h
3  *
4  * Created on: Mar 30, 2018
5  * Author: adrimbar
6  */
7 
8 #ifndef SRC_I5G_H_
9 #define SRC_I5G_H_
10 
11 /* Register addresses & data (direct access) */
12 #define I5G_VERSION_ADDR (0x0000 << 2)
13 #define I5G_IDENTIFIER_ADDR (0x0001 << 2)
14 #define I5G_SCRATCH_ADDR (0x0002 << 2)
15 #define I5G_TIMER_ADDR (0x0003 << 2)
16 #define I5G_SPI_REQUEST_ADDR (0x0010 << 2)
17 #define I5G_SPI_GRANT_ADDR (0x0011 << 2)
18 #define I5G_SPI_SELECT_N_ADDR (0x0012 << 2)
19 #define I5G_SPI_TRANSMIT_ADDR (0x0013 << 2)
20 #define I5G_SPI_RECEIVE_ADDR (0x0014 << 2)
21 #define I5G_SPI_BUSY_ADDR (0x0015 << 2)
22 #define I5G_DELAY_ADDR (0x0020 << 2)
23 #define I5G_DELAY_VERIFY_ADDR (0x0021 << 2)
24 #define I5G_DELAY_LOCKED_ADDR (0x0022 << 2)
25 #define I5G_SYNC_CONTROL_ADDR (0x0030 << 2)
26 #define I5G_SYNC_STATUS_ADDR (0x0031 << 2)
27 #define I5G_SYSREF_CONTROL_ADDR (0x0040 << 2)
28 #define I5G_SYSREF_REQUEST_ADDR (0x0041 << 2)
29 #define I5G_VCAL_CNT_ADDR (0x0050 << 2)
30 #define I5G_VCAL_ENABLE_ADDR (0x0051 << 2)
31 #define I5G_CAL_ENABLE_ADDR (0x0060 << 2)
32 #define I5G_CAL_MAX_0_ADDR (0x0064 << 2)
33 #define I5G_CAL_MIN_0_ADDR (0x0065 << 2)
34 #define I5G_CAL_MAX_1_ADDR (0x0066 << 2)
35 #define I5G_CAL_MIN_1_ADDR (0x0067 << 2)
36 #define I5G_COR_ENABLE_ADDR (0x0061 << 2)
37 #define I5G_COR_SCALE_0_ADDR (0x0068 << 2)
38 #define I5G_COR_OFFSET_0_ADDR (0x0069 << 2)
39 #define I5G_COR_SCALE_1_ADDR (0x006a << 2)
40 #define I5G_COR_OFFSET_1_ADDR (0x006b << 2)
41 
42 /* Register addresses & data (direct access) */
43 #define I5G_VERSION 0x040063 /* version (4.0a) */
44 #define I5G_SPI_REQUEST_ACCESS 0x000001 /* request access */
45 #define I5G_SPI_REQUEST_RELEASE 0x000000 /* release access */
46 #define I5G_SPI_ACCESS_ENABLED 0x000001 /* request enabled */
47 #define I5G_SPI_ACCESS_DISABLED 0x000000 /* request disabled */
48 #define I5G_SPI_BUSY 0x000001 /* access busy */
49 #define I5G_DELAY_LOCKED 0x000001 /* delay is locked */
50 #define I5G_SYNC_SET 0x000007 /* dual mode and disabled */
51 #define I5G_SYNC_RELEASE 0x000004 /* dual mode and enabled */
52 #define I5G_SYNC_OOS 0x000000 /* out-of-sync */
53 #define I5G_SYSREF_SET 0x000021 /* one-shot and disabled */
54 #define I5G_SYSREF_RELEASE 0x000020 /* one-shot and enabled */
55 #define I5G_SYSREF_REQUEST 0x000001 /* sysref-request */
56 #define I5G_SYSREF_BUSY 0x000001 /* sysref-busy */
57 #define I5G_VCAL_CNT_10M 0x000004 /* 100/((n+1)*2) */
58 #define I5G_VCAL_ENABLE 0x000001 /* enable */
59 #define I5G_VCAL_DISABLE 0x000000 /* enable */
60 #define I5G_CAL_ENABLE 0x000001 /* enable */
61 #define I5G_CAL_DISABLE 0x000000 /* enable */
62 #define I5G_COR_ENABLE 0x000001 /* enable */
63 #define I5G_COR_DISABLE 0x000000 /* enable */
64 
65 /* Register addresses & data (indirect access) */
66 #define I5G_AD9625_ID_ADDR 0x000001 /* identifier address */
67 #define I5G_AD9625_ID_DATA 0x000041 /* refer data sheet for details */
68 #define I5G_AD9625_ST_ADDR 0x000072 /* sysref time-stamp address [7:6] */
69 #define I5G_AD9625_ST_DATA 0x00008b /* sysref timestamping enabled (2'b10) */
70 #define I5G_AD9625_SG_ADDR 0x00013c /* sysref guard band [7:5] */
71 #define I5G_AD9625_SS_ADDR 0x000100 /* sysref status reporting [2] */
72 #define I5G_AD9625_SS_MASK 0x000004 /* setup violations mask */
73 #define I5G_AD9625_SS_SET 0x000004 /* setup violations detected */
74 #define I5G_AD9625_IO_ADDR 0x0000ff /* internal update address [0] */
75 #define I5G_AD9625_IO_DATA 0x000001 /* register update(1), self-clearing */
76 #define I5G_AD9625_SC_ADDR 0x00003a /* sysref control address */
77 
78 /* [6] run(0)/clear(1), [3] @pos(0)/@neg(1), [2] continous(0)/one-shot(1),
79  * [1] disable(0)/enable(0)
80  * */
81 #define I5G_AD9625_SC_ENABLE(sel) ((sel == 1) ? 0x00000e : 0x000006)
82 #define I5G_AD9625_SC_RECEIVED(sel) ((sel == 1) ? 0x00000c : 0x000004)
83 #define I5G_AD9625_SC_CLEAR(sel) ((sel == 1) ? 0x00004e : 0x000046)
84 
85 /* Default is ms, we need finer delays (10ns) */
86 #define I5G_TIMER_US(d) ((d*100)-1)
87 
88 /******************************************************************************/
89 /*************************** Types Declarations *******************************/
90 /******************************************************************************/
91 struct s_i5g {
94  int32_t regs;
95  int32_t ad9625_cs_0;
96  int32_t ad9625_cs_1;
97  int32_t sysref_delay;
98 };
99 
100 struct s_i5g_init {
103  int32_t regs;
104  int32_t ad9625_cs_0;
105  int32_t ad9625_cs_1;
106  int32_t sysref_delay;
107 };
108 
109 /******************************************************************************/
110 /************************ Functions Declarations ******************************/
111 /******************************************************************************/
112 /* Initializes core descriptor with the devices */
113 int32_t i5g_setup(struct s_i5g **descriptor,
114  struct s_i5g_init init_param);
115 
116 /* Free the resources allocated by i5g_setup() */
117 int32_t i5g_remove(struct s_i5g *desc);
118 
119 #endif /* SRC_I5G_H_ */
axi_adc_core.h
Driver for the Analog Devices AXI-ADC-CORE module.
I5G_SPI_REQUEST_RELEASE
#define I5G_SPI_REQUEST_RELEASE
Definition: axi_fmcadc5_sync.h:45
IIO_APP_DEVICE
#define IIO_APP_DEVICE(_name, _dev, _dev_descriptor, _read_buff, _write_buff)
Definition: iio_app.h:46
I5G_SPI_REQUEST_ADDR
#define I5G_SPI_REQUEST_ADDR
Definition: axi_fmcadc5_sync.h:16
timeout
uint32_t timeout
Definition: ad413x.c:54
s_i5g_init::sysref_delay
int32_t sysref_delay
Definition: axi_fmcadc5_sync.h:106
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
I5G_AD9625_SC_ADDR
#define I5G_AD9625_SC_ADDR
Definition: axi_fmcadc5_sync.h:76
I5G_CAL_MIN_0_ADDR
#define I5G_CAL_MIN_0_ADDR
Definition: axi_fmcadc5_sync.h:33
ad9625_spi_read
int32_t ad9625_spi_read(struct ad9625_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9625_spi_read
Definition: ad9625.c:50
adxcvr::name
const char * name
Definition: altera_adxcvr.h:96
I5G_SPI_BUSY_ADDR
#define I5G_SPI_BUSY_ADDR
Definition: axi_fmcadc5_sync.h:21
I5G_CAL_ENABLE_ADDR
#define I5G_CAL_ENABLE_ADDR
Definition: axi_fmcadc5_sync.h:31
I5G_AD9625_ID_ADDR
#define I5G_AD9625_ID_ADDR
Definition: axi_fmcadc5_sync.h:66
GPIO_PS
@ GPIO_PS
Definition: xilinx_gpio.h:62
ADC_MAX_SAMPLES
#define ADC_MAX_SAMPLES
Definition: parameters.h:46
SPI_PS
@ SPI_PS
Definition: xilinx_spi.h:68
I5G_AD9625_ST_DATA
#define I5G_AD9625_ST_DATA
Definition: axi_fmcadc5_sync.h:69
iio_data_buffer::size
uint32_t size
Definition: iio_app.h:61
AD9625_TEST_OFF
#define AD9625_TEST_OFF
Definition: ad9625.h:70
axi_dmac_init
Definition: axi_dmac.h:129
axi_dmac_init::name
const char * name
Definition: axi_dmac.h:130
s_i5g::ad9625_0_device
struct ad9625_dev * ad9625_0_device
Definition: axi_fmcadc5_sync.h:92
parameters.h
Platform dependent parameters.
I5G_COR_SCALE_0_ADDR
#define I5G_COR_SCALE_0_ADDR
Definition: axi_fmcadc5_sync.h:37
I5G_COR_ENABLE
#define I5G_COR_ENABLE
Definition: axi_fmcadc5_sync.h:62
AD9625_REG_CHIP_ID
#define AD9625_REG_CHIP_ID
Definition: ad9625.h:53
s_i5g::ad9625_cs_1
int32_t ad9625_cs_1
Definition: axi_fmcadc5_sync.h:96
no_os_spi.h
Header file of SPI Interface.
I5G_SYSREF_RELEASE
#define I5G_SYSREF_RELEASE
Definition: axi_fmcadc5_sync.h:54
i5g_setup
int32_t i5g_setup(struct s_i5g **descriptor, struct s_i5g_init init_param)
Definition: axi_fmcadc5_sync.c:376
ad9625.h
Header file of AD9625 Driver.
I5G_AD9625_SS_MASK
#define I5G_AD9625_SS_MASK
Definition: axi_fmcadc5_sync.h:72
adxcvr
ADI JESD204B/C AXI_ADXCVR Highspeed Transceiver Device structure.
Definition: altera_adxcvr.h:95
axi_adc_init
AXI ADC Initialization Parameters structure.
Definition: axi_adc_core.h:142
iio_app.h
Header file of iio_app.
i5g_remove
int32_t i5g_remove(struct s_i5g *desc)
Definition: axi_fmcadc5_sync.c:415
I5G_SYSREF_SET
#define I5G_SYSREF_SET
Definition: axi_fmcadc5_sync.h:53
I5G_VERSION
#define I5G_VERSION
Definition: axi_fmcadc5_sync.h:43
axi_dmac_transfer_wait_completion
int32_t axi_dmac_transfer_wait_completion(struct axi_dmac *dmac, uint32_t timeout_ms)
Definition: axi_dmac.c:506
ad9625_init_param::test_samples
uint32_t test_samples[4]
Definition: ad9625.h:89
iio_data_buffer::buff
void * buff
Definition: iio_app.h:62
I5G_AD9625_ID_DATA
#define I5G_AD9625_ID_DATA
Definition: axi_fmcadc5_sync.h:67
axi_dma_transfer::transfer_done
volatile bool transfer_done
Definition: axi_dmac.h:108
no_os_delay.h
Header file of Delay functions.
axi_jesd204_rx_status_read
uint32_t axi_jesd204_rx_status_read(struct axi_jesd204_rx *jesd)
Read status of the JESD204 Receive Peripherial.
Definition: axi_jesd204_rx.c:208
xil_gpio_ops
const struct no_os_gpio_platform_ops xil_gpio_ops
Xilinx platform specific GPIO platform ops structure.
Definition: xilinx_gpio.c:455
I5G_SPI_SELECT_N_ADDR
#define I5G_SPI_SELECT_N_ADDR
Definition: axi_fmcadc5_sync.h:18
axi_adc
AXI ADC Device Descriptor.
Definition: axi_adc_core.h:125
xil_gpio_param
struct xil_gpio_init_param xil_gpio_param
Definition: ad7616_sdz.c:86
I5G_VCAL_DISABLE
#define I5G_VCAL_DISABLE
Definition: axi_fmcadc5_sync.h:59
I5G_VCAL_ENABLE_ADDR
#define I5G_VCAL_ENABLE_ADDR
Definition: axi_fmcadc5_sync.h:30
I5G_AD9625_SS_SET
#define I5G_AD9625_SS_SET
Definition: axi_fmcadc5_sync.h:73
I5G_CAL_MIN_1_ADDR
#define I5G_CAL_MIN_1_ADDR
Definition: axi_fmcadc5_sync.h:35
axi_fmcadc5_sync.h
no_os_gpio_init_param::number
int32_t number
Definition: no_os_gpio.h:89
axi_adc::name
const char * name
Definition: axi_adc_core.h:127
iio_axi_adc_init_param
iio configuration.
Definition: iio_axi_adc.h:81
s_i5g
Definition: axi_fmcadc5_sync.h:91
I5G_AD9625_SC_ENABLE
#define I5G_AD9625_SC_ENABLE(sel)
Definition: axi_fmcadc5_sync.h:81
I5G_CAL_MAX_0_ADDR
#define I5G_CAL_MAX_0_ADDR
Definition: axi_fmcadc5_sync.h:32
I5G_TIMER_ADDR
#define I5G_TIMER_ADDR
Definition: axi_fmcadc5_sync.h:15
axi_jesd204_rx_init
int32_t axi_jesd204_rx_init(struct axi_jesd204_rx **jesd204, const struct jesd204_rx_init *init)
Device initialization.
Definition: axi_jesd204_rx.c:559
no_os_axi_io.h
Header file of AXI IO.
I5G_DELAY_LOCKED
#define I5G_DELAY_LOCKED
Definition: axi_fmcadc5_sync.h:49
NO_OS_ARRAY_SIZE
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
ad9625_init_param
Definition: ad9625.h:84
jesd204_rx_init::name
const char * name
Definition: axi_jesd204_rx.h:98
ADXCVR_OUTCLK_PMA
#define ADXCVR_OUTCLK_PMA
Definition: axi_adxcvr.h:60
no_os_gpio_init_param::platform_ops
const struct no_os_gpio_platform_ops * platform_ops
Definition: no_os_gpio.h:93
iio_axi_adc_desc
iio_axi_adc_descriptor
Definition: iio_axi_adc.h:59
ad9625_init_param::lane_rate_kbps
uint32_t lane_rate_kbps
Definition: ad9625.h:88
I5G_TIMER_US
#define I5G_TIMER_US(d)
Definition: axi_fmcadc5_sync.h:86
no_os_spi_init_param::device_id
uint32_t device_id
Definition: no_os_spi.h:123
RX_DMA_BASEADDR
#define RX_DMA_BASEADDR
Definition: parameters.h:69
I5G_CAL_DISABLE
#define I5G_CAL_DISABLE
Definition: axi_fmcadc5_sync.h:61
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
iio_app_device::read_buff
struct iio_data_buffer * read_buff
Definition: iio_app.h:69
axi_dma_transfer
Definition: axi_dmac.h:106
axi_adxcvr.h
Driver for the ADI AXI-ADXCVR Module.
iio_axi_adc_init
int32_t iio_axi_adc_init(struct iio_axi_adc_desc **desc, struct iio_axi_adc_init_param *init)
Registers a iio_axi_adc_desc for reading/writing and parameterization of axi_adc device.
Definition: iio_axi_adc.c:484
no_os_error.h
Error codes definition.
s_i5g_init::ad9625_0_device
struct ad9625_dev * ad9625_0_device
Definition: axi_fmcadc5_sync.h:101
I5G_SYSREF_CONTROL_ADDR
#define I5G_SYSREF_CONTROL_ADDR
Definition: axi_fmcadc5_sync.h:27
I5G_SYSREF_REQUEST
#define I5G_SYSREF_REQUEST
Definition: axi_fmcadc5_sync.h:55
iio_app_device
Definition: iio_app.h:65
I5G_SYSREF_REQUEST_ADDR
#define I5G_SYSREF_REQUEST_ADDR
Definition: axi_fmcadc5_sync.h:28
I5G_VCAL_ENABLE
#define I5G_VCAL_ENABLE
Definition: axi_fmcadc5_sync.h:58
IRQ_DISABLED
@ IRQ_DISABLED
Definition: axi_dmac.h:83
I5G_VERSION_ADDR
#define I5G_VERSION_ADDR
Definition: axi_fmcadc5_sync.h:12
SPI_PL
@ SPI_PL
Definition: xilinx_spi.h:66
I5G_SPI_GRANT_ADDR
#define I5G_SPI_GRANT_ADDR
Definition: axi_fmcadc5_sync.h:17
I5G_SYNC_STATUS_ADDR
#define I5G_SYNC_STATUS_ADDR
Definition: axi_fmcadc5_sync.h:26
I5G_SPI_RECEIVE_ADDR
#define I5G_SPI_RECEIVE_ADDR
Definition: axi_fmcadc5_sync.h:20
s_i5g::ad9625_1_device
struct ad9625_dev * ad9625_1_device
Definition: axi_fmcadc5_sync.h:93
I5G_COR_DISABLE
#define I5G_COR_DISABLE
Definition: axi_fmcadc5_sync.h:63
axi_dmac.h
Driver for the Analog Devices AXI-DMAC core.
iio_data_buffer
Definition: iio_app.h:60
axi_dma_transfer::src_addr
uint32_t src_addr
Definition: axi_dmac.h:110
I5G_SYNC_SET
#define I5G_SYNC_SET
Definition: axi_fmcadc5_sync.h:50
I5G_AD9625_ST_ADDR
#define I5G_AD9625_ST_ADDR
Definition: axi_fmcadc5_sync.h:68
I5G_AD9625_SS_ADDR
#define I5G_AD9625_SS_ADDR
Definition: axi_fmcadc5_sync.h:71
I5G_SPI_TRANSMIT_ADDR
#define I5G_SPI_TRANSMIT_ADDR
Definition: axi_fmcadc5_sync.h:19
I5G_AD9625_IO_ADDR
#define I5G_AD9625_IO_ADDR
Definition: axi_fmcadc5_sync.h:74
s_i5g::sysref_delay
int32_t sysref_delay
Definition: axi_fmcadc5_sync.h:97
iio_axi_adc.h
Header file of iio_axi_adc.
adxcvr_init
Definition: altera_adxcvr.h:108
axi_dma_transfer::dest_addr
uint32_t dest_addr
Definition: axi_dmac.h:111
no_os_gpio_remove
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:95
adxcvr_init::name
const char * name
Definition: altera_adxcvr.h:109
xilinx_gpio.h
no_os_axi_io_read
int32_t no_os_axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
AXI IO Altera specific read function.
Definition: altera_axi_io.c:59
xil_spi_init_param::type
enum xil_spi_type type
Definition: xilinx_spi.h:80
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
ad9625_spi_write
int32_t ad9625_spi_write(struct ad9625_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9625_spi_write
Definition: ad9625.c:72
axi_dma_transfer::cyclic
enum cyclic_transfer cyclic
Definition: axi_dmac.h:109
GPIO_JESD204_SYSREF
#define GPIO_JESD204_SYSREF
Definition: parameters.h:84
I5G_COR_SCALE_1_ADDR
#define I5G_COR_SCALE_1_ADDR
Definition: axi_fmcadc5_sync.h:39
I5G_CAL_ENABLE
#define I5G_CAL_ENABLE
Definition: axi_fmcadc5_sync.h:60
s_i5g_init::ad9625_cs_0
int32_t ad9625_cs_0
Definition: axi_fmcadc5_sync.h:104
I5G_CAL_MAX_1_ADDR
#define I5G_CAL_MAX_1_ADDR
Definition: axi_fmcadc5_sync.h:34
main
int main(void)
Definition: fmcadc2.c:69
RX_XCVR_BASEADDR
#define RX_XCVR_BASEADDR
Definition: parameters.h:71
I5G_SPI_ACCESS_ENABLED
#define I5G_SPI_ACCESS_ENABLED
Definition: axi_fmcadc5_sync.h:46
xil_spi_init_param
Structure holding the initialization parameters for Xilinx platform specific SPI parameters when usin...
Definition: xilinx_spi.h:78
no_os_gpio_get
int32_t no_os_gpio_get(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Obtain the GPIO decriptor.
Definition: no_os_gpio.c:55
no_os_spi_init_param::max_speed_hz
uint32_t max_speed_hz
Definition: no_os_spi.h:125
I5G_SPI_BUSY
#define I5G_SPI_BUSY
Definition: axi_fmcadc5_sync.h:48
SPI_DEVICE_ID
#define SPI_DEVICE_ID
Definition: parameters.h:76
I5G_SYNC_CONTROL_ADDR
#define I5G_SYNC_CONTROL_ADDR
Definition: axi_fmcadc5_sync.h:25
NO
@ NO
Definition: axi_dmac.h:102
ADXCVR_SYS_CLK_CPLL
#define ADXCVR_SYS_CLK_CPLL
Definition: axi_adxcvr.h:54
iio_axi_adc_init_param::rx_adc
struct axi_adc * rx_adc
Definition: iio_axi_adc.h:83
axi_adc_init
int32_t axi_adc_init(struct axi_adc **adc_core, const struct axi_adc_init *init)
AXI ADC Main Initialization.
Definition: axi_adc_core.c:596
axi_dmac_init
int32_t axi_dmac_init(struct axi_dmac **dmac_core, const struct axi_dmac_init *init)
Definition: axi_dmac.c:331
RX_CORE_BASEADDR
#define RX_CORE_BASEADDR
Definition: parameters.h:68
ad9625_test
int32_t ad9625_test(struct ad9625_dev *dev, uint32_t test_mode)
ad9625_test
Definition: ad9625.c:162
ad9625_init_param::spi_init
struct no_os_spi_init_param spi_init
Definition: ad9625.h:86
NULL
#define NULL
Definition: wrapper.h:64
xil_spi_ops
const struct no_os_spi_platform_ops xil_spi_ops
Spi engine platform specific SPI platform ops structure.
Definition: xilinx_spi.c:456
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
s_i5g_init::ad9625_1_device
struct ad9625_dev * ad9625_1_device
Definition: axi_fmcadc5_sync.h:102
iio_device
Structure holding channels and attributes of a device.
Definition: iio_types.h:254
i5g_setup
int32_t i5g_setup(struct s_i5g **descriptor, struct s_i5g_init init_param)
Definition: axi_fmcadc5_sync.c:376
I5G_COR_ENABLE_ADDR
#define I5G_COR_ENABLE_ADDR
Definition: axi_fmcadc5_sync.h:36
I5G_SYNC_OOS
#define I5G_SYNC_OOS
Definition: axi_fmcadc5_sync.h:52
axi_jesd204_rx
Definition: axi_jesd204_rx.h:69
ad9625_dev
Definition: ad9625.h:92
I5G_COR_OFFSET_0_ADDR
#define I5G_COR_OFFSET_0_ADDR
Definition: axi_fmcadc5_sync.h:38
GPIO_DEVICE_ID
#define GPIO_DEVICE_ID
Definition: parameters.h:77
ad9625_setup
int32_t ad9625_setup(struct ad9625_dev **device, struct ad9625_init_param init_param)
ad9625_setup
Definition: ad9625.c:93
I5G_AD9625_SC_RECEIVED
#define I5G_AD9625_SC_RECEIVED(sel)
Definition: axi_fmcadc5_sync.h:82
axi_jesd204_rx.h
Driver for the Analog Devices AXI-JESD204-RX peripheral.
s_i5g::regs
int32_t regs
Definition: axi_fmcadc5_sync.h:94
RX_JESD_BASEADDR
#define RX_JESD_BASEADDR
Definition: parameters.h:70
xil_gpio_init_param
Structure holding the initialization parameters for Xilinx platform specific GPIO parameters.
Definition: xilinx_gpio.h:70
I5G_DELAY_LOCKED_ADDR
#define I5G_DELAY_LOCKED_ADDR
Definition: axi_fmcadc5_sync.h:24
no_os_axi_io_write
int32_t no_os_axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
AXI IO Altera specific write function.
Definition: altera_axi_io.c:73
no_os_gpio_init_param::extra
void * extra
Definition: no_os_gpio.h:95
no_os_gpio.h
Header file of GPIO Interface.
I5G_SPI_ACCESS_DISABLED
#define I5G_SPI_ACCESS_DISABLED
Definition: axi_fmcadc5_sync.h:47
s_i5g::ad9625_cs_0
int32_t ad9625_cs_0
Definition: axi_fmcadc5_sync.h:95
iio_app_run
int32_t iio_app_run(struct iio_app_device *devices, uint32_t len)
Register devices and start an iio application.
jesd204_rx_init
JESD204B/C Receive Peripheral Initialization Structure.
Definition: axi_jesd204_rx.h:96
I5G_COR_OFFSET_1_ADDR
#define I5G_COR_OFFSET_1_ADDR
Definition: axi_fmcadc5_sync.h:40
i5g_remove
int32_t i5g_remove(struct s_i5g *desc)
Definition: axi_fmcadc5_sync.c:415
GPIO_PL
@ GPIO_PL
Definition: xilinx_gpio.h:60
I5G_SPI_REQUEST_ACCESS
#define I5G_SPI_REQUEST_ACCESS
Definition: axi_fmcadc5_sync.h:44
axi_adc_pn_mon
int32_t axi_adc_pn_mon(struct axi_adc *adc, enum axi_adc_pn_sel sel, uint32_t delay_ms)
Monitor the AXI ADC PN Sequence.
Definition: axi_adc_core.c:112
axi_dmac_transfer_start
int32_t axi_dmac_transfer_start(struct axi_dmac *dmac, struct axi_dma_transfer *dma_transfer)
Definition: axi_dmac.c:378
axi_jesd204_rx::name
const char * name
Definition: axi_jesd204_rx.h:71
I5G_SYSREF_BUSY
#define I5G_SYSREF_BUSY
Definition: axi_fmcadc5_sync.h:56
I5G_DELAY_VERIFY_ADDR
#define I5G_DELAY_VERIFY_ADDR
Definition: axi_fmcadc5_sync.h:23
I5G_AD9625_SC_CLEAR
#define I5G_AD9625_SC_CLEAR(sel)
Definition: axi_fmcadc5_sync.h:83
no_os_spi_init_param::extra
void * extra
Definition: no_os_spi.h:134
I5G_DELAY_ADDR
#define I5G_DELAY_ADDR
Definition: axi_fmcadc5_sync.h:22
s_i5g_init
Definition: axi_fmcadc5_sync.h:100
NO_OS_SPI_MODE_0
@ NO_OS_SPI_MODE_0
Definition: no_os_spi.h:66
I5G_SYNC_RELEASE
#define I5G_SYNC_RELEASE
Definition: axi_fmcadc5_sync.h:51
xilinx_spi.h
iio_axi_adc_get_dev_descriptor
void iio_axi_adc_get_dev_descriptor(struct iio_axi_adc_desc *desc, struct iio_device **dev_descriptor)
Get device descriptor.
Definition: iio_axi_adc.c:471
no_os_gpio_direction_output
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:124
AD9625_TEST_PNLONG
#define AD9625_TEST_PNLONG
Definition: ad9625.h:75
axi_dma_transfer::size
uint32_t size
Definition: axi_dmac.h:107
xil_gpio_init_param::type
enum xil_gpio_type type
Definition: xilinx_gpio.h:72
ad9625_remove
int32_t ad9625_remove(struct ad9625_dev *dev)
ad9625_remove
Definition: ad9625.c:148
s_i5g_init::ad9625_cs_1
int32_t ad9625_cs_1
Definition: axi_fmcadc5_sync.h:105
axi_adc_init::name
const char * name
Definition: axi_adc_core.h:144
adxcvr_clk_enable
int32_t adxcvr_clk_enable(struct adxcvr *xcvr)
AXI ADXCVR Clock Enable.
Definition: axi_adxcvr.c:404
axi_jesd204_rx_lane_clk_enable
int32_t axi_jesd204_rx_lane_clk_enable(struct axi_jesd204_rx *jesd)
JESD204 RX Lane Clock Enable.
Definition: axi_jesd204_rx.c:185
I5G_AD9625_SG_ADDR
#define I5G_AD9625_SG_ADDR
Definition: axi_fmcadc5_sync.h:70
axi_dmac
Definition: axi_dmac.h:114
s_i5g_init::regs
int32_t regs
Definition: axi_fmcadc5_sync.h:103
I5G_AD9625_IO_DATA
#define I5G_AD9625_IO_DATA
Definition: axi_fmcadc5_sync.h:75
adxcvr_init
int32_t adxcvr_init(struct adxcvr **ad_xcvr, const struct adxcvr_init *init)
adxcvr_init
Definition: altera_adxcvr.c:443
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:121
AXI_ADC_PN23
@ AXI_ADC_PN23
Definition: axi_adc_core.h:156