Go to the documentation of this file.
12 #define I5G_VERSION_ADDR (0x0000 << 2)
13 #define I5G_IDENTIFIER_ADDR (0x0001 << 2)
14 #define I5G_SCRATCH_ADDR (0x0002 << 2)
15 #define I5G_TIMER_ADDR (0x0003 << 2)
16 #define I5G_SPI_REQUEST_ADDR (0x0010 << 2)
17 #define I5G_SPI_GRANT_ADDR (0x0011 << 2)
18 #define I5G_SPI_SELECT_N_ADDR (0x0012 << 2)
19 #define I5G_SPI_TRANSMIT_ADDR (0x0013 << 2)
20 #define I5G_SPI_RECEIVE_ADDR (0x0014 << 2)
21 #define I5G_SPI_BUSY_ADDR (0x0015 << 2)
22 #define I5G_DELAY_ADDR (0x0020 << 2)
23 #define I5G_DELAY_VERIFY_ADDR (0x0021 << 2)
24 #define I5G_DELAY_LOCKED_ADDR (0x0022 << 2)
25 #define I5G_SYNC_CONTROL_ADDR (0x0030 << 2)
26 #define I5G_SYNC_STATUS_ADDR (0x0031 << 2)
27 #define I5G_SYSREF_CONTROL_ADDR (0x0040 << 2)
28 #define I5G_SYSREF_REQUEST_ADDR (0x0041 << 2)
29 #define I5G_VCAL_CNT_ADDR (0x0050 << 2)
30 #define I5G_VCAL_ENABLE_ADDR (0x0051 << 2)
31 #define I5G_CAL_ENABLE_ADDR (0x0060 << 2)
32 #define I5G_CAL_MAX_0_ADDR (0x0064 << 2)
33 #define I5G_CAL_MIN_0_ADDR (0x0065 << 2)
34 #define I5G_CAL_MAX_1_ADDR (0x0066 << 2)
35 #define I5G_CAL_MIN_1_ADDR (0x0067 << 2)
36 #define I5G_COR_ENABLE_ADDR (0x0061 << 2)
37 #define I5G_COR_SCALE_0_ADDR (0x0068 << 2)
38 #define I5G_COR_OFFSET_0_ADDR (0x0069 << 2)
39 #define I5G_COR_SCALE_1_ADDR (0x006a << 2)
40 #define I5G_COR_OFFSET_1_ADDR (0x006b << 2)
43 #define I5G_VERSION 0x040063
44 #define I5G_SPI_REQUEST_ACCESS 0x000001
45 #define I5G_SPI_REQUEST_RELEASE 0x000000
46 #define I5G_SPI_ACCESS_ENABLED 0x000001
47 #define I5G_SPI_ACCESS_DISABLED 0x000000
48 #define I5G_SPI_BUSY 0x000001
49 #define I5G_DELAY_LOCKED 0x000001
50 #define I5G_SYNC_SET 0x000007
51 #define I5G_SYNC_RELEASE 0x000004
52 #define I5G_SYNC_OOS 0x000000
53 #define I5G_SYSREF_SET 0x000021
54 #define I5G_SYSREF_RELEASE 0x000020
55 #define I5G_SYSREF_REQUEST 0x000001
56 #define I5G_SYSREF_BUSY 0x000001
57 #define I5G_VCAL_CNT_10M 0x000004
58 #define I5G_VCAL_ENABLE 0x000001
59 #define I5G_VCAL_DISABLE 0x000000
60 #define I5G_CAL_ENABLE 0x000001
61 #define I5G_CAL_DISABLE 0x000000
62 #define I5G_COR_ENABLE 0x000001
63 #define I5G_COR_DISABLE 0x000000
66 #define I5G_AD9625_ID_ADDR 0x000001
67 #define I5G_AD9625_ID_DATA 0x000041
68 #define I5G_AD9625_ST_ADDR 0x000072
69 #define I5G_AD9625_ST_DATA 0x00008b
70 #define I5G_AD9625_SG_ADDR 0x00013c
71 #define I5G_AD9625_SS_ADDR 0x000100
72 #define I5G_AD9625_SS_MASK 0x000004
73 #define I5G_AD9625_SS_SET 0x000004
74 #define I5G_AD9625_IO_ADDR 0x0000ff
75 #define I5G_AD9625_IO_DATA 0x000001
76 #define I5G_AD9625_SC_ADDR 0x00003a
81 #define I5G_AD9625_SC_ENABLE(sel) ((sel == 1) ? 0x00000e : 0x000006)
82 #define I5G_AD9625_SC_RECEIVED(sel) ((sel == 1) ? 0x00000c : 0x000004)
83 #define I5G_AD9625_SC_CLEAR(sel) ((sel == 1) ? 0x00004e : 0x000046)
86 #define I5G_TIMER_US(d) ((d*100)-1)
Driver for the Analog Devices AXI-ADC-CORE module.
#define I5G_SPI_REQUEST_RELEASE
Definition: axi_fmcadc5_sync.h:45
#define IIO_APP_DEVICE(_name, _dev, _dev_descriptor, _read_buff, _write_buff)
Definition: iio_app.h:46
#define I5G_SPI_REQUEST_ADDR
Definition: axi_fmcadc5_sync.h:16
int32_t sysref_delay
Definition: axi_fmcadc5_sync.h:106
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
#define I5G_AD9625_SC_ADDR
Definition: axi_fmcadc5_sync.h:76
#define I5G_CAL_MIN_0_ADDR
Definition: axi_fmcadc5_sync.h:33
int32_t ad9625_spi_read(struct ad9625_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9625_spi_read
Definition: ad9625.c:50
const char * name
Definition: altera_adxcvr.h:96
#define I5G_SPI_BUSY_ADDR
Definition: axi_fmcadc5_sync.h:21
#define I5G_CAL_ENABLE_ADDR
Definition: axi_fmcadc5_sync.h:31
#define I5G_AD9625_ID_ADDR
Definition: axi_fmcadc5_sync.h:66
#define ADC_MAX_SAMPLES
Definition: parameters.h:46
#define I5G_AD9625_ST_DATA
Definition: axi_fmcadc5_sync.h:69
uint32_t size
Definition: iio_app.h:61
#define AD9625_TEST_OFF
Definition: ad9625.h:70
Definition: axi_dmac.h:129
const char * name
Definition: axi_dmac.h:130
struct ad9625_dev * ad9625_0_device
Definition: axi_fmcadc5_sync.h:92
Platform dependent parameters.
#define I5G_COR_SCALE_0_ADDR
Definition: axi_fmcadc5_sync.h:37
#define I5G_COR_ENABLE
Definition: axi_fmcadc5_sync.h:62
#define AD9625_REG_CHIP_ID
Definition: ad9625.h:53
int32_t ad9625_cs_1
Definition: axi_fmcadc5_sync.h:96
Header file of SPI Interface.
#define I5G_SYSREF_RELEASE
Definition: axi_fmcadc5_sync.h:54
int32_t i5g_setup(struct s_i5g **descriptor, struct s_i5g_init init_param)
Definition: axi_fmcadc5_sync.c:376
Header file of AD9625 Driver.
#define I5G_AD9625_SS_MASK
Definition: axi_fmcadc5_sync.h:72
ADI JESD204B/C AXI_ADXCVR Highspeed Transceiver Device structure.
Definition: altera_adxcvr.h:95
AXI ADC Initialization Parameters structure.
Definition: axi_adc_core.h:142
int32_t i5g_remove(struct s_i5g *desc)
Definition: axi_fmcadc5_sync.c:415
#define I5G_SYSREF_SET
Definition: axi_fmcadc5_sync.h:53
#define I5G_VERSION
Definition: axi_fmcadc5_sync.h:43
int32_t axi_dmac_transfer_wait_completion(struct axi_dmac *dmac, uint32_t timeout_ms)
Definition: axi_dmac.c:506
uint32_t test_samples[4]
Definition: ad9625.h:89
void * buff
Definition: iio_app.h:62
#define I5G_AD9625_ID_DATA
Definition: axi_fmcadc5_sync.h:67
volatile bool transfer_done
Definition: axi_dmac.h:108
Header file of Delay functions.
uint32_t axi_jesd204_rx_status_read(struct axi_jesd204_rx *jesd)
Read status of the JESD204 Receive Peripherial.
Definition: axi_jesd204_rx.c:208
#define I5G_SPI_SELECT_N_ADDR
Definition: axi_fmcadc5_sync.h:18
AXI ADC Device Descriptor.
Definition: axi_adc_core.h:125
struct xil_gpio_init_param xil_gpio_param
Definition: ad7616_sdz.c:86
#define I5G_VCAL_DISABLE
Definition: axi_fmcadc5_sync.h:59
#define I5G_VCAL_ENABLE_ADDR
Definition: axi_fmcadc5_sync.h:30
#define I5G_AD9625_SS_SET
Definition: axi_fmcadc5_sync.h:73
#define I5G_CAL_MIN_1_ADDR
Definition: axi_fmcadc5_sync.h:35
int32_t number
Definition: no_os_gpio.h:89
const char * name
Definition: axi_adc_core.h:127
iio configuration.
Definition: iio_axi_adc.h:81
Definition: axi_fmcadc5_sync.h:91
#define I5G_AD9625_SC_ENABLE(sel)
Definition: axi_fmcadc5_sync.h:81
#define I5G_CAL_MAX_0_ADDR
Definition: axi_fmcadc5_sync.h:32
#define I5G_TIMER_ADDR
Definition: axi_fmcadc5_sync.h:15
int32_t axi_jesd204_rx_init(struct axi_jesd204_rx **jesd204, const struct jesd204_rx_init *init)
Device initialization.
Definition: axi_jesd204_rx.c:559
#define I5G_DELAY_LOCKED
Definition: axi_fmcadc5_sync.h:49
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
const char * name
Definition: axi_jesd204_rx.h:98
const struct no_os_gpio_platform_ops * platform_ops
Definition: no_os_gpio.h:93
iio_axi_adc_descriptor
Definition: iio_axi_adc.h:59
uint32_t lane_rate_kbps
Definition: ad9625.h:88
#define I5G_TIMER_US(d)
Definition: axi_fmcadc5_sync.h:86
uint32_t device_id
Definition: no_os_spi.h:114
no_os_spi_init_param spi_init
Definition: ad9625.h:86
#define RX_DMA_BASEADDR
Definition: parameters.h:69
#define I5G_CAL_DISABLE
Definition: axi_fmcadc5_sync.h:61
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
struct iio_data_buffer * read_buff
Definition: iio_app.h:69
Definition: axi_dmac.h:106
Driver for the ADI AXI-ADXCVR Module.
int32_t iio_axi_adc_init(struct iio_axi_adc_desc **desc, struct iio_axi_adc_init_param *init)
Registers a iio_axi_adc_desc for reading/writing and parameterization of axi_adc device.
Definition: iio_axi_adc.c:484
struct ad9625_dev * ad9625_0_device
Definition: axi_fmcadc5_sync.h:101
#define I5G_SYSREF_CONTROL_ADDR
Definition: axi_fmcadc5_sync.h:27
#define I5G_SYSREF_REQUEST
Definition: axi_fmcadc5_sync.h:55
#define I5G_SYSREF_REQUEST_ADDR
Definition: axi_fmcadc5_sync.h:28
#define I5G_VCAL_ENABLE
Definition: axi_fmcadc5_sync.h:58
@ IRQ_DISABLED
Definition: axi_dmac.h:83
#define I5G_VERSION_ADDR
Definition: axi_fmcadc5_sync.h:12
#define I5G_SPI_GRANT_ADDR
Definition: axi_fmcadc5_sync.h:17
#define I5G_SYNC_STATUS_ADDR
Definition: axi_fmcadc5_sync.h:26
#define I5G_SPI_RECEIVE_ADDR
Definition: axi_fmcadc5_sync.h:20
struct ad9625_dev * ad9625_1_device
Definition: axi_fmcadc5_sync.h:93
#define I5G_COR_DISABLE
Definition: axi_fmcadc5_sync.h:63
Driver for the Analog Devices AXI-DMAC core.
uint32_t src_addr
Definition: axi_dmac.h:110
#define I5G_SYNC_SET
Definition: axi_fmcadc5_sync.h:50
#define I5G_AD9625_ST_ADDR
Definition: axi_fmcadc5_sync.h:68
#define I5G_AD9625_SS_ADDR
Definition: axi_fmcadc5_sync.h:71
#define I5G_SPI_TRANSMIT_ADDR
Definition: axi_fmcadc5_sync.h:19
#define I5G_AD9625_IO_ADDR
Definition: axi_fmcadc5_sync.h:74
int32_t sysref_delay
Definition: axi_fmcadc5_sync.h:97
Header file of iio_axi_adc.
Definition: altera_adxcvr.h:108
uint32_t dest_addr
Definition: axi_dmac.h:111
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:95
const char * name
Definition: altera_adxcvr.h:109
int32_t no_os_axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
AXI IO Altera specific read function.
Definition: axi_io.c:59
enum xil_spi_type type
Definition: spi_extra.h:80
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
int32_t ad9625_spi_write(struct ad9625_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9625_spi_write
Definition: ad9625.c:72
enum cyclic_transfer cyclic
Definition: axi_dmac.h:109
#define GPIO_JESD204_SYSREF
Definition: parameters.h:84
#define I5G_COR_SCALE_1_ADDR
Definition: axi_fmcadc5_sync.h:39
#define I5G_CAL_ENABLE
Definition: axi_fmcadc5_sync.h:60
int32_t ad9625_cs_0
Definition: axi_fmcadc5_sync.h:104
#define I5G_CAL_MAX_1_ADDR
Definition: axi_fmcadc5_sync.h:34
int main(void)
Definition: fmcadc2.c:69
#define RX_XCVR_BASEADDR
Definition: parameters.h:71
#define I5G_SPI_ACCESS_ENABLED
Definition: axi_fmcadc5_sync.h:46
Structure holding the initialization parameters for Xilinx platform specific SPI parameters when usin...
Definition: spi_extra.h:78
int32_t no_os_gpio_get(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Obtain the GPIO decriptor.
Definition: no_os_gpio.c:55
uint32_t max_speed_hz
Definition: no_os_spi.h:116
#define I5G_SPI_BUSY
Definition: axi_fmcadc5_sync.h:48
#define SPI_DEVICE_ID
Definition: parameters.h:76
#define I5G_SYNC_CONTROL_ADDR
Definition: axi_fmcadc5_sync.h:25
@ NO
Definition: axi_dmac.h:102
struct axi_adc * rx_adc
Definition: iio_axi_adc.h:83
int32_t axi_adc_init(struct axi_adc **adc_core, const struct axi_adc_init *init)
AXI ADC Main Initialization.
Definition: axi_adc_core.c:596
int32_t axi_dmac_init(struct axi_dmac **dmac_core, const struct axi_dmac_init *init)
Definition: axi_dmac.c:331
#define RX_CORE_BASEADDR
Definition: parameters.h:68
int32_t ad9625_test(struct ad9625_dev *dev, uint32_t test_mode)
ad9625_test
Definition: ad9625.c:162
#define NULL
Definition: wrapper.h:64
const struct no_os_spi_platform_ops xil_spi_ops
Spi engine platform specific SPI platform ops structure.
Definition: xilinx_spi.c:456
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
struct ad9625_dev * ad9625_1_device
Definition: axi_fmcadc5_sync.h:102
Structure holding channels and attributes of a device.
Definition: iio_types.h:242
int32_t i5g_setup(struct s_i5g **descriptor, struct s_i5g_init init_param)
Definition: axi_fmcadc5_sync.c:376
#define I5G_COR_ENABLE_ADDR
Definition: axi_fmcadc5_sync.h:36
#define I5G_SYNC_OOS
Definition: axi_fmcadc5_sync.h:52
Definition: axi_jesd204_rx.h:69
#define I5G_COR_OFFSET_0_ADDR
Definition: axi_fmcadc5_sync.h:38
#define GPIO_DEVICE_ID
Definition: parameters.h:77
int32_t ad9625_setup(struct ad9625_dev **device, struct ad9625_init_param init_param)
ad9625_setup
Definition: ad9625.c:93
#define I5G_AD9625_SC_RECEIVED(sel)
Definition: axi_fmcadc5_sync.h:82
Driver for the Analog Devices AXI-JESD204-RX peripheral.
int32_t regs
Definition: axi_fmcadc5_sync.h:94
#define RX_JESD_BASEADDR
Definition: parameters.h:70
Structure holding the initialization parameters for Xilinx platform specific GPIO parameters.
Definition: gpio_extra.h:70
#define I5G_DELAY_LOCKED_ADDR
Definition: axi_fmcadc5_sync.h:24
int32_t no_os_axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
AXI IO Altera specific write function.
Definition: axi_io.c:73
void * extra
Definition: no_os_gpio.h:95
Header file of GPIO Interface.
#define I5G_SPI_ACCESS_DISABLED
Definition: axi_fmcadc5_sync.h:47
int32_t ad9625_cs_0
Definition: axi_fmcadc5_sync.h:95
int32_t iio_app_run(struct iio_app_device *devices, uint32_t len)
Register devices and start an iio application.
JESD204B/C Receive Peripheral Initialization Structure.
Definition: axi_jesd204_rx.h:96
#define I5G_COR_OFFSET_1_ADDR
Definition: axi_fmcadc5_sync.h:40
int32_t i5g_remove(struct s_i5g *desc)
Definition: axi_fmcadc5_sync.c:415
#define I5G_SPI_REQUEST_ACCESS
Definition: axi_fmcadc5_sync.h:44
int32_t axi_adc_pn_mon(struct axi_adc *adc, enum axi_adc_pn_sel sel, uint32_t delay_ms)
Monitor the AXI ADC PN Sequence.
Definition: axi_adc_core.c:112
int32_t axi_dmac_transfer_start(struct axi_dmac *dmac, struct axi_dma_transfer *dma_transfer)
Definition: axi_dmac.c:378
const char * name
Definition: axi_jesd204_rx.h:71
#define I5G_SYSREF_BUSY
Definition: axi_fmcadc5_sync.h:56
#define I5G_DELAY_VERIFY_ADDR
Definition: axi_fmcadc5_sync.h:23
#define I5G_AD9625_SC_CLEAR(sel)
Definition: axi_fmcadc5_sync.h:83
void * extra
Definition: no_os_spi.h:125
#define I5G_DELAY_ADDR
Definition: axi_fmcadc5_sync.h:22
Definition: axi_fmcadc5_sync.h:100
@ NO_OS_SPI_MODE_0
Definition: no_os_spi.h:66
#define I5G_SYNC_RELEASE
Definition: axi_fmcadc5_sync.h:51
void iio_axi_adc_get_dev_descriptor(struct iio_axi_adc_desc *desc, struct iio_device **dev_descriptor)
Get device descriptor.
Definition: iio_axi_adc.c:471
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:124
#define AD9625_TEST_PNLONG
Definition: ad9625.h:75
uint32_t size
Definition: axi_dmac.h:107
enum xil_gpio_type type
Definition: gpio_extra.h:72
int32_t ad9625_remove(struct ad9625_dev *dev)
ad9625_remove
Definition: ad9625.c:148
int32_t ad9625_cs_1
Definition: axi_fmcadc5_sync.h:105
const char * name
Definition: axi_adc_core.h:144
int32_t adxcvr_clk_enable(struct adxcvr *xcvr)
AXI ADXCVR Clock Enable.
Definition: axi_adxcvr.c:322
int32_t axi_jesd204_rx_lane_clk_enable(struct axi_jesd204_rx *jesd)
JESD204 RX Lane Clock Enable.
Definition: axi_jesd204_rx.c:185
#define I5G_AD9625_SG_ADDR
Definition: axi_fmcadc5_sync.h:70
Definition: axi_dmac.h:114
int32_t regs
Definition: axi_fmcadc5_sync.h:103
#define I5G_AD9625_IO_DATA
Definition: axi_fmcadc5_sync.h:75
int32_t adxcvr_init(struct adxcvr **ad_xcvr, const struct adxcvr_init *init)
adxcvr_init
Definition: altera_adxcvr.c:443
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
@ AXI_ADC_PN23
Definition: axi_adc_core.h:156