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39 #ifndef CLK_AXI_CLKGEN_H_
40 #define CLK_AXI_CLKGEN_H_
uint32_t parent_rate
Definition: clk_axi_clkgen.h:53
const char * name
Definition: clk_axi_clkgen.h:57
const char * name
Definition: clk_axi_clkgen.h:51
@ AXI_FPGA_TECH_UNKNOWN
Definition: clk_axi_clkgen.c:130
@ AXI_FPGA_SPEED_2L
Definition: clk_axi_clkgen.c:152
@ AXI_FPGA_SPEED_3
Definition: clk_axi_clkgen.c:154
#define AXI_CLKGEN_REG_STATUS
Definition: clk_axi_clkgen.c:79
#define AXI_CLKGEN_REG_DRP_STATUS
Definition: clk_axi_clkgen.c:86
@ AXI_FPGA_SPEED_1H
Definition: clk_axi_clkgen.c:148
Driver for the Analog Devices AXI CLKGEN.
@ AXI_FPGA_FAMILY_KINTEX
Definition: clk_axi_clkgen.c:139
Header file of Delay functions.
@ AXI_FPGA_SPEED_UNKNOWN
Definition: clk_axi_clkgen.c:145
#define no_os_max(x, y)
Definition: no_os_util.h:68
#define MMCM_REG_CLKOUT0_1
Definition: clk_axi_clkgen.c:89
Definition: clk_axi_clkgen.h:56
int32_t axi_clkgen_set_rate(struct axi_clkgen *clkgen, uint32_t rate)
axi_clkgen_set_rate
Definition: clk_axi_clkgen.c:418
axi_fgpa_technology
Definition: clk_axi_clkgen.c:129
#define MMCM_REG_LOCK2
Definition: clk_axi_clkgen.c:97
uint32_t base
Definition: clk_axi_clkgen.h:52
int32_t axi_clkgen_init(struct axi_clkgen **clk, const struct axi_clkgen_init *init)
axi_clkgen_init
Definition: clk_axi_clkgen.c:524
Definition: clk_axi_clkgen.h:50
@ AXI_FPGA_TECH_ULTRASCALE
Definition: clk_axi_clkgen.c:132
#define MMCM_REG_CLK_FB1
Definition: clk_axi_clkgen.c:93
@ AXI_FPGA_FAMILY_VIRTEX
Definition: clk_axi_clkgen.c:140
int32_t axi_clkgen_get_rate(struct axi_clkgen *clkgen, uint32_t *rate)
axi_clkgen_get_rate
Definition: clk_axi_clkgen.c:492
int32_t axi_clkgen_remove(struct axi_clkgen *clkgen)
axi_clkgen_remove
Definition: clk_axi_clkgen.c:545
@ AXI_FPGA_SPEED_2
Definition: clk_axi_clkgen.c:151
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
#define no_os_min(x, y)
Definition: no_os_util.h:63
#define AXI_REG_FPGA_INFO
Definition: clk_axi_clkgen.c:66
#define MMCM_REG_CLKOUT1_2
Definition: clk_axi_clkgen.c:92
@ AXI_FPGA_FAMILY_ARTIX
Definition: clk_axi_clkgen.c:138
@ AXI_FPGA_FAMILY_UNKNOWN
Definition: clk_axi_clkgen.c:137
@ AXI_FPGA_FAMILY_ZYNQ
Definition: clk_axi_clkgen.c:141
#define NO_OS_DIV_ROUND_UP(x, y)
Definition: no_os_util.h:56
@ AXI_FPGA_SPEED_1HV
Definition: clk_axi_clkgen.c:149
#define MMCM_REG_CLK_FB2
Definition: clk_axi_clkgen.c:94
void axi_clkgen_calc_params(struct axi_clkgen *axi_clkgen, uint32_t fin, uint32_t fout, uint32_t *best_d, uint32_t *best_m, uint32_t *best_dout)
axi_clkgen_calc_params
Definition: clk_axi_clkgen.c:318
#define MMCM_REG_CLKOUT1_1
Definition: clk_axi_clkgen.c:91
#define AXI_CLKGEN_REG_RESETN
Definition: clk_axi_clkgen.c:75
int32_t axi_clkgen_get_rate(struct axi_clkgen *clkgen, uint32_t *rate)
axi_clkgen_get_rate
Definition: clk_axi_clkgen.c:492
#define AXI_CLKGEN_RESETN
Definition: clk_axi_clkgen.c:77
uint32_t base
Definition: clk_axi_clkgen.h:58
@ AXI_FPGA_SPEED_1
Definition: clk_axi_clkgen.c:146
int32_t axi_clkgen_init(struct axi_clkgen **clk, const struct axi_clkgen_init *init)
axi_clkgen_init
Definition: clk_axi_clkgen.c:524
#define MMCM_REG_FILTER1
Definition: clk_axi_clkgen.c:99
uint32_t parent_rate
Definition: clk_axi_clkgen.h:59
#define AXI_CLKGEN_REG_DRP_CNTRL
Definition: clk_axi_clkgen.c:82
#define AXI_CLKGEN_DRP_CNTRL_READ
Definition: clk_axi_clkgen.c:84
#define AXI_REG_VERSION
Definition: clk_axi_clkgen.c:61
@ AXI_FPGA_SPEED_2LV
Definition: clk_axi_clkgen.c:153
#define MMCM_REG_CLKOUT0_2
Definition: clk_axi_clkgen.c:90
int32_t no_os_axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
AXI IO Altera specific read function.
Definition: axi_io.c:59
#define no_os_clamp(val, min_val, max_val)
Definition: no_os_util.h:73
int32_t axi_clkgen_read(struct axi_clkgen *clkgen, uint32_t reg_addr, uint32_t *reg_val)
axi_clkgen_read
Definition: clk_axi_clkgen.c:172
#define MMCM_REG_CLK_DIV
Definition: clk_axi_clkgen.c:95
#define AXI_REG_FPGA_VOLTAGE
Definition: clk_axi_clkgen.c:67
void axi_clkgen_mmcm_write(struct axi_clkgen *clkgen, uint32_t reg, uint32_t val, uint32_t mask)
axi_clkgen_mmcm_write
Definition: clk_axi_clkgen.c:217
#define MMCM_REG_LOCK3
Definition: clk_axi_clkgen.c:98
void axi_clkgen_calc_clk_params(uint32_t divider, uint32_t *low, uint32_t *high, uint32_t *edge, uint32_t *nocount)
axi_clkgen_calc_clk_params
Definition: clk_axi_clkgen.c:386
#define MMCM_REG_FILTER2
Definition: clk_axi_clkgen.c:100
@ AXI_FPGA_TECH_SERIES7
Definition: clk_axi_clkgen.c:131
#define AXI_CLKGEN_DRP_STATUS_BUSY
Definition: clk_axi_clkgen.c:87
#define AXI_PCORE_VER_MAJOR(version)
Definition: clk_axi_clkgen.c:57
int32_t axi_clkgen_set_rate(struct axi_clkgen *clkgen, uint32_t rate)
axi_clkgen_set_rate
Definition: clk_axi_clkgen.c:418
int32_t no_os_axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
AXI IO Altera specific write function.
Definition: axi_io.c:73
#define AXI_CLKGEN_MMCM_RESETN
Definition: clk_axi_clkgen.c:76
#define AXI_INFO_FPGA_TECH(info)
Definition: clk_axi_clkgen.c:69
axi_fpga_speed_grade
Definition: clk_axi_clkgen.c:144
#define AXI_CLKGEN_STATUS
Definition: clk_axi_clkgen.c:80
#define AXI_CLKGEN_DRP_CNTRL_SEL
Definition: clk_axi_clkgen.c:83
@ AXI_FPGA_TECH_ULTRASCALE_PLUS
Definition: clk_axi_clkgen.c:133
int32_t axi_clkgen_remove(struct axi_clkgen *clkgen)
axi_clkgen_remove
Definition: clk_axi_clkgen.c:545
Implementation of utility functions.
#define MMCM_REG_LOCK1
Definition: clk_axi_clkgen.c:96
int32_t axi_clkgen_write(struct axi_clkgen *clkgen, uint32_t reg_addr, uint32_t reg_val)
axi_clkgen_write
Definition: clk_axi_clkgen.c:160
axi_fpga_family
Definition: clk_axi_clkgen.c:136
@ AXI_FPGA_SPEED_1L
Definition: clk_axi_clkgen.c:147
#define AXI_INFO_FPGA_FAMILY(info)
Definition: clk_axi_clkgen.c:70
#define NO_OS_DIV_ROUND_CLOSEST(x, y)
Definition: no_os_util.h:58
@ AXI_FPGA_SPEED_1LV
Definition: clk_axi_clkgen.c:150
#define AXI_INFO_FPGA_VOLTAGE(val)
Definition: clk_axi_clkgen.c:73
#define AXI_INFO_FPGA_SPEED_GRADE(info)
Definition: clk_axi_clkgen.c:71
