no-OS
clk_axi_clkgen.h
Go to the documentation of this file.
1 /***************************************************************************/
39 #ifndef CLK_AXI_CLKGEN_H_
40 #define CLK_AXI_CLKGEN_H_
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include <stdint.h>
46 
47 /******************************************************************************/
48 /*************************** Types Declarations *******************************/
49 /******************************************************************************/
50 struct axi_clkgen {
51  const char *name;
52  uint32_t base;
53  uint32_t parent_rate;
54 };
55 
57  const char *name;
58  uint32_t base;
59  uint32_t parent_rate;
60 };
61 
62 /******************************************************************************/
63 /************************ Functions Declarations ******************************/
64 /******************************************************************************/
65 int32_t axi_clkgen_set_rate(struct axi_clkgen *clkgen, uint32_t rate);
66 int32_t axi_clkgen_get_rate(struct axi_clkgen *clkgen, uint32_t *rate);
67 int32_t axi_clkgen_init(struct axi_clkgen **clk,
68  const struct axi_clkgen_init *init);
69 int32_t axi_clkgen_remove(struct axi_clkgen *clkgen);
70 
71 #endif
axi_clkgen::parent_rate
uint32_t parent_rate
Definition: clk_axi_clkgen.h:53
axi_clkgen_init::name
const char * name
Definition: clk_axi_clkgen.h:57
axi_clkgen::name
const char * name
Definition: clk_axi_clkgen.h:51
timeout
uint32_t timeout
Definition: ad413x.c:54
AXI_FPGA_TECH_UNKNOWN
@ AXI_FPGA_TECH_UNKNOWN
Definition: clk_axi_clkgen.c:130
AXI_FPGA_SPEED_2L
@ AXI_FPGA_SPEED_2L
Definition: clk_axi_clkgen.c:152
AXI_FPGA_SPEED_3
@ AXI_FPGA_SPEED_3
Definition: clk_axi_clkgen.c:154
AXI_CLKGEN_REG_STATUS
#define AXI_CLKGEN_REG_STATUS
Definition: clk_axi_clkgen.c:79
AXI_CLKGEN_REG_DRP_STATUS
#define AXI_CLKGEN_REG_DRP_STATUS
Definition: clk_axi_clkgen.c:86
AXI_FPGA_SPEED_1H
@ AXI_FPGA_SPEED_1H
Definition: clk_axi_clkgen.c:148
clk_axi_clkgen.h
Driver for the Analog Devices AXI CLKGEN.
AXI_FPGA_FAMILY_KINTEX
@ AXI_FPGA_FAMILY_KINTEX
Definition: clk_axi_clkgen.c:139
no_os_delay.h
Header file of Delay functions.
AXI_FPGA_SPEED_UNKNOWN
@ AXI_FPGA_SPEED_UNKNOWN
Definition: clk_axi_clkgen.c:145
no_os_max
#define no_os_max(x, y)
Definition: no_os_util.h:68
MMCM_REG_CLKOUT0_1
#define MMCM_REG_CLKOUT0_1
Definition: clk_axi_clkgen.c:89
axi_clkgen_init
Definition: clk_axi_clkgen.h:56
axi_clkgen_set_rate
int32_t axi_clkgen_set_rate(struct axi_clkgen *clkgen, uint32_t rate)
axi_clkgen_set_rate
Definition: clk_axi_clkgen.c:418
axi_fgpa_technology
axi_fgpa_technology
Enum for technology/generation of the FPGA device.
Definition: clk_axi_clkgen.c:129
MMCM_REG_LOCK2
#define MMCM_REG_LOCK2
Definition: clk_axi_clkgen.c:97
axi_clkgen::base
uint32_t base
Definition: clk_axi_clkgen.h:52
axi_clkgen_init
int32_t axi_clkgen_init(struct axi_clkgen **clk, const struct axi_clkgen_init *init)
axi_clkgen_init
Definition: clk_axi_clkgen.c:524
axi_clkgen
Definition: clk_axi_clkgen.h:50
AXI_FPGA_TECH_ULTRASCALE
@ AXI_FPGA_TECH_ULTRASCALE
Definition: clk_axi_clkgen.c:132
no_os_axi_io.h
Header file of AXI IO.
MMCM_REG_CLK_FB1
#define MMCM_REG_CLK_FB1
Definition: clk_axi_clkgen.c:93
AXI_FPGA_FAMILY_VIRTEX
@ AXI_FPGA_FAMILY_VIRTEX
Definition: clk_axi_clkgen.c:140
axi_clkgen_get_rate
int32_t axi_clkgen_get_rate(struct axi_clkgen *clkgen, uint32_t *rate)
axi_clkgen_get_rate
Definition: clk_axi_clkgen.c:492
axi_clkgen_remove
int32_t axi_clkgen_remove(struct axi_clkgen *clkgen)
axi_clkgen_remove
Definition: clk_axi_clkgen.c:545
AXI_FPGA_SPEED_2
@ AXI_FPGA_SPEED_2
Definition: clk_axi_clkgen.c:151
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
no_os_min
#define no_os_min(x, y)
Definition: no_os_util.h:63
AXI_REG_FPGA_INFO
#define AXI_REG_FPGA_INFO
Definition: clk_axi_clkgen.c:66
MMCM_REG_CLKOUT1_2
#define MMCM_REG_CLKOUT1_2
Definition: clk_axi_clkgen.c:92
AXI_FPGA_FAMILY_ARTIX
@ AXI_FPGA_FAMILY_ARTIX
Definition: clk_axi_clkgen.c:138
no_os_error.h
Error codes definition.
AXI_FPGA_FAMILY_UNKNOWN
@ AXI_FPGA_FAMILY_UNKNOWN
Definition: clk_axi_clkgen.c:137
AXI_FPGA_FAMILY_ZYNQ
@ AXI_FPGA_FAMILY_ZYNQ
Definition: clk_axi_clkgen.c:141
NO_OS_DIV_ROUND_UP
#define NO_OS_DIV_ROUND_UP(x, y)
Definition: no_os_util.h:56
AXI_FPGA_SPEED_1HV
@ AXI_FPGA_SPEED_1HV
Definition: clk_axi_clkgen.c:149
MMCM_REG_CLK_FB2
#define MMCM_REG_CLK_FB2
Definition: clk_axi_clkgen.c:94
axi_clkgen_calc_params
void axi_clkgen_calc_params(struct axi_clkgen *axi_clkgen, uint32_t fin, uint32_t fout, uint32_t *best_d, uint32_t *best_m, uint32_t *best_dout)
axi_clkgen_calc_params
Definition: clk_axi_clkgen.c:318
MMCM_REG_CLKOUT1_1
#define MMCM_REG_CLKOUT1_1
Definition: clk_axi_clkgen.c:91
AXI_CLKGEN_REG_RESETN
#define AXI_CLKGEN_REG_RESETN
Definition: clk_axi_clkgen.c:75
axi_clkgen_get_rate
int32_t axi_clkgen_get_rate(struct axi_clkgen *clkgen, uint32_t *rate)
axi_clkgen_get_rate
Definition: clk_axi_clkgen.c:492
AXI_CLKGEN_RESETN
#define AXI_CLKGEN_RESETN
Definition: clk_axi_clkgen.c:77
axi_clkgen_init::base
uint32_t base
Definition: clk_axi_clkgen.h:58
AXI_FPGA_SPEED_1
@ AXI_FPGA_SPEED_1
Definition: clk_axi_clkgen.c:146
axi_clkgen_init
int32_t axi_clkgen_init(struct axi_clkgen **clk, const struct axi_clkgen_init *init)
axi_clkgen_init
Definition: clk_axi_clkgen.c:524
MMCM_REG_FILTER1
#define MMCM_REG_FILTER1
Definition: clk_axi_clkgen.c:99
axi_clkgen_init::parent_rate
uint32_t parent_rate
Definition: clk_axi_clkgen.h:59
AXI_CLKGEN_REG_DRP_CNTRL
#define AXI_CLKGEN_REG_DRP_CNTRL
Definition: clk_axi_clkgen.c:82
AXI_CLKGEN_DRP_CNTRL_READ
#define AXI_CLKGEN_DRP_CNTRL_READ
Definition: clk_axi_clkgen.c:84
AXI_REG_VERSION
#define AXI_REG_VERSION
Definition: clk_axi_clkgen.c:61
AXI_FPGA_SPEED_2LV
@ AXI_FPGA_SPEED_2LV
Definition: clk_axi_clkgen.c:153
MMCM_REG_CLKOUT0_2
#define MMCM_REG_CLKOUT0_2
Definition: clk_axi_clkgen.c:90
no_os_axi_io_read
int32_t no_os_axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
AXI IO Altera specific read function.
Definition: axi_io.c:59
no_os_clamp
#define no_os_clamp(val, min_val, max_val)
Definition: no_os_util.h:73
axi_clkgen_read
int32_t axi_clkgen_read(struct axi_clkgen *clkgen, uint32_t reg_addr, uint32_t *reg_val)
axi_clkgen_read
Definition: clk_axi_clkgen.c:172
MMCM_REG_CLK_DIV
#define MMCM_REG_CLK_DIV
Definition: clk_axi_clkgen.c:95
AXI_REG_FPGA_VOLTAGE
#define AXI_REG_FPGA_VOLTAGE
Definition: clk_axi_clkgen.c:67
axi_clkgen_mmcm_write
void axi_clkgen_mmcm_write(struct axi_clkgen *clkgen, uint32_t reg, uint32_t val, uint32_t mask)
axi_clkgen_mmcm_write
Definition: clk_axi_clkgen.c:217
MMCM_REG_LOCK3
#define MMCM_REG_LOCK3
Definition: clk_axi_clkgen.c:98
axi_clkgen_calc_clk_params
void axi_clkgen_calc_clk_params(uint32_t divider, uint32_t *low, uint32_t *high, uint32_t *edge, uint32_t *nocount)
axi_clkgen_calc_clk_params
Definition: clk_axi_clkgen.c:386
MMCM_REG_FILTER2
#define MMCM_REG_FILTER2
Definition: clk_axi_clkgen.c:100
AXI_FPGA_TECH_SERIES7
@ AXI_FPGA_TECH_SERIES7
Definition: clk_axi_clkgen.c:131
AXI_CLKGEN_DRP_STATUS_BUSY
#define AXI_CLKGEN_DRP_STATUS_BUSY
Definition: clk_axi_clkgen.c:87
AXI_PCORE_VER_MAJOR
#define AXI_PCORE_VER_MAJOR(version)
Definition: clk_axi_clkgen.c:57
axi_clkgen_set_rate
int32_t axi_clkgen_set_rate(struct axi_clkgen *clkgen, uint32_t rate)
axi_clkgen_set_rate
Definition: clk_axi_clkgen.c:418
no_os_axi_io_write
int32_t no_os_axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
AXI IO Altera specific write function.
Definition: axi_io.c:73
AXI_CLKGEN_MMCM_RESETN
#define AXI_CLKGEN_MMCM_RESETN
Definition: clk_axi_clkgen.c:76
AXI_INFO_FPGA_TECH
#define AXI_INFO_FPGA_TECH(info)
Definition: clk_axi_clkgen.c:69
axi_fpga_speed_grade
axi_fpga_speed_grade
Enum for FPGA's speed-grade.
Definition: clk_axi_clkgen.c:144
AXI_CLKGEN_STATUS
#define AXI_CLKGEN_STATUS
Definition: clk_axi_clkgen.c:80
AXI_CLKGEN_DRP_CNTRL_SEL
#define AXI_CLKGEN_DRP_CNTRL_SEL
Definition: clk_axi_clkgen.c:83
AXI_FPGA_TECH_ULTRASCALE_PLUS
@ AXI_FPGA_TECH_ULTRASCALE_PLUS
Definition: clk_axi_clkgen.c:133
axi_clkgen_remove
int32_t axi_clkgen_remove(struct axi_clkgen *clkgen)
axi_clkgen_remove
Definition: clk_axi_clkgen.c:545
no_os_util.h
Header file of utility functions.
MMCM_REG_LOCK1
#define MMCM_REG_LOCK1
Definition: clk_axi_clkgen.c:96
axi_clkgen_write
int32_t axi_clkgen_write(struct axi_clkgen *clkgen, uint32_t reg_addr, uint32_t reg_val)
axi_clkgen_write
Definition: clk_axi_clkgen.c:160
axi_fpga_family
axi_fpga_family
Enum for family variant of the FPGA device.
Definition: clk_axi_clkgen.c:136
AXI_FPGA_SPEED_1L
@ AXI_FPGA_SPEED_1L
Definition: clk_axi_clkgen.c:147
AXI_INFO_FPGA_FAMILY
#define AXI_INFO_FPGA_FAMILY(info)
Definition: clk_axi_clkgen.c:70
NO_OS_DIV_ROUND_CLOSEST
#define NO_OS_DIV_ROUND_CLOSEST(x, y)
Definition: no_os_util.h:58
AXI_FPGA_SPEED_1LV
@ AXI_FPGA_SPEED_1LV
Definition: clk_axi_clkgen.c:150
AXI_INFO_FPGA_VOLTAGE
#define AXI_INFO_FPGA_VOLTAGE(val)
Definition: clk_axi_clkgen.c:73
AXI_INFO_FPGA_SPEED_GRADE
#define AXI_INFO_FPGA_SPEED_GRADE(info)
Definition: clk_axi_clkgen.c:71