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Navassa_CMOS_profile.h
Go to the documentation of this file.
1
const
char
*
json_profile
=
"{ \
2
\"clocks\": { \
3
\"deviceClock_kHz\": 38400, \
4
\"clkPllVcoFreq_daHz\": 884736000, \
5
\"clkPllHsDiv\": 0, \
6
\"clkPllMode\": 0, \
7
\"clk1105Div\": 2, \
8
\"armClkDiv\": 6, \
9
\"armPowerSavingClkDiv\": 1, \
10
\"refClockOutEnable\": true, \
11
\"auxPllPower\": 2, \
12
\"clkPllPower\": 2, \
13
\"padRefClkDrv\": 0, \
14
\"extLo1OutFreq_kHz\": 0, \
15
\"extLo2OutFreq_kHz\": 0, \
16
\"rfPll1LoMode\": 0, \
17
\"rfPll2LoMode\": 0, \
18
\"ext1LoType\": 0, \
19
\"ext2LoType\": 0, \
20
\"rx1RfInputSel\": 0, \
21
\"rx2RfInputSel\": 0, \
22
\"extLo1Divider\": 2, \
23
\"extLo2Divider\": 2, \
24
\"rfPllPhaseSyncMode\": 0, \
25
\"rx1LoSelect\": 2, \
26
\"rx2LoSelect\": 2, \
27
\"tx1LoSelect\": 1, \
28
\"tx2LoSelect\": 1, \
29
\"rx1LoDivMode\": 1, \
30
\"rx2LoDivMode\": 1, \
31
\"tx1LoDivMode\": 1, \
32
\"tx2LoDivMode\": 1, \
33
\"loGen1Select\": 1, \
34
\"loGen2Select\": 1 \
35
}, \
36
\"rx\": { \
37
\"rxInitChannelMask\": 195, \
38
\"rxChannelCfg\": [ { \
39
\"profile\": { \
40
\"primarySigBandwidth_Hz\": 1008000, \
41
\"rxOutputRate_Hz\": 1920000, \
42
\"rxInterfaceSampleRate_Hz\": 1920000, \
43
\"rxOffsetLo_kHz\": 0, \
44
\"rxNcoEnable\": false, \
45
\"outputSignaling\": 0, \
46
\"filterOrder\": 1, \
47
\"filterOrderLp\": 1, \
48
\"hpAdcCorner\": 20000000, \
49
\"lpAdcCorner\": 0, \
50
\"adcClk_kHz\": 2211840, \
51
\"rxCorner3dB_kHz\": 40000, \
52
\"rxCorner3dBLp_kHz\": 40000, \
53
\"tiaPower\": 2, \
54
\"tiaPowerLp\": 2, \
55
\"channelType\": 1, \
56
\"adcType\": 1, \
57
\"lpAdcCalMode\": 0, \
58
\"gainTableType\": 0, \
59
\"rxDpProfile\": { \
60
\"rxNbDecTop\": { \
61
\"scicBlk23En\": 0, \
62
\"scicBlk23DivFactor\": 1, \
63
\"scicBlk23LowRippleEn\": 0, \
64
\"decBy2Blk35En\": 0, \
65
\"decBy2Blk37En\": 0, \
66
\"decBy2Blk39En\": 0, \
67
\"decBy2Blk41En\": 0, \
68
\"decBy2Blk43En\": 0, \
69
\"decBy3Blk45En\": 0, \
70
\"decBy2Blk47En\": 0 \
71
}, \
72
\"rxWbDecTop\": { \
73
\"decBy2Blk25En\": 1, \
74
\"decBy2Blk27En\": 1, \
75
\"decBy2Blk29En\": 1, \
76
\"decBy2Blk31En\": 1, \
77
\"decBy2Blk33En\": 1, \
78
\"wbLpfBlk33p1En\": 0 \
79
}, \
80
\"rxDecTop\": { \
81
\"decBy3Blk15En\": 1, \
82
\"decBy2Hb3Blk17p1En\": 0, \
83
\"decBy2Hb4Blk17p2En\": 0, \
84
\"decBy2Hb5Blk19p1En\": 0, \
85
\"decBy2Hb6Blk19p2En\": 0 \
86
}, \
87
\"rxSincHBTop\": { \
88
\"sincGainMux\": 1, \
89
\"sincMux\": 4, \
90
\"hbMux\": 4, \
91
\"isGainCompEnabled\": 0, \
92
\"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
93
\"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
94
}, \
95
\"rxNbDem\": { \
96
\"dpInFifo\": { \
97
\"dpInFifoEn\": 0, \
98
\"dpInFifoMode\": 0, \
99
\"dpInFifoTestDataSel\": 0 \
100
}, \
101
\"rxNbNco\": { \
102
\"rxNbNcoEn\": 1, \
103
\"rxNbNcoConfig\": { \
104
\"freq\": 0, \
105
\"sampleFreq\": 1920000, \
106
\"phase\": 0, \
107
\"realOut\": 0 \
108
} \
109
}, \
110
\"rxWbNbCompPFir\": { \
111
\"bankSel\": 0, \
112
\"rxWbNbCompPFirInMuxSel\": 0, \
113
\"rxWbNbCompPFirEn\": 1 \
114
}, \
115
\"resamp\": { \
116
\"rxResampEn\": 0, \
117
\"resampPhaseI\": 0, \
118
\"resampPhaseQ\": 0 \
119
}, \
120
\"gsOutMuxSel\": 1, \
121
\"rxOutSel\": 0, \
122
\"rxRoundMode\": 0, \
123
\"dpArmSel\": 0 \
124
} \
125
}, \
126
\"lnaConfig\": { \
127
\"externalLnaPresent\": false, \
128
\"gpioSourceSel\": 0, \
129
\"externalLnaPinSel\": 0, \
130
\"settlingDelay\": 0, \
131
\"numberLnaGainSteps\": 0, \
132
\"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
133
\"lnaDigitalGainDelay\": 0, \
134
\"minGainIndex\": 0, \
135
\"lnaType\": 0 \
136
}, \
137
\"rxSsiConfig\": { \
138
\"ssiType\": 1, \
139
\"ssiDataFormatSel\": 4, \
140
\"numLaneSel\": 0, \
141
\"strobeType\": 0, \
142
\"lsbFirst\": 0, \
143
\"qFirst\": 0, \
144
\"txRefClockPin\": 0, \
145
\"lvdsIBitInversion\": false, \
146
\"lvdsQBitInversion\": false, \
147
\"lvdsStrobeBitInversion\": false, \
148
\"lvdsUseLsbIn12bitMode\": 0, \
149
\"lvdsRxClkInversionEn\": false, \
150
\"cmosDdrPosClkEn\": false, \
151
\"cmosClkInversionEn\": false, \
152
\"ddrEn\": false, \
153
\"rxMaskStrobeEn\": false \
154
} \
155
} \
156
}, { \
157
\"profile\": { \
158
\"primarySigBandwidth_Hz\": 1008000, \
159
\"rxOutputRate_Hz\": 1920000, \
160
\"rxInterfaceSampleRate_Hz\": 1920000, \
161
\"rxOffsetLo_kHz\": 0, \
162
\"rxNcoEnable\": false, \
163
\"outputSignaling\": 0, \
164
\"filterOrder\": 1, \
165
\"filterOrderLp\": 1, \
166
\"hpAdcCorner\": 20000000, \
167
\"lpAdcCorner\": 0, \
168
\"adcClk_kHz\": 2211840, \
169
\"rxCorner3dB_kHz\": 40000, \
170
\"rxCorner3dBLp_kHz\": 40000, \
171
\"tiaPower\": 2, \
172
\"tiaPowerLp\": 2, \
173
\"channelType\": 2, \
174
\"adcType\": 1, \
175
\"lpAdcCalMode\": 0, \
176
\"gainTableType\": 0, \
177
\"rxDpProfile\": { \
178
\"rxNbDecTop\": { \
179
\"scicBlk23En\": 0, \
180
\"scicBlk23DivFactor\": 1, \
181
\"scicBlk23LowRippleEn\": 0, \
182
\"decBy2Blk35En\": 0, \
183
\"decBy2Blk37En\": 0, \
184
\"decBy2Blk39En\": 0, \
185
\"decBy2Blk41En\": 0, \
186
\"decBy2Blk43En\": 0, \
187
\"decBy3Blk45En\": 0, \
188
\"decBy2Blk47En\": 0 \
189
}, \
190
\"rxWbDecTop\": { \
191
\"decBy2Blk25En\": 1, \
192
\"decBy2Blk27En\": 1, \
193
\"decBy2Blk29En\": 1, \
194
\"decBy2Blk31En\": 1, \
195
\"decBy2Blk33En\": 1, \
196
\"wbLpfBlk33p1En\": 0 \
197
}, \
198
\"rxDecTop\": { \
199
\"decBy3Blk15En\": 1, \
200
\"decBy2Hb3Blk17p1En\": 0, \
201
\"decBy2Hb4Blk17p2En\": 0, \
202
\"decBy2Hb5Blk19p1En\": 0, \
203
\"decBy2Hb6Blk19p2En\": 0 \
204
}, \
205
\"rxSincHBTop\": { \
206
\"sincGainMux\": 1, \
207
\"sincMux\": 4, \
208
\"hbMux\": 4, \
209
\"isGainCompEnabled\": 0, \
210
\"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
211
\"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
212
}, \
213
\"rxNbDem\": { \
214
\"dpInFifo\": { \
215
\"dpInFifoEn\": 0, \
216
\"dpInFifoMode\": 0, \
217
\"dpInFifoTestDataSel\": 0 \
218
}, \
219
\"rxNbNco\": { \
220
\"rxNbNcoEn\": 1, \
221
\"rxNbNcoConfig\": { \
222
\"freq\": 0, \
223
\"sampleFreq\": 1920000, \
224
\"phase\": 0, \
225
\"realOut\": 0 \
226
} \
227
}, \
228
\"rxWbNbCompPFir\": { \
229
\"bankSel\": 2, \
230
\"rxWbNbCompPFirInMuxSel\": 0, \
231
\"rxWbNbCompPFirEn\": 1 \
232
}, \
233
\"resamp\": { \
234
\"rxResampEn\": 0, \
235
\"resampPhaseI\": 0, \
236
\"resampPhaseQ\": 0 \
237
}, \
238
\"gsOutMuxSel\": 1, \
239
\"rxOutSel\": 0, \
240
\"rxRoundMode\": 0, \
241
\"dpArmSel\": 0 \
242
} \
243
}, \
244
\"lnaConfig\": { \
245
\"externalLnaPresent\": false, \
246
\"gpioSourceSel\": 0, \
247
\"externalLnaPinSel\": 0, \
248
\"settlingDelay\": 0, \
249
\"numberLnaGainSteps\": 0, \
250
\"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
251
\"lnaDigitalGainDelay\": 0, \
252
\"minGainIndex\": 0, \
253
\"lnaType\": 0 \
254
}, \
255
\"rxSsiConfig\": { \
256
\"ssiType\": 1, \
257
\"ssiDataFormatSel\": 4, \
258
\"numLaneSel\": 0, \
259
\"strobeType\": 0, \
260
\"lsbFirst\": 0, \
261
\"qFirst\": 0, \
262
\"txRefClockPin\": 0, \
263
\"lvdsIBitInversion\": false, \
264
\"lvdsQBitInversion\": false, \
265
\"lvdsStrobeBitInversion\": false, \
266
\"lvdsUseLsbIn12bitMode\": 0, \
267
\"lvdsRxClkInversionEn\": false, \
268
\"cmosDdrPosClkEn\": false, \
269
\"cmosClkInversionEn\": false, \
270
\"ddrEn\": false, \
271
\"rxMaskStrobeEn\": false \
272
} \
273
} \
274
}, { \
275
\"profile\": { \
276
\"primarySigBandwidth_Hz\": 12500, \
277
\"rxOutputRate_Hz\": 0, \
278
\"rxInterfaceSampleRate_Hz\": 0, \
279
\"rxOffsetLo_kHz\": 0, \
280
\"rxNcoEnable\": false, \
281
\"outputSignaling\": 0, \
282
\"filterOrder\": 1, \
283
\"filterOrderLp\": 1, \
284
\"hpAdcCorner\": 0, \
285
\"lpAdcCorner\": 0, \
286
\"adcClk_kHz\": 0, \
287
\"rxCorner3dB_kHz\": 0, \
288
\"rxCorner3dBLp_kHz\": 0, \
289
\"tiaPower\": 2, \
290
\"tiaPowerLp\": 2, \
291
\"channelType\": 0, \
292
\"adcType\": 1, \
293
\"lpAdcCalMode\": 0, \
294
\"gainTableType\": 0, \
295
\"rxDpProfile\": { \
296
\"rxNbDecTop\": { \
297
\"scicBlk23En\": 0, \
298
\"scicBlk23DivFactor\": 0, \
299
\"scicBlk23LowRippleEn\": 0, \
300
\"decBy2Blk35En\": 0, \
301
\"decBy2Blk37En\": 0, \
302
\"decBy2Blk39En\": 0, \
303
\"decBy2Blk41En\": 0, \
304
\"decBy2Blk43En\": 0, \
305
\"decBy3Blk45En\": 0, \
306
\"decBy2Blk47En\": 0 \
307
}, \
308
\"rxWbDecTop\": { \
309
\"decBy2Blk25En\": 0, \
310
\"decBy2Blk27En\": 0, \
311
\"decBy2Blk29En\": 0, \
312
\"decBy2Blk31En\": 0, \
313
\"decBy2Blk33En\": 0, \
314
\"wbLpfBlk33p1En\": 0 \
315
}, \
316
\"rxDecTop\": { \
317
\"decBy3Blk15En\": 0, \
318
\"decBy2Hb3Blk17p1En\": 0, \
319
\"decBy2Hb4Blk17p2En\": 0, \
320
\"decBy2Hb5Blk19p1En\": 0, \
321
\"decBy2Hb6Blk19p2En\": 0 \
322
}, \
323
\"rxSincHBTop\": { \
324
\"sincGainMux\": 1, \
325
\"sincMux\": 0, \
326
\"hbMux\": 4, \
327
\"isGainCompEnabled\": 0, \
328
\"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
329
\"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
330
}, \
331
\"rxNbDem\": { \
332
\"dpInFifo\": { \
333
\"dpInFifoEn\": 0, \
334
\"dpInFifoMode\": 0, \
335
\"dpInFifoTestDataSel\": 0 \
336
}, \
337
\"rxNbNco\": { \
338
\"rxNbNcoEn\": 0, \
339
\"rxNbNcoConfig\": { \
340
\"freq\": 0, \
341
\"sampleFreq\": 0, \
342
\"phase\": 0, \
343
\"realOut\": 0 \
344
} \
345
}, \
346
\"rxWbNbCompPFir\": { \
347
\"bankSel\": 0, \
348
\"rxWbNbCompPFirInMuxSel\": 0, \
349
\"rxWbNbCompPFirEn\": 0 \
350
}, \
351
\"resamp\": { \
352
\"rxResampEn\": 0, \
353
\"resampPhaseI\": 0, \
354
\"resampPhaseQ\": 0 \
355
}, \
356
\"gsOutMuxSel\": 1, \
357
\"rxOutSel\": 0, \
358
\"rxRoundMode\": 0, \
359
\"dpArmSel\": 0 \
360
} \
361
}, \
362
\"lnaConfig\": { \
363
\"externalLnaPresent\": false, \
364
\"gpioSourceSel\": 0, \
365
\"externalLnaPinSel\": 0, \
366
\"settlingDelay\": 0, \
367
\"numberLnaGainSteps\": 0, \
368
\"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
369
\"lnaDigitalGainDelay\": 0, \
370
\"minGainIndex\": 0, \
371
\"lnaType\": 0 \
372
}, \
373
\"rxSsiConfig\": { \
374
\"ssiType\": 0, \
375
\"ssiDataFormatSel\": 0, \
376
\"numLaneSel\": 0, \
377
\"strobeType\": 0, \
378
\"lsbFirst\": 0, \
379
\"qFirst\": 0, \
380
\"txRefClockPin\": 0, \
381
\"lvdsIBitInversion\": false, \
382
\"lvdsQBitInversion\": false, \
383
\"lvdsStrobeBitInversion\": false, \
384
\"lvdsUseLsbIn12bitMode\": 0, \
385
\"lvdsRxClkInversionEn\": false, \
386
\"cmosDdrPosClkEn\": false, \
387
\"cmosClkInversionEn\": false, \
388
\"ddrEn\": false, \
389
\"rxMaskStrobeEn\": false \
390
} \
391
} \
392
}, { \
393
\"profile\": { \
394
\"primarySigBandwidth_Hz\": 12500, \
395
\"rxOutputRate_Hz\": 0, \
396
\"rxInterfaceSampleRate_Hz\": 0, \
397
\"rxOffsetLo_kHz\": 0, \
398
\"rxNcoEnable\": false, \
399
\"outputSignaling\": 0, \
400
\"filterOrder\": 1, \
401
\"filterOrderLp\": 1, \
402
\"hpAdcCorner\": 0, \
403
\"lpAdcCorner\": 0, \
404
\"adcClk_kHz\": 0, \
405
\"rxCorner3dB_kHz\": 0, \
406
\"rxCorner3dBLp_kHz\": 0, \
407
\"tiaPower\": 2, \
408
\"tiaPowerLp\": 2, \
409
\"channelType\": 0, \
410
\"adcType\": 1, \
411
\"lpAdcCalMode\": 0, \
412
\"gainTableType\": 0, \
413
\"rxDpProfile\": { \
414
\"rxNbDecTop\": { \
415
\"scicBlk23En\": 0, \
416
\"scicBlk23DivFactor\": 0, \
417
\"scicBlk23LowRippleEn\": 0, \
418
\"decBy2Blk35En\": 0, \
419
\"decBy2Blk37En\": 0, \
420
\"decBy2Blk39En\": 0, \
421
\"decBy2Blk41En\": 0, \
422
\"decBy2Blk43En\": 0, \
423
\"decBy3Blk45En\": 0, \
424
\"decBy2Blk47En\": 0 \
425
}, \
426
\"rxWbDecTop\": { \
427
\"decBy2Blk25En\": 0, \
428
\"decBy2Blk27En\": 0, \
429
\"decBy2Blk29En\": 0, \
430
\"decBy2Blk31En\": 0, \
431
\"decBy2Blk33En\": 0, \
432
\"wbLpfBlk33p1En\": 0 \
433
}, \
434
\"rxDecTop\": { \
435
\"decBy3Blk15En\": 0, \
436
\"decBy2Hb3Blk17p1En\": 0, \
437
\"decBy2Hb4Blk17p2En\": 0, \
438
\"decBy2Hb5Blk19p1En\": 0, \
439
\"decBy2Hb6Blk19p2En\": 0 \
440
}, \
441
\"rxSincHBTop\": { \
442
\"sincGainMux\": 1, \
443
\"sincMux\": 0, \
444
\"hbMux\": 4, \
445
\"isGainCompEnabled\": 0, \
446
\"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
447
\"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
448
}, \
449
\"rxNbDem\": { \
450
\"dpInFifo\": { \
451
\"dpInFifoEn\": 0, \
452
\"dpInFifoMode\": 0, \
453
\"dpInFifoTestDataSel\": 0 \
454
}, \
455
\"rxNbNco\": { \
456
\"rxNbNcoEn\": 0, \
457
\"rxNbNcoConfig\": { \
458
\"freq\": 0, \
459
\"sampleFreq\": 0, \
460
\"phase\": 0, \
461
\"realOut\": 0 \
462
} \
463
}, \
464
\"rxWbNbCompPFir\": { \
465
\"bankSel\": 0, \
466
\"rxWbNbCompPFirInMuxSel\": 0, \
467
\"rxWbNbCompPFirEn\": 0 \
468
}, \
469
\"resamp\": { \
470
\"rxResampEn\": 0, \
471
\"resampPhaseI\": 0, \
472
\"resampPhaseQ\": 0 \
473
}, \
474
\"gsOutMuxSel\": 1, \
475
\"rxOutSel\": 0, \
476
\"rxRoundMode\": 0, \
477
\"dpArmSel\": 0 \
478
} \
479
}, \
480
\"lnaConfig\": { \
481
\"externalLnaPresent\": false, \
482
\"gpioSourceSel\": 0, \
483
\"externalLnaPinSel\": 0, \
484
\"settlingDelay\": 0, \
485
\"numberLnaGainSteps\": 0, \
486
\"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
487
\"lnaDigitalGainDelay\": 0, \
488
\"minGainIndex\": 0, \
489
\"lnaType\": 0 \
490
}, \
491
\"rxSsiConfig\": { \
492
\"ssiType\": 0, \
493
\"ssiDataFormatSel\": 0, \
494
\"numLaneSel\": 0, \
495
\"strobeType\": 0, \
496
\"lsbFirst\": 0, \
497
\"qFirst\": 0, \
498
\"txRefClockPin\": 0, \
499
\"lvdsIBitInversion\": false, \
500
\"lvdsQBitInversion\": false, \
501
\"lvdsStrobeBitInversion\": false, \
502
\"lvdsUseLsbIn12bitMode\": 0, \
503
\"lvdsRxClkInversionEn\": false, \
504
\"cmosDdrPosClkEn\": false, \
505
\"cmosClkInversionEn\": false, \
506
\"ddrEn\": false, \
507
\"rxMaskStrobeEn\": false \
508
} \
509
} \
510
}, { \
511
\"profile\": { \
512
\"primarySigBandwidth_Hz\": 1008000, \
513
\"rxOutputRate_Hz\": 1920000, \
514
\"rxInterfaceSampleRate_Hz\": 1920000, \
515
\"rxOffsetLo_kHz\": 0, \
516
\"rxNcoEnable\": false, \
517
\"outputSignaling\": 0, \
518
\"filterOrder\": 1, \
519
\"filterOrderLp\": 1, \
520
\"hpAdcCorner\": 50000000, \
521
\"lpAdcCorner\": 0, \
522
\"adcClk_kHz\": 2211840, \
523
\"rxCorner3dB_kHz\": 100000, \
524
\"rxCorner3dBLp_kHz\": 100000, \
525
\"tiaPower\": 2, \
526
\"tiaPowerLp\": 2, \
527
\"channelType\": 64, \
528
\"adcType\": 1, \
529
\"lpAdcCalMode\": 0, \
530
\"gainTableType\": 0, \
531
\"rxDpProfile\": { \
532
\"rxNbDecTop\": { \
533
\"scicBlk23En\": 0, \
534
\"scicBlk23DivFactor\": 1, \
535
\"scicBlk23LowRippleEn\": 0, \
536
\"decBy2Blk35En\": 0, \
537
\"decBy2Blk37En\": 0, \
538
\"decBy2Blk39En\": 0, \
539
\"decBy2Blk41En\": 0, \
540
\"decBy2Blk43En\": 0, \
541
\"decBy3Blk45En\": 0, \
542
\"decBy2Blk47En\": 0 \
543
}, \
544
\"rxWbDecTop\": { \
545
\"decBy2Blk25En\": 1, \
546
\"decBy2Blk27En\": 1, \
547
\"decBy2Blk29En\": 1, \
548
\"decBy2Blk31En\": 1, \
549
\"decBy2Blk33En\": 1, \
550
\"wbLpfBlk33p1En\": 0 \
551
}, \
552
\"rxDecTop\": { \
553
\"decBy3Blk15En\": 1, \
554
\"decBy2Hb3Blk17p1En\": 0, \
555
\"decBy2Hb4Blk17p2En\": 0, \
556
\"decBy2Hb5Blk19p1En\": 0, \
557
\"decBy2Hb6Blk19p2En\": 0 \
558
}, \
559
\"rxSincHBTop\": { \
560
\"sincGainMux\": 1, \
561
\"sincMux\": 4, \
562
\"hbMux\": 2, \
563
\"isGainCompEnabled\": 0, \
564
\"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
565
\"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
566
}, \
567
\"rxNbDem\": { \
568
\"dpInFifo\": { \
569
\"dpInFifoEn\": 0, \
570
\"dpInFifoMode\": 0, \
571
\"dpInFifoTestDataSel\": 0 \
572
}, \
573
\"rxNbNco\": { \
574
\"rxNbNcoEn\": 0, \
575
\"rxNbNcoConfig\": { \
576
\"freq\": 0, \
577
\"sampleFreq\": 0, \
578
\"phase\": 0, \
579
\"realOut\": 0 \
580
} \
581
}, \
582
\"rxWbNbCompPFir\": { \
583
\"bankSel\": 1, \
584
\"rxWbNbCompPFirInMuxSel\": 0, \
585
\"rxWbNbCompPFirEn\": 0 \
586
}, \
587
\"resamp\": { \
588
\"rxResampEn\": 0, \
589
\"resampPhaseI\": 0, \
590
\"resampPhaseQ\": 0 \
591
}, \
592
\"gsOutMuxSel\": 1, \
593
\"rxOutSel\": 0, \
594
\"rxRoundMode\": 0, \
595
\"dpArmSel\": 0 \
596
} \
597
}, \
598
\"lnaConfig\": { \
599
\"externalLnaPresent\": false, \
600
\"gpioSourceSel\": 0, \
601
\"externalLnaPinSel\": 0, \
602
\"settlingDelay\": 0, \
603
\"numberLnaGainSteps\": 0, \
604
\"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
605
\"lnaDigitalGainDelay\": 0, \
606
\"minGainIndex\": 0, \
607
\"lnaType\": 0 \
608
}, \
609
\"rxSsiConfig\": { \
610
\"ssiType\": 1, \
611
\"ssiDataFormatSel\": 4, \
612
\"numLaneSel\": 0, \
613
\"strobeType\": 0, \
614
\"lsbFirst\": 0, \
615
\"qFirst\": 0, \
616
\"txRefClockPin\": 0, \
617
\"lvdsIBitInversion\": false, \
618
\"lvdsQBitInversion\": false, \
619
\"lvdsStrobeBitInversion\": false, \
620
\"lvdsUseLsbIn12bitMode\": 0, \
621
\"lvdsRxClkInversionEn\": false, \
622
\"cmosDdrPosClkEn\": false, \
623
\"cmosClkInversionEn\": false, \
624
\"ddrEn\": false, \
625
\"rxMaskStrobeEn\": false \
626
} \
627
} \
628
}, { \
629
\"profile\": { \
630
\"primarySigBandwidth_Hz\": 1008000, \
631
\"rxOutputRate_Hz\": 1920000, \
632
\"rxInterfaceSampleRate_Hz\": 1920000, \
633
\"rxOffsetLo_kHz\": 0, \
634
\"rxNcoEnable\": false, \
635
\"outputSignaling\": 0, \
636
\"filterOrder\": 1, \
637
\"filterOrderLp\": 1, \
638
\"hpAdcCorner\": 50000000, \
639
\"lpAdcCorner\": 0, \
640
\"adcClk_kHz\": 2211840, \
641
\"rxCorner3dB_kHz\": 100000, \
642
\"rxCorner3dBLp_kHz\": 100000, \
643
\"tiaPower\": 2, \
644
\"tiaPowerLp\": 2, \
645
\"channelType\": 128, \
646
\"adcType\": 1, \
647
\"lpAdcCalMode\": 0, \
648
\"gainTableType\": 0, \
649
\"rxDpProfile\": { \
650
\"rxNbDecTop\": { \
651
\"scicBlk23En\": 0, \
652
\"scicBlk23DivFactor\": 1, \
653
\"scicBlk23LowRippleEn\": 0, \
654
\"decBy2Blk35En\": 0, \
655
\"decBy2Blk37En\": 0, \
656
\"decBy2Blk39En\": 0, \
657
\"decBy2Blk41En\": 0, \
658
\"decBy2Blk43En\": 0, \
659
\"decBy3Blk45En\": 0, \
660
\"decBy2Blk47En\": 0 \
661
}, \
662
\"rxWbDecTop\": { \
663
\"decBy2Blk25En\": 1, \
664
\"decBy2Blk27En\": 1, \
665
\"decBy2Blk29En\": 1, \
666
\"decBy2Blk31En\": 1, \
667
\"decBy2Blk33En\": 1, \
668
\"wbLpfBlk33p1En\": 0 \
669
}, \
670
\"rxDecTop\": { \
671
\"decBy3Blk15En\": 1, \
672
\"decBy2Hb3Blk17p1En\": 0, \
673
\"decBy2Hb4Blk17p2En\": 0, \
674
\"decBy2Hb5Blk19p1En\": 0, \
675
\"decBy2Hb6Blk19p2En\": 0 \
676
}, \
677
\"rxSincHBTop\": { \
678
\"sincGainMux\": 1, \
679
\"sincMux\": 4, \
680
\"hbMux\": 2, \
681
\"isGainCompEnabled\": 0, \
682
\"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
683
\"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
684
}, \
685
\"rxNbDem\": { \
686
\"dpInFifo\": { \
687
\"dpInFifoEn\": 0, \
688
\"dpInFifoMode\": 0, \
689
\"dpInFifoTestDataSel\": 0 \
690
}, \
691
\"rxNbNco\": { \
692
\"rxNbNcoEn\": 0, \
693
\"rxNbNcoConfig\": { \
694
\"freq\": 0, \
695
\"sampleFreq\": 0, \
696
\"phase\": 0, \
697
\"realOut\": 0 \
698
} \
699
}, \
700
\"rxWbNbCompPFir\": { \
701
\"bankSel\": 3, \
702
\"rxWbNbCompPFirInMuxSel\": 0, \
703
\"rxWbNbCompPFirEn\": 0 \
704
}, \
705
\"resamp\": { \
706
\"rxResampEn\": 0, \
707
\"resampPhaseI\": 0, \
708
\"resampPhaseQ\": 0 \
709
}, \
710
\"gsOutMuxSel\": 1, \
711
\"rxOutSel\": 0, \
712
\"rxRoundMode\": 0, \
713
\"dpArmSel\": 0 \
714
} \
715
}, \
716
\"lnaConfig\": { \
717
\"externalLnaPresent\": false, \
718
\"gpioSourceSel\": 0, \
719
\"externalLnaPinSel\": 0, \
720
\"settlingDelay\": 0, \
721
\"numberLnaGainSteps\": 0, \
722
\"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
723
\"lnaDigitalGainDelay\": 0, \
724
\"minGainIndex\": 0, \
725
\"lnaType\": 0 \
726
}, \
727
\"rxSsiConfig\": { \
728
\"ssiType\": 1, \
729
\"ssiDataFormatSel\": 4, \
730
\"numLaneSel\": 0, \
731
\"strobeType\": 0, \
732
\"lsbFirst\": 0, \
733
\"qFirst\": 0, \
734
\"txRefClockPin\": 0, \
735
\"lvdsIBitInversion\": false, \
736
\"lvdsQBitInversion\": false, \
737
\"lvdsStrobeBitInversion\": false, \
738
\"lvdsUseLsbIn12bitMode\": 0, \
739
\"lvdsRxClkInversionEn\": false, \
740
\"cmosDdrPosClkEn\": false, \
741
\"cmosClkInversionEn\": false, \
742
\"ddrEn\": false, \
743
\"rxMaskStrobeEn\": false \
744
} \
745
} \
746
}, { \
747
\"profile\": { \
748
\"primarySigBandwidth_Hz\": 12500, \
749
\"rxOutputRate_Hz\": 0, \
750
\"rxInterfaceSampleRate_Hz\": 0, \
751
\"rxOffsetLo_kHz\": 0, \
752
\"rxNcoEnable\": false, \
753
\"outputSignaling\": 0, \
754
\"filterOrder\": 1, \
755
\"filterOrderLp\": 1, \
756
\"hpAdcCorner\": 0, \
757
\"lpAdcCorner\": 0, \
758
\"adcClk_kHz\": 0, \
759
\"rxCorner3dB_kHz\": 0, \
760
\"rxCorner3dBLp_kHz\": 0, \
761
\"tiaPower\": 2, \
762
\"tiaPowerLp\": 2, \
763
\"channelType\": 0, \
764
\"adcType\": 1, \
765
\"lpAdcCalMode\": 0, \
766
\"gainTableType\": 0, \
767
\"rxDpProfile\": { \
768
\"rxNbDecTop\": { \
769
\"scicBlk23En\": 0, \
770
\"scicBlk23DivFactor\": 0, \
771
\"scicBlk23LowRippleEn\": 0, \
772
\"decBy2Blk35En\": 0, \
773
\"decBy2Blk37En\": 0, \
774
\"decBy2Blk39En\": 0, \
775
\"decBy2Blk41En\": 0, \
776
\"decBy2Blk43En\": 0, \
777
\"decBy3Blk45En\": 0, \
778
\"decBy2Blk47En\": 0 \
779
}, \
780
\"rxWbDecTop\": { \
781
\"decBy2Blk25En\": 0, \
782
\"decBy2Blk27En\": 0, \
783
\"decBy2Blk29En\": 0, \
784
\"decBy2Blk31En\": 0, \
785
\"decBy2Blk33En\": 0, \
786
\"wbLpfBlk33p1En\": 0 \
787
}, \
788
\"rxDecTop\": { \
789
\"decBy3Blk15En\": 0, \
790
\"decBy2Hb3Blk17p1En\": 0, \
791
\"decBy2Hb4Blk17p2En\": 0, \
792
\"decBy2Hb5Blk19p1En\": 0, \
793
\"decBy2Hb6Blk19p2En\": 0 \
794
}, \
795
\"rxSincHBTop\": { \
796
\"sincGainMux\": 1, \
797
\"sincMux\": 0, \
798
\"hbMux\": 4, \
799
\"isGainCompEnabled\": 0, \
800
\"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
801
\"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
802
}, \
803
\"rxNbDem\": { \
804
\"dpInFifo\": { \
805
\"dpInFifoEn\": 0, \
806
\"dpInFifoMode\": 0, \
807
\"dpInFifoTestDataSel\": 0 \
808
}, \
809
\"rxNbNco\": { \
810
\"rxNbNcoEn\": 0, \
811
\"rxNbNcoConfig\": { \
812
\"freq\": 0, \
813
\"sampleFreq\": 0, \
814
\"phase\": 0, \
815
\"realOut\": 0 \
816
} \
817
}, \
818
\"rxWbNbCompPFir\": { \
819
\"bankSel\": 0, \
820
\"rxWbNbCompPFirInMuxSel\": 0, \
821
\"rxWbNbCompPFirEn\": 0 \
822
}, \
823
\"resamp\": { \
824
\"rxResampEn\": 0, \
825
\"resampPhaseI\": 0, \
826
\"resampPhaseQ\": 0 \
827
}, \
828
\"gsOutMuxSel\": 1, \
829
\"rxOutSel\": 0, \
830
\"rxRoundMode\": 0, \
831
\"dpArmSel\": 0 \
832
} \
833
}, \
834
\"lnaConfig\": { \
835
\"externalLnaPresent\": false, \
836
\"gpioSourceSel\": 0, \
837
\"externalLnaPinSel\": 0, \
838
\"settlingDelay\": 0, \
839
\"numberLnaGainSteps\": 0, \
840
\"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
841
\"lnaDigitalGainDelay\": 0, \
842
\"minGainIndex\": 0, \
843
\"lnaType\": 0 \
844
}, \
845
\"rxSsiConfig\": { \
846
\"ssiType\": 0, \
847
\"ssiDataFormatSel\": 0, \
848
\"numLaneSel\": 0, \
849
\"strobeType\": 0, \
850
\"lsbFirst\": 0, \
851
\"qFirst\": 0, \
852
\"txRefClockPin\": 0, \
853
\"lvdsIBitInversion\": false, \
854
\"lvdsQBitInversion\": false, \
855
\"lvdsStrobeBitInversion\": false, \
856
\"lvdsUseLsbIn12bitMode\": 0, \
857
\"lvdsRxClkInversionEn\": false, \
858
\"cmosDdrPosClkEn\": false, \
859
\"cmosClkInversionEn\": false, \
860
\"ddrEn\": false, \
861
\"rxMaskStrobeEn\": false \
862
} \
863
} \
864
}, { \
865
\"profile\": { \
866
\"primarySigBandwidth_Hz\": 12500, \
867
\"rxOutputRate_Hz\": 0, \
868
\"rxInterfaceSampleRate_Hz\": 0, \
869
\"rxOffsetLo_kHz\": 0, \
870
\"rxNcoEnable\": false, \
871
\"outputSignaling\": 0, \
872
\"filterOrder\": 1, \
873
\"filterOrderLp\": 1, \
874
\"hpAdcCorner\": 0, \
875
\"lpAdcCorner\": 0, \
876
\"adcClk_kHz\": 0, \
877
\"rxCorner3dB_kHz\": 0, \
878
\"rxCorner3dBLp_kHz\": 0, \
879
\"tiaPower\": 2, \
880
\"tiaPowerLp\": 2, \
881
\"channelType\": 0, \
882
\"adcType\": 1, \
883
\"lpAdcCalMode\": 0, \
884
\"gainTableType\": 0, \
885
\"rxDpProfile\": { \
886
\"rxNbDecTop\": { \
887
\"scicBlk23En\": 0, \
888
\"scicBlk23DivFactor\": 0, \
889
\"scicBlk23LowRippleEn\": 0, \
890
\"decBy2Blk35En\": 0, \
891
\"decBy2Blk37En\": 0, \
892
\"decBy2Blk39En\": 0, \
893
\"decBy2Blk41En\": 0, \
894
\"decBy2Blk43En\": 0, \
895
\"decBy3Blk45En\": 0, \
896
\"decBy2Blk47En\": 0 \
897
}, \
898
\"rxWbDecTop\": { \
899
\"decBy2Blk25En\": 0, \
900
\"decBy2Blk27En\": 0, \
901
\"decBy2Blk29En\": 0, \
902
\"decBy2Blk31En\": 0, \
903
\"decBy2Blk33En\": 0, \
904
\"wbLpfBlk33p1En\": 0 \
905
}, \
906
\"rxDecTop\": { \
907
\"decBy3Blk15En\": 0, \
908
\"decBy2Hb3Blk17p1En\": 0, \
909
\"decBy2Hb4Blk17p2En\": 0, \
910
\"decBy2Hb5Blk19p1En\": 0, \
911
\"decBy2Hb6Blk19p2En\": 0 \
912
}, \
913
\"rxSincHBTop\": { \
914
\"sincGainMux\": 1, \
915
\"sincMux\": 0, \
916
\"hbMux\": 4, \
917
\"isGainCompEnabled\": 0, \
918
\"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
919
\"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
920
}, \
921
\"rxNbDem\": { \
922
\"dpInFifo\": { \
923
\"dpInFifoEn\": 0, \
924
\"dpInFifoMode\": 0, \
925
\"dpInFifoTestDataSel\": 0 \
926
}, \
927
\"rxNbNco\": { \
928
\"rxNbNcoEn\": 0, \
929
\"rxNbNcoConfig\": { \
930
\"freq\": 0, \
931
\"sampleFreq\": 0, \
932
\"phase\": 0, \
933
\"realOut\": 0 \
934
} \
935
}, \
936
\"rxWbNbCompPFir\": { \
937
\"bankSel\": 0, \
938
\"rxWbNbCompPFirInMuxSel\": 0, \
939
\"rxWbNbCompPFirEn\": 0 \
940
}, \
941
\"resamp\": { \
942
\"rxResampEn\": 0, \
943
\"resampPhaseI\": 0, \
944
\"resampPhaseQ\": 0 \
945
}, \
946
\"gsOutMuxSel\": 1, \
947
\"rxOutSel\": 0, \
948
\"rxRoundMode\": 0, \
949
\"dpArmSel\": 0 \
950
} \
951
}, \
952
\"lnaConfig\": { \
953
\"externalLnaPresent\": false, \
954
\"gpioSourceSel\": 0, \
955
\"externalLnaPinSel\": 0, \
956
\"settlingDelay\": 0, \
957
\"numberLnaGainSteps\": 0, \
958
\"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
959
\"lnaDigitalGainDelay\": 0, \
960
\"minGainIndex\": 0, \
961
\"lnaType\": 0 \
962
}, \
963
\"rxSsiConfig\": { \
964
\"ssiType\": 0, \
965
\"ssiDataFormatSel\": 0, \
966
\"numLaneSel\": 0, \
967
\"strobeType\": 0, \
968
\"lsbFirst\": 0, \
969
\"qFirst\": 0, \
970
\"txRefClockPin\": 0, \
971
\"lvdsIBitInversion\": false, \
972
\"lvdsQBitInversion\": false, \
973
\"lvdsStrobeBitInversion\": false, \
974
\"lvdsUseLsbIn12bitMode\": 0, \
975
\"lvdsRxClkInversionEn\": false, \
976
\"cmosDdrPosClkEn\": false, \
977
\"cmosClkInversionEn\": false, \
978
\"ddrEn\": false, \
979
\"rxMaskStrobeEn\": false \
980
} \
981
} \
982
} ] \
983
}, \
984
\"tx\": { \
985
\"txInitChannelMask\": 12, \
986
\"txProfile\": [ { \
987
\"primarySigBandwidth_Hz\": 1008000, \
988
\"txInputRate_Hz\": 1920000, \
989
\"txInterfaceSampleRate_Hz\": 1920000, \
990
\"txOffsetLo_kHz\": 0, \
991
\"validDataDelay\": 0, \
992
\"txBbf3dBCorner_kHz\": 50000, \
993
\"outputSignaling\": 0, \
994
\"txPdBiasCurrent\": 1, \
995
\"txPdGainEnable\": 0, \
996
\"txPrePdRealPole_kHz\": 1000000, \
997
\"txPostPdRealPole_kHz\": 530000, \
998
\"txBbfPower\": 2, \
999
\"txExtLoopBackType\": 0, \
1000
\"txExtLoopBackForInitCal\": 0, \
1001
\"txPeakLoopBackPower\": 0, \
1002
\"frequencyDeviation_Hz\": 0, \
1003
\"txDpProfile\": { \
1004
\"txPreProc\": { \
1005
\"txPreProcSymbol0\": 0, \
1006
\"txPreProcSymbol1\": 0, \
1007
\"txPreProcSymbol2\": 0, \
1008
\"txPreProcSymbol3\": 0, \
1009
\"txPreProcSymMapDivFactor\": 1, \
1010
\"txPreProcMode\": 1, \
1011
\"txPreProcWbNbPfirIBankSel\": 0, \
1012
\"txPreProcWbNbPfirQBankSel\": 1 \
1013
}, \
1014
\"txWbIntTop\": { \
1015
\"txInterpBy2Blk30En\": 1, \
1016
\"txInterpBy2Blk28En\": 1, \
1017
\"txInterpBy2Blk26En\": 1, \
1018
\"txInterpBy2Blk24En\": 1, \
1019
\"txInterpBy2Blk22En\": 1, \
1020
\"txWbLpfBlk22p1En\": 0 \
1021
}, \
1022
\"txNbIntTop\": { \
1023
\"txInterpBy2Blk20En\": 0, \
1024
\"txInterpBy2Blk18En\": 0, \
1025
\"txInterpBy2Blk16En\": 0, \
1026
\"txInterpBy2Blk14En\": 0, \
1027
\"txInterpBy2Blk12En\": 0, \
1028
\"txInterpBy3Blk10En\": 0, \
1029
\"txInterpBy2Blk8En\": 0, \
1030
\"txScicBlk32En\": 0, \
1031
\"txScicBlk32DivFactor\": 1 \
1032
}, \
1033
\"txIntTop\": { \
1034
\"interpBy3Blk44p1En\": 1, \
1035
\"sinc3Blk44En\": 0, \
1036
\"sinc2Blk42En\": 0, \
1037
\"interpBy3Blk40En\": 1, \
1038
\"interpBy2Blk38En\": 0, \
1039
\"interpBy2Blk36En\": 0 \
1040
}, \
1041
\"txIntTopFreqDevMap\": { \
1042
\"rrc2Frac\": 0, \
1043
\"mpll\": 0, \
1044
\"nchLsw\": 0, \
1045
\"nchMsb\": 0, \
1046
\"freqDevMapEn\": 0, \
1047
\"txRoundEn\": 1 \
1048
}, \
1049
\"txIqdmDuc\": { \
1050
\"iqdmDucMode\": 2, \
1051
\"iqdmDev\": 0, \
1052
\"iqdmDevOffset\": 0, \
1053
\"iqdmScalar\": 0, \
1054
\"iqdmThreshold\": 0, \
1055
\"iqdmNco\": { \
1056
\"freq\": 0, \
1057
\"sampleFreq\": 61440000, \
1058
\"phase\": 0, \
1059
\"realOut\": 0 \
1060
} \
1061
} \
1062
}, \
1063
\"txSsiConfig\": { \
1064
\"ssiType\": 1, \
1065
\"ssiDataFormatSel\": 4, \
1066
\"numLaneSel\": 0, \
1067
\"strobeType\": 0, \
1068
\"lsbFirst\": 0, \
1069
\"qFirst\": 0, \
1070
\"txRefClockPin\": 1, \
1071
\"lvdsIBitInversion\": false, \
1072
\"lvdsQBitInversion\": false, \
1073
\"lvdsStrobeBitInversion\": false, \
1074
\"lvdsUseLsbIn12bitMode\": 0, \
1075
\"lvdsRxClkInversionEn\": false, \
1076
\"cmosDdrPosClkEn\": false, \
1077
\"cmosClkInversionEn\": false, \
1078
\"ddrEn\": false, \
1079
\"rxMaskStrobeEn\": false \
1080
} \
1081
}, { \
1082
\"primarySigBandwidth_Hz\": 1008000, \
1083
\"txInputRate_Hz\": 1920000, \
1084
\"txInterfaceSampleRate_Hz\": 1920000, \
1085
\"txOffsetLo_kHz\": 0, \
1086
\"validDataDelay\": 0, \
1087
\"txBbf3dBCorner_kHz\": 50000, \
1088
\"outputSignaling\": 0, \
1089
\"txPdBiasCurrent\": 1, \
1090
\"txPdGainEnable\": 0, \
1091
\"txPrePdRealPole_kHz\": 1000000, \
1092
\"txPostPdRealPole_kHz\": 530000, \
1093
\"txBbfPower\": 2, \
1094
\"txExtLoopBackType\": 0, \
1095
\"txExtLoopBackForInitCal\": 0, \
1096
\"txPeakLoopBackPower\": 0, \
1097
\"frequencyDeviation_Hz\": 0, \
1098
\"txDpProfile\": { \
1099
\"txPreProc\": { \
1100
\"txPreProcSymbol0\": 0, \
1101
\"txPreProcSymbol1\": 0, \
1102
\"txPreProcSymbol2\": 0, \
1103
\"txPreProcSymbol3\": 0, \
1104
\"txPreProcSymMapDivFactor\": 1, \
1105
\"txPreProcMode\": 1, \
1106
\"txPreProcWbNbPfirIBankSel\": 2, \
1107
\"txPreProcWbNbPfirQBankSel\": 3 \
1108
}, \
1109
\"txWbIntTop\": { \
1110
\"txInterpBy2Blk30En\": 1, \
1111
\"txInterpBy2Blk28En\": 1, \
1112
\"txInterpBy2Blk26En\": 1, \
1113
\"txInterpBy2Blk24En\": 1, \
1114
\"txInterpBy2Blk22En\": 1, \
1115
\"txWbLpfBlk22p1En\": 0 \
1116
}, \
1117
\"txNbIntTop\": { \
1118
\"txInterpBy2Blk20En\": 0, \
1119
\"txInterpBy2Blk18En\": 0, \
1120
\"txInterpBy2Blk16En\": 0, \
1121
\"txInterpBy2Blk14En\": 0, \
1122
\"txInterpBy2Blk12En\": 0, \
1123
\"txInterpBy3Blk10En\": 0, \
1124
\"txInterpBy2Blk8En\": 0, \
1125
\"txScicBlk32En\": 0, \
1126
\"txScicBlk32DivFactor\": 1 \
1127
}, \
1128
\"txIntTop\": { \
1129
\"interpBy3Blk44p1En\": 1, \
1130
\"sinc3Blk44En\": 0, \
1131
\"sinc2Blk42En\": 0, \
1132
\"interpBy3Blk40En\": 1, \
1133
\"interpBy2Blk38En\": 0, \
1134
\"interpBy2Blk36En\": 0 \
1135
}, \
1136
\"txIntTopFreqDevMap\": { \
1137
\"rrc2Frac\": 0, \
1138
\"mpll\": 0, \
1139
\"nchLsw\": 0, \
1140
\"nchMsb\": 0, \
1141
\"freqDevMapEn\": 0, \
1142
\"txRoundEn\": 1 \
1143
}, \
1144
\"txIqdmDuc\": { \
1145
\"iqdmDucMode\": 2, \
1146
\"iqdmDev\": 0, \
1147
\"iqdmDevOffset\": 0, \
1148
\"iqdmScalar\": 0, \
1149
\"iqdmThreshold\": 0, \
1150
\"iqdmNco\": { \
1151
\"freq\": 0, \
1152
\"sampleFreq\": 61440000, \
1153
\"phase\": 0, \
1154
\"realOut\": 0 \
1155
} \
1156
} \
1157
}, \
1158
\"txSsiConfig\": { \
1159
\"ssiType\": 1, \
1160
\"ssiDataFormatSel\": 4, \
1161
\"numLaneSel\": 0, \
1162
\"strobeType\": 0, \
1163
\"lsbFirst\": 0, \
1164
\"qFirst\": 0, \
1165
\"txRefClockPin\": 1, \
1166
\"lvdsIBitInversion\": false, \
1167
\"lvdsQBitInversion\": false, \
1168
\"lvdsStrobeBitInversion\": false, \
1169
\"lvdsUseLsbIn12bitMode\": 0, \
1170
\"lvdsRxClkInversionEn\": false, \
1171
\"cmosDdrPosClkEn\": false, \
1172
\"cmosClkInversionEn\": false, \
1173
\"ddrEn\": false, \
1174
\"rxMaskStrobeEn\": false \
1175
} \
1176
} ] \
1177
}, \
1178
\"sysConfig\": { \
1179
\"duplexMode\": 1, \
1180
\"fhModeOn\": 0, \
1181
\"numDynamicProfiles\": 1, \
1182
\"mcsMode\": 0, \
1183
\"mcsInterfaceType\": 0, \
1184
\"adcTypeMonitor\": 1, \
1185
\"pllLockTime_us\": 380, \
1186
\"pllPhaseSyncWait_us\": 0, \
1187
\"pllModulus\": { \
1188
\"modulus\": [ 8388593, 8388593, 8388593, 8388593, 8388593 ], \
1189
\"dmModulus\": [ 8388593, 8388593 ] \
1190
}, \
1191
\"warmBootEnable\": false \
1192
}, \
1193
\"pfirBuffer\": { \
1194
\"pfirRxWbNbChFilterCoeff_A\": { \
1195
\"numCoeff\": 128, \
1196
\"symmetricSel\": 0, \
1197
\"tapsSel\": 3, \
1198
\"gainSel\": 2, \
1199
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -392, -228, 1164, -426, -2275, 3118, 1517, -7492, 4673, 8616, -16569, 2081, 24816, -27732, -11318, 53353, -35059, -44826, 94798, -27039, -110096, 145573, 15827, -224287, 197850, 132551, -432387, 241249, 465740, -1004873, 265939, 4480229, 4480229, 265939, -1004873, 465740, 241249, -432387, 132551, 197850, -224287, 15827, 145573, -110096, -27039, 94798, -44826, -35059, 53353, -11318, -27732, 24816, 2081, -16569, 8616, 4673, -7492, 1517, 3118, -2275, -426, 1164, -228, -392, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1200
}, \
1201
\"pfirRxWbNbChFilterCoeff_B\": { \
1202
\"numCoeff\": 128, \
1203
\"symmetricSel\": 0, \
1204
\"tapsSel\": 3, \
1205
\"gainSel\": 2, \
1206
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8388608, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1207
}, \
1208
\"pfirRxWbNbChFilterCoeff_C\": { \
1209
\"numCoeff\": 128, \
1210
\"symmetricSel\": 0, \
1211
\"tapsSel\": 3, \
1212
\"gainSel\": 2, \
1213
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -392, -228, 1164, -426, -2275, 3118, 1517, -7492, 4673, 8616, -16569, 2081, 24816, -27732, -11318, 53353, -35059, -44826, 94798, -27039, -110096, 145573, 15827, -224287, 197850, 132551, -432387, 241249, 465740, -1004873, 265939, 4480229, 4480229, 265939, -1004873, 465740, 241249, -432387, 132551, 197850, -224287, 15827, 145573, -110096, -27039, 94798, -44826, -35059, 53353, -11318, -27732, 24816, 2081, -16569, 8616, 4673, -7492, 1517, 3118, -2275, -426, 1164, -228, -392, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1214
}, \
1215
\"pfirRxWbNbChFilterCoeff_D\": { \
1216
\"numCoeff\": 128, \
1217
\"symmetricSel\": 0, \
1218
\"tapsSel\": 3, \
1219
\"gainSel\": 2, \
1220
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8388608, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1221
}, \
1222
\"pfirTxWbNbPulShpCoeff_A\": { \
1223
\"numCoeff\": 128, \
1224
\"symmetricSel\": 0, \
1225
\"tapsSel\": 3, \
1226
\"gainSel\": 2, \
1227
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1228
}, \
1229
\"pfirTxWbNbPulShpCoeff_B\": { \
1230
\"numCoeff\": 128, \
1231
\"symmetricSel\": 0, \
1232
\"tapsSel\": 3, \
1233
\"gainSel\": 2, \
1234
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1235
}, \
1236
\"pfirTxWbNbPulShpCoeff_C\": { \
1237
\"numCoeff\": 128, \
1238
\"symmetricSel\": 0, \
1239
\"tapsSel\": 3, \
1240
\"gainSel\": 2, \
1241
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1242
}, \
1243
\"pfirTxWbNbPulShpCoeff_D\": { \
1244
\"numCoeff\": 128, \
1245
\"symmetricSel\": 0, \
1246
\"tapsSel\": 3, \
1247
\"gainSel\": 2, \
1248
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1249
}, \
1250
\"pfirRxNbPulShp\": [ { \
1251
\"numCoeff\": 128, \
1252
\"symmetricSel\": 0, \
1253
\"taps\": 128, \
1254
\"gainSel\": 2, \
1255
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8388608, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1256
}, { \
1257
\"numCoeff\": 128, \
1258
\"symmetricSel\": 0, \
1259
\"taps\": 128, \
1260
\"gainSel\": 2, \
1261
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8388608, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1262
} ], \
1263
\"pfirRxMagLowTiaLowSRHp\": [ { \
1264
\"numCoeff\": 21, \
1265
\"coefficients\": [ -12, 83, -293, 734, -1489, 2594, -3965, 5403, -6516, 5868, 27957, 5868, -6516, 5403, -3965, 2594, -1489, 734, -293, 83, -12 ] \
1266
}, { \
1267
\"numCoeff\": 21, \
1268
\"coefficients\": [ -12, 83, -293, 734, -1489, 2594, -3965, 5403, -6516, 5868, 27957, 5868, -6516, 5403, -3965, 2594, -1489, 734, -293, 83, -12 ] \
1269
} ], \
1270
\"pfirRxMagLowTiaHighSRHp\": [ { \
1271
\"numCoeff\": 21, \
1272
\"coefficients\": [ -62, 194, 80, -829, 201, 1857, -179, -4602, -1259, 11431, 19102, 11431, -1259, -4602, -179, 1857, 201, -829, 80, 194, -62 ] \
1273
}, { \
1274
\"numCoeff\": 21, \
1275
\"coefficients\": [ -62, 194, 80, -829, 201, 1857, -179, -4602, -1259, 11431, 19102, 11431, -1259, -4602, -179, 1857, 201, -829, 80, 194, -62 ] \
1276
} ], \
1277
\"pfirRxMagHighTiaHighSRHp\": [ { \
1278
\"numCoeff\": 21, \
1279
\"coefficients\": [ 39, -229, 714, -1485, 2134, -1844, -219, 4147, -8514, 8496, 26292, 8496, -8514, 4147, -219, -1844, 2134, -1485, 714, -229, 39 ] \
1280
}, { \
1281
\"numCoeff\": 21, \
1282
\"coefficients\": [ 39, -229, 714, -1485, 2134, -1844, -219, 4147, -8514, 8496, 26292, 8496, -8514, 4147, -219, -1844, 2134, -1485, 714, -229, 39 ] \
1283
} ], \
1284
\"pfirRxMagLowTiaLowSRLp\": [ { \
1285
\"numCoeff\": 21, \
1286
\"coefficients\": [ -12, 83, -293, 733, -1488, 2593, -3963, 5401, -6514, 5870, 27953, 5870, -6514, 5401, -3963, 2593, -1488, 733, -293, 83, -12 ] \
1287
}, { \
1288
\"numCoeff\": 21, \
1289
\"coefficients\": [ -12, 83, -293, 733, -1488, 2593, -3963, 5401, -6514, 5870, 27953, 5870, -6514, 5401, -3963, 2593, -1488, 733, -293, 83, -12 ] \
1290
} ], \
1291
\"pfirRxMagLowTiaHighSRLp\": [ { \
1292
\"numCoeff\": 21, \
1293
\"coefficients\": [ -62, 194, 80, -828, 201, 1855, -180, -4597, -1254, 11428, 19093, 11428, -1254, -4597, -180, 1855, 201, -828, 80, 194, -62 ] \
1294
}, { \
1295
\"numCoeff\": 21, \
1296
\"coefficients\": [ -62, 194, 80, -828, 201, 1855, -180, -4597, -1254, 11428, 19093, 11428, -1254, -4597, -180, 1855, 201, -828, 80, 194, -62 ] \
1297
} ], \
1298
\"pfirRxMagHighTiaHighSRLp\": [ { \
1299
\"numCoeff\": 21, \
1300
\"coefficients\": [ 39, -229, 712, -1481, 2128, -1841, -215, 4131, -8490, 8497, 26266, 8497, -8490, 4131, -215, -1841, 2128, -1481, 712, -229, 39 ] \
1301
}, { \
1302
\"numCoeff\": 21, \
1303
\"coefficients\": [ 39, -229, 712, -1481, 2128, -1841, -215, 4131, -8490, 8497, 26266, 8497, -8490, 4131, -215, -1841, 2128, -1481, 712, -229, 39 ] \
1304
} ], \
1305
\"pfirTxMagComp1\": { \
1306
\"numCoeff\": 21, \
1307
\"coefficients\": [ 69, -384, 1125, -2089, 2300, -165, -5248, 12368, -13473, 4864, 34039, 4864, -13473, 12368, -5248, -165, 2300, -2089, 1125, -384, 69 ] \
1308
}, \
1309
\"pfirTxMagComp2\": { \
1310
\"numCoeff\": 21, \
1311
\"coefficients\": [ 69, -384, 1125, -2089, 2300, -165, -5248, 12368, -13473, 4864, 34039, 4864, -13473, 12368, -5248, -165, 2300, -2089, 1125, -384, 69 ] \
1312
}, \
1313
\"pfirTxMagCompNb\": [ { \
1314
\"numCoeff\": 13, \
1315
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1316
}, { \
1317
\"numCoeff\": 13, \
1318
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1319
} ], \
1320
\"pfirRxMagCompNb\": [ { \
1321
\"numCoeff\": 13, \
1322
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1323
}, { \
1324
\"numCoeff\": 13, \
1325
\"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1326
} ] \
1327
} \
1328
}"
;
json_profile
const char * json_profile
Definition
Navassa_CMOS_profile.h:1
projects
adrv9001
src
app
Navassa_CMOS_profile.h
Copyright © 2024
Analog Devices Inc.
. All Rights Reserved.
