no-OS
Navassa_LVDS_profile.h
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1 const char *json_profile = "{ \
2  \"clocks\": { \
3  \"deviceClock_kHz\": 38400, \
4  \"clkPllVcoFreq_daHz\": 884736000, \
5  \"clkPllHsDiv\": 0, \
6  \"clkPllMode\": 0, \
7  \"clk1105Div\": 2, \
8  \"armClkDiv\": 6, \
9  \"armPowerSavingClkDiv\": 1, \
10  \"refClockOutEnable\": true, \
11  \"auxPllPower\": 2, \
12  \"clkPllPower\": 2, \
13  \"padRefClkDrv\": 0, \
14  \"extLo1OutFreq_kHz\": 0, \
15  \"extLo2OutFreq_kHz\": 0, \
16  \"rfPll1LoMode\": 0, \
17  \"rfPll2LoMode\": 0, \
18  \"ext1LoType\": 0, \
19  \"ext2LoType\": 0, \
20  \"rx1RfInputSel\": 0, \
21  \"rx2RfInputSel\": 0, \
22  \"extLo1Divider\": 2, \
23  \"extLo2Divider\": 2, \
24  \"rfPllPhaseSyncMode\": 0, \
25  \"rx1LoSelect\": 2, \
26  \"rx2LoSelect\": 2, \
27  \"tx1LoSelect\": 1, \
28  \"tx2LoSelect\": 1, \
29  \"rx1LoDivMode\": 1, \
30  \"rx2LoDivMode\": 1, \
31  \"tx1LoDivMode\": 1, \
32  \"tx2LoDivMode\": 1, \
33  \"loGen1Select\": 1, \
34  \"loGen2Select\": 1 \
35  }, \
36  \"rx\": { \
37  \"rxInitChannelMask\": 195, \
38  \"rxChannelCfg\": [ { \
39  \"profile\": { \
40  \"primarySigBandwidth_Hz\": 9000000, \
41  \"rxOutputRate_Hz\": 15360000, \
42  \"rxInterfaceSampleRate_Hz\": 15360000, \
43  \"rxOffsetLo_kHz\": 0, \
44  \"rxNcoEnable\": false, \
45  \"outputSignaling\": 0, \
46  \"filterOrder\": 1, \
47  \"filterOrderLp\": 1, \
48  \"hpAdcCorner\": 20000000, \
49  \"lpAdcCorner\": 0, \
50  \"adcClk_kHz\": 2211840, \
51  \"rxCorner3dB_kHz\": 10000, \
52  \"rxCorner3dBLp_kHz\": 10000, \
53  \"tiaPower\": 2, \
54  \"tiaPowerLp\": 2, \
55  \"channelType\": 1, \
56  \"adcType\": 1, \
57  \"lpAdcCalMode\": 0, \
58  \"gainTableType\": 0, \
59  \"rxDpProfile\": { \
60  \"rxNbDecTop\": { \
61  \"scicBlk23En\": 0, \
62  \"scicBlk23DivFactor\": 1, \
63  \"scicBlk23LowRippleEn\": 0, \
64  \"decBy2Blk35En\": 0, \
65  \"decBy2Blk37En\": 0, \
66  \"decBy2Blk39En\": 0, \
67  \"decBy2Blk41En\": 0, \
68  \"decBy2Blk43En\": 0, \
69  \"decBy3Blk45En\": 0, \
70  \"decBy2Blk47En\": 0 \
71  }, \
72  \"rxWbDecTop\": { \
73  \"decBy2Blk25En\": 0, \
74  \"decBy2Blk27En\": 0, \
75  \"decBy2Blk29En\": 0, \
76  \"decBy2Blk31En\": 1, \
77  \"decBy2Blk33En\": 1, \
78  \"wbLpfBlk33p1En\": 0 \
79  }, \
80  \"rxDecTop\": { \
81  \"decBy3Blk15En\": 1, \
82  \"decBy2Hb3Blk17p1En\": 0, \
83  \"decBy2Hb4Blk17p2En\": 0, \
84  \"decBy2Hb5Blk19p1En\": 0, \
85  \"decBy2Hb6Blk19p2En\": 0 \
86  }, \
87  \"rxSincHBTop\": { \
88  \"sincGainMux\": 1, \
89  \"sincMux\": 4, \
90  \"hbMux\": 4, \
91  \"isGainCompEnabled\": 0, \
92  \"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
93  \"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
94  }, \
95  \"rxNbDem\": { \
96  \"dpInFifo\": { \
97  \"dpInFifoEn\": 0, \
98  \"dpInFifoMode\": 0, \
99  \"dpInFifoTestDataSel\": 0 \
100  }, \
101  \"rxNbNco\": { \
102  \"rxNbNcoEn\": 1, \
103  \"rxNbNcoConfig\": { \
104  \"freq\": 0, \
105  \"sampleFreq\": 15360000, \
106  \"phase\": 0, \
107  \"realOut\": 0 \
108  } \
109  }, \
110  \"rxWbNbCompPFir\": { \
111  \"bankSel\": 0, \
112  \"rxWbNbCompPFirInMuxSel\": 0, \
113  \"rxWbNbCompPFirEn\": 1 \
114  }, \
115  \"resamp\": { \
116  \"rxResampEn\": 0, \
117  \"resampPhaseI\": 0, \
118  \"resampPhaseQ\": 0 \
119  }, \
120  \"gsOutMuxSel\": 1, \
121  \"rxOutSel\": 0, \
122  \"rxRoundMode\": 0, \
123  \"dpArmSel\": 0 \
124  } \
125  }, \
126  \"lnaConfig\": { \
127  \"externalLnaPresent\": false, \
128  \"gpioSourceSel\": 0, \
129  \"externalLnaPinSel\": 0, \
130  \"settlingDelay\": 0, \
131  \"numberLnaGainSteps\": 0, \
132  \"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
133  \"lnaDigitalGainDelay\": 0, \
134  \"minGainIndex\": 0 \
135  }, \
136  \"rxSsiConfig\": { \
137  \"ssiType\": 2, \
138  \"ssiDataFormatSel\": 4, \
139  \"numLaneSel\": 1, \
140  \"strobeType\": 0, \
141  \"lsbFirst\": 0, \
142  \"qFirst\": 0, \
143  \"txRefClockPin\": 0, \
144  \"lvdsIBitInversion\": false, \
145  \"lvdsQBitInversion\": false, \
146  \"lvdsStrobeBitInversion\": false, \
147  \"lvdsUseLsbIn12bitMode\": 0, \
148  \"lvdsRxClkInversionEn\": false, \
149  \"cmosDdrPosClkEn\": false, \
150  \"cmosClkInversionEn\": false, \
151  \"ddrEn\": true, \
152  \"rxMaskStrobeEn\": false \
153  } \
154  } \
155  }, { \
156  \"profile\": { \
157  \"primarySigBandwidth_Hz\": 9000000, \
158  \"rxOutputRate_Hz\": 15360000, \
159  \"rxInterfaceSampleRate_Hz\": 15360000, \
160  \"rxOffsetLo_kHz\": 0, \
161  \"rxNcoEnable\": false, \
162  \"outputSignaling\": 0, \
163  \"filterOrder\": 1, \
164  \"filterOrderLp\": 1, \
165  \"hpAdcCorner\": 20000000, \
166  \"lpAdcCorner\": 0, \
167  \"adcClk_kHz\": 2211840, \
168  \"rxCorner3dB_kHz\": 10000, \
169  \"rxCorner3dBLp_kHz\": 10000, \
170  \"tiaPower\": 2, \
171  \"tiaPowerLp\": 2, \
172  \"channelType\": 2, \
173  \"adcType\": 1, \
174  \"lpAdcCalMode\": 0, \
175  \"gainTableType\": 0, \
176  \"rxDpProfile\": { \
177  \"rxNbDecTop\": { \
178  \"scicBlk23En\": 0, \
179  \"scicBlk23DivFactor\": 1, \
180  \"scicBlk23LowRippleEn\": 0, \
181  \"decBy2Blk35En\": 0, \
182  \"decBy2Blk37En\": 0, \
183  \"decBy2Blk39En\": 0, \
184  \"decBy2Blk41En\": 0, \
185  \"decBy2Blk43En\": 0, \
186  \"decBy3Blk45En\": 0, \
187  \"decBy2Blk47En\": 0 \
188  }, \
189  \"rxWbDecTop\": { \
190  \"decBy2Blk25En\": 0, \
191  \"decBy2Blk27En\": 0, \
192  \"decBy2Blk29En\": 0, \
193  \"decBy2Blk31En\": 1, \
194  \"decBy2Blk33En\": 1, \
195  \"wbLpfBlk33p1En\": 0 \
196  }, \
197  \"rxDecTop\": { \
198  \"decBy3Blk15En\": 1, \
199  \"decBy2Hb3Blk17p1En\": 0, \
200  \"decBy2Hb4Blk17p2En\": 0, \
201  \"decBy2Hb5Blk19p1En\": 0, \
202  \"decBy2Hb6Blk19p2En\": 0 \
203  }, \
204  \"rxSincHBTop\": { \
205  \"sincGainMux\": 1, \
206  \"sincMux\": 4, \
207  \"hbMux\": 4, \
208  \"isGainCompEnabled\": 0, \
209  \"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
210  \"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
211  }, \
212  \"rxNbDem\": { \
213  \"dpInFifo\": { \
214  \"dpInFifoEn\": 0, \
215  \"dpInFifoMode\": 0, \
216  \"dpInFifoTestDataSel\": 0 \
217  }, \
218  \"rxNbNco\": { \
219  \"rxNbNcoEn\": 1, \
220  \"rxNbNcoConfig\": { \
221  \"freq\": 0, \
222  \"sampleFreq\": 15360000, \
223  \"phase\": 0, \
224  \"realOut\": 0 \
225  } \
226  }, \
227  \"rxWbNbCompPFir\": { \
228  \"bankSel\": 2, \
229  \"rxWbNbCompPFirInMuxSel\": 0, \
230  \"rxWbNbCompPFirEn\": 1 \
231  }, \
232  \"resamp\": { \
233  \"rxResampEn\": 0, \
234  \"resampPhaseI\": 0, \
235  \"resampPhaseQ\": 0 \
236  }, \
237  \"gsOutMuxSel\": 1, \
238  \"rxOutSel\": 0, \
239  \"rxRoundMode\": 0, \
240  \"dpArmSel\": 0 \
241  } \
242  }, \
243  \"lnaConfig\": { \
244  \"externalLnaPresent\": false, \
245  \"gpioSourceSel\": 0, \
246  \"externalLnaPinSel\": 0, \
247  \"settlingDelay\": 0, \
248  \"numberLnaGainSteps\": 0, \
249  \"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
250  \"lnaDigitalGainDelay\": 0, \
251  \"minGainIndex\": 0 \
252  }, \
253  \"rxSsiConfig\": { \
254  \"ssiType\": 2, \
255  \"ssiDataFormatSel\": 4, \
256  \"numLaneSel\": 1, \
257  \"strobeType\": 0, \
258  \"lsbFirst\": 0, \
259  \"qFirst\": 0, \
260  \"txRefClockPin\": 0, \
261  \"lvdsIBitInversion\": false, \
262  \"lvdsQBitInversion\": false, \
263  \"lvdsStrobeBitInversion\": false, \
264  \"lvdsUseLsbIn12bitMode\": 0, \
265  \"lvdsRxClkInversionEn\": false, \
266  \"cmosDdrPosClkEn\": false, \
267  \"cmosClkInversionEn\": false, \
268  \"ddrEn\": true, \
269  \"rxMaskStrobeEn\": false \
270  } \
271  } \
272  }, { \
273  \"profile\": { \
274  \"primarySigBandwidth_Hz\": 12500, \
275  \"rxOutputRate_Hz\": 0, \
276  \"rxInterfaceSampleRate_Hz\": 0, \
277  \"rxOffsetLo_kHz\": 0, \
278  \"rxNcoEnable\": false, \
279  \"outputSignaling\": 0, \
280  \"filterOrder\": 1, \
281  \"filterOrderLp\": 1, \
282  \"hpAdcCorner\": 0, \
283  \"lpAdcCorner\": 0, \
284  \"adcClk_kHz\": 0, \
285  \"rxCorner3dB_kHz\": 0, \
286  \"rxCorner3dBLp_kHz\": 0, \
287  \"tiaPower\": 2, \
288  \"tiaPowerLp\": 2, \
289  \"channelType\": 0, \
290  \"adcType\": 1, \
291  \"lpAdcCalMode\": 0, \
292  \"gainTableType\": 0, \
293  \"rxDpProfile\": { \
294  \"rxNbDecTop\": { \
295  \"scicBlk23En\": 0, \
296  \"scicBlk23DivFactor\": 0, \
297  \"scicBlk23LowRippleEn\": 0, \
298  \"decBy2Blk35En\": 0, \
299  \"decBy2Blk37En\": 0, \
300  \"decBy2Blk39En\": 0, \
301  \"decBy2Blk41En\": 0, \
302  \"decBy2Blk43En\": 0, \
303  \"decBy3Blk45En\": 0, \
304  \"decBy2Blk47En\": 0 \
305  }, \
306  \"rxWbDecTop\": { \
307  \"decBy2Blk25En\": 0, \
308  \"decBy2Blk27En\": 0, \
309  \"decBy2Blk29En\": 0, \
310  \"decBy2Blk31En\": 0, \
311  \"decBy2Blk33En\": 0, \
312  \"wbLpfBlk33p1En\": 0 \
313  }, \
314  \"rxDecTop\": { \
315  \"decBy3Blk15En\": 0, \
316  \"decBy2Hb3Blk17p1En\": 0, \
317  \"decBy2Hb4Blk17p2En\": 0, \
318  \"decBy2Hb5Blk19p1En\": 0, \
319  \"decBy2Hb6Blk19p2En\": 0 \
320  }, \
321  \"rxSincHBTop\": { \
322  \"sincGainMux\": 1, \
323  \"sincMux\": 0, \
324  \"hbMux\": 4, \
325  \"isGainCompEnabled\": 0, \
326  \"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
327  \"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
328  }, \
329  \"rxNbDem\": { \
330  \"dpInFifo\": { \
331  \"dpInFifoEn\": 0, \
332  \"dpInFifoMode\": 0, \
333  \"dpInFifoTestDataSel\": 0 \
334  }, \
335  \"rxNbNco\": { \
336  \"rxNbNcoEn\": 0, \
337  \"rxNbNcoConfig\": { \
338  \"freq\": 0, \
339  \"sampleFreq\": 0, \
340  \"phase\": 0, \
341  \"realOut\": 0 \
342  } \
343  }, \
344  \"rxWbNbCompPFir\": { \
345  \"bankSel\": 0, \
346  \"rxWbNbCompPFirInMuxSel\": 0, \
347  \"rxWbNbCompPFirEn\": 0 \
348  }, \
349  \"resamp\": { \
350  \"rxResampEn\": 0, \
351  \"resampPhaseI\": 0, \
352  \"resampPhaseQ\": 0 \
353  }, \
354  \"gsOutMuxSel\": 1, \
355  \"rxOutSel\": 0, \
356  \"rxRoundMode\": 0, \
357  \"dpArmSel\": 0 \
358  } \
359  }, \
360  \"lnaConfig\": { \
361  \"externalLnaPresent\": false, \
362  \"gpioSourceSel\": 0, \
363  \"externalLnaPinSel\": 0, \
364  \"settlingDelay\": 0, \
365  \"numberLnaGainSteps\": 0, \
366  \"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
367  \"lnaDigitalGainDelay\": 0, \
368  \"minGainIndex\": 0 \
369  }, \
370  \"rxSsiConfig\": { \
371  \"ssiType\": 0, \
372  \"ssiDataFormatSel\": 0, \
373  \"numLaneSel\": 0, \
374  \"strobeType\": 0, \
375  \"lsbFirst\": 0, \
376  \"qFirst\": 0, \
377  \"txRefClockPin\": 0, \
378  \"lvdsIBitInversion\": false, \
379  \"lvdsQBitInversion\": false, \
380  \"lvdsStrobeBitInversion\": false, \
381  \"lvdsUseLsbIn12bitMode\": 0, \
382  \"lvdsRxClkInversionEn\": false, \
383  \"cmosDdrPosClkEn\": false, \
384  \"cmosClkInversionEn\": false, \
385  \"ddrEn\": false, \
386  \"rxMaskStrobeEn\": false \
387  } \
388  } \
389  }, { \
390  \"profile\": { \
391  \"primarySigBandwidth_Hz\": 12500, \
392  \"rxOutputRate_Hz\": 0, \
393  \"rxInterfaceSampleRate_Hz\": 0, \
394  \"rxOffsetLo_kHz\": 0, \
395  \"rxNcoEnable\": false, \
396  \"outputSignaling\": 0, \
397  \"filterOrder\": 1, \
398  \"filterOrderLp\": 1, \
399  \"hpAdcCorner\": 0, \
400  \"lpAdcCorner\": 0, \
401  \"adcClk_kHz\": 0, \
402  \"rxCorner3dB_kHz\": 0, \
403  \"rxCorner3dBLp_kHz\": 0, \
404  \"tiaPower\": 2, \
405  \"tiaPowerLp\": 2, \
406  \"channelType\": 0, \
407  \"adcType\": 1, \
408  \"lpAdcCalMode\": 0, \
409  \"gainTableType\": 0, \
410  \"rxDpProfile\": { \
411  \"rxNbDecTop\": { \
412  \"scicBlk23En\": 0, \
413  \"scicBlk23DivFactor\": 0, \
414  \"scicBlk23LowRippleEn\": 0, \
415  \"decBy2Blk35En\": 0, \
416  \"decBy2Blk37En\": 0, \
417  \"decBy2Blk39En\": 0, \
418  \"decBy2Blk41En\": 0, \
419  \"decBy2Blk43En\": 0, \
420  \"decBy3Blk45En\": 0, \
421  \"decBy2Blk47En\": 0 \
422  }, \
423  \"rxWbDecTop\": { \
424  \"decBy2Blk25En\": 0, \
425  \"decBy2Blk27En\": 0, \
426  \"decBy2Blk29En\": 0, \
427  \"decBy2Blk31En\": 0, \
428  \"decBy2Blk33En\": 0, \
429  \"wbLpfBlk33p1En\": 0 \
430  }, \
431  \"rxDecTop\": { \
432  \"decBy3Blk15En\": 0, \
433  \"decBy2Hb3Blk17p1En\": 0, \
434  \"decBy2Hb4Blk17p2En\": 0, \
435  \"decBy2Hb5Blk19p1En\": 0, \
436  \"decBy2Hb6Blk19p2En\": 0 \
437  }, \
438  \"rxSincHBTop\": { \
439  \"sincGainMux\": 1, \
440  \"sincMux\": 0, \
441  \"hbMux\": 4, \
442  \"isGainCompEnabled\": 0, \
443  \"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
444  \"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
445  }, \
446  \"rxNbDem\": { \
447  \"dpInFifo\": { \
448  \"dpInFifoEn\": 0, \
449  \"dpInFifoMode\": 0, \
450  \"dpInFifoTestDataSel\": 0 \
451  }, \
452  \"rxNbNco\": { \
453  \"rxNbNcoEn\": 0, \
454  \"rxNbNcoConfig\": { \
455  \"freq\": 0, \
456  \"sampleFreq\": 0, \
457  \"phase\": 0, \
458  \"realOut\": 0 \
459  } \
460  }, \
461  \"rxWbNbCompPFir\": { \
462  \"bankSel\": 0, \
463  \"rxWbNbCompPFirInMuxSel\": 0, \
464  \"rxWbNbCompPFirEn\": 0 \
465  }, \
466  \"resamp\": { \
467  \"rxResampEn\": 0, \
468  \"resampPhaseI\": 0, \
469  \"resampPhaseQ\": 0 \
470  }, \
471  \"gsOutMuxSel\": 1, \
472  \"rxOutSel\": 0, \
473  \"rxRoundMode\": 0, \
474  \"dpArmSel\": 0 \
475  } \
476  }, \
477  \"lnaConfig\": { \
478  \"externalLnaPresent\": false, \
479  \"gpioSourceSel\": 0, \
480  \"externalLnaPinSel\": 0, \
481  \"settlingDelay\": 0, \
482  \"numberLnaGainSteps\": 0, \
483  \"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
484  \"lnaDigitalGainDelay\": 0, \
485  \"minGainIndex\": 0 \
486  }, \
487  \"rxSsiConfig\": { \
488  \"ssiType\": 0, \
489  \"ssiDataFormatSel\": 0, \
490  \"numLaneSel\": 0, \
491  \"strobeType\": 0, \
492  \"lsbFirst\": 0, \
493  \"qFirst\": 0, \
494  \"txRefClockPin\": 0, \
495  \"lvdsIBitInversion\": false, \
496  \"lvdsQBitInversion\": false, \
497  \"lvdsStrobeBitInversion\": false, \
498  \"lvdsUseLsbIn12bitMode\": 0, \
499  \"lvdsRxClkInversionEn\": false, \
500  \"cmosDdrPosClkEn\": false, \
501  \"cmosClkInversionEn\": false, \
502  \"ddrEn\": false, \
503  \"rxMaskStrobeEn\": false \
504  } \
505  } \
506  }, { \
507  \"profile\": { \
508  \"primarySigBandwidth_Hz\": 9000000, \
509  \"rxOutputRate_Hz\": 15360000, \
510  \"rxInterfaceSampleRate_Hz\": 15360000, \
511  \"rxOffsetLo_kHz\": 0, \
512  \"rxNcoEnable\": false, \
513  \"outputSignaling\": 0, \
514  \"filterOrder\": 1, \
515  \"filterOrderLp\": 1, \
516  \"hpAdcCorner\": 50000000, \
517  \"lpAdcCorner\": 0, \
518  \"adcClk_kHz\": 2211840, \
519  \"rxCorner3dB_kHz\": 100000, \
520  \"rxCorner3dBLp_kHz\": 100000, \
521  \"tiaPower\": 2, \
522  \"tiaPowerLp\": 2, \
523  \"channelType\": 64, \
524  \"adcType\": 1, \
525  \"lpAdcCalMode\": 0, \
526  \"gainTableType\": 0, \
527  \"rxDpProfile\": { \
528  \"rxNbDecTop\": { \
529  \"scicBlk23En\": 0, \
530  \"scicBlk23DivFactor\": 1, \
531  \"scicBlk23LowRippleEn\": 0, \
532  \"decBy2Blk35En\": 0, \
533  \"decBy2Blk37En\": 0, \
534  \"decBy2Blk39En\": 0, \
535  \"decBy2Blk41En\": 0, \
536  \"decBy2Blk43En\": 0, \
537  \"decBy3Blk45En\": 0, \
538  \"decBy2Blk47En\": 0 \
539  }, \
540  \"rxWbDecTop\": { \
541  \"decBy2Blk25En\": 0, \
542  \"decBy2Blk27En\": 0, \
543  \"decBy2Blk29En\": 0, \
544  \"decBy2Blk31En\": 1, \
545  \"decBy2Blk33En\": 1, \
546  \"wbLpfBlk33p1En\": 0 \
547  }, \
548  \"rxDecTop\": { \
549  \"decBy3Blk15En\": 1, \
550  \"decBy2Hb3Blk17p1En\": 0, \
551  \"decBy2Hb4Blk17p2En\": 0, \
552  \"decBy2Hb5Blk19p1En\": 0, \
553  \"decBy2Hb6Blk19p2En\": 0 \
554  }, \
555  \"rxSincHBTop\": { \
556  \"sincGainMux\": 1, \
557  \"sincMux\": 4, \
558  \"hbMux\": 2, \
559  \"isGainCompEnabled\": 0, \
560  \"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
561  \"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
562  }, \
563  \"rxNbDem\": { \
564  \"dpInFifo\": { \
565  \"dpInFifoEn\": 0, \
566  \"dpInFifoMode\": 0, \
567  \"dpInFifoTestDataSel\": 0 \
568  }, \
569  \"rxNbNco\": { \
570  \"rxNbNcoEn\": 0, \
571  \"rxNbNcoConfig\": { \
572  \"freq\": 0, \
573  \"sampleFreq\": 0, \
574  \"phase\": 0, \
575  \"realOut\": 0 \
576  } \
577  }, \
578  \"rxWbNbCompPFir\": { \
579  \"bankSel\": 1, \
580  \"rxWbNbCompPFirInMuxSel\": 0, \
581  \"rxWbNbCompPFirEn\": 0 \
582  }, \
583  \"resamp\": { \
584  \"rxResampEn\": 0, \
585  \"resampPhaseI\": 0, \
586  \"resampPhaseQ\": 0 \
587  }, \
588  \"gsOutMuxSel\": 1, \
589  \"rxOutSel\": 0, \
590  \"rxRoundMode\": 0, \
591  \"dpArmSel\": 0 \
592  } \
593  }, \
594  \"lnaConfig\": { \
595  \"externalLnaPresent\": false, \
596  \"gpioSourceSel\": 0, \
597  \"externalLnaPinSel\": 0, \
598  \"settlingDelay\": 0, \
599  \"numberLnaGainSteps\": 0, \
600  \"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
601  \"lnaDigitalGainDelay\": 0, \
602  \"minGainIndex\": 0 \
603  }, \
604  \"rxSsiConfig\": { \
605  \"ssiType\": 2, \
606  \"ssiDataFormatSel\": 4, \
607  \"numLaneSel\": 1, \
608  \"strobeType\": 0, \
609  \"lsbFirst\": 0, \
610  \"qFirst\": 0, \
611  \"txRefClockPin\": 0, \
612  \"lvdsIBitInversion\": false, \
613  \"lvdsQBitInversion\": false, \
614  \"lvdsStrobeBitInversion\": false, \
615  \"lvdsUseLsbIn12bitMode\": 0, \
616  \"lvdsRxClkInversionEn\": false, \
617  \"cmosDdrPosClkEn\": false, \
618  \"cmosClkInversionEn\": false, \
619  \"ddrEn\": true, \
620  \"rxMaskStrobeEn\": false \
621  } \
622  } \
623  }, { \
624  \"profile\": { \
625  \"primarySigBandwidth_Hz\": 9000000, \
626  \"rxOutputRate_Hz\": 15360000, \
627  \"rxInterfaceSampleRate_Hz\": 15360000, \
628  \"rxOffsetLo_kHz\": 0, \
629  \"rxNcoEnable\": false, \
630  \"outputSignaling\": 0, \
631  \"filterOrder\": 1, \
632  \"filterOrderLp\": 1, \
633  \"hpAdcCorner\": 50000000, \
634  \"lpAdcCorner\": 0, \
635  \"adcClk_kHz\": 2211840, \
636  \"rxCorner3dB_kHz\": 100000, \
637  \"rxCorner3dBLp_kHz\": 100000, \
638  \"tiaPower\": 2, \
639  \"tiaPowerLp\": 2, \
640  \"channelType\": 128, \
641  \"adcType\": 1, \
642  \"lpAdcCalMode\": 0, \
643  \"gainTableType\": 0, \
644  \"rxDpProfile\": { \
645  \"rxNbDecTop\": { \
646  \"scicBlk23En\": 0, \
647  \"scicBlk23DivFactor\": 1, \
648  \"scicBlk23LowRippleEn\": 0, \
649  \"decBy2Blk35En\": 0, \
650  \"decBy2Blk37En\": 0, \
651  \"decBy2Blk39En\": 0, \
652  \"decBy2Blk41En\": 0, \
653  \"decBy2Blk43En\": 0, \
654  \"decBy3Blk45En\": 0, \
655  \"decBy2Blk47En\": 0 \
656  }, \
657  \"rxWbDecTop\": { \
658  \"decBy2Blk25En\": 0, \
659  \"decBy2Blk27En\": 0, \
660  \"decBy2Blk29En\": 0, \
661  \"decBy2Blk31En\": 1, \
662  \"decBy2Blk33En\": 1, \
663  \"wbLpfBlk33p1En\": 0 \
664  }, \
665  \"rxDecTop\": { \
666  \"decBy3Blk15En\": 1, \
667  \"decBy2Hb3Blk17p1En\": 0, \
668  \"decBy2Hb4Blk17p2En\": 0, \
669  \"decBy2Hb5Blk19p1En\": 0, \
670  \"decBy2Hb6Blk19p2En\": 0 \
671  }, \
672  \"rxSincHBTop\": { \
673  \"sincGainMux\": 1, \
674  \"sincMux\": 4, \
675  \"hbMux\": 2, \
676  \"isGainCompEnabled\": 0, \
677  \"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
678  \"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
679  }, \
680  \"rxNbDem\": { \
681  \"dpInFifo\": { \
682  \"dpInFifoEn\": 0, \
683  \"dpInFifoMode\": 0, \
684  \"dpInFifoTestDataSel\": 0 \
685  }, \
686  \"rxNbNco\": { \
687  \"rxNbNcoEn\": 0, \
688  \"rxNbNcoConfig\": { \
689  \"freq\": 0, \
690  \"sampleFreq\": 0, \
691  \"phase\": 0, \
692  \"realOut\": 0 \
693  } \
694  }, \
695  \"rxWbNbCompPFir\": { \
696  \"bankSel\": 3, \
697  \"rxWbNbCompPFirInMuxSel\": 0, \
698  \"rxWbNbCompPFirEn\": 0 \
699  }, \
700  \"resamp\": { \
701  \"rxResampEn\": 0, \
702  \"resampPhaseI\": 0, \
703  \"resampPhaseQ\": 0 \
704  }, \
705  \"gsOutMuxSel\": 1, \
706  \"rxOutSel\": 0, \
707  \"rxRoundMode\": 0, \
708  \"dpArmSel\": 0 \
709  } \
710  }, \
711  \"lnaConfig\": { \
712  \"externalLnaPresent\": false, \
713  \"gpioSourceSel\": 0, \
714  \"externalLnaPinSel\": 0, \
715  \"settlingDelay\": 0, \
716  \"numberLnaGainSteps\": 0, \
717  \"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
718  \"lnaDigitalGainDelay\": 0, \
719  \"minGainIndex\": 0 \
720  }, \
721  \"rxSsiConfig\": { \
722  \"ssiType\": 2, \
723  \"ssiDataFormatSel\": 4, \
724  \"numLaneSel\": 1, \
725  \"strobeType\": 0, \
726  \"lsbFirst\": 0, \
727  \"qFirst\": 0, \
728  \"txRefClockPin\": 0, \
729  \"lvdsIBitInversion\": false, \
730  \"lvdsQBitInversion\": false, \
731  \"lvdsStrobeBitInversion\": false, \
732  \"lvdsUseLsbIn12bitMode\": 0, \
733  \"lvdsRxClkInversionEn\": false, \
734  \"cmosDdrPosClkEn\": false, \
735  \"cmosClkInversionEn\": false, \
736  \"ddrEn\": true, \
737  \"rxMaskStrobeEn\": false \
738  } \
739  } \
740  }, { \
741  \"profile\": { \
742  \"primarySigBandwidth_Hz\": 12500, \
743  \"rxOutputRate_Hz\": 0, \
744  \"rxInterfaceSampleRate_Hz\": 0, \
745  \"rxOffsetLo_kHz\": 0, \
746  \"rxNcoEnable\": false, \
747  \"outputSignaling\": 0, \
748  \"filterOrder\": 1, \
749  \"filterOrderLp\": 1, \
750  \"hpAdcCorner\": 0, \
751  \"lpAdcCorner\": 0, \
752  \"adcClk_kHz\": 0, \
753  \"rxCorner3dB_kHz\": 0, \
754  \"rxCorner3dBLp_kHz\": 0, \
755  \"tiaPower\": 2, \
756  \"tiaPowerLp\": 2, \
757  \"channelType\": 0, \
758  \"adcType\": 1, \
759  \"lpAdcCalMode\": 0, \
760  \"gainTableType\": 0, \
761  \"rxDpProfile\": { \
762  \"rxNbDecTop\": { \
763  \"scicBlk23En\": 0, \
764  \"scicBlk23DivFactor\": 0, \
765  \"scicBlk23LowRippleEn\": 0, \
766  \"decBy2Blk35En\": 0, \
767  \"decBy2Blk37En\": 0, \
768  \"decBy2Blk39En\": 0, \
769  \"decBy2Blk41En\": 0, \
770  \"decBy2Blk43En\": 0, \
771  \"decBy3Blk45En\": 0, \
772  \"decBy2Blk47En\": 0 \
773  }, \
774  \"rxWbDecTop\": { \
775  \"decBy2Blk25En\": 0, \
776  \"decBy2Blk27En\": 0, \
777  \"decBy2Blk29En\": 0, \
778  \"decBy2Blk31En\": 0, \
779  \"decBy2Blk33En\": 0, \
780  \"wbLpfBlk33p1En\": 0 \
781  }, \
782  \"rxDecTop\": { \
783  \"decBy3Blk15En\": 0, \
784  \"decBy2Hb3Blk17p1En\": 0, \
785  \"decBy2Hb4Blk17p2En\": 0, \
786  \"decBy2Hb5Blk19p1En\": 0, \
787  \"decBy2Hb6Blk19p2En\": 0 \
788  }, \
789  \"rxSincHBTop\": { \
790  \"sincGainMux\": 1, \
791  \"sincMux\": 0, \
792  \"hbMux\": 4, \
793  \"isGainCompEnabled\": 0, \
794  \"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
795  \"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
796  }, \
797  \"rxNbDem\": { \
798  \"dpInFifo\": { \
799  \"dpInFifoEn\": 0, \
800  \"dpInFifoMode\": 0, \
801  \"dpInFifoTestDataSel\": 0 \
802  }, \
803  \"rxNbNco\": { \
804  \"rxNbNcoEn\": 0, \
805  \"rxNbNcoConfig\": { \
806  \"freq\": 0, \
807  \"sampleFreq\": 0, \
808  \"phase\": 0, \
809  \"realOut\": 0 \
810  } \
811  }, \
812  \"rxWbNbCompPFir\": { \
813  \"bankSel\": 0, \
814  \"rxWbNbCompPFirInMuxSel\": 0, \
815  \"rxWbNbCompPFirEn\": 0 \
816  }, \
817  \"resamp\": { \
818  \"rxResampEn\": 0, \
819  \"resampPhaseI\": 0, \
820  \"resampPhaseQ\": 0 \
821  }, \
822  \"gsOutMuxSel\": 1, \
823  \"rxOutSel\": 0, \
824  \"rxRoundMode\": 0, \
825  \"dpArmSel\": 0 \
826  } \
827  }, \
828  \"lnaConfig\": { \
829  \"externalLnaPresent\": false, \
830  \"gpioSourceSel\": 0, \
831  \"externalLnaPinSel\": 0, \
832  \"settlingDelay\": 0, \
833  \"numberLnaGainSteps\": 0, \
834  \"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
835  \"lnaDigitalGainDelay\": 0, \
836  \"minGainIndex\": 0 \
837  }, \
838  \"rxSsiConfig\": { \
839  \"ssiType\": 0, \
840  \"ssiDataFormatSel\": 0, \
841  \"numLaneSel\": 0, \
842  \"strobeType\": 0, \
843  \"lsbFirst\": 0, \
844  \"qFirst\": 0, \
845  \"txRefClockPin\": 0, \
846  \"lvdsIBitInversion\": false, \
847  \"lvdsQBitInversion\": false, \
848  \"lvdsStrobeBitInversion\": false, \
849  \"lvdsUseLsbIn12bitMode\": 0, \
850  \"lvdsRxClkInversionEn\": false, \
851  \"cmosDdrPosClkEn\": false, \
852  \"cmosClkInversionEn\": false, \
853  \"ddrEn\": false, \
854  \"rxMaskStrobeEn\": false \
855  } \
856  } \
857  }, { \
858  \"profile\": { \
859  \"primarySigBandwidth_Hz\": 12500, \
860  \"rxOutputRate_Hz\": 0, \
861  \"rxInterfaceSampleRate_Hz\": 0, \
862  \"rxOffsetLo_kHz\": 0, \
863  \"rxNcoEnable\": false, \
864  \"outputSignaling\": 0, \
865  \"filterOrder\": 1, \
866  \"filterOrderLp\": 1, \
867  \"hpAdcCorner\": 0, \
868  \"lpAdcCorner\": 0, \
869  \"adcClk_kHz\": 0, \
870  \"rxCorner3dB_kHz\": 0, \
871  \"rxCorner3dBLp_kHz\": 0, \
872  \"tiaPower\": 2, \
873  \"tiaPowerLp\": 2, \
874  \"channelType\": 0, \
875  \"adcType\": 1, \
876  \"lpAdcCalMode\": 0, \
877  \"gainTableType\": 0, \
878  \"rxDpProfile\": { \
879  \"rxNbDecTop\": { \
880  \"scicBlk23En\": 0, \
881  \"scicBlk23DivFactor\": 0, \
882  \"scicBlk23LowRippleEn\": 0, \
883  \"decBy2Blk35En\": 0, \
884  \"decBy2Blk37En\": 0, \
885  \"decBy2Blk39En\": 0, \
886  \"decBy2Blk41En\": 0, \
887  \"decBy2Blk43En\": 0, \
888  \"decBy3Blk45En\": 0, \
889  \"decBy2Blk47En\": 0 \
890  }, \
891  \"rxWbDecTop\": { \
892  \"decBy2Blk25En\": 0, \
893  \"decBy2Blk27En\": 0, \
894  \"decBy2Blk29En\": 0, \
895  \"decBy2Blk31En\": 0, \
896  \"decBy2Blk33En\": 0, \
897  \"wbLpfBlk33p1En\": 0 \
898  }, \
899  \"rxDecTop\": { \
900  \"decBy3Blk15En\": 0, \
901  \"decBy2Hb3Blk17p1En\": 0, \
902  \"decBy2Hb4Blk17p2En\": 0, \
903  \"decBy2Hb5Blk19p1En\": 0, \
904  \"decBy2Hb6Blk19p2En\": 0 \
905  }, \
906  \"rxSincHBTop\": { \
907  \"sincGainMux\": 1, \
908  \"sincMux\": 0, \
909  \"hbMux\": 4, \
910  \"isGainCompEnabled\": 0, \
911  \"gainComp9GainI\": [ 16384, 16384, 16384, 16384, 16384, 16384 ], \
912  \"gainComp9GainQ\": [ 0, 0, 0, 0, 0, 0 ] \
913  }, \
914  \"rxNbDem\": { \
915  \"dpInFifo\": { \
916  \"dpInFifoEn\": 0, \
917  \"dpInFifoMode\": 0, \
918  \"dpInFifoTestDataSel\": 0 \
919  }, \
920  \"rxNbNco\": { \
921  \"rxNbNcoEn\": 0, \
922  \"rxNbNcoConfig\": { \
923  \"freq\": 0, \
924  \"sampleFreq\": 0, \
925  \"phase\": 0, \
926  \"realOut\": 0 \
927  } \
928  }, \
929  \"rxWbNbCompPFir\": { \
930  \"bankSel\": 0, \
931  \"rxWbNbCompPFirInMuxSel\": 0, \
932  \"rxWbNbCompPFirEn\": 0 \
933  }, \
934  \"resamp\": { \
935  \"rxResampEn\": 0, \
936  \"resampPhaseI\": 0, \
937  \"resampPhaseQ\": 0 \
938  }, \
939  \"gsOutMuxSel\": 1, \
940  \"rxOutSel\": 0, \
941  \"rxRoundMode\": 0, \
942  \"dpArmSel\": 0 \
943  } \
944  }, \
945  \"lnaConfig\": { \
946  \"externalLnaPresent\": false, \
947  \"gpioSourceSel\": 0, \
948  \"externalLnaPinSel\": 0, \
949  \"settlingDelay\": 0, \
950  \"numberLnaGainSteps\": 0, \
951  \"lnaGainSteps_mdB\": [ 0, 0, 0, 0 ], \
952  \"lnaDigitalGainDelay\": 0, \
953  \"minGainIndex\": 0 \
954  }, \
955  \"rxSsiConfig\": { \
956  \"ssiType\": 0, \
957  \"ssiDataFormatSel\": 0, \
958  \"numLaneSel\": 0, \
959  \"strobeType\": 0, \
960  \"lsbFirst\": 0, \
961  \"qFirst\": 0, \
962  \"txRefClockPin\": 0, \
963  \"lvdsIBitInversion\": false, \
964  \"lvdsQBitInversion\": false, \
965  \"lvdsStrobeBitInversion\": false, \
966  \"lvdsUseLsbIn12bitMode\": 0, \
967  \"lvdsRxClkInversionEn\": false, \
968  \"cmosDdrPosClkEn\": false, \
969  \"cmosClkInversionEn\": false, \
970  \"ddrEn\": false, \
971  \"rxMaskStrobeEn\": false \
972  } \
973  } \
974  } ] \
975  }, \
976  \"tx\": { \
977  \"txInitChannelMask\": 12, \
978  \"txProfile\": [ { \
979  \"primarySigBandwidth_Hz\": 9000000, \
980  \"txInputRate_Hz\": 15360000, \
981  \"txInterfaceSampleRate_Hz\": 15360000, \
982  \"txOffsetLo_kHz\": 0, \
983  \"validDataDelay\": 0, \
984  \"txBbf3dBCorner_kHz\": 50000, \
985  \"outputSignaling\": 0, \
986  \"txPdBiasCurrent\": 1, \
987  \"txPdGainEnable\": 0, \
988  \"txPrePdRealPole_kHz\": 1000000, \
989  \"txPostPdRealPole_kHz\": 530000, \
990  \"txBbfPower\": 2, \
991  \"txExtLoopBackType\": 0, \
992  \"txExtLoopBackForInitCal\": 0, \
993  \"txPeakLoopBackPower\": 0, \
994  \"frequencyDeviation_Hz\": 0, \
995  \"txDpProfile\": { \
996  \"txPreProc\": { \
997  \"txPreProcSymbol0\": 0, \
998  \"txPreProcSymbol1\": 0, \
999  \"txPreProcSymbol2\": 0, \
1000  \"txPreProcSymbol3\": 0, \
1001  \"txPreProcSymMapDivFactor\": 1, \
1002  \"txPreProcMode\": 1, \
1003  \"txPreProcWbNbPfirIBankSel\": 0, \
1004  \"txPreProcWbNbPfirQBankSel\": 1 \
1005  }, \
1006  \"txWbIntTop\": { \
1007  \"txInterpBy2Blk30En\": 0, \
1008  \"txInterpBy2Blk28En\": 0, \
1009  \"txInterpBy2Blk26En\": 0, \
1010  \"txInterpBy2Blk24En\": 1, \
1011  \"txInterpBy2Blk22En\": 1, \
1012  \"txWbLpfBlk22p1En\": 0 \
1013  }, \
1014  \"txNbIntTop\": { \
1015  \"txInterpBy2Blk20En\": 0, \
1016  \"txInterpBy2Blk18En\": 0, \
1017  \"txInterpBy2Blk16En\": 0, \
1018  \"txInterpBy2Blk14En\": 0, \
1019  \"txInterpBy2Blk12En\": 0, \
1020  \"txInterpBy3Blk10En\": 0, \
1021  \"txInterpBy2Blk8En\": 0, \
1022  \"txScicBlk32En\": 0, \
1023  \"txScicBlk32DivFactor\": 1 \
1024  }, \
1025  \"txIntTop\": { \
1026  \"interpBy3Blk44p1En\": 1, \
1027  \"sinc3Blk44En\": 0, \
1028  \"sinc2Blk42En\": 0, \
1029  \"interpBy3Blk40En\": 1, \
1030  \"interpBy2Blk38En\": 0, \
1031  \"interpBy2Blk36En\": 0 \
1032  }, \
1033  \"txIntTopFreqDevMap\": { \
1034  \"rrc2Frac\": 0, \
1035  \"mpll\": 0, \
1036  \"nchLsw\": 0, \
1037  \"nchMsb\": 0, \
1038  \"freqDevMapEn\": 0, \
1039  \"txRoundEn\": 1 \
1040  }, \
1041  \"txIqdmDuc\": { \
1042  \"iqdmDucMode\": 2, \
1043  \"iqdmDev\": 0, \
1044  \"iqdmDevOffset\": 0, \
1045  \"iqdmScalar\": 0, \
1046  \"iqdmThreshold\": 0, \
1047  \"iqdmNco\": { \
1048  \"freq\": 0, \
1049  \"sampleFreq\": 61440000, \
1050  \"phase\": 0, \
1051  \"realOut\": 0 \
1052  } \
1053  } \
1054  }, \
1055  \"txSsiConfig\": { \
1056  \"ssiType\": 2, \
1057  \"ssiDataFormatSel\": 4, \
1058  \"numLaneSel\": 1, \
1059  \"strobeType\": 0, \
1060  \"lsbFirst\": 0, \
1061  \"qFirst\": 0, \
1062  \"txRefClockPin\": 1, \
1063  \"lvdsIBitInversion\": false, \
1064  \"lvdsQBitInversion\": false, \
1065  \"lvdsStrobeBitInversion\": false, \
1066  \"lvdsUseLsbIn12bitMode\": 0, \
1067  \"lvdsRxClkInversionEn\": false, \
1068  \"cmosDdrPosClkEn\": false, \
1069  \"cmosClkInversionEn\": false, \
1070  \"ddrEn\": true, \
1071  \"rxMaskStrobeEn\": false \
1072  } \
1073  }, { \
1074  \"primarySigBandwidth_Hz\": 9000000, \
1075  \"txInputRate_Hz\": 15360000, \
1076  \"txInterfaceSampleRate_Hz\": 15360000, \
1077  \"txOffsetLo_kHz\": 0, \
1078  \"validDataDelay\": 0, \
1079  \"txBbf3dBCorner_kHz\": 50000, \
1080  \"outputSignaling\": 0, \
1081  \"txPdBiasCurrent\": 1, \
1082  \"txPdGainEnable\": 0, \
1083  \"txPrePdRealPole_kHz\": 1000000, \
1084  \"txPostPdRealPole_kHz\": 530000, \
1085  \"txBbfPower\": 2, \
1086  \"txExtLoopBackType\": 0, \
1087  \"txExtLoopBackForInitCal\": 0, \
1088  \"txPeakLoopBackPower\": 0, \
1089  \"frequencyDeviation_Hz\": 0, \
1090  \"txDpProfile\": { \
1091  \"txPreProc\": { \
1092  \"txPreProcSymbol0\": 0, \
1093  \"txPreProcSymbol1\": 0, \
1094  \"txPreProcSymbol2\": 0, \
1095  \"txPreProcSymbol3\": 0, \
1096  \"txPreProcSymMapDivFactor\": 1, \
1097  \"txPreProcMode\": 1, \
1098  \"txPreProcWbNbPfirIBankSel\": 2, \
1099  \"txPreProcWbNbPfirQBankSel\": 3 \
1100  }, \
1101  \"txWbIntTop\": { \
1102  \"txInterpBy2Blk30En\": 0, \
1103  \"txInterpBy2Blk28En\": 0, \
1104  \"txInterpBy2Blk26En\": 0, \
1105  \"txInterpBy2Blk24En\": 1, \
1106  \"txInterpBy2Blk22En\": 1, \
1107  \"txWbLpfBlk22p1En\": 0 \
1108  }, \
1109  \"txNbIntTop\": { \
1110  \"txInterpBy2Blk20En\": 0, \
1111  \"txInterpBy2Blk18En\": 0, \
1112  \"txInterpBy2Blk16En\": 0, \
1113  \"txInterpBy2Blk14En\": 0, \
1114  \"txInterpBy2Blk12En\": 0, \
1115  \"txInterpBy3Blk10En\": 0, \
1116  \"txInterpBy2Blk8En\": 0, \
1117  \"txScicBlk32En\": 0, \
1118  \"txScicBlk32DivFactor\": 1 \
1119  }, \
1120  \"txIntTop\": { \
1121  \"interpBy3Blk44p1En\": 1, \
1122  \"sinc3Blk44En\": 0, \
1123  \"sinc2Blk42En\": 0, \
1124  \"interpBy3Blk40En\": 1, \
1125  \"interpBy2Blk38En\": 0, \
1126  \"interpBy2Blk36En\": 0 \
1127  }, \
1128  \"txIntTopFreqDevMap\": { \
1129  \"rrc2Frac\": 0, \
1130  \"mpll\": 0, \
1131  \"nchLsw\": 0, \
1132  \"nchMsb\": 0, \
1133  \"freqDevMapEn\": 0, \
1134  \"txRoundEn\": 1 \
1135  }, \
1136  \"txIqdmDuc\": { \
1137  \"iqdmDucMode\": 2, \
1138  \"iqdmDev\": 0, \
1139  \"iqdmDevOffset\": 0, \
1140  \"iqdmScalar\": 0, \
1141  \"iqdmThreshold\": 0, \
1142  \"iqdmNco\": { \
1143  \"freq\": 0, \
1144  \"sampleFreq\": 61440000, \
1145  \"phase\": 0, \
1146  \"realOut\": 0 \
1147  } \
1148  } \
1149  }, \
1150  \"txSsiConfig\": { \
1151  \"ssiType\": 2, \
1152  \"ssiDataFormatSel\": 4, \
1153  \"numLaneSel\": 1, \
1154  \"strobeType\": 0, \
1155  \"lsbFirst\": 0, \
1156  \"qFirst\": 0, \
1157  \"txRefClockPin\": 1, \
1158  \"lvdsIBitInversion\": false, \
1159  \"lvdsQBitInversion\": false, \
1160  \"lvdsStrobeBitInversion\": false, \
1161  \"lvdsUseLsbIn12bitMode\": 0, \
1162  \"lvdsRxClkInversionEn\": false, \
1163  \"cmosDdrPosClkEn\": false, \
1164  \"cmosClkInversionEn\": false, \
1165  \"ddrEn\": true, \
1166  \"rxMaskStrobeEn\": false \
1167  } \
1168  } ] \
1169  }, \
1170  \"sysConfig\": { \
1171  \"duplexMode\": 1, \
1172  \"fhModeOn\": 0, \
1173  \"numDynamicProfiles\": 1, \
1174  \"mcsMode\": 0, \
1175  \"mcsInterfaceType\": 0, \
1176  \"adcTypeMonitor\": 1, \
1177  \"pllLockTime_us\": 750, \
1178  \"pllPhaseSyncWait_us\": 0, \
1179  \"pllModulus\": { \
1180  \"modulus\": [ 8388593, 8388593, 8388593, 8388593, 8388593 ], \
1181  \"dmModulus\": [ 8388593, 8388593 ] \
1182  }, \
1183  \"warmBootEnable\": false \
1184  }, \
1185  \"pfirBuffer\": { \
1186  \"pfirRxWbNbChFilterCoeff_A\": { \
1187  \"numCoeff\": 128, \
1188  \"symmetricSel\": 0, \
1189  \"tapsSel\": 3, \
1190  \"gainSel\": 2, \
1191  \"coefficients\": [ 475, 312, -782, -39, 1201, -777, -1182, 1981, 177, -2874, 1941, 2393, -4416, 225, 5594, -4581, -3668, 8650, -1992, -9342, 9646, 4213, -15137, 6404, 13615, -18199, -2610, 23969, -15142, -17198, 31204, -3269, -34604, 30213, 17955, -49337, 16361, 45636, -53954, -12567, 72920, -40769, -54562, 89506, -4148, -102269, 83183, 57280, -142874, 41767, 139213, -158628, -45955, 231679, -125964, -193870, 320642, -4532, -442087, 390927, 347244, -1055854, 429729, 4391599, 4391599, 429729, -1055854, 347244, 390927, -442087, -4532, 320642, -193870, -125964, 231679, -45955, -158628, 139213, 41767, -142874, 57280, 83183, -102269, -4148, 89506, -54562, -40769, 72920, -12567, -53954, 45636, 16361, -49337, 17955, 30213, -34604, -3269, 31204, -17198, -15142, 23969, -2610, -18199, 13615, 6404, -15137, 4213, 9646, -9342, -1992, 8650, -3668, -4581, 5594, 225, -4416, 2393, 1941, -2874, 177, 1981, -1182, -777, 1201, -39, -782, 312, 0 ] \
1192  }, \
1193  \"pfirRxWbNbChFilterCoeff_B\": { \
1194  \"numCoeff\": 128, \
1195  \"symmetricSel\": 0, \
1196  \"tapsSel\": 3, \
1197  \"gainSel\": 2, \
1198  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8388608, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1199  }, \
1200  \"pfirRxWbNbChFilterCoeff_C\": { \
1201  \"numCoeff\": 128, \
1202  \"symmetricSel\": 0, \
1203  \"tapsSel\": 3, \
1204  \"gainSel\": 2, \
1205  \"coefficients\": [ 475, 312, -782, -39, 1201, -777, -1182, 1981, 177, -2874, 1941, 2393, -4416, 225, 5594, -4581, -3668, 8650, -1992, -9342, 9646, 4213, -15137, 6404, 13615, -18199, -2610, 23969, -15142, -17198, 31204, -3269, -34604, 30213, 17955, -49337, 16361, 45636, -53954, -12567, 72920, -40769, -54562, 89506, -4148, -102269, 83183, 57280, -142874, 41767, 139213, -158628, -45955, 231679, -125964, -193870, 320642, -4532, -442087, 390927, 347244, -1055854, 429729, 4391599, 4391599, 429729, -1055854, 347244, 390927, -442087, -4532, 320642, -193870, -125964, 231679, -45955, -158628, 139213, 41767, -142874, 57280, 83183, -102269, -4148, 89506, -54562, -40769, 72920, -12567, -53954, 45636, 16361, -49337, 17955, 30213, -34604, -3269, 31204, -17198, -15142, 23969, -2610, -18199, 13615, 6404, -15137, 4213, 9646, -9342, -1992, 8650, -3668, -4581, 5594, 225, -4416, 2393, 1941, -2874, 177, 1981, -1182, -777, 1201, -39, -782, 312, 0 ] \
1206  }, \
1207  \"pfirRxWbNbChFilterCoeff_D\": { \
1208  \"numCoeff\": 128, \
1209  \"symmetricSel\": 0, \
1210  \"tapsSel\": 3, \
1211  \"gainSel\": 2, \
1212  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8388608, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1213  }, \
1214  \"pfirTxWbNbPulShpCoeff_A\": { \
1215  \"numCoeff\": 128, \
1216  \"symmetricSel\": 0, \
1217  \"tapsSel\": 3, \
1218  \"gainSel\": 2, \
1219  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1220  }, \
1221  \"pfirTxWbNbPulShpCoeff_B\": { \
1222  \"numCoeff\": 128, \
1223  \"symmetricSel\": 0, \
1224  \"tapsSel\": 3, \
1225  \"gainSel\": 2, \
1226  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1227  }, \
1228  \"pfirTxWbNbPulShpCoeff_C\": { \
1229  \"numCoeff\": 128, \
1230  \"symmetricSel\": 0, \
1231  \"tapsSel\": 3, \
1232  \"gainSel\": 2, \
1233  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1234  }, \
1235  \"pfirTxWbNbPulShpCoeff_D\": { \
1236  \"numCoeff\": 128, \
1237  \"symmetricSel\": 0, \
1238  \"tapsSel\": 3, \
1239  \"gainSel\": 2, \
1240  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1241  }, \
1242  \"pfirRxNbPulShp\": [ { \
1243  \"numCoeff\": 128, \
1244  \"symmetricSel\": 0, \
1245  \"taps\": 128, \
1246  \"gainSel\": 2, \
1247  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8388608, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1248  }, { \
1249  \"numCoeff\": 128, \
1250  \"symmetricSel\": 0, \
1251  \"taps\": 128, \
1252  \"gainSel\": 2, \
1253  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8388608, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1254  } ], \
1255  \"pfirRxMagLowTiaLowSRHp\": [ { \
1256  \"numCoeff\": 21, \
1257  \"coefficients\": [ -346, 1329, -1178, -1281, 1308, 2727, -1341, -5852, -1018, 12236, 19599, 12236, -1018, -5852, -1341, 2727, 1308, -1281, -1178, 1329, -346 ] \
1258  }, { \
1259  \"numCoeff\": 21, \
1260  \"coefficients\": [ -346, 1329, -1178, -1281, 1308, 2727, -1341, -5852, -1018, 12236, 19599, 12236, -1018, -5852, -1341, 2727, 1308, -1281, -1178, 1329, -346 ] \
1261  } ], \
1262  \"pfirRxMagLowTiaHighSRHp\": [ { \
1263  \"numCoeff\": 21, \
1264  \"coefficients\": [ -2474, 892, 6049, 4321, -7599, -15881, -6074, 13307, 18926, 6338, -2843, 6338, 18926, 13307, -6074, -15881, -7599, 4321, 6049, 892, -2474 ] \
1265  }, { \
1266  \"numCoeff\": 21, \
1267  \"coefficients\": [ -2474, 892, 6049, 4321, -7599, -15881, -6074, 13307, 18926, 6338, -2843, 6338, 18926, 13307, -6074, -15881, -7599, 4321, 6049, 892, -2474 ] \
1268  } ], \
1269  \"pfirRxMagHighTiaHighSRHp\": [ { \
1270  \"numCoeff\": 21, \
1271  \"coefficients\": [ 39, -229, 714, -1485, 2134, -1844, -219, 4147, -8514, 8496, 26292, 8496, -8514, 4147, -219, -1844, 2134, -1485, 714, -229, 39 ] \
1272  }, { \
1273  \"numCoeff\": 21, \
1274  \"coefficients\": [ 39, -229, 714, -1485, 2134, -1844, -219, 4147, -8514, 8496, 26292, 8496, -8514, 4147, -219, -1844, 2134, -1485, 714, -229, 39 ] \
1275  } ], \
1276  \"pfirRxMagLowTiaLowSRLp\": [ { \
1277  \"numCoeff\": 21, \
1278  \"coefficients\": [ -346, 1329, -1178, -1281, 1308, 2727, -1341, -5851, -1018, 12236, 19599, 12236, -1018, -5851, -1341, 2727, 1308, -1281, -1178, 1329, -346 ] \
1279  }, { \
1280  \"numCoeff\": 21, \
1281  \"coefficients\": [ -346, 1329, -1178, -1281, 1308, 2727, -1341, -5851, -1018, 12236, 19599, 12236, -1018, -5851, -1341, 2727, 1308, -1281, -1178, 1329, -346 ] \
1282  } ], \
1283  \"pfirRxMagLowTiaHighSRLp\": [ { \
1284  \"numCoeff\": 21, \
1285  \"coefficients\": [ -2473, 892, 6048, 4321, -7598, -15879, -6072, 13306, 18924, 6338, -2843, 6338, 18924, 13306, -6072, -15879, -7598, 4321, 6048, 892, -2473 ] \
1286  }, { \
1287  \"numCoeff\": 21, \
1288  \"coefficients\": [ -2473, 892, 6048, 4321, -7598, -15879, -6072, 13306, 18924, 6338, -2843, 6338, 18924, 13306, -6072, -15879, -7598, 4321, 6048, 892, -2473 ] \
1289  } ], \
1290  \"pfirRxMagHighTiaHighSRLp\": [ { \
1291  \"numCoeff\": 21, \
1292  \"coefficients\": [ 39, -229, 712, -1481, 2128, -1841, -215, 4131, -8490, 8497, 26266, 8497, -8490, 4131, -215, -1841, 2128, -1481, 712, -229, 39 ] \
1293  }, { \
1294  \"numCoeff\": 21, \
1295  \"coefficients\": [ 39, -229, 712, -1481, 2128, -1841, -215, 4131, -8490, 8497, 26266, 8497, -8490, 4131, -215, -1841, 2128, -1481, 712, -229, 39 ] \
1296  } ], \
1297  \"pfirTxMagComp1\": { \
1298  \"numCoeff\": 21, \
1299  \"coefficients\": [ 69, -384, 1125, -2089, 2300, -165, -5248, 12368, -13473, 4864, 34039, 4864, -13473, 12368, -5248, -165, 2300, -2089, 1125, -384, 69 ] \
1300  }, \
1301  \"pfirTxMagComp2\": { \
1302  \"numCoeff\": 21, \
1303  \"coefficients\": [ 69, -384, 1125, -2089, 2300, -165, -5248, 12368, -13473, 4864, 34039, 4864, -13473, 12368, -5248, -165, 2300, -2089, 1125, -384, 69 ] \
1304  }, \
1305  \"pfirTxMagCompNb\": [ { \
1306  \"numCoeff\": 13, \
1307  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1308  }, { \
1309  \"numCoeff\": 13, \
1310  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1311  } ], \
1312  \"pfirRxMagCompNb\": [ { \
1313  \"numCoeff\": 13, \
1314  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1315  }, { \
1316  \"numCoeff\": 13, \
1317  \"coefficients\": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] \
1318  } ] \
1319  } \
1320 }";
json_profile
const char * json_profile
Definition: Navassa_LVDS_profile.h:1