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ad3530r.h File Reference
#include <stdint.h>
#include <stdbool.h>
#include "no_os_spi.h"
#include "no_os_gpio.h"
#include "no_os_util.h"
#include "no_os_crc8.h"
Include dependency graph for ad3530r.h:
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Go to the source code of this file.

Classes

struct  ad3530r_transfer_config
 
struct  ad3530r_transfer_data
 
struct  ad3530r_desc
 
struct  ad3530r_init_param
 

Macros

#define AD3530R_R1B   (1ul << 16)
 
#define AD3530R_R2B   (2ul << 16)
 
#define AD3530R_LEN(x)
 
#define AD3530R_ADDR(x)
 
#define AD3530R_MAX_REG_SIZE   2
 
#define AD3530R_MAX_CHANNEL_OP_MODE_0   4
 
#define AD3530R_MAX_SHORT_REG_ADDR   (AD3530R_R1B | 0x80)
 
#define AD3530R_READ_BIT   NO_OS_BIT(7)
 
#define AD3530R_ADDR_MASK   (~AD3530R_READ_BIT)
 
#define AD3530R_WRITE_BIT_LONG_INSTR   0x00
 
#define AD3530R_EXTERNAL_VREF_MASK   NO_OS_BIT(1)
 
#define AD3530R_DEFAULT_STATUS_REG_VAL   0x04
 
#define AD3530R_SCRATCH_PAD_TEST_VAL   0x34
 
#define AD3530R_CRC_POLY   0x07
 
#define AD3530R_CRC_SEED   0xA5
 
#define AD3530R_REG_ADDR_OPERATING_MODE_CHN(x)
 
#define AD3530R_REG_ADDR_INTERFACE_CONFIG_A   (AD3530R_R1B | 0x00)
 
#define AD3530R_REG_ADDR_INTERFACE_CONFIG_B   (AD3530R_R1B | 0x01)
 
#define AD3530R_REG_ADDR_DEVICE_CONFIG   (AD3530R_R1B | 0x02)
 
#define AD3530R_REG_ADDR_CHIP_TYPE   (AD3530R_R1B | 0x03)
 
#define AD3530R_REG_ADDR_PRODUCT_ID_L   (AD3530R_R1B | 0x04)
 
#define AD3530R_REG_ADDR_PRODUCT_ID_H   (AD3530R_R1B | 0x05)
 
#define AD3530R_REG_ADDR_CHIP_GRADE   (AD3530R_R1B | 0x06)
 
#define AD3530R_REG_ADDR_SCRATCH_PAD   (AD3530R_R1B | 0x0A)
 
#define AD3530R_REG_ADDR_SPI_REVISION   (AD3530R_R1B | 0x0B)
 
#define AD3530R_REG_ADDR_VENDOR_L   (AD3530R_R1B | 0x0C)
 
#define AD3530R_REG_ADDR_VENDOR_H   (AD3530R_R1B | 0x0D)
 
#define AD3530R_REG_ADDR_STREAM_MODE   (AD3530R_R1B | 0x0E)
 
#define AD3530R_REG_ADDR_TRANSFER_REGISTER   (AD3530R_R1B | 0x0F)
 
#define AD3530R_REG_ADDR_INTERFACE_CONFIG_C   (AD3530R_R1B | 0x10)
 
#define AD3530R_REG_ADDR_INTERFACE_STATUS_A   (AD3530R_R1B | 0x11)
 
#define AD3530R_REG_ADDR_OPERATING_MODE_0   (AD3530R_R1B | 0x20)
 
#define AD3530R_REG_ADDR_OPERATING_MODE_1   (AD3530R_R1B | 0x21)
 
#define AD3530R_REG_ADDR_OUTPUT_CONTROL_0   (AD3530R_R1B | 0x2A)
 
#define AD3530R_REG_ADDR_REF_CONTROL_0   (AD3530R_R1B | 0x3C)
 
#define AD3530R_REG_ADDR_MUX_OUT_SELECT   (AD3530R_R1B | 0x93)
 
#define AD3530R_REG_ADDR_STATUS_CONTROL   (AD3530R_R1B | 0xC2)
 
#define AD3530R_REG_ADDR_HW_LDAC_EN_0   (AD3530R_R1B | 0xD0)
 
#define AD3530R_REG_ADDR_SW_LDAC_EN_0   (AD3530R_R1B | 0xD1)
 
#define AD3530R_REG_ADDR_DAC_CHN(x)
 
#define AD3530R_REG_ADDR_MULTI_DAC_CH   (AD3530R_R2B | 0XE2)
 
#define AD3530R_REG_ADDR_MULTI_DAC_SEL_0   (AD3530R_R1B | 0XE4)
 
#define AD3530R_REG_ADDR_SW_LDAC_TRIG_A   (AD3530R_R1B | 0XE5)
 
#define AD3530R_REG_ADDR_MULTI_INPUT_CH   (AD3530R_R2B | 0XE6)
 
#define AD3530R_REG_ADDR_MULTI_INPUT_SEL_0   (AD3530R_R1B | 0XE8)
 
#define AD3530R_REG_ADDR_SW_LDAC_TRIG_B   (AD3530R_R1B | 0XE9)
 
#define AD3530R_REG_ADDR_INPUT_CHN(x)
 
#define AD3530R_MASK_SOFTWARE_RESET   (NO_OS_BIT(7) | NO_OS_BIT(0))
 
#define AD3530R_MASK_ADDR_ASCENSION   NO_OS_BIT(5)
 
#define AD3530R_MASK_SDO_ACTIVE   NO_OS_BIT(4)
 
#define AD3530R_MASK_SINGLE_INST   NO_OS_BIT(7)
 
#define AD3530R_MASK_SHORT_INSTRUCTION   NO_OS_BIT(3)
 
#define AD3530R_MASK_OPERATING_MODES   NO_OS_GENMASK(1, 0)
 
#define AD3530R_MASK_GRADE   NO_OS_GENMASK(7, 4)
 
#define AD3530R_MASK_DEVICE_REVISION   NO_OS_GENMASK(3, 0)
 
#define AD3530R_MASK_LENGTH   0xFF
 
#define AD3530R_MASK_STREAM_LENGTH_KEEP_VALUE   NO_OS_BIT(2)
 
#define AD3530R_MASK_CRC_ENABLE   (NO_OS_GENMASK(7, 6) | NO_OS_GENMASK(1, 0))
 
#define AD3530R_MASK_STRICT_REGISTER_ACCESS   NO_OS_BIT(5)
 
#define AD3530R_MASK_ACTIVE_INTERFACE_MODE   NO_OS_GENMASK(3, 2)
 
#define AD3530R_MASK_INTERFACE_NOT_READY   NO_OS_BIT(7)
 
#define AD3530R_MASK_CLOCK_COUNTING_ERROR   NO_OS_BIT(4)
 
#define AD3530R_MASK_INVALID_OR_NO_CRC   NO_OS_BIT(3)
 
#define AD3530R_MASK_PARTIAL_REGISTER_ACCESS   NO_OS_BIT(1)
 
#define AD3530R_MASK_OPERATING_MODE(x)
 
#define AD3530R_MASK_OUTPUT_RANGE   NO_OS_BIT(2)
 
#define AD3530R_MASK_REERENCE_SELECT   NO_OS_BIT(0)
 
#define AD3530R_MASK_MUX_SELECT   NO_OS_GENMASK(4, 0)
 
#define AD3530R_MASK_HW_LDAC_EN_0(x)
 
#define AD3530R_MASK_SW_LDAC_EN_0(x)
 
#define AD3530R_MASK_SW_LDAC_TRIG_B   NO_OS_BIT(7)
 
#define AD3530R_REG_ADDR_MAX   0xF9
 
#define AD3530R_NUM_CH   8
 
#define AD3530R_MASK_CH(ch)
 
#define AD3530R_LDAC_PULSE_US   1
 
#define AD3530R_CH_DAC_DATA_LSB(x)
 
#define AD3530R_CH_DAC_DATA_MSB(x)
 
#define AD3530R_CRC_ENABLE_VALUE   (NO_OS_BIT(6) | NO_OS_BIT(1))
 
#define AD3530R_CRC_DISABLE_VALUE   (NO_OS_BIT(1) | NO_OS_BIT(0))
 
#define AD3530R_NUM_MUX_OUT_SELECTS   27
 
#define AD3530R_NUM_REGS   45
 
#define AD3530R_CH_GRP(x)
 
#define AD3531R_NUM_CH   4
 
#define AD3531R_NUM_MUX_OUT_SELECTS   27
 
#define AD3531R_REG_ADDR_MAX   0xE9
 
#define AD3531R_CH_REG_OFFSET   8
 

Enumerations

enum  ad3530r_id {
  AD3530R_ID ,
  AD3531R_ID
}
 Device IDs. More...
 
enum  ad3530r_ch_sel {
  CH_0_TO_7 ,
  CH_8_TO_15
}
 Channel select options. More...
 
enum  ad3530r_ch_vref_select {
  AD3530R_EXTERNAL_VREF_PIN_INPUT ,
  AD3530R_INTERNAL_VREF_PIN_2P5V
}
 Channel voltage reference options. More...
 
enum  ad3530r_status {
  AD3530R_DEVICE_NOT_READY = 0x0001 ,
  AD3530R_INTERFACE_NOT_READY = 0x0002 ,
  AD3530R_RESET_STATUS = 0x0004 ,
  AD3530R_DAC_UPDATE_STATUS = 0x0008 ,
  AD3530R_PARTIAL_REGISTER_ACCESS = 0x0002 ,
  AD3530R_INVALID_OR_NO_CRC = 0x0008 ,
  AD3530R_CLOCK_COUNTING_ERROR = 0x0010 ,
  AD3530R_DEVICE_NOT_READY_ERR = 0x0080
}
 
enum  ad3530r_ch_output_range {
  AD3530R_CH_OUTPUT_RANGE_0_VREF ,
  AD3530R_CH_OUTPUT_RANGE_0_2VREF
}
 Channel output range options. More...
 
enum  ad3530r_operating_mode {
  AD3530R_CH_OPERATING_MODE_0 ,
  AD3530R_CH_OPERATING_MODE_1 ,
  AD3530R_CH_OPERATING_MODE_2 ,
  AD3530R_CH_OPERATING_MODE_3
}
 Operating modes. More...
 
enum  ad3530r_write_mode {
  AD3530R_WRITE_DAC_REGS ,
  AD3530R_WRITE_INPUT_REGS ,
  AD3530R_WRITE_INPUT_REGS_AND_TRIGGER_LDAC
}
 Write modes. More...
 
enum  ad3530r_mux_out_select {
  POWERED_DOWN ,
  VOUT0 ,
  IOUT0_SOURCE_MODE ,
  IOUT0_SINK_MODE ,
  VOUT1 ,
  IOUT1_SOURCE_MODE ,
  IOUT1_SINK_MODE ,
  VOUT2 ,
  IOUT2_SOURCE_MODE ,
  IOUT2_SINK_MODE ,
  VOUT3 ,
  IOUT3_SOURCE_MODE ,
  IOUT3_SINK_MODE ,
  VOUT4 ,
  IOUT4_SOURCE_MODE ,
  IOUT4_SINK_MODE ,
  VOUT5 ,
  IOUT5_SOURCE_MODE ,
  IOUT5_SINK_MODE ,
  VOUT6 ,
  IOUT6_SOURCE_MODE ,
  IOUT6_SINK_MODE ,
  VOUT7 ,
  IOUT7_SOURCE_MODE ,
  IOUT7_SINK_MODE ,
  DIE_TEMPERATURE ,
  TIED_TO_AGND_INTERNALLY
}
 Signals to monitor on MUX_OUT pin. More...
 

Functions

int ad3530r_reg_write (struct ad3530r_desc *desc, uint32_t reg_addr, uint16_t reg_val)
 Write into device register.
 
int ad3530r_reg_read (struct ad3530r_desc *desc, uint32_t reg_addr, uint16_t *reg_val)
 Read from device register.
 
int ad3530r_spi_write_mask (struct ad3530r_desc *desc, uint32_t addr, uint32_t mask, uint16_t val)
 SPI write to device using a mask.
 
int ad3530r_update_interface_cfg (struct ad3530r_desc *desc, struct ad3530r_transfer_config *cfg)
 Updates the interface configuration.
 
int ad3530r_multiple_reg_write (struct ad3530r_desc *desc, uint32_t start_addr, uint8_t buff_len, uint8_t *buff)
 Write multiple register's values.
 
int ad3530r_multiple_reg_read (struct ad3530r_desc *desc, uint32_t addr, uint8_t buff_len, uint8_t *buff)
 Read multiple register's values.
 
int ad3530r_set_reference (struct ad3530r_desc *desc, enum ad3530r_ch_vref_select reference_selector)
 
int ad3530r_set_operating_mode (struct ad3530r_desc *desc, uint8_t chn_num, enum ad3530r_operating_mode chn_op_mode)
 
int ad3530r_set_output_range (struct ad3530r_desc *desc, enum ad3530r_ch_output_range range_sel)
 
int ad3530r_set_crc_enable (struct ad3530r_desc *desc, bool en_di)
 
int ad3530r_set_mux_out_select (struct ad3530r_desc *desc, enum ad3530r_mux_out_select mux_output_sel)
 
int ad3530r_set_hw_ldac (struct ad3530r_desc *desc, uint16_t mask_hw_ldac)
 
int ad3530r_set_sw_ldac (struct ad3530r_desc *desc, uint16_t mask_sw_ldac)
 
int ad3530r_set_dac_value (struct ad3530r_desc *desc, uint16_t dac_value, uint8_t dac_channel, enum ad3530r_write_mode write_mode)
 
int ad3530r_set_multidac_value (struct ad3530r_desc *desc, uint16_t dac_value, uint16_t dac_chn_mask, enum ad3530r_write_mode write_mode)
 
int ad3530r_sw_ldac_trigger (struct ad3530r_desc *desc)
 Trigger the LDAC using software.
 
int ad3530r_hw_ldac_trigger (struct ad3530r_desc *desc)
 Trigger the LDAC using hardware.
 
int ad3530r_reset (struct ad3530r_desc *desc)
 Perform a hard/soft reset.
 
int ad3530r_init (struct ad3530r_desc **desc, struct ad3530r_init_param *init_param)
 Initialize the device structure.
 
int ad3530r_remove (struct ad3530r_desc *desc)
 Free the device descriptor.
 
uint32_t get_reg_addr (uint32_t addr, enum ad3530r_id chip_id, enum ad3530r_ch_sel ch_sel)
 Get adjusted register address based on the chip id selected.
 

Macro Definition Documentation

◆ AD3530R_ADDR

#define AD3530R_ADDR ( x)
Value:
(x & 0xFFFF)

◆ AD3530R_ADDR_MASK

#define AD3530R_ADDR_MASK   (~AD3530R_READ_BIT)

◆ AD3530R_CH_DAC_DATA_LSB

#define AD3530R_CH_DAC_DATA_LSB ( x)
Value:
((x) & 0xFF)

◆ AD3530R_CH_DAC_DATA_MSB

#define AD3530R_CH_DAC_DATA_MSB ( x)
Value:
((x) >> 8 & 0xFF)

◆ AD3530R_CH_GRP

#define AD3530R_CH_GRP ( x)
Value:
((x) / 8)

◆ AD3530R_CRC_DISABLE_VALUE

#define AD3530R_CRC_DISABLE_VALUE   (NO_OS_BIT(1) | NO_OS_BIT(0))

◆ AD3530R_CRC_ENABLE_VALUE

#define AD3530R_CRC_ENABLE_VALUE   (NO_OS_BIT(6) | NO_OS_BIT(1))

◆ AD3530R_CRC_POLY

#define AD3530R_CRC_POLY   0x07

◆ AD3530R_CRC_SEED

#define AD3530R_CRC_SEED   0xA5

◆ AD3530R_DEFAULT_STATUS_REG_VAL

#define AD3530R_DEFAULT_STATUS_REG_VAL   0x04

◆ AD3530R_EXTERNAL_VREF_MASK

#define AD3530R_EXTERNAL_VREF_MASK   NO_OS_BIT(1)

◆ AD3530R_LDAC_PULSE_US

#define AD3530R_LDAC_PULSE_US   1

◆ AD3530R_LEN

#define AD3530R_LEN ( x)
Value:
(x >> 16)

◆ AD3530R_MASK_ACTIVE_INTERFACE_MODE

#define AD3530R_MASK_ACTIVE_INTERFACE_MODE   NO_OS_GENMASK(3, 2)

◆ AD3530R_MASK_ADDR_ASCENSION

#define AD3530R_MASK_ADDR_ASCENSION   NO_OS_BIT(5)

◆ AD3530R_MASK_CH

#define AD3530R_MASK_CH ( ch)
Value:
NO_OS_BIT(ch)
NO_OS_BIT
#define NO_OS_BIT(x)
Definition no_os_util.h:39

◆ AD3530R_MASK_CLOCK_COUNTING_ERROR

#define AD3530R_MASK_CLOCK_COUNTING_ERROR   NO_OS_BIT(4)

◆ AD3530R_MASK_CRC_ENABLE

#define AD3530R_MASK_CRC_ENABLE   (NO_OS_GENMASK(7, 6) | NO_OS_GENMASK(1, 0))

◆ AD3530R_MASK_DEVICE_REVISION

#define AD3530R_MASK_DEVICE_REVISION   NO_OS_GENMASK(3, 0)

◆ AD3530R_MASK_GRADE

#define AD3530R_MASK_GRADE   NO_OS_GENMASK(7, 4)

◆ AD3530R_MASK_HW_LDAC_EN_0

#define AD3530R_MASK_HW_LDAC_EN_0 ( x)
Value:
NO_OS_BIT((x) & 7)

◆ AD3530R_MASK_INTERFACE_NOT_READY

#define AD3530R_MASK_INTERFACE_NOT_READY   NO_OS_BIT(7)

◆ AD3530R_MASK_INVALID_OR_NO_CRC

#define AD3530R_MASK_INVALID_OR_NO_CRC   NO_OS_BIT(3)

◆ AD3530R_MASK_LENGTH

#define AD3530R_MASK_LENGTH   0xFF

◆ AD3530R_MASK_MUX_SELECT

#define AD3530R_MASK_MUX_SELECT   NO_OS_GENMASK(4, 0)

◆ AD3530R_MASK_OPERATING_MODE

#define AD3530R_MASK_OPERATING_MODE ( x)
Value:
0x03 << ((x % 4)*2)

◆ AD3530R_MASK_OPERATING_MODES

#define AD3530R_MASK_OPERATING_MODES   NO_OS_GENMASK(1, 0)

◆ AD3530R_MASK_OUTPUT_RANGE

#define AD3530R_MASK_OUTPUT_RANGE   NO_OS_BIT(2)

◆ AD3530R_MASK_PARTIAL_REGISTER_ACCESS

#define AD3530R_MASK_PARTIAL_REGISTER_ACCESS   NO_OS_BIT(1)

◆ AD3530R_MASK_REERENCE_SELECT

#define AD3530R_MASK_REERENCE_SELECT   NO_OS_BIT(0)

◆ AD3530R_MASK_SDO_ACTIVE

#define AD3530R_MASK_SDO_ACTIVE   NO_OS_BIT(4)

◆ AD3530R_MASK_SHORT_INSTRUCTION

#define AD3530R_MASK_SHORT_INSTRUCTION   NO_OS_BIT(3)

◆ AD3530R_MASK_SINGLE_INST

#define AD3530R_MASK_SINGLE_INST   NO_OS_BIT(7)

◆ AD3530R_MASK_SOFTWARE_RESET

#define AD3530R_MASK_SOFTWARE_RESET   (NO_OS_BIT(7) | NO_OS_BIT(0))

◆ AD3530R_MASK_STREAM_LENGTH_KEEP_VALUE

#define AD3530R_MASK_STREAM_LENGTH_KEEP_VALUE   NO_OS_BIT(2)

◆ AD3530R_MASK_STRICT_REGISTER_ACCESS

#define AD3530R_MASK_STRICT_REGISTER_ACCESS   NO_OS_BIT(5)

◆ AD3530R_MASK_SW_LDAC_EN_0

#define AD3530R_MASK_SW_LDAC_EN_0 ( x)
Value:
NO_OS_BIT((x) & 7)

◆ AD3530R_MASK_SW_LDAC_TRIG_B

#define AD3530R_MASK_SW_LDAC_TRIG_B   NO_OS_BIT(7)

◆ AD3530R_MAX_CHANNEL_OP_MODE_0

#define AD3530R_MAX_CHANNEL_OP_MODE_0   4

◆ AD3530R_MAX_REG_SIZE

#define AD3530R_MAX_REG_SIZE   2

◆ AD3530R_MAX_SHORT_REG_ADDR

#define AD3530R_MAX_SHORT_REG_ADDR   (AD3530R_R1B | 0x80)

◆ AD3530R_NUM_CH

#define AD3530R_NUM_CH   8

◆ AD3530R_NUM_MUX_OUT_SELECTS

#define AD3530R_NUM_MUX_OUT_SELECTS   27

◆ AD3530R_NUM_REGS

#define AD3530R_NUM_REGS   45

◆ AD3530R_R1B

#define AD3530R_R1B   (1ul << 16)

◆ AD3530R_R2B

#define AD3530R_R2B   (2ul << 16)

◆ AD3530R_READ_BIT

#define AD3530R_READ_BIT   NO_OS_BIT(7)

◆ AD3530R_REG_ADDR_CHIP_GRADE

#define AD3530R_REG_ADDR_CHIP_GRADE   (AD3530R_R1B | 0x06)

◆ AD3530R_REG_ADDR_CHIP_TYPE

#define AD3530R_REG_ADDR_CHIP_TYPE   (AD3530R_R1B | 0x03)

◆ AD3530R_REG_ADDR_DAC_CHN

#define AD3530R_REG_ADDR_DAC_CHN ( x)
Value:
(AD3530R_R2B | (0xD2 + (((x) & 7) << 1)))
AD3530R_R2B
#define AD3530R_R2B
Definition ad3530r.h:43

◆ AD3530R_REG_ADDR_DEVICE_CONFIG

#define AD3530R_REG_ADDR_DEVICE_CONFIG   (AD3530R_R1B | 0x02)

◆ AD3530R_REG_ADDR_HW_LDAC_EN_0

#define AD3530R_REG_ADDR_HW_LDAC_EN_0   (AD3530R_R1B | 0xD0)

◆ AD3530R_REG_ADDR_INPUT_CHN

#define AD3530R_REG_ADDR_INPUT_CHN ( x)
Value:
(AD3530R_R2B | (0xEA + (((x) & 7) << 1)))

◆ AD3530R_REG_ADDR_INTERFACE_CONFIG_A

#define AD3530R_REG_ADDR_INTERFACE_CONFIG_A   (AD3530R_R1B | 0x00)

◆ AD3530R_REG_ADDR_INTERFACE_CONFIG_B

#define AD3530R_REG_ADDR_INTERFACE_CONFIG_B   (AD3530R_R1B | 0x01)

◆ AD3530R_REG_ADDR_INTERFACE_CONFIG_C

#define AD3530R_REG_ADDR_INTERFACE_CONFIG_C   (AD3530R_R1B | 0x10)

◆ AD3530R_REG_ADDR_INTERFACE_STATUS_A

#define AD3530R_REG_ADDR_INTERFACE_STATUS_A   (AD3530R_R1B | 0x11)

◆ AD3530R_REG_ADDR_MAX

#define AD3530R_REG_ADDR_MAX   0xF9

◆ AD3530R_REG_ADDR_MULTI_DAC_CH

#define AD3530R_REG_ADDR_MULTI_DAC_CH   (AD3530R_R2B | 0XE2)

◆ AD3530R_REG_ADDR_MULTI_DAC_SEL_0

#define AD3530R_REG_ADDR_MULTI_DAC_SEL_0   (AD3530R_R1B | 0XE4)

◆ AD3530R_REG_ADDR_MULTI_INPUT_CH

#define AD3530R_REG_ADDR_MULTI_INPUT_CH   (AD3530R_R2B | 0XE6)

◆ AD3530R_REG_ADDR_MULTI_INPUT_SEL_0

#define AD3530R_REG_ADDR_MULTI_INPUT_SEL_0   (AD3530R_R1B | 0XE8)

◆ AD3530R_REG_ADDR_MUX_OUT_SELECT

#define AD3530R_REG_ADDR_MUX_OUT_SELECT   (AD3530R_R1B | 0x93)

◆ AD3530R_REG_ADDR_OPERATING_MODE_0

#define AD3530R_REG_ADDR_OPERATING_MODE_0   (AD3530R_R1B | 0x20)

◆ AD3530R_REG_ADDR_OPERATING_MODE_1

#define AD3530R_REG_ADDR_OPERATING_MODE_1   (AD3530R_R1B | 0x21)

◆ AD3530R_REG_ADDR_OPERATING_MODE_CHN

#define AD3530R_REG_ADDR_OPERATING_MODE_CHN ( x)
Value:
(AD3530R_R1B | (0x20 + (((x) & 4) >> 2)))
AD3530R_R1B
#define AD3530R_R1B
Definition ad3530r.h:42

◆ AD3530R_REG_ADDR_OUTPUT_CONTROL_0

#define AD3530R_REG_ADDR_OUTPUT_CONTROL_0   (AD3530R_R1B | 0x2A)

◆ AD3530R_REG_ADDR_PRODUCT_ID_H

#define AD3530R_REG_ADDR_PRODUCT_ID_H   (AD3530R_R1B | 0x05)

◆ AD3530R_REG_ADDR_PRODUCT_ID_L

#define AD3530R_REG_ADDR_PRODUCT_ID_L   (AD3530R_R1B | 0x04)

◆ AD3530R_REG_ADDR_REF_CONTROL_0

#define AD3530R_REG_ADDR_REF_CONTROL_0   (AD3530R_R1B | 0x3C)

◆ AD3530R_REG_ADDR_SCRATCH_PAD

#define AD3530R_REG_ADDR_SCRATCH_PAD   (AD3530R_R1B | 0x0A)

◆ AD3530R_REG_ADDR_SPI_REVISION

#define AD3530R_REG_ADDR_SPI_REVISION   (AD3530R_R1B | 0x0B)

◆ AD3530R_REG_ADDR_STATUS_CONTROL

#define AD3530R_REG_ADDR_STATUS_CONTROL   (AD3530R_R1B | 0xC2)

◆ AD3530R_REG_ADDR_STREAM_MODE

#define AD3530R_REG_ADDR_STREAM_MODE   (AD3530R_R1B | 0x0E)

◆ AD3530R_REG_ADDR_SW_LDAC_EN_0

#define AD3530R_REG_ADDR_SW_LDAC_EN_0   (AD3530R_R1B | 0xD1)

◆ AD3530R_REG_ADDR_SW_LDAC_TRIG_A

#define AD3530R_REG_ADDR_SW_LDAC_TRIG_A   (AD3530R_R1B | 0XE5)

◆ AD3530R_REG_ADDR_SW_LDAC_TRIG_B

#define AD3530R_REG_ADDR_SW_LDAC_TRIG_B   (AD3530R_R1B | 0XE9)

◆ AD3530R_REG_ADDR_TRANSFER_REGISTER

#define AD3530R_REG_ADDR_TRANSFER_REGISTER   (AD3530R_R1B | 0x0F)

◆ AD3530R_REG_ADDR_VENDOR_H

#define AD3530R_REG_ADDR_VENDOR_H   (AD3530R_R1B | 0x0D)

◆ AD3530R_REG_ADDR_VENDOR_L

#define AD3530R_REG_ADDR_VENDOR_L   (AD3530R_R1B | 0x0C)

◆ AD3530R_SCRATCH_PAD_TEST_VAL

#define AD3530R_SCRATCH_PAD_TEST_VAL   0x34

◆ AD3530R_WRITE_BIT_LONG_INSTR

#define AD3530R_WRITE_BIT_LONG_INSTR   0x00

◆ AD3531R_CH_REG_OFFSET

#define AD3531R_CH_REG_OFFSET   8

◆ AD3531R_NUM_CH

#define AD3531R_NUM_CH   4

◆ AD3531R_NUM_MUX_OUT_SELECTS

#define AD3531R_NUM_MUX_OUT_SELECTS   27

◆ AD3531R_REG_ADDR_MAX

#define AD3531R_REG_ADDR_MAX   0xE9

Enumeration Type Documentation

◆ ad3530r_ch_output_range

enum ad3530r_ch_output_range

Channel output range options.

Enumerator
AD3530R_CH_OUTPUT_RANGE_0_VREF 
AD3530R_CH_OUTPUT_RANGE_0_2VREF 

◆ ad3530r_ch_sel

enum ad3530r_ch_sel

Channel select options.

Enumerator
CH_0_TO_7 
CH_8_TO_15 

◆ ad3530r_ch_vref_select

enum ad3530r_ch_vref_select

Channel voltage reference options.

Enumerator
AD3530R_EXTERNAL_VREF_PIN_INPUT 
AD3530R_INTERNAL_VREF_PIN_2P5V 

◆ ad3530r_id

enum ad3530r_id

Device IDs.

Enumerator
AD3530R_ID 
AD3531R_ID 

◆ ad3530r_mux_out_select

enum ad3530r_mux_out_select

Signals to monitor on MUX_OUT pin.

Enumerator
POWERED_DOWN 
VOUT0 
IOUT0_SOURCE_MODE 
IOUT0_SINK_MODE 
VOUT1 
IOUT1_SOURCE_MODE 
IOUT1_SINK_MODE 
VOUT2 
IOUT2_SOURCE_MODE 
IOUT2_SINK_MODE 
VOUT3 
IOUT3_SOURCE_MODE 
IOUT3_SINK_MODE 
VOUT4 
IOUT4_SOURCE_MODE 
IOUT4_SINK_MODE 
VOUT5 
IOUT5_SOURCE_MODE 
IOUT5_SINK_MODE 
VOUT6 
IOUT6_SOURCE_MODE 
IOUT6_SINK_MODE 
VOUT7 
IOUT7_SOURCE_MODE 
IOUT7_SINK_MODE 
DIE_TEMPERATURE 
TIED_TO_AGND_INTERNALLY 

◆ ad3530r_operating_mode

enum ad3530r_operating_mode

Operating modes.

Enumerator
AD3530R_CH_OPERATING_MODE_0 
AD3530R_CH_OPERATING_MODE_1 
AD3530R_CH_OPERATING_MODE_2 
AD3530R_CH_OPERATING_MODE_3 

◆ ad3530r_status

enum ad3530r_status
Enumerator
AD3530R_DEVICE_NOT_READY 
AD3530R_INTERFACE_NOT_READY 
AD3530R_RESET_STATUS 
AD3530R_DAC_UPDATE_STATUS 
AD3530R_PARTIAL_REGISTER_ACCESS 
AD3530R_INVALID_OR_NO_CRC 
AD3530R_CLOCK_COUNTING_ERROR 
AD3530R_DEVICE_NOT_READY_ERR 

◆ ad3530r_write_mode

enum ad3530r_write_mode

Write modes.

Enumerator
AD3530R_WRITE_DAC_REGS 
AD3530R_WRITE_INPUT_REGS 
AD3530R_WRITE_INPUT_REGS_AND_TRIGGER_LDAC 

Function Documentation

◆ ad3530r_hw_ldac_trigger()

int ad3530r_hw_ldac_trigger ( struct ad3530r_desc * desc)

Trigger the LDAC using hardware.

Parameters
desc- The device structure.
Returns
0 in case of success, negative error code otherwise.
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◆ ad3530r_init()

int ad3530r_init ( struct ad3530r_desc ** desc,
struct ad3530r_init_param * init_param )

Initialize the device structure.

Parameters
desc- The device structure to be initialized.
init_param- Initialization parameter for the device descriptor.
Returns
0 in case of success, negative error code otherwise.

◆ ad3530r_multiple_reg_read()

int ad3530r_multiple_reg_read ( struct ad3530r_desc * desc,
uint32_t addr,
uint8_t count,
uint8_t * buff )

Read multiple register's values.

Parameters
desc- The device structure.
addr- Starting register address to read from.
count- Number of bytes to read.
buff- Buffer to store data.
Returns
0 in case of success, negative error otherwise.

◆ ad3530r_multiple_reg_write()

int ad3530r_multiple_reg_write ( struct ad3530r_desc * desc,
uint32_t start_addr,
uint8_t count,
uint8_t * buff )

Write multiple register's values.

Parameters
desc- The device structure.
start_addr- Starting register address to write into.
count- Number of bytes to write.
buff- Buffer to write data from.
Returns
0 in case of success, negative error otherwise.

◆ ad3530r_reg_read()

int ad3530r_reg_read ( struct ad3530r_desc * desc,
uint32_t reg_addr,
uint16_t * reg_val )

Read from device register.

Parameters
desc- The device structure.
reg_addr- The register's address.
reg_val- The register's read value.
Returns
0 in case of success, negative error otherwise.
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◆ ad3530r_reg_write()

int ad3530r_reg_write ( struct ad3530r_desc * desc,
uint32_t reg_addr,
uint16_t reg_val )

Write into device register.

Parameters
desc- The device structure.
reg_addr- The register's address.
reg_val- The register's value.
Returns
0 in case of success, negative error otherwise.
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◆ ad3530r_remove()

int ad3530r_remove ( struct ad3530r_desc * desc)

Free the device descriptor.

Parameters
desc- The device structure.
Returns
0 in case of success, negative error code otherwise.

◆ ad3530r_reset()

int ad3530r_reset ( struct ad3530r_desc * desc)

Perform a hard/soft reset.

Parameters
desc- The device structure.
Returns
0 in case of success, negative error code otherwise.
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◆ ad3530r_set_crc_enable()

int ad3530r_set_crc_enable ( struct ad3530r_desc * desc,
bool en_di )

Configures the CRC selection bit .

Parameters
desc- The device structure.
en_di- boolean selection for crc bit.
Returns
0 in case of success, negative error code otherwise.
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◆ ad3530r_set_dac_value()

int ad3530r_set_dac_value ( struct ad3530r_desc * desc,
uint16_t dac_value,
uint8_t dac_channel,
enum ad3530r_write_mode write_mode )

Set dac value based on the user selected DAC update mode.

Parameters
desc- The device structure.
dac_value- value that will be set in the register.
dac_channel- selected channel.
write_mode- selected write mode.
Returns
0 in case of success, negative error code otherwise.

◆ ad3530r_set_hw_ldac()

int ad3530r_set_hw_ldac ( struct ad3530r_desc * desc,
uint16_t mask_hw_ldac )

Set the hardware ldac configuration.

Parameters
desc- The device structure.
mask_hw_ldac- The array contains HW LDAC channel masks.
Returns
0 in case of success, negative error code otherwise.
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◆ ad3530r_set_multidac_value()

int ad3530r_set_multidac_value ( struct ad3530r_desc * desc,
uint16_t dac_value,
uint16_t dac_chn_mask,
enum ad3530r_write_mode write_mode )

Sets dac value for multiple channels.

Parameters
desc- The device structure.
dac_value- value that will be set in the register.
dac_chn_mask- mask for selected channels.
write_mode- selected write mode.
Returns
0 in case of success, negative error code otherwise.

◆ ad3530r_set_mux_out_select()

int ad3530r_set_mux_out_select ( struct ad3530r_desc * desc,
enum ad3530r_mux_out_select mux_output_sel )

Set the multiplexer output select register.

Parameters
desc- The device structure.
mux_output_sel- signal to be monitored on the mux_out pin.
Returns
0 in case of success, negative error code otherwise.
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◆ ad3530r_set_operating_mode()

int ad3530r_set_operating_mode ( struct ad3530r_desc * desc,
uint8_t chn_num,
enum ad3530r_operating_mode chn_op_mode )

Set operating mode for each channel.

Parameters
desc- The device structure.
chn_num- Channel number to be configured.
chn_op_mode- Operation mode to be set.
Returns
0 in case of success, negative error code otherwise.
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◆ ad3530r_set_output_range()

int ad3530r_set_output_range ( struct ad3530r_desc * desc,
enum ad3530r_ch_output_range range_sel )

Set output range for all channels.

Parameters
desc- The device structure.
range_sel- Output range to be selected.
Returns
0 in case of success, negative error code otherwise.
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◆ ad3530r_set_reference()

int ad3530r_set_reference ( struct ad3530r_desc * desc,
enum ad3530r_ch_vref_select reference_selector )

Set reference configuration.

Parameters
desc- The device structure.
reference_selector- The reference to be selected.
Returns
0 in case of success, negative error code otherwise.
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◆ ad3530r_set_sw_ldac()

int ad3530r_set_sw_ldac ( struct ad3530r_desc * desc,
uint16_t mask_sw_ldac )

Set the software ldac configuration.

Parameters
desc- The device structure.
mask_sw_ldac- The array contains SW LDAC channel masks.
Returns
0 in case of success, negative error code otherwise.
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◆ ad3530r_spi_write_mask()

int ad3530r_spi_write_mask ( struct ad3530r_desc * desc,
uint32_t addr,
uint32_t mask,
uint16_t val )

SPI write to device using a mask.

Parameters
desc- The device structure.
addr- The register's address.
mask- The mask for a specific register field.
val- The register's value.
Returns
0 in case of success, negative error otherwise.
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◆ ad3530r_sw_ldac_trigger()

int ad3530r_sw_ldac_trigger ( struct ad3530r_desc * desc)

Trigger the LDAC using software.

Parameters
desc- The device structure.
Returns
0 in case of success, negative error code otherwise.
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◆ ad3530r_update_interface_cfg()

int ad3530r_update_interface_cfg ( struct ad3530r_desc * desc,
struct ad3530r_transfer_config * cfg )

Updates the interface configuration.

Parameters
desc- The device structure.
cfg- Updated interface configuration structure.
Returns
0 in case of success, negative error otherwise.
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◆ get_reg_addr()

uint32_t get_reg_addr ( uint32_t addr,
enum ad3530r_id chip_id,
enum ad3530r_ch_sel ch_sel )

Get adjusted register address based on the chip id selected.

Parameters
addr- The Base register address.
chip_id- Device id.
ch_sel- Channel set selection. Available options: CH_0_TO_7, CH_8_TO_15
Returns
actual register address in case of success, negative error otherwise.
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