ad4080.h

Go to the documentation of this file.

/***************************************************************************/
 
#ifndef __AD4080_H__
#define __AD4080_H__
 
#include <stdint.h>
#include <string.h>
#include "no_os_util.h"
#include "no_os_spi.h"
#include "no_os_gpio.h"

#define AD4080_REG_INTERFACE_CONFIG_A       0x0000
#define AD4080_REG_INTERFACE_CONFIG_B       0x0001
#define AD4080_REG_DEVICE_CONFIG        0x0002
#define AD4080_REG_CHIP_TYPE            0x0003
#define AD4080_REG_PRODUCT_ID_L         0x0004
#define AD4080_REG_PRODUCT_ID_H         0x0005
#define AD4080_REG_CHIP_GRADE           0x0006
#define AD4080_REG_SCRATCH_PAD          0x000A
#define AD4080_REG_SPI_REVISION         0x000B
#define AD4080_REG_VENDOR_L         0x000C
#define AD4080_REG_VENDOR_H         0x000D
#define AD4080_REG_STREAM_MODE          0x000E
#define AD4080_REG_TRANSFER_CONFIG      0x000F
#define AD4080_REG_INTERFACE_CONFIG_C       0x0010
#define AD4080_REG_INTERFACE_STATUS_A       0x0011
#define AD4080_REG_DEVICE_STATUS        0x0014
#define AD4080_REG_DATA_INTF_CONFIG_A       0x0015
#define AD4080_REG_DATA_INTF_CONFIG_B       0x0016
#define AD4080_REG_DATA_INTF_CONFIG_C       0x0017
#define AD4080_REG_PWR_CTRL         0x0018
#define AD4080_REG_GPIO_CONFIG_A        0x0019
#define AD4080_REG_GPIO_CONFIG_B        0x001A
#define AD4080_REG_GPIO_CONFIG_C        0x001B
#define AD4080_REG_GENERAL_CONFIG       0x001C
#define AD4080_REG_FIFO_WATERMARK       0x001D
#define AD4080_REG_EVENT_HYSTERESIS     0x001F
#define AD4080_REG_EVENT_DETECTION_HI       0x0021
#define AD4080_REG_EVENT_DETECTION_LO       0x0023
#define AD4080_REG_OFFSET           0x0025
#define AD4080_REG_GAIN             0x0027
#define AD4080_REG_FILTER_CONFIG        0x0029

#define AD4080_SW_RESET_MSK         NO_OS_BIT(7) | NO_OS_BIT(0)
#define AD4080_ADDR_ASC_MSK         NO_OS_BIT(5)
#define AD4080_SDO_ENABLE_MSK           NO_OS_BIT(4)

#define AD4080_SINGLE_INST_MSK          NO_OS_BIT(7)
#define AD4080_SHORT_INST_MSK           NO_OS_BIT(3)

#define AD4080_OP_MODE_MSK          NO_OS_GENMASK(1, 0)

#define AD4080_KEEP_STREAM_LEN_VAL_MSK      NO_OS_BIT(2)

#define AD4080_STRICT_REG_ACCESS_MSK        NO_OS_BIT(5)

#define AD4080_INTF_CHK_EN_MSK          NO_OS_BIT(4)
#define AD4080_SPI_LVDS_LANES_MSK       NO_OS_BIT(2)
#define AD4080_DATA_INTF_MODE_MSK       NO_OS_BIT(0)

#define AD4080_LVDS_CNV_CLK_CNT_MSK     NO_OS_GENMASK(7, 4)
#define AD4080_LVDS_SELF_CLK_MODE_MSK       NO_OS_BIT(3)
#define AD4080_LVDS_CNV_EN          NO_OS_BIT(0)

#define AD4080_LVDS_VOD_MSK         NO_OS_GENMASK(6, 4)

#define AD4080_ANA_DIG_LDO_PD_MSK       NO_OS_BIT(1)
#define AD4080_INTF_LDO_PD_MSK          NO_OS_BIT(0)

#define AD4080_GPIO_EN_MSK(x)           NO_OS_BIT(x)
#define AD4080_GPIO_SEL_MSK(x)          (NO_OS_GENMASK(3, 0) << (4 * ((x)%2)))
#define AD4080_GPIO_DATA_MSK(x)         (NO_OS_BIT(x) << 4)

#define AD4080_FIFO_MODE_MSK            NO_OS_GENMASK(1, 0)

#define AD4080_FILTER_SEL_MSK           NO_OS_GENMASK(1, 0)
#define AD4080_SINC_DECIMATION_MSK      NO_OS_GENMASK(6, 3)
 
#define AD4080_FILTER_SINC1         1
#define AD4080_FILTER_SINC5         2
#define AD4080_FILTER_SINC5_PLUS    3
 
#define AD4080_SINC_DEC_2       0
#define AD4080_SINC_DEC_4       1
#define AD4080_SINC_DEC_8       2
#define AD4080_SINC_DEC_16      3
#define AD4080_SINC_DEC_32      4
#define AD4080_SINC_DEC_64      5
#define AD4080_SINC_DEC_128         6
#define AD4080_SINC_DEC_256         7
#define AD4080_SINC_DEC_512         8
#define AD4080_SINC_DEC_1024        9

#define AD4080_SW_RESET             NO_OS_BIT(7) | NO_OS_BIT(0)
#define AD4080_SPI_READ                 NO_OS_BIT(7)
#define BYTE_ADDR_H             NO_OS_GENMASK(15, 8)
#define BYTE_ADDR_L             NO_OS_GENMASK(7, 0)
#define AD4080_CHIP_ID              NO_OS_GENMASK(2, 0)

#define AD4080_PRODUCT_ID           0x0050
#define AD4081_PRODUCT_ID           0x0051
#define AD4082_PRODUCT_ID           0x0052
#define AD4083_PRODUCT_ID           0x0053
#define AD4085_PRODUCT_ID           0x0055
#define AD4086_PRODUCT_ID           0x0056
#define AD4087_PRODUCT_ID           0x0057
#define AD4088_PRODUCT_ID           0x0058
#define AD4080_FIFO_SIZE          NO_OS_BIT(14)
#define AD4080_FIFO_DEPTH   16384   /* AD4080 is 16K deep maximum */
#define AD4080_MAX_FIFO_WATERMARK   (AD4080_FIFO_DEPTH)
#define AD4080_LAST_REG_ADDR    AD4080_REG_FILTER_CONFIG
#define AD4080_ADC_GRANULARITY  20  /* 20 Bits precision */
#define ADC_REF_VOLTAGE     3300    /* mV granularity */
#define AD4080_ADC_MAX_RESOLUTION_VAL   ((1 << AD4080_ADC_GRANULARITY) - 1)
#define OFFSET_CORRECTION_NEGATIVE_LIMIT    0x800
 

enum ad4080_addr_asc {
    AD4080_ADDR_DECR,
    AD4080_ADDR_INCR,
};

enum ad4080_single_instr {
    AD4080_STREAM_MODE,
    AD4080_SINGLE_INST,
};

enum ad4080_short_instr {
    AD4080_15_BIT_ADDR,
    AD4080_7_BIT_ADDR,
};

enum ad4080_op_mode {
    AD4080_OP_NORMAL,
    AD4080_OP_STANDBY,
    AD4080_OP_LOW_POWER,
};

enum ad4080_strict_reg_access {
    AD4080_REG_NORMAL_MODE,
    AD4080_REG_STRICT_MODE,
};

enum ad4080_intf_chk_en {
    AD4080_DATA,
    AD4080_FIXED_PATTERN,
};

enum ad4080_cnv_spi_lvds_lanes {
    AD4080_ONE_LANE,
    AD4080_MULTIPLE_LANES
};

enum ad4080_conv_data_spi_lvds {
    AD4080_CONV_DATA_LVDS,
    AD4080_CONV_DATA_SPI
};

enum ad4080_lvds_self_clk_mode {
    AD4080_ECHO_CLK_MODE,
    AD4080_SELF_CLK_MODE,
};

enum ad4080_lvds_cnv_clk_mode {
    AD4080_CNV_CMOS_MODE,
    AD4080_CNV_LVDS_MODE,
};

enum ad4080_lvds_vod {
    AD4080_185mVPP = 1,
    AD4080_240mVPP = 2,
    AD4080_325mVPP = 4,
};

enum ad4080_ana_dig_ldo_pd {
    AD4080_AD_LDO_EN,
    AD4080_AD_LDO_DISABLE,
};

enum ad4080_intf_ldo_pd {
    AD4080_INTF_LDO_EN,
    AD4080_INTF_LDO_DISABLE,
};
 
/* AD4080 GPIOs */
enum ad4080_gpio {
    AD4080_GPIO_0,
    AD4080_GPIO_1,
    AD4080_GPIO_2,
    AD4080_GPIO_3,
    NUM_AD4080_GPIO
};
 
/* AD4080 GPIO Output Enable Selection */
enum ad4080_gpio_op_enable {
    AD4080_GPIO_INPUT,
    AD4080_GPIO_OUTPUT
};

enum ad4080_gpio_op_func_sel {
    AD4080_GPIO_ADI_NSPI_SDO_DATA,
    AD4080_GPIO_FIFO_FULL,
    AD4080_GPIO_FIFO_READ_DONE,
    AD4080_GPIO_FILTER_RESULT_READY,
    AD4080_GPIO_HT_DETECT,
    AD4080_GPIO_LT_DETECT,
    AD4080_GPIO_STATUS_ALERT,
    AD4080_GPIO_GPO_DATA,
    AD4080_GPIO_FILTER_SYNC_INPUT,
    AD4080_GPIO_EXT_EVENT_TRIGGER_FIFO,
    AD4080_GPIO_CNV_INHIBIT_INPUT
};

enum ad4080_fifo_mode {
    AD4080_FIFO_DISABLE,
    AD4080_IMMEDIATE_TRIGGER,
    AD4080_EVENT_TRIGGER_LAST_WM,
    AD4080_EVENT_TRIGGER,
};

enum ad4080_id {
    ID_AD4080,
    ID_AD4081,
    ID_AD4082,
    ID_AD4083,
    ID_AD4085,
    ID_AD4086,
    ID_AD4087,
    ID_AD4088,
    NUM_AD4080_DEVICES,
};

struct ad4080_chip_info {
    const char *name;
    uint16_t product_id;
    uint8_t num_bits;
    uint8_t lvds_cnv_clk_cnt_max;
};
 
extern const struct ad4080_chip_info ad4080_chip_info_tbl[NUM_AD4080_DEVICES];
 
struct ad4080_spi_desc {
    struct no_os_spi_desc *spi;
    struct no_os_gpio_desc *ss;
};
 
struct ad4080_gp_desc {
    enum ad4080_gpio_op_enable op_enable;
    enum ad4080_gpio_op_func_sel func_sel;
    struct no_os_gpio_desc *gp;
};

struct ad4080_dev {
    const struct ad4080_chip_info *chip_info;
    /* SPI */
    struct ad4080_spi_desc   cfg;
    struct ad4080_spi_desc   data;
    /* SPI 3-Wire Connection */
    bool spi3wire;
    enum ad4080_addr_asc addr_asc;
    enum ad4080_single_instr single_instr;
    enum ad4080_short_instr   short_instr;
    enum ad4080_op_mode op_mode;
    enum ad4080_strict_reg_access strict_reg;
    enum ad4080_intf_chk_en intf_chk_en;
    enum ad4080_cnv_spi_lvds_lanes cnv_spi_lvds_lanes;
    enum ad4080_conv_data_spi_lvds conv_data_spi_lvds;
    uint8_t lvds_cnv_clk_cnt;
    enum ad4080_lvds_self_clk_mode lvds_self_clk_mode;
    enum ad4080_lvds_cnv_clk_mode cnv_clk_mode;
    enum ad4080_lvds_vod lvds_vod;
    enum ad4080_ana_dig_ldo_pd ana_dig_ldo_pd;
    enum ad4080_intf_ldo_pd intf_ldo_pd;
    enum ad4080_fifo_mode fifo_mode;
    enum ad4080_gpio_op_enable gpio_op_enable[NUM_AD4080_GPIO];
    enum ad4080_gpio_op_func_sel gpio_op_func_sel[NUM_AD4080_GPIO];
    char __attribute__((aligned(16))) privdata[0];
};
 
struct ad4080_spi_init_param {
    struct no_os_spi_init_param *spi;
    struct no_os_gpio_init_param *ss;
};
 
struct ad4080_gp_init_param {
    enum ad4080_gpio_op_enable op_enable;
    enum ad4080_gpio_op_func_sel func_sel;
    struct no_os_gpio_init_param *gp;
};

struct ad4080_init_param {
    enum ad4080_id id;
    /* SPI */
    struct ad4080_spi_init_param cfg;
    struct ad4080_spi_init_param data;
    /* SPI 3-Wire Connection */
    bool spi3wire;
    enum ad4080_addr_asc addr_asc;
    enum ad4080_single_instr single_instr;
    enum ad4080_short_instr   short_instr;
    enum ad4080_op_mode op_mode;
    enum ad4080_strict_reg_access strict_reg;
    enum ad4080_intf_chk_en intf_chk_en;
    enum ad4080_cnv_spi_lvds_lanes cnv_spi_lvds_lanes;
    enum ad4080_conv_data_spi_lvds conv_data_spi_lvds;
    uint8_t lvds_cnv_clk_cnt;
    enum ad4080_lvds_self_clk_mode lvds_self_clk_mode;
    enum ad4080_lvds_cnv_clk_mode cnv_clk_mode;
    enum ad4080_lvds_vod lvds_vod;
    enum ad4080_ana_dig_ldo_pd ana_dig_ldo_pd;
    enum ad4080_intf_ldo_pd intf_ldo_pd;
    enum ad4080_fifo_mode fifo_mode;
    size_t privdata_len;
};

static inline void *ad4080_privdata(struct ad4080_dev *dev)
{
    if (!dev)
        return NULL;
    return dev->privdata;
}

int ad4080_read_data(struct ad4080_dev *dev, uint8_t *buf, size_t len);

int ad4080_write(struct ad4080_dev *dev, uint16_t reg_addr, uint8_t reg_val);

int ad4080_read(struct ad4080_dev *dev, uint16_t reg_addr, uint8_t *reg_val);

int ad4080_update_bits(struct ad4080_dev *dev, uint16_t reg_addr, uint8_t mask,
               uint8_t reg_val);

int ad4080_soft_reset(struct ad4080_dev *dev);

int ad4080_set_addr_asc(struct ad4080_dev *dev, enum ad4080_addr_asc addr_asc);

int ad4080_get_addr_asc(struct ad4080_dev *dev, enum ad4080_addr_asc *addr_asc);

int ad4080_set_single_instr(struct ad4080_dev *dev,
                enum ad4080_single_instr single_instr);

int ad4080_get_single_instr(struct ad4080_dev *dev,
                enum ad4080_single_instr *single_instr);

int ad4080_set_short_instr(struct ad4080_dev *dev,
               enum ad4080_short_instr short_instr);

int ad4080_get_short_instr(struct ad4080_dev *dev,
               enum ad4080_short_instr *short_instr);

int ad4080_set_op_mode(struct ad4080_dev *dev,
               enum ad4080_op_mode op_mode);

int ad4080_get_op_mode(struct ad4080_dev *dev,
               enum ad4080_op_mode *op_mode);

int ad4080_set_strict_reg_access(struct ad4080_dev *dev,
                 enum ad4080_strict_reg_access strict_reg);

int ad4080_get_strict_reg_access(struct ad4080_dev *dev,
                 enum ad4080_strict_reg_access *strict_reg);

int ad4080_set_intf_chk_en(struct ad4080_dev *dev,
               enum ad4080_intf_chk_en intf_chk_en);

int ad4080_get_intf_chk_en(struct ad4080_dev *dev,
               enum ad4080_intf_chk_en *intf_chk_en);

int ad4080_set_cnv_spi_lvds_lanes(struct ad4080_dev *dev,
                  enum ad4080_cnv_spi_lvds_lanes cnv_spi_lvds_lanes);

int ad4080_get_cnv_spi_lvds_lanes(struct ad4080_dev *dev,
                  enum ad4080_cnv_spi_lvds_lanes *cnv_spi_lvds_lanes);

int ad4080_set_conv_data_spi_lvds(struct ad4080_dev *dev,
                  enum ad4080_conv_data_spi_lvds conv_data_spi_lvds);

int ad4080_get_conv_data_spi_lvds(struct ad4080_dev *dev,
                  enum ad4080_conv_data_spi_lvds *conv_data_spi_lvds);

int ad4080_set_lvds_cnv_clk_cnt(struct ad4080_dev *dev,
                uint8_t lvds_cnv_clk_cnt);

int ad4080_get_lvds_cnv_clk_cnt(struct ad4080_dev *dev,
                uint8_t *lvds_cnv_clk_cnt);

int ad4080_set_lvds_self_clk_mode(struct ad4080_dev *dev,
                  enum ad4080_lvds_self_clk_mode lvds_self_clk_mode);

int ad4080_get_lvds_self_clk_mode(struct ad4080_dev *dev,
                  enum ad4080_lvds_self_clk_mode *lvds_self_clk_mode);
 

int ad4080_set_lvds_cnv_clk_mode(struct ad4080_dev *dev,
                 enum ad4080_lvds_cnv_clk_mode cnv_clk_mode);

int ad4080_get_lvds_cnv_clk_mode(struct ad4080_dev *dev,
                 enum ad4080_lvds_cnv_clk_mode *cnv_clk_mode);

int ad4080_set_lvds_vod(struct ad4080_dev *dev,
            enum ad4080_lvds_vod lvds_vod);

int ad4080_get_lvds_vod(struct ad4080_dev *dev, enum ad4080_lvds_vod *lvds_vod);

int ad4080_set_ana_dig_ldo_pd(struct ad4080_dev *dev,
                  enum ad4080_ana_dig_ldo_pd ana_dig_ldo_pd);

int ad4080_get_ana_dig_ldo_pd(struct ad4080_dev *dev,
                  enum ad4080_ana_dig_ldo_pd *ana_dig_ldo_pd);

int ad4080_set_intf_ldo_pd(struct ad4080_dev *dev,
               enum ad4080_intf_ldo_pd intf_ldo_pd);

int ad4080_get_intf_ldo_pd(struct ad4080_dev *dev,
               enum ad4080_intf_ldo_pd *intf_ldo_pd);

int ad4080_set_fifo_mode(struct ad4080_dev *dev,
             enum ad4080_fifo_mode fifo_mode);

int ad4080_get_fifo_mode(struct ad4080_dev *dev,
             enum ad4080_fifo_mode *fifo_mode);

int ad4080_set_fifo_watermark(struct ad4080_dev *dev,
                  uint16_t fifo_watermark);

int ad4080_get_fifo_watermark(struct ad4080_dev *dev,
                  uint16_t *fifo_watermark);

int ad4080_set_gpio_output_enable(struct ad4080_dev *dev,
                  enum ad4080_gpio gpio,
                  enum ad4080_gpio_op_enable gpio_op_enable);

int ad4080_set_gpio_output_func(struct ad4080_dev *dev,
                enum ad4080_gpio gpio,
                enum ad4080_gpio_op_func_sel gpio_func);

int ad4080_gpio_write_data(struct ad4080_dev *dev,
               enum ad4080_gpio gpio,
               bool data);

int ad4080_gpio_read_data(struct ad4080_dev *dev,
              enum ad4080_gpio gpio,
              bool *data);

int ad4080_configuration_intf_init(struct ad4080_dev *device,
                   struct ad4080_init_param init_param);

int ad4080_data_intf_init(struct ad4080_dev *device,
              struct ad4080_init_param init_param);

int ad4080_init(struct ad4080_dev **device,
        struct ad4080_init_param init_param);

int ad4080_remove(struct ad4080_dev *dev);
 
#endif /* __AD4080_H__ */