34#ifndef __PARAMETERS_H__
35#define __PARAMETERS_H__
37#include <xparameters.h>
44#define DCACHE_INVALIDATE Xil_DCacheInvalidateRange
46#define DMA_BASEADDR XPAR_AXI_AD469X_DMA_BASEADDR
47#define SPI_ENGINE_BASEADDR XPAR_SPI_AD469X_SPI_AD469X_AXI_REGMAP_BASEADDR
48#define RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR
49#define AXI_PWMGEN_BASEADDR XPAR_AD469X_TRIGGER_GEN_BASEADDR
50#define SPI_ENG_REF_CLK_FREQ_HZ XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ
52#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
54#define NUM_SAMPLES 2000
55#define BYTES_PER_SAMPLE 4
56#define MAX_CHANNELS 17
57#define ADC_DDR_BASEADDR XPAR_DDR_MEM_BASEADDR + 0x800000
58#define MAX_SIZE_BASE_ADDR (NUM_SAMPLES * BYTES_PER_SAMPLE * MAX_CHANNELS)
61#define UART_EXTRA &uart_extra_ip
62#define UART_OPS &xil_uart_ops
63#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
64#define UART_IRQ_ID XPAR_XUARTPS_1_INTR
65#define UART_BAUDRATE 115200
68#define PWM_OPS &axi_pwm_ops
69#define PWM_EXTRA &pwm_extra_ip
70#define PWM_PERIOD 1000
74#define GPIO_OPS &xil_gpio_ops
75#define GPIO_EXTRA &gpio_extra_ip
77#define GPIO_RESETN_1 GPIO_OFFSET + 32
78#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
81#define SPI_DEVICE_ID 0
82#define SPI_OPS &spi_eng_platform_ops
83#define SPI_EXTRA &spi_eng_extra_ip
85#define SPI_BAUDRATE 80000000
Structure holding the initialization parameters for axi PWM.
Definition axi_pwm_extra.h:44
Structure containing the init parameters needed by the SPI engine.
Definition spi_engine.h:71
Structure holding the initialization parameters for Xilinx platform specific GPIO parameters.
Definition xilinx_gpio.h:56
Structure holding the initialization parameters for Xilinx platform specific UART parameters.
Definition xilinx_uart.h:56