ad4858.h File Reference

#include <stdint.h>
#include <stdbool.h>
#include "no_os_util.h"
#include "no_os_spi.h"
#include "no_os_gpio.h"
#include "no_os_error.h"

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Go to the source code of this file.

Classes
struct	ad4858_conv_data
	ADC conversion data structure. More...
struct	ad4858_init_param
	AD4858 init parameters structure used for initializing the ad4858_dev. More...
struct	ad4858_dev
	AD4858 device descriptor. More...

Macros
#define	AD4858_R1B   (1ul << 16)
#define	AD4858_R2B   (2ul << 16)
#define	AD4858_R3B   (3ul << 16)
#define	AD4858_R4B   (4ul << 16)
#define	AD4858_LEN(x)
#define	AD4858_ADDR(x)
#define	AD4858_REG_INTERFACE_CONFIG_A   (AD4858_R1B | 0x00)
#define	AD4858_REG_INTERFACE_CONFIG_B   (AD4858_R1B | 0x01)
#define	AD4858_REG_DEVICE_CONFIG   (AD4858_R1B | 0x02)
#define	AD4858_REG_CHIP_TYPE   (AD4858_R1B | 0x03)
#define	AD4858_REG_PRODUCT_ID_L   (AD4858_R1B | 0x04)
#define	AD4858_REG_PRODUCT_ID_H   (AD4858_R1B | 0x05)
#define	AD4858_REG_CHIP_GRADE   (AD4858_R1B | 0x06)
#define	AD4858_REG_SCRATCH_PAD   (AD4858_R1B | 0x0A)
#define	AD4858_REG_SPI_REV   (AD4858_R1B | 0x0B)
#define	AD4858_REG_VENDOR_L   (AD4858_R1B | 0x0C)
#define	AD4858_REG_VENDOR_H   (AD4858_R1B | 0x0D)
#define	AD4858_REG_STREAM_MODE   (AD4858_R1B | 0x0E)
#define	AD4858_REG_TRANSFER_CONFIG   (AD4858_R1B | 0x0F)
#define	AD4858_REG_INTERFACE_CONFIG_C   (AD4858_R1B | 0x10)
#define	AD4858_REG_INTERFACE_STATUS_A   (AD4858_R1B | 0x11)
#define	AD4858_REG_SPI_CONFIG_D   (AD4858_R1B | 0x14)
#define	AD4858_REG_DEVICE_STATUS   (AD4858_R1B | 0x20)
#define	AD4858_REG_CH_OR_STATUS   (AD4858_R1B | 0x21)
#define	AD4858_REG_CH_UR_STATUS   (AD4858_R1B | 0x22)
#define	AD4858_REG_REGMAP_CRC   (AD4858_R2B | 0x23)
#define	AD4858_REG_DEVICE_CTRL   (AD4858_R1B | 0x25)
#define	AD4858_REG_PACKET   (AD4858_R1B | 0x26)
#define	AD4858_REG_OVERSAMPLE   (AD4858_R1B | 0x27)
#define	AD4858_REG_SEAMLESS_HDR   (AD4858_R1B | 0x28)
#define	AD4858_REG_CH_SLEEP   (AD4858_R1B | 0x29)
#define	AD4858_REG_CH_SOFTSPAN(chn)
#define	AD4858_REG_CH_OFFSET(chn)
#define	AD4858_REG_CH_GAIN(chn)
#define	AD4858_REG_CH_PHASE(chn)
#define	AD4858_REG_CH_OR(chn)
#define	AD4858_REG_CH_UR(chn)
#define	AD4858_REG_CH_TESTPAT(chn)
#define	AD4858_SW_RESET_MSK   NO_OS_BIT(7) | NO_OS_BIT(0)
#define	AD4858_SDO_ENABLE_MSK   NO_OS_BIT(4)
#define	AD4858_ADDR_ASCENSION_MSK   NO_OS_BIT(5)
#define	AD4858_SINGLE_INST_MSK   NO_OS_BIT(7)
#define	AD4858_OPERATING_MODES_MSK   NO_OS_GENMASK(1,0)
#define	AD4858_STATUS_BIT0_MSK   NO_OS_BIT(4)
#define	AD4858_STATUS_BIT1_MSK   NO_OS_BIT(5)
#define	AD4858_STATUS_BIT2_MSK   NO_OS_BIT(6)
#define	AD4858_STATUS_BIT3_MSK   NO_OS_BIT(7)
#define	AD4858_KEEP_STRM_LEN_MSK   NO_OS_BIT(2)
#define	AD4858_ACTIVE_INF_MODE_MSK   NO_OS_GENMASK(3,2)
#define	AD4858_CRC_ENABLE_MSK   NO_OS_GENMASK(7,6)
#define	AD4858_ADDR_INVALID_ERR_MSK   NO_OS_BIT(0)
#define	AD4858_WR_TO_RD_ONLY_ERR_MSK   NO_OS_BIT(2)
#define	AD4858_CRC_ERR_MSK   NO_OS_BIT(3)
#define	AD4858_CLK_COUNT_ERR_MSK   NO_OS_BIT(4)
#define	AD4858_NOT_READY_ERR_MSK   NO_OS_BIT(7)
#define	AD4858_CSDO_ON_SDO_MSK   NO_OS_BIT(0)
#define	AD4858_TEST_PATTERN_MSK   NO_OS_BIT(2)
#define	AD4858_PACKET_FORMAT_MSK   NO_OS_GENMASK(1,0)
#define	AD4858_OS_ENABLE_MSK   NO_OS_BIT(7)
#define	AD4858_OS_RATIO_MSK   NO_OS_GENMASK(3,0)
#define	AD4858_SOFTSPAN_MSK   NO_OS_GENMASK(3,0)
#define	AD4858_OR_UR_STATUS_MSK_16_BIT   NO_OS_BIT(7)
#define	AD4858_CHN_ID_MSK_16_BIT   NO_OS_GENMASK(6,4)
#define	AD4858_SOFTSPAN_ID_MSK_16_BIT   NO_OS_GENMASK(3,0)
#define	AD4858_OR_UR_STATUS_MSK_20_BIT   NO_OS_BIT(3)
#define	AD4858_CHN_ID_MSK_20_BIT   NO_OS_GENMASK(2,0)
#define	AD4858_SOFTSPAN_ID_MSK_20_BIT   NO_OS_GENMASK(7,4)
#define	AD4858_RAW_DATA_MSK_20_BIT   NO_OS_GENMASK(23,4)
#define	AD4858_RAW_DATA_MSK_EVEN_20_BIT   NO_OS_GENMASK(23,4)
#define	AD4858_RAW_DATA_MSK_ODD_20_BIT   NO_OS_GENMASK(19,0)
#define	AD4858_REG_RD_BIT_MSK   NO_OS_BIT(7)
#define	AD4858_PRODUCT_ID_L   0x60
#define	AD4857_PRODUCT_ID_L   0x61
#define	AD4856_PRODUCT_ID_L   0x62
#define	AD4855_PRODUCT_ID_L   0x63
#define	AD4854_PRODUCT_ID_L   0x64
#define	AD4853_PRODUCT_ID_L   0x65
#define	AD4852_PRODUCT_ID_L   0x66
#define	AD4851_PRODUCT_ID_L   0x67
#define	AD4858I_PRODUCT_ID_L   0x6F
#define	AD485X_PRODUCT_ID_H   0x00
#define	AD4858_NUM_CHANNELS   8
#define	AD4858_DEF_CHN_SOFTSPAN   0xf
#define	AD4858_DEF_CHN_OFFSET   0x0
#define	AD4858_DEF_CHN_GAIN   0x8000
#define	AD4858_DEF_CHN_PHASE   0x0
#define	AD4858_DEF_CHN_OR_16_BIT   0x7fff00
#define	AD4858_DEF_CHN_OR_20_BIT   0x7ffff0
#define	AD4858_DEF_CHN_UR   0x800000

Enumerations
enum	ad4858_prod_id {   AD4858_PROD_ID_L = 0x60 ,   AD4857_PROD_ID_L = 0x61 ,   AD4856_PROD_ID_L = 0x62 ,   AD4855_PROD_ID_L = 0x63 ,   AD4854_PROD_ID_L = 0x64 ,   AD4853_PROD_ID_L = 0x65 ,   AD4852_PROD_ID_L = 0x66 ,   AD4851_PROD_ID_L = 0x67 ,   AD4858I_PROD_ID_L = 0x6F }
	AD485X Product ID. More...
enum	ad4858_prod_res {   AD4858_16_BIT_RES ,   AD4858_20_BIT_RES }
	AD485X Product resolution. More...
enum	ad4858_operating_mode {   AD4858_NORMAL_OP_MODE = 0x0 ,   AD4858_LOW_POWER_OP_MODE = 0x3 ,   AD4858_NUM_OF_OP_MODES = 0x4 }
	Operating modes. More...
enum	ad4858_ch_sleep_value {   AD4858_SLEEP_DISABLE ,   AD4858_SLEEP_ENABLE }
	Enable/diable sleep. More...
enum	ad4858_ch_seamless_hdr {   AD4858_SEAMLESS_HDR_DISABLE ,   AD4858_SEAMLESS_HDR_ENABLE }
	Enable/diable seamless high dynamic range. More...
enum	ad4858_interface_mode {   AD4858_CONFIG_INTERFACE_MODE ,   AD4858_DATA_INTERFACE_MODE ,   AD4858_NUM_OF_INTF_MODES }
	Interface modes. More...
enum	ad4858_spi_data_mode {   AD4858_STREAMING_MODE ,   AD4858_SINGLE_INSTRUCTION_MODE ,   AD4858_NUM_OF_SPI_DATA_MODES }
	SPI data modes. More...
enum	ad4858_osr_ratio {   AD4858_OSR_2 ,   AD4858_OSR_4 ,   AD4858_OSR_8 ,   AD4858_OSR_16 ,   AD4858_OSR_32 ,   AD4858_OSR_64 ,   AD4858_OSR_128 ,   AD4858_OSR_256 ,   AD4858_OSR_512 ,   AD4858_OSR_1024 ,   AD4858_OSR_2048 ,   AD4858_OSR_4096 ,   AD4858_OSR_8192 ,   AD4858_OSR_16384 ,   AD4858_OSR_32768 ,   AD4858_OSR_65536 ,   AD4858_NUM_OF_OSR_RATIO }
	OSR ratio values. More...
enum	ad4858_packet_format {   AD4858_PACKET_16_BIT ,   AD4858_PACKET_20_BIT ,   AD4858_PACKET_24_BIT ,   AD4858_PACKET_32_BIT }
	Packet formats. More...
enum	ad4858_chn_softspan {   AD4858_RANGE_0V_TO_2_5V ,   AD4858_RANGE_NEG_2_5V_TO_POS_2_5V ,   AD4858_RANGE_0V_TO_5_0V ,   AD4858_RANGE_NEG_5_0V_TO_POS_5_0V ,   AD4858_RANGE_0V_TO_6_25V ,   AD4858_RANGE_NEG_6_25V_TO_POS_6_25V ,   AD4858_RANGE_0V_TO_10_0V ,   AD4858_RANGE_NEG_10_0V_TO_POS_10_0V ,   AD4858_RANGE_0V_TO_12_5V ,   AD4858_RANGE_NEG_12_5V_TO_POS_12_5V ,   AD4858_RANGE_0V_TO_20_0V ,   AD4858_RANGE_NEG_20_0V_TO_POS_20_0V ,   AD4858_RANGE_0V_TO_25_0V ,   AD4858_RANGE_NEG_25_0V_TO_POS_25_0V ,   AD4858_RANGE_0V_TO_40_0V ,   AD4858_RANGE_NEG_40_0V_TO_POS_40_0V ,   AD4858_NUM_OF_SOFTSPAN }
	Channel softspan. More...

Functions
int	ad4858_init (struct ad4858_dev **device, struct ad4858_init_param *init_param)
	Initialize an AD4858 device structure.
int	ad4858_remove (struct ad4858_dev *dev)
	Remove an AD4858 device (free memory allocated by ad4858_init function).
int	ad4858_reg_write (struct ad4858_dev *dev, uint32_t reg_addr, uint32_t reg_val)
	Write device register.
int	ad4858_reg_read (struct ad4858_dev *dev, uint32_t reg_addr, uint32_t *reg_val)
	Read device register.
int	ad4858_reg_mask (struct ad4858_dev *dev, uint32_t reg_addr, uint32_t mask, uint32_t reg_val)
	Update specific register bits of an input register.
int	ad4858_soft_reset (struct ad4858_dev *dev)
	Perform an AD4858 software reset.
int	ad4858_set_operating_mode (struct ad4858_dev *dev, enum ad4858_operating_mode mode)
	Set the device operating mode.
int	ad4858_set_spi_data_mode (struct ad4858_dev *dev, enum ad4858_spi_data_mode mode)
	Set the SPI data mode.
int	ad4858_set_config_interface_mode (struct ad4858_dev *dev)
	Set device config interface mode.
int	ad4858_set_data_interface_mode (struct ad4858_dev *dev)
	Set device data interface mode.
int	ad4858_enable_osr (struct ad4858_dev *dev, bool osr_status)
	Enable OSR.
int	ad4858_set_osr_ratio (struct ad4858_dev *dev, enum ad4858_osr_ratio osr_ratio)
	Set OSR ratio.
int	ad4858_set_packet_format (struct ad4858_dev *dev, enum ad4858_packet_format packet_format)
	Set packet format.
int	ad4858_enable_test_pattern (struct ad4858_dev *dev, bool test_pattern)
	Enable/Disable test pattern on ADC data output.
int	ad4858_set_chn_softspan (struct ad4858_dev *dev, uint8_t chn, enum ad4858_chn_softspan chn_softspan)
	Set channel softspan.
int	ad4858_set_chn_offset (struct ad4858_dev *dev, uint8_t chn, uint32_t offset)
	Set channel offset.
int	ad4858_set_chn_gain (struct ad4858_dev *dev, uint8_t chn, uint16_t gain)
	Set channel gain.
int	ad4858_set_chn_phase (struct ad4858_dev *dev, uint8_t chn, uint16_t phase)
	Set channel phase.
int	ad4858_set_chn_or_limit (struct ad4858_dev *dev, uint8_t chn, uint32_t or_limit)
	Set channel overrange (OR) limit.
int	ad4858_set_chn_ur_limit (struct ad4858_dev *dev, uint8_t chn, uint32_t ur_limit)
	Set channel underrange (UR) limit.
int	ad4858_convst (struct ad4858_dev *dev)
	Toggle the CNV pin to start a conversion.
int	ad4858_perform_conv (struct ad4858_dev *dev)
	Perform ADC conversion.
int	ad4858_spi_data_read (struct ad4858_dev *dev, struct ad4858_conv_data *data)
	Read ADC conversion data over SPI.
int	ad4858_read_data (struct ad4858_dev *dev, struct ad4858_conv_data *data)
	Read ADC data (for all channels).
int	ad4858_enable_ch_sleep (struct ad4858_dev *dev, uint8_t chn, enum ad4858_ch_sleep_value sleep_status)
	Enable/Disable channel sleep.
int	ad4858_enable_ch_seamless_hdr (struct ad4858_dev *dev, uint8_t chn, enum ad4858_ch_seamless_hdr seamless_hdr_status)
	Enable/Disable seamless hdr.

Macro Definition Documentation

AD4851_PRODUCT_ID_L

#define AD4851_PRODUCT_ID_L   0x67

AD4852_PRODUCT_ID_L

#define AD4852_PRODUCT_ID_L   0x66

AD4853_PRODUCT_ID_L

#define AD4853_PRODUCT_ID_L   0x65

AD4854_PRODUCT_ID_L

#define AD4854_PRODUCT_ID_L   0x64

AD4855_PRODUCT_ID_L

#define AD4855_PRODUCT_ID_L   0x63

AD4856_PRODUCT_ID_L

#define AD4856_PRODUCT_ID_L   0x62

AD4857_PRODUCT_ID_L

#define AD4857_PRODUCT_ID_L   0x61

AD4858_ACTIVE_INF_MODE_MSK

#define AD4858_ACTIVE_INF_MODE_MSK   NO_OS_GENMASK(3,2)

AD4858_REG_INTERFACE_CONFIG_C bit masks

AD4858_ADDR

#define AD4858_ADDR

(

x

)

Value:

((x) & 0xFFFF)

AD4858_ADDR_ASCENSION_MSK

#define AD4858_ADDR_ASCENSION_MSK   NO_OS_BIT(5)

AD4858_ADDR_INVALID_ERR_MSK

#define AD4858_ADDR_INVALID_ERR_MSK   NO_OS_BIT(0)

AD4858_REG_INTERFACE_STATUS_A bit masks

AD4858_CHN_ID_MSK_16_BIT

#define AD4858_CHN_ID_MSK_16_BIT   NO_OS_GENMASK(6,4)

AD4858_CHN_ID_MSK_20_BIT

#define AD4858_CHN_ID_MSK_20_BIT   NO_OS_GENMASK(2,0)

AD4858_CLK_COUNT_ERR_MSK

#define AD4858_CLK_COUNT_ERR_MSK   NO_OS_BIT(4)

AD4858_CRC_ENABLE_MSK

#define AD4858_CRC_ENABLE_MSK   NO_OS_GENMASK(7,6)

AD4858_CRC_ERR_MSK

#define AD4858_CRC_ERR_MSK   NO_OS_BIT(3)

AD4858_CSDO_ON_SDO_MSK

#define AD4858_CSDO_ON_SDO_MSK   NO_OS_BIT(0)

AD4858_REG_SPI_CONFIG_D bit masks

AD4858_DEF_CHN_GAIN

#define AD4858_DEF_CHN_GAIN   0x8000

AD4858_DEF_CHN_OFFSET

#define AD4858_DEF_CHN_OFFSET   0x0

AD4858_DEF_CHN_OR_16_BIT

#define AD4858_DEF_CHN_OR_16_BIT   0x7fff00

AD4858_DEF_CHN_OR_20_BIT

#define AD4858_DEF_CHN_OR_20_BIT   0x7ffff0

AD4858_DEF_CHN_PHASE

#define AD4858_DEF_CHN_PHASE   0x0

AD4858_DEF_CHN_SOFTSPAN

#define AD4858_DEF_CHN_SOFTSPAN   0xf

AD4858_DEF_CHN_UR

#define AD4858_DEF_CHN_UR   0x800000

AD4858_KEEP_STRM_LEN_MSK

#define AD4858_KEEP_STRM_LEN_MSK   NO_OS_BIT(2)

AD4858_REG_TRANSFER_CONFIG bit masks

AD4858_LEN

#define AD4858_LEN

(

x

)

Value:

((x) >> 16)

AD4858_NOT_READY_ERR_MSK

#define AD4858_NOT_READY_ERR_MSK   NO_OS_BIT(7)

AD4858_NUM_CHANNELS

#define AD4858_NUM_CHANNELS   8

AD4858_OPERATING_MODES_MSK

#define AD4858_OPERATING_MODES_MSK   NO_OS_GENMASK(1,0)

AD4858_REG_DEVICE_CONFIG bit masks

AD4858_OR_UR_STATUS_MSK_16_BIT

#define AD4858_OR_UR_STATUS_MSK_16_BIT   NO_OS_BIT(7)

Status bit masks for 16-bit resolution ADC

AD4858_OR_UR_STATUS_MSK_20_BIT

#define AD4858_OR_UR_STATUS_MSK_20_BIT   NO_OS_BIT(3)

Status bit masks for 20-bit resolution ADC

AD4858_OS_ENABLE_MSK

#define AD4858_OS_ENABLE_MSK   NO_OS_BIT(7)

AD4858_REG_OVERSAMPLE bit masks

AD4858_OS_RATIO_MSK

#define AD4858_OS_RATIO_MSK   NO_OS_GENMASK(3,0)

AD4858_PACKET_FORMAT_MSK

#define AD4858_PACKET_FORMAT_MSK   NO_OS_GENMASK(1,0)

AD4858_PRODUCT_ID_L

#define AD4858_PRODUCT_ID_L   0x60

AD4858_R1B

#define AD4858_R1B   (1ul << 16)

AD4858_R2B

#define AD4858_R2B   (2ul << 16)

AD4858_R3B

#define AD4858_R3B   (3ul << 16)

AD4858_R4B

#define AD4858_R4B   (4ul << 16)

AD4858_RAW_DATA_MSK_20_BIT

#define AD4858_RAW_DATA_MSK_20_BIT   NO_OS_GENMASK(23,4)

Raw data bit masks for 20-bit resolution ADC

AD4858_RAW_DATA_MSK_EVEN_20_BIT

#define AD4858_RAW_DATA_MSK_EVEN_20_BIT   NO_OS_GENMASK(23,4)

AD4858_RAW_DATA_MSK_ODD_20_BIT

#define AD4858_RAW_DATA_MSK_ODD_20_BIT   NO_OS_GENMASK(19,0)

AD4858_REG_CH_GAIN

#define AD4858_REG_CH_GAIN

(

chn

)

Value:

(AD4858_R2B | (0x2E + (0x12 * chn)))

AD4858_REG_CH_OFFSET

#define AD4858_REG_CH_OFFSET

(

chn

)

Value:

(AD4858_R3B | (0x2B + (0x12 * chn)))

AD4858_REG_CH_OR

#define AD4858_REG_CH_OR

(

chn

)

Value:

(AD4858_R3B | (0x32 + (0x12 * chn)))

AD4858_REG_CH_OR_STATUS

#define AD4858_REG_CH_OR_STATUS   (AD4858_R1B | 0x21)

AD4858_REG_CH_PHASE

#define AD4858_REG_CH_PHASE

(

chn

)

Value:

(AD4858_R2B | (0x30 + (0x12 * chn)))

AD4858_REG_CH_SLEEP

#define AD4858_REG_CH_SLEEP   (AD4858_R1B | 0x29)

AD4858_REG_CH_SOFTSPAN

#define AD4858_REG_CH_SOFTSPAN

(

chn

)

Value:

(AD4858_R1B | (0x2A + (0x12 * chn)))

AD4858_REG_CH_TESTPAT

#define AD4858_REG_CH_TESTPAT

(

chn

)

Value:

(AD4858_R4B | (0x38 + (0x12 * chn)))

AD4858_REG_CH_UR

#define AD4858_REG_CH_UR

(

chn

)

Value:

(AD4858_R3B | (0x35 + (0x12 * chn)))

AD4858_REG_CH_UR_STATUS

#define AD4858_REG_CH_UR_STATUS   (AD4858_R1B | 0x22)

AD4858_REG_CHIP_GRADE

#define AD4858_REG_CHIP_GRADE   (AD4858_R1B | 0x06)

AD4858_REG_CHIP_TYPE

#define AD4858_REG_CHIP_TYPE   (AD4858_R1B | 0x03)

AD4858_REG_DEVICE_CONFIG

#define AD4858_REG_DEVICE_CONFIG   (AD4858_R1B | 0x02)

AD4858_REG_DEVICE_CTRL

#define AD4858_REG_DEVICE_CTRL   (AD4858_R1B | 0x25)

AD4858_REG_DEVICE_STATUS

#define AD4858_REG_DEVICE_STATUS   (AD4858_R1B | 0x20)

AD4858_REG_INTERFACE_CONFIG_A

#define AD4858_REG_INTERFACE_CONFIG_A   (AD4858_R1B | 0x00)

Register definitions

AD4858_REG_INTERFACE_CONFIG_B

#define AD4858_REG_INTERFACE_CONFIG_B   (AD4858_R1B | 0x01)

AD4858_REG_INTERFACE_CONFIG_C

#define AD4858_REG_INTERFACE_CONFIG_C   (AD4858_R1B | 0x10)

AD4858_REG_INTERFACE_STATUS_A

#define AD4858_REG_INTERFACE_STATUS_A   (AD4858_R1B | 0x11)

AD4858_REG_OVERSAMPLE

#define AD4858_REG_OVERSAMPLE   (AD4858_R1B | 0x27)

AD4858_REG_PACKET

#define AD4858_REG_PACKET   (AD4858_R1B | 0x26)

AD4858_REG_PRODUCT_ID_H

#define AD4858_REG_PRODUCT_ID_H   (AD4858_R1B | 0x05)

AD4858_REG_PRODUCT_ID_L

#define AD4858_REG_PRODUCT_ID_L   (AD4858_R1B | 0x04)

AD4858_REG_RD_BIT_MSK

#define AD4858_REG_RD_BIT_MSK   NO_OS_BIT(7)

Miscellaneous Definitions

AD4858_REG_REGMAP_CRC

#define AD4858_REG_REGMAP_CRC   (AD4858_R2B | 0x23)

AD4858_REG_SCRATCH_PAD

#define AD4858_REG_SCRATCH_PAD   (AD4858_R1B | 0x0A)

AD4858_REG_SEAMLESS_HDR

#define AD4858_REG_SEAMLESS_HDR   (AD4858_R1B | 0x28)

AD4858_REG_SPI_CONFIG_D

#define AD4858_REG_SPI_CONFIG_D   (AD4858_R1B | 0x14)

AD4858_REG_SPI_REV

#define AD4858_REG_SPI_REV   (AD4858_R1B | 0x0B)

AD4858_REG_STREAM_MODE

#define AD4858_REG_STREAM_MODE   (AD4858_R1B | 0x0E)

AD4858_REG_TRANSFER_CONFIG

#define AD4858_REG_TRANSFER_CONFIG   (AD4858_R1B | 0x0F)

AD4858_REG_VENDOR_H

#define AD4858_REG_VENDOR_H   (AD4858_R1B | 0x0D)

AD4858_REG_VENDOR_L

#define AD4858_REG_VENDOR_L   (AD4858_R1B | 0x0C)

AD4858_SDO_ENABLE_MSK

#define AD4858_SDO_ENABLE_MSK   NO_OS_BIT(4)

AD4858_SINGLE_INST_MSK

#define AD4858_SINGLE_INST_MSK   NO_OS_BIT(7)

AD4858_REG_INTERFACE_CONFIG_B bit masks

AD4858_SOFTSPAN_ID_MSK_16_BIT

#define AD4858_SOFTSPAN_ID_MSK_16_BIT   NO_OS_GENMASK(3,0)

AD4858_SOFTSPAN_ID_MSK_20_BIT

#define AD4858_SOFTSPAN_ID_MSK_20_BIT   NO_OS_GENMASK(7,4)

AD4858_SOFTSPAN_MSK

#define AD4858_SOFTSPAN_MSK   NO_OS_GENMASK(3,0)

AD4858_REG_CH_SOFTSPAN bit masks

AD4858_STATUS_BIT0_MSK

#define AD4858_STATUS_BIT0_MSK   NO_OS_BIT(4)

AD4858_STATUS_BIT1_MSK

#define AD4858_STATUS_BIT1_MSK   NO_OS_BIT(5)

AD4858_STATUS_BIT2_MSK

#define AD4858_STATUS_BIT2_MSK   NO_OS_BIT(6)

AD4858_STATUS_BIT3_MSK

#define AD4858_STATUS_BIT3_MSK   NO_OS_BIT(7)

AD4858_SW_RESET_MSK

#define AD4858_SW_RESET_MSK   NO_OS_BIT(7) | NO_OS_BIT(0)

AD4858_REG_INTERFACE_CONFIG_A bit masks

AD4858_TEST_PATTERN_MSK

#define AD4858_TEST_PATTERN_MSK   NO_OS_BIT(2)

AD4858_REG_PACKET bit masks

AD4858_WR_TO_RD_ONLY_ERR_MSK

#define AD4858_WR_TO_RD_ONLY_ERR_MSK   NO_OS_BIT(2)

AD4858I_PRODUCT_ID_L

#define AD4858I_PRODUCT_ID_L   0x6F

AD485X_PRODUCT_ID_H

#define AD485X_PRODUCT_ID_H   0x00

Enumeration Type Documentation

ad4858_ch_seamless_hdr

enum ad4858_ch_seamless_hdr

Enable/diable seamless high dynamic range.

Enumerator
AD4858_SEAMLESS_HDR_DISABLE
AD4858_SEAMLESS_HDR_ENABLE

ad4858_ch_sleep_value

enum ad4858_ch_sleep_value

Enable/diable sleep.

Enumerator
AD4858_SLEEP_DISABLE
AD4858_SLEEP_ENABLE

ad4858_chn_softspan

enum ad4858_chn_softspan

Channel softspan.

Enumerator
AD4858_RANGE_0V_TO_2_5V
AD4858_RANGE_NEG_2_5V_TO_POS_2_5V
AD4858_RANGE_0V_TO_5_0V
AD4858_RANGE_NEG_5_0V_TO_POS_5_0V
AD4858_RANGE_0V_TO_6_25V
AD4858_RANGE_NEG_6_25V_TO_POS_6_25V
AD4858_RANGE_0V_TO_10_0V
AD4858_RANGE_NEG_10_0V_TO_POS_10_0V
AD4858_RANGE_0V_TO_12_5V
AD4858_RANGE_NEG_12_5V_TO_POS_12_5V
AD4858_RANGE_0V_TO_20_0V
AD4858_RANGE_NEG_20_0V_TO_POS_20_0V
AD4858_RANGE_0V_TO_25_0V
AD4858_RANGE_NEG_25_0V_TO_POS_25_0V
AD4858_RANGE_0V_TO_40_0V
AD4858_RANGE_NEG_40_0V_TO_POS_40_0V
AD4858_NUM_OF_SOFTSPAN

ad4858_interface_mode

enum ad4858_interface_mode

Interface modes.

Enumerator
AD4858_CONFIG_INTERFACE_MODE
AD4858_DATA_INTERFACE_MODE
AD4858_NUM_OF_INTF_MODES

ad4858_operating_mode

enum ad4858_operating_mode

Operating modes.

Enumerator
AD4858_NORMAL_OP_MODE
AD4858_LOW_POWER_OP_MODE
AD4858_NUM_OF_OP_MODES

ad4858_osr_ratio

enum ad4858_osr_ratio

OSR ratio values.

Enumerator
AD4858_OSR_2
AD4858_OSR_4
AD4858_OSR_8
AD4858_OSR_16
AD4858_OSR_32
AD4858_OSR_64
AD4858_OSR_128
AD4858_OSR_256
AD4858_OSR_512
AD4858_OSR_1024
AD4858_OSR_2048
AD4858_OSR_4096
AD4858_OSR_8192
AD4858_OSR_16384
AD4858_OSR_32768
AD4858_OSR_65536
AD4858_NUM_OF_OSR_RATIO

ad4858_packet_format

enum ad4858_packet_format

Packet formats.

Enumerator
AD4858_PACKET_16_BIT
AD4858_PACKET_20_BIT
AD4858_PACKET_24_BIT
AD4858_PACKET_32_BIT

ad4858_prod_id

enum ad4858_prod_id

AD485X Product ID.

Enumerator
AD4858_PROD_ID_L
AD4857_PROD_ID_L
AD4856_PROD_ID_L
AD4855_PROD_ID_L
AD4854_PROD_ID_L
AD4853_PROD_ID_L
AD4852_PROD_ID_L
AD4851_PROD_ID_L
AD4858I_PROD_ID_L

ad4858_prod_res

enum ad4858_prod_res

AD485X Product resolution.

Enumerator
AD4858_16_BIT_RES
AD4858_20_BIT_RES

ad4858_spi_data_mode

enum ad4858_spi_data_mode

SPI data modes.

Enumerator
AD4858_STREAMING_MODE
AD4858_SINGLE_INSTRUCTION_MODE
AD4858_NUM_OF_SPI_DATA_MODES

Function Documentation

ad4858_convst()

int ad4858_convst

(

struct ad4858_dev *

dev

)

Toggle the CNV pin to start a conversion.

Parameters

dev	- Pointer to the device structure.

Returns

0 in case of success, negative error code otherwise.

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ad4858_enable_ch_seamless_hdr()

int ad4858_enable_ch_seamless_hdr	(	struct ad4858_dev *	dev,
		uint8_t	chn,
		enum ad4858_ch_seamless_hdr	seamless_hdr_status )

Enable/Disable seamless hdr.

Parameters

dev	- Pointer to the device structure.
chn	- Input channel.
seamless_hdr_status	- seamless hdr status.

Returns

0 in case of success, negative error code otherwise.

ad4858_enable_ch_sleep()

int ad4858_enable_ch_sleep	(	struct ad4858_dev *	dev,
		uint8_t	chn,
		enum ad4858_ch_sleep_value	sleep_status )

Enable/Disable channel sleep.

Parameters

dev	- Pointer to the device structure.
chn	- Input channel.
sleep_status	- Sleep status.

Returns

0 in case of success, negative error code otherwise.

ad4858_enable_osr()

int ad4858_enable_osr	(	struct ad4858_dev *	dev,
		bool	osr_status )

Enable OSR.

Parameters

dev	- Pointer to the device structure.
osr_status	- OSR enable/disable status.

Returns

0 in case of success, negative error code otherwise.

ad4858_enable_test_pattern()

int ad4858_enable_test_pattern	(	struct ad4858_dev *	dev,
		bool	test_pattern )

Enable/Disable test pattern on ADC data output.

Parameters

dev	- Pointer to the device structure.
test_pattern	- Test pattern enable status.

Returns

0 in case of success, negative error code otherwise.

ad4858_init()

int ad4858_init	(	struct ad4858_dev **	device,
		struct ad4858_init_param *	init_param )

Initialize an AD4858 device structure.

Parameters

device	- Pointer to the device structure (memory is allocated within this function).
init_param	- Pointer to the initialization parameters.

Returns

0 in case of success, negative error code otherwise.

ad4858_perform_conv()

int ad4858_perform_conv

(

struct ad4858_dev *

dev

)

Perform ADC conversion.

Parameters

dev	- Pointer to the device structure.

Returns

0 in case of success, negative error code otherwise.

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ad4858_read_data()

int ad4858_read_data	(	struct ad4858_dev *	dev,
		struct ad4858_conv_data *	data )

Read ADC data (for all channels).

Parameters

dev	- Pointer to the device structure.
data	- Pointer to adc conversion data structure.

Returns

0 in case of success, negative error code otherwise.

ad4858_reg_mask()

int ad4858_reg_mask	(	struct ad4858_dev *	dev,
		uint32_t	reg_addr,
		uint32_t	mask,
		uint32_t	reg_val )

Update specific register bits of an input register.

Parameters

dev	- The device structure.
reg_addr	- The register address.
mask	- Specific bits mask.
reg_val	- The data to be written.

Returns

0 in case of success, negative error code otherwise.

Note

Multibyte read/write with streaming mode is supported by default.

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ad4858_reg_read()

int ad4858_reg_read	(	struct ad4858_dev *	dev,
		uint32_t	reg_addr,
		uint32_t *	reg_val )

Read device register.

Parameters

dev	- The device structure.
reg_addr	- The register address.
reg_val	- The data read from the register.

Returns

0 in case of success, negative error code otherwise.

Note

Multibyte read with streaming mode is supported by default.

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ad4858_reg_write()

int ad4858_reg_write	(	struct ad4858_dev *	dev,
		uint32_t	reg_addr,
		uint32_t	reg_val )

Write device register.

Parameters

dev-	The device structure.
reg_addr	- The register address.
reg_val	- The data to be written.

Returns

0 in case of success, negative error code otherwise.

Note

Multibyte write with streaming mode is supported by default.

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ad4858_remove()

int ad4858_remove

(

struct ad4858_dev *

dev

)

Remove an AD4858 device (free memory allocated by ad4858_init function).

Parameters

dev	- Pointer to the device structure.

Returns

0 in case of success, negative error code otherwise.

ad4858_set_chn_gain()

int ad4858_set_chn_gain	(	struct ad4858_dev *	dev,
		uint8_t	chn,
		uint16_t	gain )

Set channel gain.

Parameters

dev	- Pointer to the device structure.
chn	- Input channel.
gain	- Gain value.

Returns

0 in case of success, negative error code otherwise.

ad4858_set_chn_offset()

int ad4858_set_chn_offset	(	struct ad4858_dev *	dev,
		uint8_t	chn,
		uint32_t	offset )

Set channel offset.

Parameters

dev	- Pointer to the device structure.
chn	- Input channel.
offset	- Offset value.

Returns

0 in case of success, negative error code otherwise.

ad4858_set_chn_or_limit()

int ad4858_set_chn_or_limit	(	struct ad4858_dev *	dev,
		uint8_t	chn,
		uint32_t	or_limit )

Set channel overrange (OR) limit.

Parameters

dev	- Pointer to the device structure.
chn	- Input channel.
or_limit	- Overrange limit.

Returns

0 in case of success, negative error code otherwise.

ad4858_set_chn_phase()

int ad4858_set_chn_phase	(	struct ad4858_dev *	dev,
		uint8_t	chn,
		uint16_t	phase )

Set channel phase.

Parameters

dev	- Pointer to the device structure.
chn	- Input channel.
phase	- Phase value.

Returns

0 in case of success, negative error code otherwise.

ad4858_set_chn_softspan()

int ad4858_set_chn_softspan	(	struct ad4858_dev *	dev,
		uint8_t	chn,
		enum ad4858_chn_softspan	chn_softspan )

Set channel softspan.

Parameters

dev	- Pointer to the device structure.
chn	- Input channel.
chn_softspan	- Softspan value.

Returns

0 in case of success, negative error code otherwise.

ad4858_set_chn_ur_limit()

int ad4858_set_chn_ur_limit	(	struct ad4858_dev *	dev,
		uint8_t	chn,
		uint32_t	ur_limit )

Set channel underrange (UR) limit.

Parameters

dev	- Pointer to the device structure.
chn	- Input channel.
ur_limit	- Underrange limit.

Returns

0 in case of success, negative error code otherwise.

ad4858_set_config_interface_mode()

int ad4858_set_config_interface_mode

(

struct ad4858_dev *

dev

)

Set device config interface mode.

Parameters

dev	- Pointer to the device structure.

Returns

0 in case of success, negative error code otherwise.

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ad4858_set_data_interface_mode()

int ad4858_set_data_interface_mode

(

struct ad4858_dev *

dev

)

Set device data interface mode.

Parameters

dev	- Pointer to the device structure.

Returns

0 in case of success, negative error code otherwise.

ad4858_set_operating_mode()

int ad4858_set_operating_mode	(	struct ad4858_dev *	dev,
		enum ad4858_operating_mode	mode )

Set the device operating mode.

Parameters

dev	- Pointer to the device structure.
mode	- Operating mode.

Returns

0 in case of success, negative error code otherwise.

ad4858_set_osr_ratio()

int ad4858_set_osr_ratio	(	struct ad4858_dev *	dev,
		enum ad4858_osr_ratio	osr_ratio )

Set OSR ratio.

Parameters

dev	- Pointer to the device structure.
osr_ratio	- OSR ratio.

Returns

0 in case of success, negative error code otherwise.

ad4858_set_packet_format()

int ad4858_set_packet_format	(	struct ad4858_dev *	dev,
		enum ad4858_packet_format	packet_format )

Set packet format.

Parameters

dev	- Pointer to the device structure.
packet_format	- Packet format.

Returns

0 in case of success, negative error code otherwise.

ad4858_set_spi_data_mode()

int ad4858_set_spi_data_mode	(	struct ad4858_dev *	dev,
		enum ad4858_spi_data_mode	mode )

Set the SPI data mode.

Parameters

dev	- Pointer to the device structure.
mode	- SPI data mode.

Returns

0 in case of success, negative error code otherwise.

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ad4858_soft_reset()

int ad4858_soft_reset

(

struct ad4858_dev *

dev

)

Perform an AD4858 software reset.

Parameters

dev	- Pointer to the device structure.

Returns

0 in case of success, negative error code otherwise.

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ad4858_spi_data_read()

int ad4858_spi_data_read	(	struct ad4858_dev *	dev,
		struct ad4858_conv_data *	data )

Read ADC conversion data over SPI.

Parameters

dev	- Pointer to the device structure.
data	- Pointer to adc conversion data structure.

Returns

0 in case of success, negative error code otherwise.

Note

As this is a simultaneously sampling ADC, data for all channels is acquired/read in a single SPI read function call.

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