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39 #ifndef APP_PARAMETERS_H_
40 #define APP_PARAMETERS_H_
42 #include <xparameters.h>
47 #define UART_BAUDRATE 115200
49 #ifdef XPS_BOARD_ZCU102
50 #define GPIO_OFFSET 78
61 #define PHY_RESET (GPIO_OFFSET + 41)
63 #define ADRF5020_CTRL_GPIO (GPIO_OFFSET + 34)
64 #define AD9081_GPIO_0_MUX (GPIO_OFFSET + 44)
66 #define GPIO_2_DEVICE_ID XPAR_AXI_GPIO_2_DEVICE_ID
67 #define SPI_2_DEVICE_ID XPAR_AXI_SPI_2_DEVICE_ID
70 #define PHY_RESET (GPIO_OFFSET + 55)
73 #if defined(PLATFORM_MB)
74 #define GPIO_DEVICE_ID XPAR_AXI_GPIO_DEVICE_ID
75 #define PHY_SPI_DEVICE_ID XPAR_AXI_SPI_DEVICE_ID
76 #define CLK_SPI_DEVICE_ID XPAR_AXI_SPI_DEVICE_ID
77 #define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
78 #define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
79 #define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
80 #define DDR_CNTRL_BASEADDR XPAR_AXI_DDR_CNTRL_BASEADDR
82 #elif defined(PLATFORM_ZYNQMP)
83 #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
84 #define GPIO_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
85 #define PHY_SPI_DEVICE_ID XPAR_PSU_SPI_0_DEVICE_ID
86 #define CLK_SPI_DEVICE_ID XPAR_PSU_SPI_1_DEVICE_ID
87 #define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
88 #define UART_IRQ_ID XPAR_XUARTPS_0_INTR
89 #define DDR_CNTRL_BASEADDR XPAR_PSU_DDRC_0_BASEADDR
92 #error Unsupported platform.
95 #define RX_JESD_BASEADDR XPAR_AXI_MXFE_RX_JESD_RX_AXI_BASEADDR
96 #define TX_JESD_BASEADDR XPAR_AXI_MXFE_TX_JESD_TX_AXI_BASEADDR
98 #ifdef XPAR_AXI_MXFE_RX_XCVR_BASEADDR
99 #define RX_XCVR_BASEADDR XPAR_AXI_MXFE_RX_XCVR_BASEADDR
101 #ifdef XPAR_AXI_MXFE_TX_XCVR_BASEADDR
102 #define TX_XCVR_BASEADDR XPAR_AXI_MXFE_TX_XCVR_BASEADDR
105 #ifdef XPAR_RX_MXFE_TPL_CORE_ADC_TPL_CORE_BASEADDR
106 #define RX_CORE_BASEADDR XPAR_RX_MXFE_TPL_CORE_ADC_TPL_CORE_BASEADDR
108 #define RX_CORE_BASEADDR XPAR_RX_MXFE_TPL_CORE_TPL_CORE_BASEADDR
110 #ifdef XPAR_TX_MXFE_TPL_CORE_DAC_TPL_CORE_BASEADDR
111 #define TX_CORE_BASEADDR XPAR_TX_MXFE_TPL_CORE_DAC_TPL_CORE_BASEADDR
113 #define TX_CORE_BASEADDR XPAR_TX_MXFE_TPL_CORE_TPL_CORE_BASEADDR
116 #define RX_DMA_BASEADDR XPAR_AXI_MXFE_RX_DMA_BASEADDR
117 #define TX_DMA_BASEADDR XPAR_AXI_MXFE_TX_DMA_BASEADDR
121 #define MAX_DAC_BUF_SAMPLES 10000000 //1MB
122 #define MAX_ADC_BUF_SAMPLES 10000000 //1MB