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parameters.h
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1/***************************************************************************/
33#ifndef APP_PARAMETERS_H_
34#define APP_PARAMETERS_H_
35
36#include <xparameters.h>
37
38#define UART_BAUDRATE 115200
39
40#ifdef XPS_BOARD_ZCU102
41#define GPIO_OFFSET 78
42#else
43#define GPIO_OFFSET 0
44#endif
45
46#define PHY_CS 0
47
48#ifdef QUAD_MXFE
49#define ADF4371_CS 0
50#define HMC7043_CS 4
51
52#define PHY_RESET (GPIO_OFFSET + 41)
53
54#define ADRF5020_CTRL_GPIO (GPIO_OFFSET + 34)
55#define AD9081_GPIO_0_MUX (GPIO_OFFSET + 44)
56
57#define GPIO_2_DEVICE_ID XPAR_AXI_GPIO_2_DEVICE_ID
58#define SPI_2_DEVICE_ID XPAR_AXI_SPI_2_DEVICE_ID
59
60#else
61#define PHY_RESET (GPIO_OFFSET + 55)
62#endif
63
64#if defined(PLATFORM_MB)
65#define GPIO_DEVICE_ID XPAR_AXI_GPIO_DEVICE_ID
66#define PHY_SPI_DEVICE_ID XPAR_AXI_SPI_DEVICE_ID
67#define CLK_SPI_DEVICE_ID XPAR_AXI_SPI_DEVICE_ID
68#define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
69#define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
70#define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
71#define DDR_CNTRL_BASEADDR XPAR_AXI_DDR_CNTRL_BASEADDR
72#define CLK_CS 1
73#elif defined(PLATFORM_ZYNQMP)
74#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
75#define GPIO_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
76#define PHY_SPI_DEVICE_ID XPAR_PSU_SPI_0_DEVICE_ID
77#define CLK_SPI_DEVICE_ID XPAR_PSU_SPI_1_DEVICE_ID
78#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
79#define UART_IRQ_ID XPAR_XUARTPS_0_INTR
80#define DDR_CNTRL_BASEADDR XPAR_PSU_DDRC_0_BASEADDR
81#define CLK_CS 0
82#else
83#error Unsupported platform.
84#endif
85
86#define RX_JESD_BASEADDR XPAR_AXI_MXFE_RX_JESD_RX_AXI_BASEADDR
87#define TX_JESD_BASEADDR XPAR_AXI_MXFE_TX_JESD_TX_AXI_BASEADDR
88
89#ifdef XPAR_AXI_MXFE_RX_XCVR_BASEADDR
90#define RX_XCVR_BASEADDR XPAR_AXI_MXFE_RX_XCVR_BASEADDR
91#endif
92#ifdef XPAR_AXI_MXFE_TX_XCVR_BASEADDR
93#define TX_XCVR_BASEADDR XPAR_AXI_MXFE_TX_XCVR_BASEADDR
94#endif
95
96#ifdef XPAR_RX_MXFE_TPL_CORE_ADC_TPL_CORE_BASEADDR
97#define RX_CORE_BASEADDR XPAR_RX_MXFE_TPL_CORE_ADC_TPL_CORE_BASEADDR
98#else
99#define RX_CORE_BASEADDR XPAR_RX_MXFE_TPL_CORE_TPL_CORE_BASEADDR
100#endif
101#ifdef XPAR_TX_MXFE_TPL_CORE_DAC_TPL_CORE_BASEADDR
102#define TX_CORE_BASEADDR XPAR_TX_MXFE_TPL_CORE_DAC_TPL_CORE_BASEADDR
103#else
104#define TX_CORE_BASEADDR XPAR_TX_MXFE_TPL_CORE_TPL_CORE_BASEADDR
105#endif
106
107#define RX_DMA_BASEADDR XPAR_AXI_MXFE_RX_DMA_BASEADDR
108#define TX_DMA_BASEADDR XPAR_AXI_MXFE_TX_DMA_BASEADDR
109
110#ifdef IIO_SUPPORT
111
112#define MAX_DAC_BUF_SAMPLES 10000000 //1MB
113#define MAX_ADC_BUF_SAMPLES 10000000 //1MB
114
115#endif
116
117#endif