no-OS
ad9152.h
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1 /***************************************************************************/
33 #ifndef AD9152_H_
34 #define AD9152_H_
35 
36 /******************************************************************************/
37 /***************************** Include Files **********************************/
38 /******************************************************************************/
39 #include <stdint.h>
40 #include "no_os_delay.h"
41 #include "no_os_spi.h"
42 
43 /******************************************************************************/
44 /********************** Macros and Constants Definitions **********************/
45 /******************************************************************************/
46 #define REG_SPI_INTFCONFA 0x000 /* Interface configuration A */
47 #define REG_SPI_INTFCONFB 0x001 /* Interface configuration B */
48 #define REG_SPI_DEVCONF 0x002 /* Device Configuration */
49 #define REG_SPI_PRODIDL 0x004 /* Product Identification Low Byte */
50 #define REG_SPI_PRODIDH 0x005 /* Product Identification High Byte */
51 #define REG_SPI_CHIPGRADE 0x006 /* Chip Grade */
52 #define REG_SPI_PAGEINDX 0x008 /* Page Pointer or Device Index */
53 #define REG_SPI_DEVINDX2 0x009 /* Secondary Device Index */
54 #define REG_SPI_SCRATCHPAD 0x00A /* Scratch Pad */
55 #define REG_SPI_MS_UPDATE 0x00F /* Master/Slave Update Bit */
56 #define REG_PWRCNTRL0 0x011 /* Power Control Reg 1 */
57 #define REG_TXENMASK1 0x012 /* TXenable masks */
58 #define REG_PWRCNTRL3 0x013 /* Power control register 3 */
59 #define REG_COARSE_GROUP_DLY 0x014 /* Coarse Group Delay Adjustment */
60 #define REG_IRQ_ENABLE0 0x01F /* Interrupt Enable */
61 #define REG_IRQ_ENABLE1 0x020 /* Interrupt Enable */
62 #define REG_IRQ_ENABLE2 0x021 /* Interrupt Enable */
63 #define REG_IRQ_ENABLE3 0x022 /* Interrupt Enable */
64 #define REG_IRQ_STATUS0 0x023 /* Interrupt Status */
65 #define REG_IRQ_STATUS1 0x024 /* Interrupt Status */
66 #define REG_IRQ_STATUS2 0x025 /* Interrupt Status */
67 #define REG_IRQ_STATUS3 0x026 /* Interrupt Status */
68 #define REG_JESD_CHECKS 0x030 /* JESD Parameter Checking */
69 #define REG_SYNC_TESTCTRL 0x031 /* Sync Control Reg0 */
70 #define REG_SYNC_DACDELAY_L 0x032 /* Sync Logic DacDelay [7:0] */
71 #define REG_SYNC_DACDELAY_H 0x033 /* Sync Logic DacDelay [8] */
72 #define REG_SYNC_ERRWINDOW 0x034 /* Sync Error Window */
73 #define REG_SYNC_DLYCOUNT 0x035 /* Sync Control Ref Delay Count */
74 #define REG_SYNC_REFCOUNT 0x036 /* Sync SysRef InActive Interval */
75 #define REG_SYNC_LASTERR_L 0x038 /* SyncLASTerror_L */
76 #define REG_SYNC_LASTERR_H 0x039 /* SyncLASTerror_H */
77 #define REG_SYNC_CTRL 0x03A /* Sync Mode Control */
78 #define REG_SYNC_STATUS 0x03B /* Sync Alignment Flags */
79 #define REG_SYNC_CURRERR_L 0x03C /* Sync Alignment Error[7:0] */
80 #define REG_SYNC_CURRERR_H 0x03D /* Sync Alignment Error[8] */
81 #define REG_ERROR_THERM 0x03E /* Sync Error Thermometer */
82 #define REG_DACGAIN0_1 0x040 /* MSBs of Full Scale Adjust DAC */
83 #define REG_DACGAIN0_0 0x041 /* LSBs of Full Scale Adjust DAC */
84 #define REG_DACGAIN1_1 0x042 /* MSBs of Full Scale Adjust DAC */
85 #define REG_DACGAIN1_0 0x043 /* LSBs of Full Scale Adjust DAC */
86 #define REG_DACGAIN2_1 0x044 /* MSBs of Full Scale Adjust DAC */
87 #define REG_DACGAIN2_0 0x045 /* LSBs of Full Scale Adjust DAC */
88 #define REG_DACGAIN3_1 0x046 /* MSBs of Full Scale Adjust DAC */
89 #define REG_DACGAIN3_0 0x047 /* LSBs of Full Scale Adjust DAC */
90 #define REG_PD_DACLDO 0x048 /* Powerdown DAC LDOs */
91 #define REG_STAT_DACLDO 0x049 /* DAC LDO Status */
92 #define REG_DECODE_CTRL0 0x04B /* Decoder Control */
93 #define REG_DECODE_CTRL1 0x04C /* Decoder Control */
94 #define REG_DECODE_CTRL2 0x04D /* Decoder Control */
95 #define REG_DECODE_CTRL3 0x04E /* Decoder Control */
96 #define REG_NCO_CLRMODE 0x050 /* NCO CLR Mode */
97 #define REG_NCOKEY_ILSB 0x051 /* NCO Clear on Data Key I lsb */
98 #define REG_NCOKEY_IMSB 0x052 /* NCO Clear on Data Key I msb */
99 #define REG_NCOKEY_QLSB 0x053 /* NCO Clear on Data Key Q lsb */
100 #define REG_NCOKEY_QMSB 0x054 /* NCO Clear on Data Key Q msb */
101 #define REG_PA_THRES0 0x060 /* PDP Threshold */
102 #define REG_PA_THRES1 0x061 /* PDP Threshold */
103 #define REG_PA_AVG_TIME 0x062 /* PDP Control */
104 #define REG_PA_POWER0 0x063 /* PDP Power */
105 #define REG_PA_POWER1 0x064 /* PDP Power */
106 #define REG_CLKCFG0 0x080 /* Clock Configuration */
107 #define REG_SYSREF_ACTRL0 0x081 /* SYSREF Analog Control 0 */
108 #define REG_SYSREF_ACTRL1 0x082 /* SYSREF Analog Control 1 */
109 #define REG_DACPLLCNTRL 0x083 /* Top Level Control DAC Clock PLL */
110 #define REG_DACPLLSTATUS 0x084 /* DAC PLL Status Bits */
111 #define REG_DACINTEGERWORD0 0x085 /* Feedback divider tuning word */
112 #define REG_DACLOOPFILT1 0x087 /* C1 and C2 control */
113 #define REG_DACLOOPFILT2 0x088 /* R1 and C3 control */
114 #define REG_DACLOOPFILT3 0x089 /* Bypass and R2 control */
115 #define REG_DACCPCNTRL 0x08A /* Charge Pump/Cntrl Voltage */
116 #define REG_DACLOGENCNTRL 0x08B /* Logen Control */
117 #define REG_DACLDOCNTRL1 0x08C /* LDO Control1 + Reference Divider */
118 #define REG_CAL_DAC_ERR 0x0E0 /* Report DAC Cal errors */
119 #define REG_CAL_MSB_THRES 0x0E1 /* MSB sweep Threshold definition */
120 #define REG_CAL_CTRL_GLOBAL 0x0E2 /* Global Calibration DAC Control */
121 #define REG_CAL_MSBHILVL 0x0E3 /* High Level for MSB level compare */
122 #define REG_CAL_MSBLOLVL 0x0E4 /* Low Level for MSB level compare */
123 #define REG_CAL_THRESH 0x0E5 /* TAC Threshold definition */
124 #define REG_CAL_AVG_CNT 0x0E6 /* CAL DAC Number of averages */
125 #define REG_CAL_CLKDIV 0x0E7 /* Calibration DAC clock divide */
126 #define REG_CAL_INDX 0x0E8 /* Calibration DAC Select */
127 #define REG_CAL_CTRL 0x0E9 /* Calibration DAC Control */
128 #define REG_CAL_ADDR 0x0EA /* Calibration DAC Address */
129 #define REG_CAL_DATA 0x0EB /* Calibration DAC Data */
130 #define REG_CAL_UPDATE 0x0EC /* Calibration DAC Write Update */
131 #define REG_DATA_FORMAT 0x110 /* Data format */
132 #define REG_DATAPATH_CTRL 0x111 /* Datapath Control */
133 #define REG_INTERP_MODE 0x112 /* Interpolation Mode */
134 #define REG_NCO_FTW_UPDATE 0x113 /* NCO Frequency Tuning Word Update */
135 #define REG_FTW0 0x114 /* NCO Frequency Tuning Word LSB */
136 #define REG_FTW1 0x115 /* NCO Frequency Tuning Word */
137 #define REG_FTW2 0x116 /* NCO Frequency Tuning Word */
138 #define REG_FTW3 0x117 /* NCO Frequency Tuning Word */
139 #define REG_FTW4 0x118 /* NCO Frequency Tuning Word */
140 #define REG_FTW5 0x119 /* NCO Frequency Tuning Word MSB */
141 #define REG_NCO_PHASE_OFFSET0 0x11A /* NCO Phase Offset LSB */
142 #define REG_NCO_PHASE_OFFSET1 0x11B /* NCO Phase Offset MSB */
143 #define REG_NCO_PHASE_ADJ0 0x11C /* I/Q Phase Adjust LSB */
144 #define REG_NCO_PHASE_ADJ1 0x11D /* I/Q Phase Adjust MSB */
145 #define REG_TXEN_FUNC 0x11E /* Transmit Enable function */
146 #define REG_TXEN_SM_0 0x11F /* Transmit enable power control state machine */
147 #define REG_TXEN_SM_1 0x120 /* Rise and fall */
148 #define REG_TXEN_SM_2 0x121 /* Transmit enable maximum A */
149 #define REG_TXEN_SM_3 0x122 /* Transmit enable maximum B */
150 #define REG_TXEN_SM_4 0x123 /* Transmit enable maximum C */
151 #define REG_TXEN_SM_5 0x124 /* Transmit enable maximum D */
152 #define REG_DACOUT_ON_DOWN 0x125 /* DAC out down control and on trigger */
153 #define REG_DACOFF 0x12C /* DAC Shutdown Source */
154 #define REG_DATA_PATH_FLUSH_COUNT0 0x12D /* Data path flush counter LSB */
155 #define REG_DATA_PATH_FLUSH_COUNT1 0x12E /* Data path flush counter MSB */
156 #define REG_DIE_TEMP_CTRL0 0x12F /* Die Temp Range Control */
157 #define REG_DIE_TEMP_CTRL1 0x130 /* Die temperature control register */
158 #define REG_DIE_TEMP_CTRL2 0x131 /* Die temperature control register */
159 #define REG_DIE_TEMP0 0x132 /* Die temp LSB */
160 #define REG_DIE_TEMP1 0x133 /* Die Temp MSB */
161 #define REG_DIE_TEMP_UPDATE 0x134 /* Die temperature update */
162 #define REG_DC_OFFSET_CTRL 0x135 /* DC Offset Control */
163 #define REG_IPATH_DC_OFFSET_1PART0 0x136 /* LSB of first part of DC Offset value for I path */
164 #define REG_IPATH_DC_OFFSET_1PART1 0x137 /* MSB of first part of DC Offset value for I path */
165 #define REG_QPATH_DC_OFFSET_1PART0 0x138 /* LSB of first part of DC Offset value for Q path */
166 #define REG_QPATH_DC_OFFSET_1PART1 0x139 /* MSB of first part of DC Offset value for Q path */
167 #define REG_IPATH_DC_OFFSET_2PART 0x13A /* Second part of DC Offset value for I path */
168 #define REG_QPATH_DC_OFFSET_2PART 0x13B /* Second part of DC Offset value for Q path */
169 #define REG_IDAC_DIG_GAIN0 0x13C /* I DAC Gain LSB */
170 #define REG_IDAC_DIG_GAIN1 0x13D /* I DAC Gain MSB */
171 #define REG_QDAC_DIG_GAIN0 0x13E /* Q DAC Gain LSB */
172 #define REG_QDAC_DIG_GAIN1 0x13F /* Q DAC Gain MSB */
173 #define REG_GAIN_RAMP_UP_STP0 0x140 /* LSB of digital gain rises */
174 #define REG_GAIN_RAMP_UP_STP1 0x141 /* MSB of digital gain rises */
175 #define REG_GAIN_RAMP_DOWN_STP0 0x142 /* LSB of digital gain drops */
176 #define REG_GAIN_RAMP_DOWN_STP1 0x143 /* MSB of digital gain drops */
177 #define REG_BLSM_CTRL 0x146 /* Blanking SM control and func */
178 #define REG_BLSM_STAT 0x147 /* Blanking SM control and func */
179 #define REG_PRBS 0x14B /* PRBS Input Data Checker */
180 #define REG_PRBS_ERROR_I 0x14C /* PRBS Error Counter Real */
181 #define REG_PRBS_ERROR_Q 0x14D /* PRBS Error Counter Imaginary */
182 #define REG_DACPLLT5 0x1B5 /* ALC/Varactor control */
183 #define REG_DACPLLTB 0x1BB /* VCO Bias Control */
184 #define REG_DACPLLTD 0x1BD /* VCO Cal control */
185 #define REG_DACPLLT17 0x1C4 /* Varactor ControlV */
186 #define REG_ASPI_SPARE0 0x1C6 /* Spare Register 0 */
187 #define REG_ASPI_SPARE1 0x1C7 /* Spare Register 1 */
188 #define REG_SPISTRENGTH 0x1DF /* Reg 70 Description */
189 #define REG_CLK_TEST 0x1EB /* Clock related control signaling */
190 #define REG_ATEST_VOLTS 0x1EC /* Analog Test Voltage Extraction */
191 #define REG_ASPI_CLKSRC 0x1ED /* Analog Spi clock source for PD machines */
192 #define REG_MASTER_PD 0x200 /* Master power down for Receiver PHYx */
193 #define REG_PHY_PD 0x201 /* Power down for individual Receiver PHYx */
194 #define REG_GENERIC_PD 0x203 /* Miscellaneous power down controls */
195 #define REG_CDR_OPERATING_MODE_REG_0 0x230 /* Clock and data recovery operating modes */
196 #define REG_EQ_CONFIG_PHY_0_1 0x250 /* Equalizer configuration for PHY 0 and PHY 1 */
197 #define REG_EQ_CONFIG_PHY_2_3 0x251 /* Equalizer configuration for PHY 2 and PHY 3 */
198 #define REG_EQ_CONFIG_PHY_4_5 0x252 /* Equalizer configuration for PHY 4 and PHY 5 */
199 #define REG_EQ_CONFIG_PHY_6_7 0x253 /* Equalizer configuration for PHY 6 and PHY 7 */
200 #define REG_EQ_BIAS_REG 0x268 /* Equalizer bias control */
201 #define REG_SYNTH_ENABLE_CNTRL 0x280 /* Rx PLL enable controls */
202 #define REG_PLL_STATUS 0x281 /* Rx PLL status readbacks */
203 #define REG_REF_CLK_DIVIDER_LDO 0x289 /* Rx PLL LDO control */
204 #define REG_TERM_BLK1_CTRLREG0 0x2A7 /* Termination controls for PHYs 0, 1, 6, and 7 */
205 #define REG_TERM_BLK1_CTRLREG1 0x2A8 /* Termination controls for PHYs 0, 1, 6, and 7 */
206 #define REG_TERM_BLK2_CTRLREG0 0x2AE /* Termination controls for PHYs 2, 3, 4, and 5 */
207 #define REG_TERM_BLK2_CTRLREG1 0x2AF /* Termination controls for PHYs 2, 3, 4, and 5 */
208 #define REG_GENERAL_JRX_CTRL_0 0x300 /* General JRX Control Register 0 */
209 #define REG_GENERAL_JRX_CTRL_1 0x301 /* General JRX Control Register 1 */
210 #define REG_DYN_LINK_LATENCY_0 0x302 /* Register 1 description */
211 #define REG_DYN_LINK_LATENCY_1 0x303 /* Register 2 description */
212 #define REG_LMFC_DELAY_0 0x304 /* Register 3 description */
213 #define REG_LMFC_DELAY_1 0x305 /* Register 4 description */
214 #define REG_LMFC_VAR_0 0x306 /* Register 5 description */
215 #define REG_LMFC_VAR_1 0x307 /* Register 6 description */
216 #define REG_XBAR_LN_0_1 0x308 /* Register 7 description */
217 #define REG_XBAR_LN_2_3 0x309 /* Register 8 description */
218 #define REG_XBAR_LN_4_5 0x30A /* Register 9 description */
219 #define REG_XBAR_LN_6_7 0x30B /* Register 10 description */
220 #define REG_FIFO_STATUS_REG_0 0x30C /* Register 11 description */
221 #define REG_FIFO_STATUS_REG_1 0x30D /* Register 12 description */
222 #define REG_FIFO_STATUS_REG_2 0x30E /* Register 13 description */
223 #define REG_SYNCB_GEN_0 0x311 /* Register 16 description */
224 #define REG_SYNCB_GEN_1 0x312 /* Register 17 description */
225 #define REG_SYNCB_GEN_3 0x313 /* Register 18 description */
226 #define REG_PHY_PRBS_TEST_EN 0x315 /* PHY PRBS TEST ENABLE FOR INDIVIDUAL LANES */
227 #define REG_PHY_PRBS_TEST_CTRL 0x316 /* Reg 20 Description */
228 #define REG_PHY_PRBS_TEST_THRESH_LOBITS 0x317 /* Reg 21 Description */
229 #define REG_PHY_PRBS_TEST_THRESH_MIDBITS 0x318 /* Reg 22 Description */
230 #define REG_PHY_PRBS_TEST_THRESH_HIBITS 0x319 /* Reg 23 Description */
231 #define REG_PHY_PRBS_TEST_ERRCNT_LOBITS 0x31A /* Reg 24 Description */
232 #define REG_PHY_PRBS_TEST_ERRCNT_MIDBITS 0x31B /* Reg 25 Description */
233 #define REG_PHY_PRBS_TEST_ERRCNT_HIBITS 0x31C /* Reg 26 Description */
234 #define REG_PHY_PRBS_TEST_STATUS 0x31D /* Reg 27 Description */
235 #define REG_SHORT_TPL_TEST_0 0x32C /* Reg 46 Description */
236 #define REG_SHORT_TPL_TEST_1 0x32D /* Reg 47 Description */
237 #define REG_SHORT_TPL_TEST_2 0x32E /* Reg 48 Description */
238 #define REG_SHORT_TPL_TEST_3 0x32F /* Reg 49 Description */
239 #define REG_JESD_BIT_INVERSE_CTRL 0x334 /* Reg 42 Description */
240 #define REG_DID_REG 0x400 /* Reg 0 Description */
241 #define REG_BID_REG 0x401 /* Reg 1 Description */
242 #define REG_LID0_REG 0x402 /* Reg 2 Description */
243 #define REG_SCR_L_REG 0x403 /* Reg 3 Description */
244 #define REG_F_REG 0x404 /* Reg 4 Description */
245 #define REG_K_REG 0x405 /* Reg 5 Description */
246 #define REG_M_REG 0x406 /* Reg 6 Description */
247 #define REG_CS_N_REG 0x407 /* Reg 7 Description */
248 #define REG_NP_REG 0x408 /* Reg 8 Description */
249 #define REG_S_REG 0x409 /* Reg 9 Description */
250 #define REG_HD_CF_REG 0x40A /* Reg 10 Description */
251 #define REG_RES1_REG 0x40B /* Reg 11 Description */
252 #define REG_RES2_REG 0x40C /* Reg 12 Description */
253 #define REG_CHECKSUM_REG 0x40D /* Reg 13 Description */
254 #define REG_COMPSUM0_REG 0x40E /* Reg 14 Description */
255 #define REG_LID1_REG 0x412 /* Reg 18 Description */
256 #define REG_CHECKSUM1_REG 0x415 /* Reg 19 Description */
257 #define REG_COMPSUM1_REG 0x416 /* Reg 22 Description */
258 #define REG_LID2_REG 0x41A /* Reg 26 Description */
259 #define REG_CHECKSUM2_REG 0x41D /* Reg 29 Description */
260 #define REG_COMPSUM2_REG 0x41E /* Reg 30 Description */
261 #define REG_LID3_REG 0x422 /* Reg 34 Description */
262 #define REG_CHECKSUM3_REG 0x425 /* Reg 37 Description */
263 #define REG_COMPSUM3_REG 0x426 /* Reg 38 Description */
264 #define REG_LID4_REG 0x42A /* Reg 34 Description */
265 #define REG_CHECKSUM4_REG 0x42D /* Reg 37 Description */
266 #define REG_COMPSUM4_REG 0x42E /* Reg 38 Description */
267 #define REG_LID5_REG 0x432 /* Reg 34 Description */
268 #define REG_CHECKSUM5_REG 0x435 /* Reg 37 Description */
269 #define REG_COMPSUM5_REG 0x436 /* Reg 38 Description */
270 #define REG_LID6_REG 0x43A /* Reg 34 Description */
271 #define REG_CHECKSUM6_REG 0x43D /* Reg 37 Description */
272 #define REG_COMPSUM6_REG 0x43E /* Reg 38 Description */
273 #define REG_LID7_REG 0x442 /* Reg 34 Description */
274 #define REG_CHECKSUM7_REG 0x445 /* Reg 37 Description */
275 #define REG_COMPSUM7_REG 0x446 /* Reg 38 Description */
276 #define REG_ILS_DID 0x450 /* Reg 80 Description */
277 #define REG_ILS_BID 0x451 /* Reg 81 Description */
278 #define REG_ILS_LID0 0x452 /* Reg 82 Description */
279 #define REG_ILS_SCR_L 0x453 /* Reg 83 Description */
280 #define REG_ILS_K 0x455 /* Reg 85 Description */
281 #define REG_ILS_M 0x456 /* Reg 86 Description */
282 #define REG_ILS_CS_N 0x457 /* Reg 87 Description */
283 #define REG_ILS_NP 0x458 /* Reg 88 Description */
284 #define REG_ILS_S 0x459 /* Reg 89 Description */
285 #define REG_ILS_HD_CF 0x45A /* Reg 90 Description */
286 #define REG_ILS_RES1 0x45B /* Reg 91 Description */
287 #define REG_ILS_RES2 0x45C /* Reg 92 Description */
288 #define REG_ILS_CHECKSUM 0x45D /* Reg 93 Description */
289 #define REG_ERRCNTRMON 0x46B /* Reg 107 Description */
290 #define REG_LANEDESKEW 0x46C /* Reg 108 Description */
291 #define REG_BADDISPARITY 0x46D /* Reg 109 Description */
292 #define REG_NITDISPARITY 0x46E /* Reg 110 Description */
293 #define REG_UNEXPECTEDKCHAR 0x46F /* Reg 111 Description */
294 #define REG_CODEGRPSYNCFLG 0x470 /* Reg 112 Description */
295 #define REG_FRAMESYNCFLG 0x471 /* Reg 113 Description */
296 #define REG_GOODCHKSUMFLG 0x472 /* Reg 114 Description */
297 #define REG_INITLANESYNCFLG 0x473 /* Reg 115 Description */
298 #define REG_CTRLREG1 0x476 /* Reg 118 Description */
299 #define REG_CTRLREG2 0x477 /* Reg 119 Description */
300 #define REG_KVAL 0x478 /* Reg 120 Description */
301 #define REG_IRQVECTOR 0x47A /* Reg 122 Description */
302 #define REG_SYNCASSERTIONMASK 0x47B /* Reg 123 Description */
303 #define REG_ERRORTHRES 0x47C /* Reg 124 Description */
304 #define REG_LANEENABLE 0x47D /* Reg 125 Description */
305 
306 /*
307  * REG_SPI_INTFCONFA
308  */
309 #define SOFTRESET_M (1 << 7) /* Soft Reset (Mirror) */
310 #define LSBFIRST_M (1 << 6) /* LSB First (Mirror) */
311 #define ADDRINC_M (1 << 5) /* Address Increment (Mirror) */
312 #define SDOACTIVE_M (1 << 4) /* SDO Active (Mirror) */
313 #define SDOACTIVE (1 << 3) /* SDO Active */
314 #define ADDRINC (1 << 2) /* Address Increment */
315 #define LSBFIRST (1 << 1) /* LSB First */
316 #define SOFTRESET (1 << 0) /* Soft Reset */
317 
318 /*
319  * REG_SPI_INTFCONFB
320  */
321 #define SINGLEINS (1 << 7) /* Single Instruction */
322 #define CSBSTALL (1 << 6) /* CSb Stalling */
323 
324 /*
325  * REG_SPI_DEVCONF
326  */
327 #define DEVSTATUS(x) (((x) & 0xF) << 4) /* Device Status */
328 #define CUSTOPMODE(x) (((x) & 0x3) << 2) /* Customer Operating Mode */
329 #define SYSOPMODE(x) (((x) & 0x3) << 0) /* System Operating Mode */
330 
331 /*
332  * REG_SPI_CHIPGRADE
333  */
334 #define PROD_GRADE(x) (((x) & 0xF) << 4) /* Product Grade */
335 #define DEV_REVISION(x) (((x) & 0xF) << 0) /* Device Revision */
336 
337 /*
338  * REG_SPI_PAGEINDX
339  */
340 #define PAGEINDX(x) (((x) & 0x3) << 0) /* Page or Index Pointer */
341 
342 /*
343  * REG_SPI_MS_UPDATE
344  */
345 #define SLAVEUPDATE (1 << 0) /* M/S Update Bit */
346 
347 /*
348  * REG_PWRCNTRL0
349  */
350 #define PD_BG (1 << 7) /* Reference PowerDown */
351 #define PD_DAC_0 (1 << 6) /* PD Ichannel DAC 0 */
352 #define PD_DAC_1 (1 << 5) /* PD Qchannel DAC 1 */
353 #define PD_DAC_2 (1 << 4) /* PD Ichannel DAC 2 */
354 #define PD_DAC_3 (1 << 3) /* PD Qchannel DAC 3 */
355 #define PD_DACM (1 << 2) /* PD Dac master Bias */
356 
357 /*
358  * REG_TXENMASK1
359  */
360 #define SYS_MASK (1 << 2) /* SYSREF Receiver TXen mask */
361 #define DACB_MASK (1 << 1) /* Dual B Dac TXen1 mask */
362 #define DACA_MASK (1 << 0) /* Dual A Dac TXen0 mask */
363 
364 /*
365  * REG_PWRCNTRL3
366  */
367 #define ENA_PA_CTRL_FROM_PAPROT_ERR (1 << 6) /* Control PDP enable from PAProt block */
368 #define ENA_PA_CTRL_FROM_TXENSM (1 << 5) /* Control PDP enable from Txen State machine */
369 #define ENA_PA_CTRL_FROM_BLSM (1 << 4) /* Control PDP enable from Blanking state machine */
370 #define ENA_PA_CTRL_FROM_SPI (1 << 3) /* Control PDP enable via SPI */
371 #define SPI_PA_CTRL (1 << 2) /* PDP on/off via SPI */
372 #define ENA_SPI_TXEN (1 << 1) /* TXEN from SPI control */
373 #define SPI_TXEN (1 << 0) /* Spi TXEN */
374 
375 /*
376  * REG_COARSE_GROUP_DLY
377  */
378 #define COARSE_GROUP_DLY(x) (((x) & 0xF) << 0) /* Coarse group delay */
379 
380 /*
381  * REG_IRQ_ENABLE0
382  */
383 #define EN_CALPASS (1 << 7) /* Enable Calib PASS detection */
384 #define EN_CALFAIL (1 << 6) /* Enable Calib FAIL detection */
385 #define EN_DACPLLLOST (1 << 5) /* Enable DAC Pll Lost detection */
386 #define EN_DACPLLLOCK (1 << 4) /* Enable DAC Pll Lock detection */
387 #define EN_SERPLLLOST (1 << 3) /* Enable Serdes PLL Lost detection */
388 #define EN_SERPLLLOCK (1 << 2) /* Enable Serdes PLL Lock detection */
389 #define EN_LANEFIFOERR (1 << 1) /* Enable Lane FIFO Error detection */
390 #define EN_DRDLFIFOERR (1 << 0) /* Enable DRDL FIFO Error detection */
391 
392 /*
393  * REG_IRQ_ENABLE1
394  */
395 #define EN_PARMBAD (1 << 7) /* enable BAD Parameter interrupt */
396 #define EN_PRBSQ1 (1 << 3) /* enable PRBS imag DAC B interrupt */
397 #define EN_PRBSI1 (1 << 2) /* enable PRBS real DAC B interrupt */
398 #define EN_PRBSQ0 (1 << 1) /* enable PRBS imag DAC A interrupt */
399 #define EN_PRBSI0 (1 << 0) /* enable PRBS real DAC A interrupt */
400 
401 /*
402  * REG_IRQ_ENABLE2
403  */
404 #define EN_PAERR0 (1 << 7) /* Link A PA Error */
405 #define EN_BIST_DONE0 (1 << 6) /* Link A BIST done */
406 #define EN_BLNKDONE0 (1 << 5) /* Link A Blanking done */
407 #define EN_REFNCOCLR0 (1 << 4) /* Link A Nco Clear Tripped */
408 #define EN_REFLOCK0 (1 << 3) /* Link A Alignment Locked */
409 #define EN_REFROTA0 (1 << 2) /* Link A Alignment Rotate */
410 #define EN_REFWLIM0 (1 << 1) /* Link A Over/Under Threshold */
411 #define EN_REFTRIP0 (1 << 0) /* Link A Alignment Trip */
412 
413 /*
414  * REG_IRQ_ENABLE3
415  */
416 #define EN_PAERR1 (1 << 7) /* Link B PA Error */
417 #define EN_BIST_DONE1 (1 << 6) /* Link B BIST done */
418 #define EN_BLNKDONE1 (1 << 5) /* Link B Blanking done */
419 #define EN_REFNCOCLR1 (1 << 4) /* Link B Nco Clear Tripped */
420 #define EN_REFLOCK1 (1 << 3) /* Link B Alignment Locked */
421 #define EN_REFROTA1 (1 << 2) /* Link B Alignment Rotate */
422 #define EN_REFWLIM1 (1 << 1) /* Link B Over/Under Threshold */
423 #define EN_REFTRIP1 (1 << 0) /* Link B Alignment Trip */
424 
425 /*
426  * REG_IRQ_STATUS0
427  */
428 #define IRQ_CALPASS (1 << 7) /* Calib PASS detection */
429 #define IRQ_CALFAIL (1 << 6) /* Calib FAIL detection */
430 #define IRQ_DACPLLLOST (1 << 5) /* DAC PLL Lost */
431 #define IRQ_DACPLLLOCK (1 << 4) /* DAC PLL Lock */
432 #define IRQ_SERPLLLOST (1 << 3) /* Serdes PLL Lost */
433 #define IRQ_SERPLLLOCK (1 << 2) /* Serdes PLL Lock */
434 #define IRQ_LANEFIFOERR (1 << 1) /* Lane Fifo Error */
435 #define IRQ_DRDLFIFOERR (1 << 0) /* DRDL Fifo Error */
436 
437 /*
438  * REG_IRQ_STATUS1
439  */
440 #define IRQ_PARMBAD (1 << 7) /* BAD Parameter interrupt */
441 #define IRQ_PRBSQ1 (1 << 3) /* PRBS data check error DAC 1 imag */
442 #define IRQ_PRBSI1 (1 << 2) /* PRBS data check error DAC 1 real */
443 #define IRQ_PRBSQ0 (1 << 1) /* PRBS data check error DAC 0 imag */
444 #define IRQ_PRBSI0 (1 << 0) /* PRBS data check error DAC 0 real */
445 
446 /*
447  * REG_IRQ_STATUS2
448  */
449 #define IRQ_PAERR0 (1 << 7) /* Link A PA Error */
450 #define IRQ_BIST_DONE0 (1 << 6) /* Link A BIST done */
451 #define IRQ_BLNKDONE0 (1 << 5) /* Link A Blanking Done */
452 #define IRQ_REFNCOCLR0 (1 << 4) /* Link A Alignment UnderRange */
453 #define IRQ_REFLOCK0 (1 << 3) /* Link A BIST done */
454 #define IRQ_REFROTA0 (1 << 2) /* Link A Alignment Trip */
455 #define IRQ_REFWLIM0 (1 << 1) /* Link A Alignment Lock */
456 #define IRQ_REFTRIP0 (1 << 0) /* Link A Alignment Rotate */
457 
458 /*
459  * REG_IRQ_STATUS3
460  */
461 #define IRQ_PAERR1 (1 << 7) /* Link B PA Error */
462 #define IRQ_BIST_DONE1 (1 << 6) /* Link B BIST done */
463 #define IRQ_BLNKDONE1 (1 << 5) /* Link A Blanking Done */
464 #define IRQ_REFNCOCLR1 (1 << 4) /* Link B Alignment UnderRange */
465 #define IRQ_REFLOCK1 (1 << 3) /* Link B BIST done */
466 #define IRQ_REFROTA1 (1 << 2) /* Link B Alignment Trip */
467 #define IRQ_REFWLIM1 (1 << 1) /* Link B Alignment Lock */
468 #define IRQ_REFTRIP1 (1 << 0) /* Link B Alignment Rotate */
469 
470 /*
471  * REG_JESD_CHECKS
472  */
473 #define ERR_DLYOVER (1 << 5) /* LMFC_Delay > JESD_K parameter */
474 #define ERR_WINLIMIT (1 << 4) /* Unsupported Window Limit */
475 #define ERR_JESDBAD (1 << 3) /* Unsupported M/L/S/F selection */
476 #define ERR_KUNSUPP (1 << 2) /* Unsupported K values */
477 #define ERR_SUBCLASS (1 << 1) /* Unsupported SubClassv value */
478 #define ERR_INTSUPP (1 << 0) /* Unsupported Interpolation rate factor */
479 
480 /*
481  * REG_SYNC_TESTCTRL
482  */
483 #define TARRFAPHAZ (1 << 0) /* Target Polarity of Rf Divider */
484 #define SYNCBYPASS(x) (((x) & 0x3) << 6) /* Sync Bypass handshaking */
485 
486 /*
487  * REG_SYNC_DACDELAY_H
488  */
489 #define DAC_DELAY_H (1 << 0) /* Dac Delay[8] */
490 
491 /*
492  * REG_SYNC_ERRWINDOW
493  */
494 #define ERRWINDOW(x) (((x) & 0x7) << 0) /* Sync Error Window */
495 
496 /*
497  * REG_SYNC_LASTERR_H
498  */
499 #define LASTUNDER (1 << 7) /* Sync Last Error Under Flag */
500 #define LASTOVER (1 << 6) /* Sync Last Error Over Flag */
501 #define LASTERROR_H (1 << 0) /* Sync Last Error[8] and Flags */
502 
503 /*
504  * REG_SYNC_CTRL
505  */
506 #define SYNCENABLE (1 << 7) /* SyncLogic Enable */
507 #define SYNCARM (1 << 6) /* Sync Arming Strobe */
508 #define SYNCCLRSTKY (1 << 5) /* Sync Sticky Bit Clear */
509 #define SYNCCLRLAST (1 << 4) /* Sync Clear LAST_ */
510 #define SYNCMODE(x) (((x) & 0xF) << 0) /* Sync Mode */
511 
512 /*
513  * REG_SYNC_STATUS
514  */
515 #define REFBUSY (1 << 7) /* Sync Machine Busy */
516 #define REFLOCK (1 << 3) /* Sync Alignment Locked */
517 #define REFROTA (1 << 2) /* Sync Rotated */
518 #define REFWLIM (1 << 1) /* Sync Alignment Limit Range */
519 #define REFTRIP (1 << 0) /* Sync Tripped after Arming */
520 
521 /*
522  * REG_SYNC_CURRERR_H
523  */
524 #define CURRUNDER (1 << 7) /* Sync Current Error Under Flag */
525 #define CURROVER (1 << 6) /* Sync Current Error Over Flag */
526 #define CURRERROR_H (1 << 0) /* SyncCurrent Error[8] */
527 
528 /*
529  * REG_ERROR_THERM
530  */
531 #define THRMOLD (1 << 7) /* Error is from a prior sample */
532 #define THRMOVER (1 << 4) /* Error > +WinLimit */
533 #define THRMPOS (1 << 3) /* Sync Current Error Under Flag */
534 #define THRMZERO (1 << 2) /* Error = 0 */
535 #define THRMNEG (1 << 1) /* Error < 0 */
536 #define THRMUNDER (1 << 0) /* Error < -WinLimit */
537 
538 /*
539  * REG_DACGAIN0_1
540  */
541 #define DACGAIN_IM0(x) (((x) & 0x3) << 0) /* I Channel DAC gain <9:8> Dual A */
542 
543 /*
544  * REG_DACGAIN1_1
545  */
546 #define DACGAIN_IM1(x) (((x) & 0x3) << 0) /* Q Channel DAC gain <9:8> Dual A */
547 
548 /*
549  * REG_DACGAIN2_1
550  */
551 #define DACGAIN_IM2(x) (((x) & 0x3) << 0) /* I Channel DAC gain <9:8> Dual B */
552 
553 /*
554  * REG_DACGAIN3_1
555  */
556 #define DACGAIN_IM3(x) (((x) & 0x3) << 0) /* Q Channel DAC gain <9:8> Dual B */
557 
558 /*
559  * REG_PD_DACLDO
560  */
561 #define ENB_DACLDO3 (1 << 7) /* Disable DAC3 ldo */
562 #define ENB_DACLDO2 (1 << 6) /* Disable DAC2 ldo */
563 #define ENB_DACLDO1 (1 << 5) /* Disable DAC1 ldo */
564 #define ENB_DACLDO0 (1 << 4) /* Disable DAC0 ldo */
565 
566 /*
567  * REG_STAT_DACLDO
568  */
569 #define STAT_LDO3 (1 << 3) /* DAC3 LDO status */
570 #define STAT_LDO2 (1 << 2) /* DAC2 LDO status */
571 #define STAT_LDO1 (1 << 1) /* DAC1 LDO status */
572 #define STAT_LDO0 (1 << 0) /* DAC0 LDO status */
573 
574 /*
575  * REG_DECODE_CTRL0
576  */
577 #define SHUFFLE_MSB0 (1 << 2) /* MSB shuffling mode */
578 #define SHUFFLE_ISB0 (1 << 1) /* ISB shuffling mode */
579 
580 /*
581  * REG_DECODE_CTRL1
582  */
583 #define SHUFFLE_MSB1 (1 << 2) /* MSB shuffling mode */
584 #define SHUFFLE_ISB1 (1 << 1) /* ISB shuffling mode */
585 
586 /*
587  * REG_DECODE_CTRL2
588  */
589 #define SHUFFLE_MSB2 (1 << 2) /* MSB shuffling mod */
590 #define SHUFFLE_ISB2 (1 << 1) /* ISB shuffling mode */
591 
592 /*
593  * REG_DECODE_CTRL3
594  */
595 #define SHUFFLE_MSB3 (1 << 2) /* MSB shuffling mode */
596 #define SHUFFLE_ISB3 (1 << 1) /* ISB shuffling mode */
597 
598 /*
599  * REG_NCO_CLRMODE
600  */
601 #define NCOCLRARM (1 << 7) /* Arm NCO Clear */
602 #define NCOCLRMTCH (1 << 5) /* NCO Clear Data Match */
603 #define NCOCLRPASS (1 << 4) /* NCO Clear PASSed */
604 #define NCOCLRFAIL (1 << 3) /* NCO Clear FAILed */
605 #define NCOCLRMODE(x) (((x) & 0x3) << 0) /* NCO Clear Mode */
606 
607 /*
608  * REG_PA_THRES1
609  */
610 #define PA_THRESH_MSB(x) (((x) & 0x1F) << 0) /* Average power threshold for comparison. */
611 
612 /*
613  * REG_PA_AVG_TIME
614  */
615 #define PA_ENABLE (1 << 7) /* 1 = Enable average power calculation and error detection */
616 #define PA_BUS_SWAP (1 << 6) /* Swap channelA or channelB databus for power calculation */
617 #define PA_AVG_TIME(x) (((x) & 0xF) << 0) /* Set power average time */
618 
619 /*
620  * REG_PA_POWER1
621  */
622 #define PA_POWER_MSB(x) (((x) & 0x1F) << 0) /* average power bus = I^2+Q^2 (I/Q use 6MSB of databus) */
623 
624 /*
625  * REG_CLKCFG0
626  */
627 #define PD_CLK01 (1 << 7) /* Powerdown clock for Dual A */
628 #define PD_CLK23 (1 << 6) /* Powerdown clock for Dual B */
629 #define PD_CLK_DIG (1 << 5) /* Powerdown clocks to all DACs */
630 #define PD_PCLK (1 << 4) /* Cal reference/Serdes PLL clock powerdown */
631 #define PD_CLK_REC (1 << 3) /* Clock reciever powerdown */
632 
633 /*
634  * REG_SYSREF_ACTRL0
635  */
636 #define PD_SYSREF (1 << 4) /* Powerdown SYSREF buffer */
637 #define HYS_ON (1 << 3) /* Hysteresis enabled */
638 #define SYSREF_RISE (1 << 2) /* Use SYSREF rising edge */
639 #define HYS_CNTRL1(x) (((x) & 0x3) << 0) /* Hysteresis control bits <9:8> */
640 
641 /*
642  * REG_DACPLLCNTRL
643  */
644 #define SYNTH_RECAL (1 << 7) /* Recalibrate VCO Band */
645 #define ENABLE_SYNTH (1 << 4) /* Synthesizer Enable */
646 
647 /*
648  * REG_DACPLLSTATUS
649  */
650 #define CP_CAL_VALID (1 << 5) /* Charge Pump Cal Valid */
651 #define RFPLL_LOCK (1 << 1) /* PLL Lock bit */
652 
653 /*
654  * REG_DACLOOPFILT1
655  */
656 #define LF_C2_WORD(x) (((x) & 0xF) << 4) /* C2 control word */
657 #define LF_C1_WORD(x) (((x) & 0xF) << 0) /* C1 control word */
658 
659 /*
660  * REG_DACLOOPFILT2
661  */
662 #define LF_R1_WORD(x) (((x) & 0xF) << 4) /* R1 control word */
663 #define LF_C3_WORD(x) (((x) & 0xF) << 0) /* C3 control word */
664 
665 /*
666  * REG_DACLOOPFILT3
667  */
668 #define LF_BYPASS_R3 (1 << 7) /* Bypass R3 res */
669 #define LF_BYPASS_R1 (1 << 6) /* Bypass R1 res */
670 #define LF_BYPASS_C2 (1 << 5) /* Bypass C2 cap */
671 #define LF_BYPASS_C1 (1 << 4) /* Bypass C1 cap */
672 #define LF_R3_WORD(x) (((x) & 0xF) << 0) /* R3 Control Word */
673 
674 /*
675  * REG_DACCPCNTRL
676  */
677 #define CP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current Control */
678 
679 /*
680  * REG_DACLOGENCNTRL
681  */
682 #define LO_DIV_MODE(x) (((x) & 0x3) << 0) /* Logen_Division */
683 
684 /*
685  * REG_DACLDOCNTRL1
686  */
687 #define REF_DIVRATE(x) (((x) & 0x7) << 0) /* Reference Clock Division Ratio */
688 
689 /*
690  * REG_CAL_DAC_ERR
691  */
692 #define INIT_SWEEP_ERR_DAC (1 << 1) /* Initial setup sweep failed */
693 #define MSB_SWEEP_ERR_DAC (1 << 0) /* MSB sweep failed */
694 
695 /*
696  * REG_CAL_MSB_THRES
697  */
698 #define CAL_MSB_TAC(x) (((x) & 0x7) << 0) /* MSB sweep TAC */
699 
700 /*
701  * REG_CAL_CTRL_GLOBAL
702  */
703 #define CAL_START_GL (1 << 1) /* Global Calibration start */
704 #define CAL_EN_GL (1 << 0) /* Global Calibration enable */
705 
706 /*
707  * REG_CAL_MSBHILVL
708  */
709 #define CAL_MSBLVLHI(x) (((x) & 0x3F) << 0) /* High level limit for msb sweep average */
710 
711 /*
712  * REG_CAL_MSBLOLVL
713  */
714 #define CAL_MSBLVLLO(x) (((x) & 0x3F) << 0) /* Low level limit for msb sweep average */
715 
716 /*
717  * REG_CAL_THRESH
718  */
719 #define CAL_LTAC_THRES(x) (((x) & 0x7) << 3) /* Long TAC threshold */
720 #define CAL_TAC_THRES(x) (((x) & 0x7) << 0) /* TAC threshold */
721 
722 /*
723  * REG_CAL_AVG_CNT
724  */
725 #define MSB_GLOBAL_SUBAVG(x) (((x) & 0x3) << 6) /* Local Averages for MSB in Global Calibration */
726 #define GLOBAL_AVG_CNT(x) (((x) & 0x7) << 3) /* Global avg Terminal count */
727 #define LOCAL_AVRG_CNT(x) (((x) & 0x7) << 0) /* Local avg terminal count */
728 
729 /*
730  * REG_CAL_CLKDIV
731  */
732 #define CAL_CLKDIV(x) (((x) & 0xF) << 0) /* Calibration clock divider */
733 
734 /*
735  * REG_CAL_INDX
736  */
737 #define CAL_INDX(x) (((x) & 0xF) << 0) /* DAC Calibration Index paging bits */
738 
739 /*
740  * REG_CAL_CTRL
741  */
742 #define CAL_FIN (1 << 7) /* Calibration finished */
743 #define CAL_ACTIVE (1 << 6) /* Calibration active */
744 #define CAL_ERRHI (1 << 5) /* SAR data error: too hi */
745 #define CAL_ERRLO (1 << 4) /* SAR data error: too lo */
746 #define CAL_TXDACBYDAC (1 << 3) /* Calibration of TXDAC by TXDAC */
747 #define CAL_START (1 << 1) /* Calibration start */
748 #define CAL_EN (1 << 0) /* Calibration enable */
749 
750 /*
751  * REG_CAL_ADDR
752  */
753 #define CAL_ADDR(x) (((x) & 0x3F) << 0) /* Calibration DAC address */
754 
755 /*
756  * REG_CAL_DATA
757  */
758 #define CAL_DATA(x) (((x) & 0x3F) << 0) /* Calibration DAC Coefficient Data */
759 
760 /*
761  * REG_CAL_UPDATE
762  */
763 #define CAL_UPDATE (1 << 7) /* Calibration DAC Coefficient Update */
764 
765 /*
766  * REG_DATA_FORMAT
767  */
768 #define BINARY_FORMAT (1 << 7) /* Binary or 2's complementary format on DATA bus */
769 
770 /*
771  * REG_DATAPATH_CTRL
772  */
773 #define INVSINC_ENABLE (1 << 7) /* 1 = Enable inver sinc filter */
774 #define DIG_GAIN_ENABLE (1 << 5) /* 1 = Enable digital gain */
775 #define PHASE_ADJ_ENABLE (1 << 4) /* 1 = Enable phase compensation */
776 #define SEL_SIDEBAND (1 << 1) /* 1 = Select upper or lower sideband from modulation result */
777 #define I_TO_Q (1 << 0) /* 1 = send I datapath into Q DAC */
778 #define MODULATION_TYPE(x) (((x) & 0x3) << 2) /* selects type of modulation operation */
779 
780 /*
781  * REG_INTERP_MODE
782  */
783 #define INTERP_MODE(x) (((x) & 0x7) << 0) /* Interpolation Mode */
784 
785 /*
786  * REG_NCO_FTW_UPDATE
787  */
788 #define FTW_UPDATE_ACK (1 << 1) /* Frequency Tuning Word Update Acknowledge */
789 #define FTW_UPDATE_REQ (1 << 0) /* Frequency Tuning Word Update Request from SPI */
790 
791 /*
792  * REG_TXEN_FUNC
793  */
794 #define TX_DIG_CLK_PD (1 << 0) /* 1 = Digital clocks will be shut down when Tx_enable pin is low. */
795 
796 /*
797  * REG_TXEN_SM_0
798  */
799 #define GP_PA_ON_INVERT (1 << 2) /* External Modulator polarity invert */
800 #define GP_PA_CTRL (1 << 1) /* External PA control */
801 #define TXEN_SM_EN (1 << 0) /* Enable TXEN state machine */
802 #define PA_FALL(x) (((x) & 0x3) << 6) /* PA fall control */
803 #define PA_RISE(x) (((x) & 0x3) << 4) /* PA rises control */
804 
805 /*
806  * REG_TXEN_SM_1
807  */
808 #define DIG_FALL(x) (((x) & 0x3) << 6) /* DIG_FALL */
809 #define DIG_RISE(x) (((x) & 0x3) << 4) /* DIG_RISE */
810 #define DAC_FALL(x) (((x) & 0x3) << 2) /* DAC_FALL */
811 #define DAC_RISE(x) (((x) & 0x3) << 0) /* DAC_RISE */
812 
813 /*
814  * REG_DACOUT_ON_DOWN
815  */
816 #define DACOUT_SHUTDOWN (1 << 1) /* Shut down DAC output. 1 means DAC get shut down manually. */
817 #define DACOUT_ON_TRIGGER (1 << 0) /* Turn on DAC output manually. Self clear signal. */
818 
819 /*
820  * REG_DACOFF
821  */
822 #define PROTECT_MODE (1 << 7) /* PROTECT_MODE */
823 #define DACOFF_AVG_PW (1 << 0) /* DACOFF_AVG_PW */
824 
825 /*
826  * REG_DIE_TEMP_CTRL0
827  */
828 #define ADC_TESTMODE (1 << 7) /* ADC_TESTMODE */
829 #define AUXADC_ENABLE (1 << 0) /* AUXADC_ENABLE */
830 #define FS_CURRENT(x) (((x) & 0x7) << 4) /* FS_CURRENT */
831 #define REF_CURRENT(x) (((x) & 0x7) << 1) /* REF_CURRENT */
832 
833 /*
834  * REG_DIE_TEMP_CTRL1
835  */
836 #define SELECT_CLKDIG (1 << 3) /* SELECT_CLKDIG */
837 #define EN_DIV2 (1 << 2) /* EN_DIV2 */
838 #define INCAP_CTRL(x) (((x) & 0x3) << 0) /* INCAP_CTRL */
839 
840 /*
841  * REG_DIE_TEMP_UPDATE
842  */
843 #define DIE_TEMP_UPDATE (1 << 0) /* Die temperature update */
844 
845 /*
846  * REG_DC_OFFSET_CTRL
847  */
848 #define DISABLE_NOISE (1 << 1) /* DISABLE_NOISE */
849 #define DC_OFFSET_ON (1 << 0) /* DC_OFFSET_ON */
850 
851 /*
852  * REG_IPATH_DC_OFFSET_2PART
853  */
854 #define IPATH_DC_OFFSET_2PART(x) (((x) & 0x1F) << 0) /* second part of DC Offset value for I path */
855 
856 /*
857  * REG_QPATH_DC_OFFSET_2PART
858  */
859 #define QPATH_DC_OFFSET_2PART(x) (((x) & 0x1F) << 0) /* second part of DC Offset value for Q path */
860 
861 /*
862  * REG_IDAC_DIG_GAIN1
863  */
864 #define IDAC_DIG_GAIN1(x) (((x) & 0xF) << 0) /* MSB of I DAC digital gain */
865 
866 /*
867  * REG_QDAC_DIG_GAIN1
868  */
869 #define QDAC_DIG_GAIN1(x) (((x) & 0xF) << 0) /* MSB of Q DAC digital gain */
870 
871 /*
872  * REG_GAIN_RAMP_UP_STP1
873  */
874 #define GAIN_RAMP_UP_STP1(x) (((x) & 0xF) << 0) /* MSB of digital gain rises */
875 
876 /*
877  * REG_GAIN_RAMP_DOWN_STP1
878  */
879 #define GAIN_RAMP_DOWN_STP1(x) (((x) & 0xF) << 0) /* MSB of digital gain drops */
880 
881 /*
882  * REG_BLSM_CTRL
883  */
884 #define RESET_BLSM (1 << 7) /* Soft rest to the new Blanking SM */
885 #define EN_FORCE_GAIN_SOFT_OFF (1 << 4) /* Enable forcing gan_soft_off from SPI */
886 #define GAIN_SOFT_OFF (1 << 3) /* gain_soft_off forced value */
887 #define GAIN_SOFT_ON (1 << 2) /* gain_soft_on forced value */
888 #define EN_FORCE_GAIN_SOFT_ON (1 << 1) /* Force the gain_soft_on from SPI */
889 
890 /*
891  * REG_BLSM_STAT
892  */
893 #define SOFT_OFF_DONE (1 << 5) /* Blanking SoftOff Enable */
894 #define SOFT_ON_DONE (1 << 4) /* Blanking SoftOn Done */
895 #define GAIN_SOFT_OFF_RB (1 << 3) /* gain soft off readback */
896 #define GAIN_SOFT_ON_RB (1 << 2) /* gain soft on readback */
897 #define SOFT_OFF_EN_RB (1 << 1) /* Blanking SM soft Off read back */
898 #define SOFT_ON_EN_RB (1 << 0) /* Blanking SM soft On read back */
899 #define SOFTBLANKRB(x) (((x) & 0x3) << 6) /* Blanking State */
900 
901 /*
902  * REG_PRBS
903  */
904 #define PRBS_GOOD_Q (1 << 7) /* Good data indicator imaginary channel */
905 #define PRBS_GOOD_I (1 << 6) /* Good data indicator real channel */
906 #define PRBS_INV_Q (1 << 4) /* Data Inversion imaginary channel */
907 #define PRBS_INV_I (1 << 3) /* Data Inversion real channel */
908 #define PRBS_MODE (1 << 2) /* Polynomial Select */
909 #define PRBS_RESET (1 << 1) /* Reset Error Counters */
910 #define PRBS_EN (1 << 0) /* Enable PRBS Checker */
911 
912 /*
913  * REG_DACPLLT5
914  */
915 #define VCO_VAR(x) (((x) & 0xF) << 0) /* Varactor KVO setting */
916 
917 /*
918  * REG_DACPLLTB
919  */
920 #define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias control */
921 
922 /*
923  * REG_DACPLLTD
924  */
925 #define VCO_CAL_REF_MON (1 << 3) /* Sent control voltage to outside world */
926 #define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* TempCo for cal ref */
927 
928 /*
929  * REG_DACPLLT17
930  */
931 #define VCO_VAR_REF_TCF(x) (((x) & 0x7) << 4) /* Varactor Reference TempCo */
932 #define VCO_VAR_OFF(x) (((x) & 0xF) << 0) /* Varactor Offset */
933 
934 /*
935  * REG_SPISTRENGTH
936  */
937 #define SPIDRV(x) (((x) & 0xF) << 0) /* Slew and drive strength for cmos interface */
938 
939 /*
940  * REG_CLK_TEST
941  */
942 #define DUTYCYCLEON (1 << 0) /* Clock Duty Cycle Control On */
943 
944 /*
945  * REG_ATEST_VOLTS
946  */
947 #define ATEST_EN (1 << 0) /* Enable Analog Test Mode */
948 #define ATEST_TOPVSEL(x) (((x) & 0x3) << 5) /* Which source at analog top to use */
949 #define ATEST_DACSEL(x) (((x) & 0x3) << 3) /* DAC from which to get voltage */
950 #define ATEST_VSEL(x) (((x) & 0x3) << 1) /* DAC Voltage to Select */
951 
952 /*
953  * REG_ASPI_CLKSRC
954  */
955 #define EN_CLKDIV (1 << 3) /* Enable the fdac/8 clock path to generate PD timing clock */
956 #define ASPI_OSC_RATE (1 << 2) /* Aspi Oscillator Rate */
957 #define ASPI_CLK_SRC (1 << 1) /* Choose Aspi Clock Source */
958 #define EN_ASPI_OSC (1 << 0) /* Enable Aspi Oscillator clock */
959 
960 /*
961  * REG_MASTER_PD
962  */
963 #define SPI_PD_MASTER (1 << 0)
964 
965 /*
966  * REG_GENERIC_PD
967  */
968 #define SPI_SYNC1_PD (1 << 1)
969 #define SPI_SYNC2_PD (1 << 0)
970 
971 /*
972  * REG_CDR_OPERATING_MODE_REG_0
973  */
974 #define SPI_ENHALFRATE (1 << 5)
975 #define SPI_DIVISION_RATE(x) (((x) & 0x3) << 1)
976 
977 /*
978  * REG_EQ_CONFIG_PHY_0_1
979  */
980 #define SPI_EQ_CONFIG1(x) (((x) & 0xF) << 4)
981 #define SPI_EQ_CONFIG0(x) (((x) & 0xF) << 0)
982 
983 /*
984  * REG_EQ_CONFIG_PHY_2_3
985  */
986 #define SPI_EQ_CONFIG3(x) (((x) & 0xF) << 4)
987 #define SPI_EQ_CONFIG2(x) (((x) & 0xF) << 0)
988 
989 /*
990  * REG_EQ_CONFIG_PHY_4_5
991  */
992 #define SPI_EQ_CONFIG5(x) (((x) & 0xF) << 4)
993 #define SPI_EQ_CONFIG4(x) (((x) & 0xF) << 0)
994 
995 /*
996  * REG_EQ_CONFIG_PHY_6_7
997  */
998 #define SPI_EQ_CONFIG7(x) (((x) & 0xF) << 4)
999 #define SPI_EQ_CONFIG6(x) (((x) & 0xF) << 0)
1000 
1001 /*
1002  * REG_EQ_BIAS_REG
1003  */
1004 #define SPI_EQ_EXTRA_SPI_LSBITS(x) (((x) & 0x3) << 6)
1005 #define SPI_EQ_BIASPTAT(x) (((x) & 0x7) << 3)
1006 #define SPI_EQ_BIASPLY(x) (((x) & 0x7) << 0)
1007 
1008 /*
1009  * REG_SYNTH_ENABLE_CNTRL
1010  */
1011 #define SPI_RECAL_SYNTH (1 << 2)
1012 #define SPI_ENABLE_SYNTH (1 << 0)
1013 
1014 /*
1015  * REG_PLL_STATUS
1016  */
1017 #define SPI_CP_CAL_VALID_RB (1 << 3)
1018 #define SPI_PLL_LOCK_RB (1 << 0)
1019 
1020 /*
1021  * REG_REF_CLK_DIVIDER_LDO
1022  */
1023 #define SPI_CDR_OVERSAMP(x) (((x) & 0x3) << 0)
1024 
1025 /*
1026  * REG_TERM_BLK1_CTRLREG0
1027  */
1028 #define SPI_I_TUNE_R_CAL_TERMBLK1 (1 << 0)
1029 
1030 /*
1031  * REG_TERM_BLK2_CTRLREG0
1032  */
1033 #define SPI_I_TUNE_R_CAL_TERMBLK2 (1 << 0)
1034 
1035 /*
1036  * REG_GENERAL_JRX_CTRL_0
1037  */
1038 #define CHECKSUM_MODE (1 << 6) /* Checksum mode */
1039 #define LINK_MODE (1 << 3) /* Link mode */
1040 #define SEL_REG_MAP_1 (1 << 2) /* Link register map selection */
1041 #define LINK_EN(x) (((x) & 0x3) << 0) /* Link enable */
1042 
1043 /*
1044  * REG_GENERAL_JRX_CTRL_1
1045  */
1046 #define SUBCLASSV_LOCAL(x) (((x) & 0x7) << 0) /* JESD204B subclass */
1047 
1048 /*
1049  * REG_DYN_LINK_LATENCY_0
1050  */
1051 #define DYN_LINK_LATENCY_0(x) (((x) & 0x1F) << 0) /* Dynamic link latency: Link 0 */
1052 
1053 /*
1054  * REG_DYN_LINK_LATENCY_1
1055  */
1056 #define DYN_LINK_LATENCY_1(x) (((x) & 0x1F) << 0) /* Dynamic link latency: Link 1 */
1057 
1058 /*
1059  * REG_LMFC_DELAY_0
1060  */
1061 #define LMFC_DELAY_0(x) (((x) & 0x1F) << 0) /* LMFC delay: Link 0 */
1062 
1063 /*
1064  * REG_LMFC_DELAY_1
1065  */
1066 #define LMFC_DELAY_1(x) (((x) & 0x1F) << 0) /* LMFC delay: Link 1 */
1067 
1068 /*
1069  * REG_LMFC_VAR_0
1070  */
1071 #define LMFC_VAR_0(x) (((x) & 0x1F) << 0) /* Location in RX LMFC where JESD words are read out from buffer */
1072 
1073 /*
1074  * REG_LMFC_VAR_1
1075  */
1076 #define LMFC_VAR_1(x) (((x) & 0x1F) << 0) /* Location in RX LMFC where JESD words are read out from buffer */
1077 
1078 /*
1079  * REG_XBAR_LN_0_1
1080  */
1081 #define SRC_LANE1(x) (((x) & 0x7) << 3) /* Logic Lane 1 source */
1082 #define SRC_LANE0(x) (((x) & 0x7) << 0) /* Logic Lane 0 source */
1083 
1084 /*
1085  * REG_XBAR_LN_2_3
1086  */
1087 #define SRC_LANE3(x) (((x) & 0x7) << 3) /* Logic Lane 3 source */
1088 #define SRC_LANE2(x) (((x) & 0x7) << 0) /* Logic Lane 2 source */
1089 
1090 /*
1091  * REG_XBAR_LN_4_5
1092  */
1093 #define SRC_LANE5(x) (((x) & 0x7) << 3) /* Logic Lane 5 source */
1094 #define SRC_LANE4(x) (((x) & 0x7) << 0) /* Logic Lane 4 source */
1095 
1096 /*
1097  * REG_XBAR_LN_6_7
1098  */
1099 #define SRC_LANE7(x) (((x) & 0x7) << 3) /* Logic Lane 7 source */
1100 #define SRC_LANE6(x) (((x) & 0x7) << 0) /* Logic Lane 6 source */
1101 
1102 /*
1103  * REG_FIFO_STATUS_REG_2
1104  */
1105 #define DRDL_FIFO_EMPTY (1 << 1) /* Deterministic latency (DRDL) FIFO is between JESD204B receiver and DAC2 and DAC3 */
1106 #define DRDL_FIFO_FULL (1 << 0) /* DRDL FIFO is between JESD204B receiver and DAC2 and DAC3 */
1107 
1108 /*
1109  * REG_SYNCB_GEN_0
1110  */
1111 #define EOMF_MASK_1 (1 << 3) /* EOMF_MASK_1 */
1112 #define EOMF_MASK_0 (1 << 2) /* EOMF_MASK_0 */
1113 #define EOF_MASK_1 (1 << 1) /* Mask EOF from QBD_1 */
1114 #define EOF_MASK_0 (1 << 0) /* Mask EOF from QBD_0 */
1115 
1116 /*
1117  * REG_SYNCB_GEN_1
1118  */
1119 #define SYNCB_ERR_DUR(x) (((x) & 0xF) << 4) /* Duration of SYNCOUT low for the purpose of error reporting */
1120 #define SYNCB_SYNCREQ_DUR(x) (((x) & 0xF) << 0) /* Duration of SYNCOUT low for purpose of synchronization request */
1121 
1122 /*
1123  * REG_PHY_PRBS_TEST_CTRL
1124  */
1125 #define PHY_TEST_START (1 << 1) /* PHY PRBS test start */
1126 #define PHY_TEST_RESET (1 << 0) /* PHY PRBS test reset */
1127 #define PHY_SRC_ERR_CNT(x) (((x) & 0x7) << 4) /* PHY error count source */
1128 #define PHY_PRBS_PAT_SEL(x) (((x) & 0x3) << 2) /* PHY PRBS pattern select */
1129 
1130 /*
1131  * REG_SHORT_TPL_TEST_0
1132  */
1133 #define SHORT_TPL_TEST_RESET (1 << 1) /* Short transport layer test reset */
1134 #define SHORT_TPL_TEST_EN (1 << 0) /* Short transport layer test enable */
1135 #define SHORT_TPL_SP_SEL(x) (((x) & 0x3) << 4) /* Short transport layer sample select */
1136 #define SHORT_TPL_M_SEL(x) (((x) & 0x3) << 2) /* Short transport layer test DAC select */
1137 
1138 /*
1139  * REG_SHORT_TPL_TEST_3
1140  */
1141 #define SHORT_TPL_FAIL (1 << 0) /* Short transport layer test fail */
1142 
1143 /*
1144  * REG_BID_REG
1145  */
1146 #define ADJCNT_RD(x) (((x) & 0xF) << 4)
1147 #define BID_RD(x) (((x) & 0xF) << 0)
1148 
1149 /*
1150  * REG_LID0_REG
1151  */
1152 #define ADJDIR_RD (1 << 6)
1153 #define PHADJ_RD (1 << 5)
1154 #define LID0_RD(x) (((x) & 0x1F) << 0)
1155 
1156 /*
1157  * REG_SCR_L_REG
1158  */
1159 #define SCR_RD (1 << 7)
1160 #define L_RD(x) (((x) & 0x1F) << 0)
1161 
1162 /*
1163  * REG_K_REG
1164  */
1165 #define K_RD(x) (((x) & 0x1F) << 0)
1166 
1167 /*
1168  * REG_CS_N_REG
1169  */
1170 #define CS_RD(x) (((x) & 0x3) << 6)
1171 #define N_RD(x) (((x) & 0x1F) << 0)
1172 
1173 /*
1174  * REG_NP_REG
1175  */
1176 #define SUBCLASSV_RD(x) (((x) & 0x7) << 5)
1177 #define NP_RD(x) (((x) & 0x1F) << 0)
1178 
1179 /*
1180  * REG_S_REG
1181  */
1182 #define JESDV_RD(x) (((x) & 0x7) << 5)
1183 #define S_RD(x) (((x) & 0x1F) << 0)
1184 
1185 /*
1186  * REG_HD_CF_REG
1187  */
1188 #define HD_RD (1 << 7)
1189 #define CF_RD(x) (((x) & 0x1F) << 0)
1190 
1191 /*
1192  * REG_LID1_REG
1193  */
1194 #define LID1_RD(x) (((x) & 0x1F) << 0)
1195 
1196 /*
1197  * REG_LID2_REG
1198  */
1199 #define LID2_RD(x) (((x) & 0x1F) << 0)
1200 
1201 /*
1202  * REG_LID3_REG
1203  */
1204 #define LID3_RD(x) (((x) & 0x1F) << 0)
1205 
1206 /*
1207  * REG_LID4_REG
1208  */
1209 #define LID4_RD(x) (((x) & 0x1F) << 0)
1210 
1211 /*
1212  * REG_LID5_REG
1213  */
1214 #define LID5_RD(x) (((x) & 0x1F) << 0)
1215 
1216 /*
1217  * REG_LID6_REG
1218  */
1219 #define LID6_RD(x) (((x) & 0x1F) << 0)
1220 
1221 /*
1222  * REG_LID7_REG
1223  */
1224 #define LID7_RD(x) (((x) & 0x1F) << 0)
1225 
1226 /*
1227  * REG_ILS_BID
1228  */
1229 #define ADJCNT(x) (((x) & 0xF) << 4)
1230 #define BID(x) (((x) & 0xF) << 0)
1231 
1232 /*
1233  * REG_ILS_LID0
1234  */
1235 #define ADJDIR (1 << 6)
1236 #define PHADJ (1 << 5)
1237 #define LID0(x) (((x) & 0x1F) << 0)
1238 
1239 /*
1240  * REG_ILS_SCR_L
1241  */
1242 #define SCR (1 << 7)
1243 #define L(x) (((x) & 0x1F) << 0)
1244 
1245 /*
1246  * REG_ILS_K
1247  */
1248 #define K(x) (((x) & 0x1F) << 0)
1249 
1250 /*
1251  * REG_ILS_CS_N
1252  */
1253 #define CS(x) (((x) & 0x3) << 6)
1254 #define N(x) (((x) & 0x1F) << 0)
1255 
1256 /*
1257  * REG_ILS_NP
1258  */
1259 #define SUBCLASSV(x) (((x) & 0x7) << 5)
1260 #define NP(x) (((x) & 0x1F) << 0)
1261 
1262 /*
1263  * REG_ILS_S
1264  */
1265 #define JESDV(x) (((x) & 0x7) << 5)
1266 #define S(x) (((x) & 0x1F) << 0)
1267 
1268 /*
1269  * REG_ILS_HD_CF
1270  */
1271 #define HD (1 << 7)
1272 #define CF(x) (((x) & 0x1F) << 0)
1273 
1274 /*
1275  * REG_ERRCNTRMON
1276  */
1277 #define LANESEL(x) (((x) & 0x7) << 4)
1278 #define CNTRSEL(x) (((x) & 0x3) << 0)
1279 
1280 /*
1281  * REG_BADDISPARITY
1282  */
1283 #define RST_IRQ_DIS (1 << 7)
1284 #define DIS_ERR_CNTR_DIS (1 << 6)
1285 #define RST_ERR_CNTR_DIS (1 << 5)
1286 #define LANE_ADDR_DIS(x) (((x) & 0x7) << 0)
1287 
1288 /*
1289  * REG_NITDISPARITY
1290  */
1291 #define RST_IRQ_NIT (1 << 7)
1292 #define DIS_ERR_CNTR_NIT (1 << 6)
1293 #define RST_ERR_CNTR_NIT (1 << 5)
1294 #define LANE_ADDR_NIT(x) (((x) & 0x7) << 0)
1295 
1296 /*
1297  * REG_UNEXPECTEDKCHAR
1298  */
1299 #define RST_IRQ_K (1 << 7)
1300 #define DIS_ERR_CNTR_K (1 << 6)
1301 #define RST_ERR_CNTR_K (1 << 5)
1302 #define LANE_ADDR_K(x) (((x) & 0x7) << 0)
1303 
1304 /*
1305  * REG_CTRLREG2
1306  */
1307 #define ILAS_MODE (1 << 7)
1308 #define REPDATATEST (1 << 5)
1309 #define QUETESTERR (1 << 4)
1310 #define AUTO_ECNTR_RST (1 << 3)
1311 
1312 /*
1313  * REG_IRQVECTOR
1314  */
1315 #define BADDIS_FLAG_OR_MASK (1 << 7)
1316 #define NITD_FLAG_OR_MASK (1 << 6)
1317 #define UEKC_FLAG_OR_MASK (1 << 5)
1318 #define INITIALLANESYNC_FLAG_OR_MASK (1 << 3)
1319 #define BADCHECKSUM_FLAG_OR_MASK (1 << 2)
1320 #define CODEGRPSYNC_FLAG_OR_MASK (1 << 0)
1321 
1322 /*
1323  * REG_SYNCASSERTIONMASK
1324  */
1325 #define BAD_DIS_S (1 << 7)
1326 #define NIT_DIS_S (1 << 6)
1327 #define UNEX_K_S (1 << 5)
1328 #define CMM_FLAG_OR_MASK (1 << 4)
1329 #define CMM_ENABLE (1 << 3)
1330 
1331 
1332 #define AD9152_MAX_DAC_RATE 2000000000UL
1333 #define AD9152_CHIP_ID 0x52
1334 #define AD9152_TEST_PN15 0x01
1335 #define AD9152_TEST_PN7 0x00
1336 
1337 /******************************************************************************/
1338 /*************************** Types Declarations *******************************/
1339 /******************************************************************************/
1340 
1341 struct ad9152_init_param {
1342  /* SPI */
1343  struct no_os_spi_init_param spi_init;
1344  /* Device Settings */
1345  uint32_t stpl_samples[2][4];
1346  uint32_t interpolation;
1347  uint32_t prbs_type;
1348  uint32_t lane_rate_kbps;
1349 };
1350 
1351 struct ad9152_dev {
1352  /* SPI */
1353  struct no_os_spi_desc *spi_desc;
1354 };
1355 
1356 /******************************************************************************/
1357 /************************ Functions Declarations ******************************/
1358 /******************************************************************************/
1359 
1360 int32_t ad9152_spi_read(struct ad9152_dev *dev,
1361  uint16_t reg_addr,
1362  uint8_t *reg_data);
1363 int32_t ad9152_spi_write(struct ad9152_dev *dev,
1364  uint16_t reg_addr,
1365  uint8_t reg_data);
1366 int32_t ad9152_setup(struct ad9152_dev **device,
1367  struct ad9152_init_param init_param);
1368 int32_t ad9152_datapath_prbs_test(struct ad9152_dev *dev,
1369  struct ad9152_init_param init_param);
1370 int32_t ad9152_short_pattern_test(struct ad9152_dev *dev,
1371  struct ad9152_init_param init_param);
1372 int32_t ad9152_status(struct ad9152_dev *dev);
1373 int32_t ad9152_remove(struct ad9152_dev *dev);
1374 
1375 #endif
ad9152_dev
Definition: ad9152.h:1351
no_os_alloc.h
ad9152_datapath_prbs_test
int32_t ad9152_datapath_prbs_test(struct ad9152_dev *dev, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:256
ad9152_init_param
Definition: ad9152.h:1341
ad9152_init_param::lane_rate_kbps
uint32_t lane_rate_kbps
Definition: ad9152.h:1348
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:159
REG_PRBS_ERROR_I
#define REG_PRBS_ERROR_I
Definition: ad9144.h:183
REG_GOODCHKSUMFLG
#define REG_GOODCHKSUMFLG
Definition: ad9144.h:310
SOFTRESET_M
#define SOFTRESET_M
Definition: ad9144.h:323
no_os_spi.h
Header file of SPI Interface.
ad9152_spi_read
int32_t ad9152_spi_read(struct ad9152_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9152_spi_read
Definition: ad9152.c:45
no_os_delay.h
Header file of Delay functions.
device
Definition: ad9361_util.h:69
REG_FRAMESYNCFLG
#define REG_FRAMESYNCFLG
Definition: ad9144.h:309
ad9152_setup
int32_t ad9152_setup(struct ad9152_dev **device, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:90
ad9152_setup
int32_t ad9152_setup(struct ad9152_dev **device, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:90
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:126
ad9152_init_param::prbs_type
uint32_t prbs_type
Definition: ad9152.h:1347
ad9152_short_pattern_test
int32_t ad9152_short_pattern_test(struct ad9152_dev *dev, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:216
AD9152_CHIP_ID
#define AD9152_CHIP_ID
Definition: ad9152.h:1333
REG_INITLANESYNCFLG
#define REG_INITLANESYNCFLG
Definition: ad9144.h:311
SOFTRESET
#define SOFTRESET
Definition: ad9144.h:330
ad9152_spi_write
int32_t ad9152_spi_write(struct ad9152_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9152_spi_write
Definition: ad9152.c:68
ad9152_spi_write
int32_t ad9152_spi_write(struct ad9152_dev *dev, uint16_t reg_addr, uint8_t reg_data)
ad9152_spi_write
Definition: ad9152.c:68
REG_SPI_PRODIDL
#define REG_SPI_PRODIDL
Definition: ad9144.h:51
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:192
ad9152_status
int32_t ad9152_status(struct ad9152_dev *dev)
ad9152_setup
Definition: ad9152.c:296
ad9152_init_param::stpl_samples
uint32_t stpl_samples[2][4]
Definition: ad9152.h:1345
ad9152_datapath_prbs_test
int32_t ad9152_datapath_prbs_test(struct ad9152_dev *dev, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:256
no_os_malloc
void * no_os_malloc(size_t size)
Allocate memory and return a pointer to it.
Definition: chibios_alloc.c:43
ad9152_remove
int32_t ad9152_remove(struct ad9152_dev *dev)
Free the resources allocated by ad9152_setup().
Definition: ad9152.c:201
no_os_free
void no_os_free(void *ptr)
Deallocate memory previously allocated by a call to no_os_calloc or no_os_malloc.
Definition: chibios_alloc.c:69
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:113
ad9152.h
Header file of AD9152 Driver.
ad9152_short_pattern_test
int32_t ad9152_short_pattern_test(struct ad9152_dev *dev, struct ad9152_init_param init_param)
ad9152_setup
Definition: ad9152.c:216
REG_SPI_INTFCONFA
#define REG_SPI_INTFCONFA
Definition: ad9144.h:48
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:116
REG_CODEGRPSYNCFLG
#define REG_CODEGRPSYNCFLG
Definition: ad9144.h:308
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:52
ad9152_dev::spi_desc
struct no_os_spi_desc * spi_desc
Definition: ad9152.h:1353
ad9152_remove
int32_t ad9152_remove(struct ad9152_dev *dev)
Free the resources allocated by ad9152_setup().
Definition: ad9152.c:201
ad9152_init_param::spi_init
struct no_os_spi_init_param spi_init
Definition: ad9152.h:1343
ad9152_spi_read
int32_t ad9152_spi_read(struct ad9152_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
ad9152_spi_read
Definition: ad9152.c:45
ad9152_init_param::interpolation
uint32_t interpolation
Definition: ad9152.h:1346
REG_PRBS_ERROR_Q
#define REG_PRBS_ERROR_Q
Definition: ad9144.h:184
ad9152_status
int32_t ad9152_status(struct ad9152_dev *dev)
ad9152_setup
Definition: ad9152.c:296
chip_id
chip_id
Definition: ad9172.h:51
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:140
REG_PRBS
#define REG_PRBS
Definition: ad9144.h:182
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