no-OS
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ad9545.h File Reference

Header file for ad9545 Driver. More...

#include <stdint.h>
#include "no_os_util.h"
#include "no_os_delay.h"
#include "no_os_clk.h"
#include "no_os_gpio.h"
#include "no_os_i2c.h"
#include "no_os_spi.h"
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Classes

struct  ad9545_outputs_regs
 
struct  ad9545_out_clk
 
struct  ad9545_dpll_profile
 
struct  ad9545_pll_clk
 
struct  ad9545_ref_in_clk
 
struct  ad9545_aux_nco_clk
 
struct  ad9545_aux_tdc_clk
 
struct  ad9545_aux_dpll_clk
 
struct  ad9545_sys_clk
 
struct  ad9545_dev
 
struct  ad9545_init_param
 

Macros

#define DRIVER_MODE_AC_COUPLED_IF   0
 
#define DRIVER_MODE_DC_COUPLED_1V2   1
 
#define DRIVER_MODE_DC_COUPLED_1V8   2
 
#define DRIVER_MODE_IN_PULL_UP   3
 
#define DRIVER_MODE_AC_COUPLED   0
 
#define DRIVER_MODE_DC_COUPLED   1
 
#define DRIVER_MODE_DC_COUPLED_LVDS   2
 
#define DRIVER_MODE_SINGLE_DIV_DIF   0
 
#define DRIVER_MODE_SINGLE_DIV   1
 
#define DRIVER_MODE_DUAL_DIV   2
 
#define AD9545_CLK_OUT   0
 
#define AD9545_CLK_PLL   1
 
#define AD9545_CLK_NCO   2
 
#define AD9545_CLK_AUX_TDC   3
 
#define AD9545_PLL0   0
 
#define AD9545_PLL1   1
 
#define AD9545_Q0A   0
 
#define AD9545_Q0AA   1
 
#define AD9545_Q0B   2
 
#define AD9545_Q0BB   3
 
#define AD9545_Q0C   4
 
#define AD9545_Q0CC   5
 
#define AD9545_Q1A   6
 
#define AD9545_Q1AA   7
 
#define AD9545_Q1B   8
 
#define AD9545_Q1BB   9
 
#define AD9545_NCO0   0
 
#define AD9545_NCO1   1
 
#define AD9545_CLK_AUX_TDC0   0
 
#define AD9545_CLK_AUX_TDC1   1
 
#define BYTE_ADDR_H   NO_OS_GENMASK(14, 8)
 
#define BYTE_ADDR_L   NO_OS_GENMASK(7, 0)
 
#define AD9545_CONFIG_0   0x0000
 
#define AD9545_PRODUCT_ID_LOW   0x0004
 
#define AD9545_PRODUCT_ID_HIGH   0x0005
 
#define AD9545_IO_UPDATE   0x000F
 
#define AD9545_M0_PIN   0x0102
 
#define AD9545_CHIP_ID   0x0121
 
#define AD9545_SYS_CLK_FB_DIV   0x0200
 
#define AD9545_SYS_CLK_INPUT   0x0201
 
#define AD9545_SYS_CLK_REF_FREQ   0x0202
 
#define AD9545_STABILITY_TIMER   0x0207
 
#define AD9545_COMPENSATE_TDCS   0x0280
 
#define AD9545_COMPENSATE_NCOS   0x0281
 
#define AD9545_COMPENSATE_DPLL   0x0282
 
#define AD9545_AUX_DPLL_CHANGE_LIMIT   0x0283
 
#define AD9545_AUX_DPLL_SOURCE   0x0284
 
#define AD9545_AUX_DPLL_LOOP_BW   0x0285
 
#define AD9545_REF_A_CTRL   0x0300
 
#define AD9545_REF_A_RDIV   0x0400
 
#define AD9545_REF_A_PERIOD   0x0404
 
#define AD9545_REF_A_OFFSET_LIMIT   0x040C
 
#define AD9545_REF_A_MONITOR_HYST   0x040F
 
#define AD9545_REF_A_VALID_TIMER   0x0410
 
#define AD9545_PHASE_LOCK_THRESH   0x0800
 
#define AD9545_PHASE_LOCK_FILL_RATE   0x0803
 
#define AD9545_PHASE_LOCK_DRAIN_RATE   0x0804
 
#define AD9545_FREQ_LOCK_THRESH   0x0805
 
#define AD9545_FREQ_LOCK_FILL_RATE   0x0808
 
#define AD9545_FREQ_LOCK_DRAIN_RATE   0x0809
 
#define AD9545_DPLL0_FTW   0x1000
 
#define AD9545_DPLL0_SLEW_RATE   0x1011
 
#define AD9545_MODULATION_COUNTER_A0   0x10C2
 
#define AD9545_MODULATION_COUNTER_B0   0x10C6
 
#define AD9545_MODULATION_COUNTER_C0   0x10CA
 
#define AD9545_MODULATOR_A0   0x10CF
 
#define AD9545_MODULATOR_B0   0x10D0
 
#define AD9545_MODULATOR_C0   0x10D1
 
#define AD9545_NSHOT_REQ_CH0   0x10D3
 
#define AD9545_NSHOT_EN_AB0   0x10D4
 
#define AD9545_NSHOT_EN_C0   0x10D5
 
#define AD9545_DRIVER_0A_CONF   0x10D7
 
#define AD9545_SYNC_CTRL0   0x10DB
 
#define AD9545_APLL0_M_DIV   0x1081
 
#define AD9545_Q0A_DIV   0x1100
 
#define AD9545_Q0A_PHASE   0x1104
 
#define AD9545_Q0A_PHASE_CONF   0x1108
 
#define AD9545_DPLL0_EN   0x1200
 
#define AD9545_DPLL0_SOURCE   0x1201
 
#define AD9545_DPLL0_ZERO_DELAY_FB   0x1202
 
#define AD9545_DPLL0_FB_MODE   0x1203
 
#define AD9545_DPLL0_LOOP_BW   0x1204
 
#define AD9545_DPLL0_HITLESS_N   0x1208
 
#define AD9545_DPLL0_N_DIV   0x120C
 
#define AD9545_DPLL0_FRAC   0x1210
 
#define AD9545_DPLL0_MOD   0x1213
 
#define AD9545_DPLL0_FAST_L1   0x1216
 
#define AD9545_DPLL0_FAST_L2   0x1217
 
#define AD9545_MODULATION_COUNTER_A1   0x14C2
 
#define AD9545_MODULATION_COUNTER_B1   0x14C6
 
#define AD9545_MODULATOR_A1   0x14CF
 
#define AD9545_MODULATOR_B1   0x14D0
 
#define AD9545_NSHOT_EN_AB1   0x14D4
 
#define AD9545_DRIVER_1A_CONF   0x14D7
 
#define AD9545_Q1A_DIV   0x1500
 
#define AD9545_Q1A_PHASE   0x1504
 
#define AD9545_Q1A_PHASE_CONF   0x1508
 
#define AD9545_CALIB_CLK   0x2000
 
#define AD9545_POWER_DOWN_REF   0x2001
 
#define AD9545_PWR_CALIB_CH0   0x2100
 
#define AD9545_CTRL_CH0   0x2101
 
#define AD9545_DIV_OPS_Q0A   0x2102
 
#define AD9545_DPLL0_MODE   0x2105
 
#define AD9545_DPLL0_FAST_MODE   0x2106
 
#define AD9545_DIV_OPS_Q1A   0x2202
 
#define AD9545_NCO0_CENTER_FREQ   0x2800
 
#define AD9545_NCO0_OFFSET_FREQ   0x2807
 
#define AD9545_NCO0_TAG_RATIO   0x280B
 
#define AD9545_NCO0_TAG_DELTA   0x280D
 
#define AD9545_NCO0_TYPE_ADJUST   0x280F
 
#define AD9545_NCO0_DELTA_RATE_LIMIT   0x2810
 
#define AD9545_NCO0_DELTA_ADJUST   0x2814
 
#define AD9545_NCO0_CYCLE_ADJUST   0x2819
 
#define AD9545_TDC0_DIV   0x2A00
 
#define AD9545_TDC0_PERIOD   0x2A01
 
#define AD9545_PLL_STATUS   0x3001
 
#define AD9545_MISC   0x3002
 
#define AD9545_TEMP0   0x3003
 
#define AD9545_REFA_STATUS   0x3005
 
#define AD9545_PLL0_STATUS   0x3100
 
#define AD9545_PLL0_OPERATION   0x3101
 
#define AD9545_SYS_CLK_STABILITY_PERIOD_MASK   NO_OS_GENMASK(19, 0)
 
#define AD9545_REF_CTRL_DIF_MSK   NO_OS_GENMASK(3, 2)
 
#define AD9545_REF_CTRL_REFA_MSK   NO_OS_GENMASK(5, 4)
 
#define AD9545_REF_CTRL_REFAA_MSK   NO_OS_GENMASK(7, 6)
 
#define AD9545_UPDATE_REGS   0x1
 
#define AD9545_RESET_REGS   0x81
 
#define AD9545_MX_PIN(x)   (AD9545_M0_PIN + (x))
 
#define AD9545_SYNC_CTRLX(x)   (AD9545_SYNC_CTRL0 + ((x) * 0x400))
 
#define AD9545_REF_X_RDIV(x)   (AD9545_REF_A_RDIV + ((x) * 0x20))
 
#define AD9545_REF_X_PERIOD(x)   (AD9545_REF_A_PERIOD + ((x) * 0x20))
 
#define AD9545_REF_X_OFFSET_LIMIT(x)   (AD9545_REF_A_OFFSET_LIMIT + ((x) * 0x20))
 
#define AD9545_REF_X_MONITOR_HYST(x)   (AD9545_REF_A_MONITOR_HYST + ((x) * 0x20))
 
#define AD9545_REF_X_VALID_TIMER(x)   (AD9545_REF_A_VALID_TIMER + ((x) * 0x20))
 
#define AD9545_REF_X_PHASE_LOCK_FILL(x)   (AD9545_PHASE_LOCK_FILL_RATE + ((x) * 0x20))
 
#define AD9545_REF_X_PHASE_LOCK_DRAIN(x)   (AD9545_PHASE_LOCK_DRAIN_RATE + ((x) * 0x20))
 
#define AD9545_REF_X_FREQ_LOCK_FILL(x)   (AD9545_FREQ_LOCK_FILL_RATE + ((x) * 0x20))
 
#define AD9545_REF_X_FREQ_LOCK_DRAIN(x)   (AD9545_FREQ_LOCK_DRAIN_RATE + ((x) * 0x20))
 
#define AD9545_SOURCEX_PHASE_THRESH(x)   (AD9545_PHASE_LOCK_THRESH + ((x) * 0x20))
 
#define AD9545_SOURCEX_FREQ_THRESH(x)   (AD9545_FREQ_LOCK_THRESH + ((x) * 0x20))
 
#define AD9545_NCOX_PHASE_THRESH(x)   (AD9545_SOURCEX_PHASE_THRESH((x) + 4))
 
#define AD9545_NCOX_FREQ_THRESH(x)   (AD9545_SOURCEX_FREQ_THRESH((x) + 4))
 
#define AD9545_APLLX_M_DIV(x)   (AD9545_APLL0_M_DIV + ((x) * 0x400))
 
#define AD9545_Q0_DIV(x)   (AD9545_Q0A_DIV + ((x) * 0x9))
 
#define AD9545_Q1_DIV(x)   (AD9545_Q1A_DIV + ((x) * 0x9))
 
#define AD9545_QX_DIV(x)
 
#define AD9545_Q0_PHASE(x)   (AD9545_Q0A_PHASE + ((x) * 0x9))
 
#define AD9545_Q1_PHASE(x)   (AD9545_Q1A_PHASE + ((x) * 0x9))
 
#define AD9545_QX_PHASE(x)
 
#define AD9545_Q0_PHASE_CONF(x)   (AD9545_Q0A_PHASE_CONF + ((x) * 0x9))
 
#define AD9545_Q1_PHASE_CONF(x)   (AD9545_Q1A_PHASE_CONF + ((x) * 0x9))
 
#define AD9545_QX_PHASE_CONF(x)
 
#define AD9545_NSHOT_REQ_CH(x)   (AD9545_NSHOT_REQ_CH0 + ((x) * 0x400))
 
#define AD9545_DPLLX_FTW(x)   (AD9545_DPLL0_FTW + ((x) * 0x400))
 
#define AD9545_DPLLX_SLEW_RATE(x)   (AD9545_DPLL0_SLEW_RATE + ((x) * 0x400))
 
#define AD9545_DPLLX_EN(x, y)   (AD9545_DPLL0_EN + ((x) * 0x400) + ((y) * 0x20))
 
#define AD9545_DPLLX_SOURCE(x, y)   (AD9545_DPLL0_SOURCE + ((x) * 0x400) + ((y) * 0x20))
 
#define AD9545_DPLLX_FB_PATH(x, y)   (AD9545_DPLL0_ZERO_DELAY_FB + ((x) * 0x400) + ((y) * 0x20))
 
#define AD9545_DPLLX_FB_MODE(x, y)   (AD9545_DPLL0_FB_MODE + ((x) * 0x400) + ((y) * 0x20))
 
#define AD9545_DPLLX_LOOP_BW(x, y)   (AD9545_DPLL0_LOOP_BW + ((x) * 0x400) + ((y) * 0x20))
 
#define AD9545_DPLLX_HITLESS_N(x, y)   (AD9545_DPLL0_HITLESS_N + ((x) * 0x400) + ((y) * 0x20))
 
#define AD9545_DPLLX_N_DIV(x, y)   (AD9545_DPLL0_N_DIV + ((x) * 0x400) + ((y) * 0x20))
 
#define AD9545_DPLLX_FRAC_DIV(x, y)   (AD9545_DPLL0_FRAC + ((x) * 0x400) + ((y) * 0x20))
 
#define AD9545_DPLLX_MOD_DIV(x, y)   (AD9545_DPLL0_MOD + ((x) * 0x400) + ((y) * 0x20))
 
#define AD9545_DPLLX_FAST_L1(x, y)   (AD9545_DPLL0_FAST_L1 + ((x) * 0x400) + ((y) * 0x20))
 
#define AD9545_DPLLX_FAST_L2(x, y)   (AD9545_DPLL0_FAST_L2 + ((x) * 0x400) + ((y) * 0x20))
 
#define AD9545_DIV_OPS_Q0(x)   (AD9545_DIV_OPS_Q0A + (x))
 
#define AD9545_DIV_OPS_Q1(x)   (AD9545_DIV_OPS_Q1A + (x))
 
#define AD9545_DIV_OPS_QX(x)
 
#define AD9545_PWR_CALIB_CHX(x)   (AD9545_PWR_CALIB_CH0 + ((x) * 0x100))
 
#define AD9545_PLLX_STATUS(x)   (AD9545_PLL0_STATUS + ((x) * 0x100))
 
#define AD9545_PLLX_OPERATION(x)   (AD9545_PLL0_OPERATION + ((x) * 0x100))
 
#define AD9545_CTRL_CH(x)   (AD9545_CTRL_CH0 + ((x) * 0x100))
 
#define AD9545_DPLLX_FAST_MODE(x)   (AD9545_DPLL0_FAST_MODE + ((x) * 0x100))
 
#define AD9545_REFX_STATUS(x)   (AD9545_REFA_STATUS + (x))
 
#define AD9545_PROFILE_SEL_MODE_MSK   NO_OS_GENMASK(3, 2)
 
#define AD9545_PROFILE_SEL_MODE(x)   no_os_field_prep(AD9545_PROFILE_SEL_MODE_MSK, x)
 
#define AD9545_NCOX_CENTER_FREQ(x)   (AD9545_NCO0_CENTER_FREQ + ((x) * 0x40))
 
#define AD9545_NCOX_OFFSET_FREQ(x)   (AD9545_NCO0_OFFSET_FREQ + ((x) * 0x40))
 
#define AD9545_NCOX_TAG_RATIO(x)   (AD9545_NCO0_TAG_RATIO + ((x) * 0x40))
 
#define AD9545_NCOX_TAG_DELTA(x)   (AD9545_NCO0_TAG_DELTA + ((x) * 0x40))
 
#define AD9545_NCOX_TYPE_ADJUST(x)   (AD9545_NCO0_TYPE_ADJUST + ((x) * 0x40))
 
#define AD9545_NCOX_DELTA_RATE_LIMIT(x)   (AD9545_NCO0_DELTA_RATE_LIMIT + ((x) * 0x40))
 
#define AD9545_NCOX_DELTA_ADJUST(x)   (AD9545_NCO0_DELTA_ADJUST + ((x) * 0x40))
 
#define AD9545_NCOX_CYCLE_ADJUST(x)   (AD9545_NCO0_CYCLE_ADJUST + ((x) * 0x40))
 
#define AD9545_NCO_CENTER_FREQ_INT_WIDTH   16
 
#define AD9545_NCO_CENTER_FREQ_FRAC_WIDTH   40
 
#define AD9545_NCO_CENTER_FREQ_WIDTH
 
#define AD9545_NCO_CENTER_FREQ_MSK   NO_OS_GENMASK_ULL(AD9545_NCO_CENTER_FREQ_WIDTH - 1, 0)
 
#define AD9545_NCO_CENTER_FREQ_INT_MSK
 
#define AD9545_NCO_CENTER_FREQ_FRAC_MSK   NO_OS_GENMASK_ULL(AD9545_NCO_CENTER_FREQ_FRAC_WIDTH - 1, 0)
 
#define AD9545_NCO_CENTER_FREQ_MAX   no_os_field_max_u64(AD9545_NCO_CENTER_FREQ_MSK)
 
#define AD9545_NCO_CENTER_FREQ_INT_MAX   no_os_field_max_u64(AD9545_NCO_CENTER_FREQ_INT_MSK)
 
#define AD9545_NCO_CENTER_FREQ_FRAC_MAX   no_os_field_max_u64(AD9545_NCO_CENTER_FREQ_FRAC_MSK)
 
#define AD9545_NCO_OFFSET_FREQ_INT_WIDTH   8
 
#define AD9545_NCO_OFFSET_FREQ_FRAC_WIDTH   24
 
#define AD9545_NCO_OFFSET_FREQ_WIDTH
 
#define AD9545_NCO_OFFSET_FREQ_MSK   NO_OS_GENMASK_ULL(AD9545_NCO_OFFSET_FREQ_WIDTH - 1, 0)
 
#define AD9545_NCO_OFFSET_FREQ_INT_MSK
 
#define AD9545_NCO_OFFSET_FREQ_FRAC_MSK   NO_OS_GENMASK_ULL(AD9545_NCO_OFFSET_FREQ_FRAC_WIDTH - 1, 0)
 
#define AD9545_NCO_OFFSET_FREQ_MAX   no_os_field_max(AD9545_NCO_OFFSET_FREQ_MSK)
 
#define AD9545_NCO_OFFSET_FREQ_INT_MAX   no_os_field_max(AD9545_NCO_OFFSET_FREQ_INT_MSK)
 
#define AD9545_NCO_OFFSET_FREQ_FRAC_MAX   no_os_field_max(AD9545_NCO_OFFSET_FREQ_FRAC_MSK)
 
#define AD9545_NCO_FREQ_INT_MAX
 
#define AD9545_TDCX_DIV(x)   (AD9545_TDC0_DIV + ((x) * 0x9))
 
#define AD9545_TDCX_PERIOD(x)   (AD9545_TDC0_PERIOD + ((x) * 0x9))
 
#define AD9545_MX_TO_TDCX(x)   (0x30 + (x))
 
#define AD9545_COMPENSATE_TDCS_VIA_AUX_DPLL   0x4
 
#define AD9545_COMPENSATE_NCOS_VIA_AUX_DPLL   0x44
 
#define AD9545_COMPNESATE_VIA_AUX_DPLL   0x44
 
#define AD9545_EN_PROFILE_MSK   NO_OS_BIT(0)
 
#define AD9545_SEL_PRIORITY_MSK   NO_OS_GENMASK(5, 1)
 
#define AD9545_EN_HITLESS_MSK   NO_OS_BIT(0)
 
#define AD9545_TAG_MODE_MSK   NO_OS_GENMASK(4, 2)
 
#define AD9545_BASE_FILTER_MSK   NO_OS_BIT(7)
 
#define AD9545_PWR_DOWN_CH   NO_OS_BIT(0)
 
#define AD9545_CALIB_APLL   NO_OS_BIT(1)
 
#define AD9545_SYNC_CTRL_DPLL_REF_MSK   NO_OS_BIT(2)
 
#define AD9545_SYNC_CTRL_MODE_MSK   NO_OS_GENMASK(1, 0)
 
#define AD9545_QX_HALF_DIV_MSK   NO_OS_BIT(5)
 
#define AD9545_QX_PHASE_32_MSK   NO_OS_BIT(6)
 
#define AD9545_DIV_OPS_MUTE_A_MSK   NO_OS_BIT(2)
 
#define AD9545_DIV_OPS_MUTE_AA_MSK   NO_OS_BIT(3)
 
#define AD9545_MODULATOR_EN   NO_OS_BIT(0)
 
#define AD9545_NSHOT_NR_MSK   NO_OS_GENMASK(5, 0)
 
#define AD9545_CTRL_CH_NSHOT_MSK   NO_OS_BIT(0)
 
#define AD9545_PLLX_LOCK(x, y)   ((1 << (4 + (x))) & (y))
 
#define AD9545_MISC_AUX_NC0_ERR_MSK   NO_OS_GENMASK(5, 4)
 
#define AD9545_MISC_AUX_NC1_ERR_MSK   NO_OS_GENMASK(7, 6)
 
#define AD9545_AUX_DPLL_LOCK_MSK   NO_OS_BIT(1)
 
#define AD9545_AUX_DPLL_REF_FAULT   NO_OS_BIT(2)
 
#define AD9545_REFX_SLOW_MSK   NO_OS_BIT(0)
 
#define AD9545_REFX_FAST_MSK   NO_OS_BIT(1)
 
#define AD9545_REFX_JITTER_MSK   NO_OS_BIT(2)
 
#define AD9545_REFX_FAULT_MSK   NO_OS_BIT(3)
 
#define AD9545_REFX_VALID_MSK   NO_OS_BIT(4)
 
#define AD9545_REFX_LOS_MSK   NO_OS_BIT(5)
 
#define AD9545_PLL_LOCKED   NO_OS_BIT(0)
 
#define AD9545_PLL_FREERUN   NO_OS_BIT(0)
 
#define AD9545_PLL_HOLDOVER   NO_OS_BIT(1)
 
#define AD9545_PLL_ACTIVE   NO_OS_BIT(3)
 
#define AD9545_PLL_ACTIVE_PROFILE   NO_OS_GENMASK(6, 4)
 
#define AD9545_SYS_PLL_STABLE_MSK   NO_OS_GENMASK(1, 0)
 
#define AD9545_SYS_PLL_STABLE(x)   (((x) & AD9545_SYS_PLL_STABLE_MSK) == 0x3)
 
#define AD9545_APLL_LOCKED(x)   ((x) & NO_OS_BIT(3))
 
#define AD9545_NO_TAGGING   0
 
#define AD9545_FB_PATH_TAG   2
 
#define AD9545_SYS_CLK_STABILITY_MS   50
 
#define AD9545_R_DIV_MSK   NO_OS_GENMASK(29, 0)
 
#define AD9545_R_DIV_MAX   0x40000000
 
#define AD9545_IN_MAX_TDC_FREQ_HZ   200000
 
#define AD9545_MAX_REFS   4
 
#define AD9545_APLL_M_DIV_MIN   1
 
#define AD9545_APLL_M_DIV_MAX   255
 
#define AD9545_DPLL_MAX_N   1073741823
 
#define AD9545_DPLL_MAX_FRAC   16777215
 
#define AD9545_DPLL_MAX_MOD   16777215
 
#define AD9545_MAX_DPLL_PROFILES   6
 
#define AD9545_MAX_NSHOT_PULSES   63
 
#define AD9545_MAX_ZERO_DELAY_RATE   200000000
 
#define AD9545_MIN_SYS_CLK_FREQ   2250
 
#define AD9545_MAX_SYS_CLK_FREQ   2415
 
#define AD9545_MIN_DIV_RATIO   4
 
#define AD9545_MAX_DIV_RATIO   256
 

Typedefs

typedef int32_t(* ad9545_reg_read_func) (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
 
typedef int32_t(* ad9545_reg_write_func) (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t reg_data)
 
typedef int32_t(* ad9545_reg_read_multi_func) (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data, uint16_t count)
 
typedef int32_t(* ad9545_reg_write_multi_func) (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data, uint16_t count)
 

Enumerations

enum  ad9545_comm_type {
  SPI,
  I2C
}
 
enum  ad9545_ref_mode {
  AD9545_SINGLE_ENDED = 0,
  AD9545_DIFFERENTIAL
}
 
enum  ad9545_single_ended_config {
  AD9545_AC_COUPLED_IF = 0,
  AD9545_DC_COUPLED_1V2,
  AD9545_DC_COUPLED_1V8,
  AD9545_IN_PULL_UP
}
 
enum  ad9545_diferential_config {
  AD9545_AC_COUPLED = 0,
  AD9545_DC_COUPLED,
  AD9545_DC_COUPLED_LVDS
}
 
enum  ad9545_output_mode {
  AD9545_SINGLE_DIV_DIF = 0,
  AD9545_SINGLE_DIV,
  AD9545_DUAL_DIV
}
 

Functions

int32_t ad9545_spi_reg_read (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
 
int32_t ad9545_spi_reg_read_multiple (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data, uint16_t count)
 
int32_t ad9545_spi_reg_write (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t reg_data)
 
int32_t ad9545_spi_reg_write_multiple (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data, uint16_t count)
 
int32_t ad9545_i2c_reg_read (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
 
int32_t ad9545_i2c_reg_write (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t reg_data)
 
int32_t ad9545_i2c_reg_read_multiple (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data, uint16_t count)
 
int32_t ad9545_i2c_reg_write_multiple (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data, uint16_t count)
 
int32_t ad9545_write_mask (struct ad9545_dev *dev, uint16_t reg_addr, uint32_t mask, uint8_t data)
 
int ad9545_calib_aplls (struct ad9545_dev *dev)
 
int32_t ad9545_setup (struct ad9545_dev *dev)
 
int32_t ad9545_init (struct ad9545_dev **device, struct ad9545_init_param *init_param)
 
int32_t ad9545_remove (struct ad9545_dev *dev)
 Free the memory allocated by ad9545_init(). More...
 

Detailed Description

Header file for ad9545 Driver.

Author
Jonathan Santos (Jonat.nosp@m.han..nosp@m.Santo.nosp@m.s@an.nosp@m.alog..nosp@m.com)

Copyright 2024(c) Analog Devices, Inc.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ AD9545_APLL0_M_DIV

#define AD9545_APLL0_M_DIV   0x1081

◆ AD9545_APLL_LOCKED

#define AD9545_APLL_LOCKED (   x)    ((x) & NO_OS_BIT(3))

◆ AD9545_APLL_M_DIV_MAX

#define AD9545_APLL_M_DIV_MAX   255

◆ AD9545_APLL_M_DIV_MIN

#define AD9545_APLL_M_DIV_MIN   1

◆ AD9545_APLLX_M_DIV

#define AD9545_APLLX_M_DIV (   x)    (AD9545_APLL0_M_DIV + ((x) * 0x400))

◆ AD9545_AUX_DPLL_CHANGE_LIMIT

#define AD9545_AUX_DPLL_CHANGE_LIMIT   0x0283

◆ AD9545_AUX_DPLL_LOCK_MSK

#define AD9545_AUX_DPLL_LOCK_MSK   NO_OS_BIT(1)

◆ AD9545_AUX_DPLL_LOOP_BW

#define AD9545_AUX_DPLL_LOOP_BW   0x0285

◆ AD9545_AUX_DPLL_REF_FAULT

#define AD9545_AUX_DPLL_REF_FAULT   NO_OS_BIT(2)

◆ AD9545_AUX_DPLL_SOURCE

#define AD9545_AUX_DPLL_SOURCE   0x0284

◆ AD9545_BASE_FILTER_MSK

#define AD9545_BASE_FILTER_MSK   NO_OS_BIT(7)

◆ AD9545_CALIB_APLL

#define AD9545_CALIB_APLL   NO_OS_BIT(1)

◆ AD9545_CALIB_CLK

#define AD9545_CALIB_CLK   0x2000

◆ AD9545_CHIP_ID

#define AD9545_CHIP_ID   0x0121

◆ AD9545_CLK_AUX_TDC

#define AD9545_CLK_AUX_TDC   3

◆ AD9545_CLK_AUX_TDC0

#define AD9545_CLK_AUX_TDC0   0

◆ AD9545_CLK_AUX_TDC1

#define AD9545_CLK_AUX_TDC1   1

◆ AD9545_CLK_NCO

#define AD9545_CLK_NCO   2

◆ AD9545_CLK_OUT

#define AD9545_CLK_OUT   0

◆ AD9545_CLK_PLL

#define AD9545_CLK_PLL   1

◆ AD9545_COMPENSATE_DPLL

#define AD9545_COMPENSATE_DPLL   0x0282

◆ AD9545_COMPENSATE_NCOS

#define AD9545_COMPENSATE_NCOS   0x0281

◆ AD9545_COMPENSATE_NCOS_VIA_AUX_DPLL

#define AD9545_COMPENSATE_NCOS_VIA_AUX_DPLL   0x44

◆ AD9545_COMPENSATE_TDCS

#define AD9545_COMPENSATE_TDCS   0x0280

◆ AD9545_COMPENSATE_TDCS_VIA_AUX_DPLL

#define AD9545_COMPENSATE_TDCS_VIA_AUX_DPLL   0x4

◆ AD9545_COMPNESATE_VIA_AUX_DPLL

#define AD9545_COMPNESATE_VIA_AUX_DPLL   0x44

◆ AD9545_CONFIG_0

#define AD9545_CONFIG_0   0x0000

◆ AD9545_CTRL_CH

#define AD9545_CTRL_CH (   x)    (AD9545_CTRL_CH0 + ((x) * 0x100))

◆ AD9545_CTRL_CH0

#define AD9545_CTRL_CH0   0x2101

◆ AD9545_CTRL_CH_NSHOT_MSK

#define AD9545_CTRL_CH_NSHOT_MSK   NO_OS_BIT(0)

◆ AD9545_DIV_OPS_MUTE_A_MSK

#define AD9545_DIV_OPS_MUTE_A_MSK   NO_OS_BIT(2)

◆ AD9545_DIV_OPS_MUTE_AA_MSK

#define AD9545_DIV_OPS_MUTE_AA_MSK   NO_OS_BIT(3)

◆ AD9545_DIV_OPS_Q0

#define AD9545_DIV_OPS_Q0 (   x)    (AD9545_DIV_OPS_Q0A + (x))

◆ AD9545_DIV_OPS_Q0A

#define AD9545_DIV_OPS_Q0A   0x2102

◆ AD9545_DIV_OPS_Q1

#define AD9545_DIV_OPS_Q1 (   x)    (AD9545_DIV_OPS_Q1A + (x))

◆ AD9545_DIV_OPS_Q1A

#define AD9545_DIV_OPS_Q1A   0x2202

◆ AD9545_DIV_OPS_QX

#define AD9545_DIV_OPS_QX (   x)
Value:
({ \
typeof(x) x_ = (x) / 2; \
\
(x_ > 2) ? AD9545_DIV_OPS_Q1(x_ - 3) : AD9545_DIV_OPS_Q0(x_); \
})

◆ AD9545_DPLL0_EN

#define AD9545_DPLL0_EN   0x1200

◆ AD9545_DPLL0_FAST_L1

#define AD9545_DPLL0_FAST_L1   0x1216

◆ AD9545_DPLL0_FAST_L2

#define AD9545_DPLL0_FAST_L2   0x1217

◆ AD9545_DPLL0_FAST_MODE

#define AD9545_DPLL0_FAST_MODE   0x2106

◆ AD9545_DPLL0_FB_MODE

#define AD9545_DPLL0_FB_MODE   0x1203

◆ AD9545_DPLL0_FRAC

#define AD9545_DPLL0_FRAC   0x1210

◆ AD9545_DPLL0_FTW

#define AD9545_DPLL0_FTW   0x1000

◆ AD9545_DPLL0_HITLESS_N

#define AD9545_DPLL0_HITLESS_N   0x1208

◆ AD9545_DPLL0_LOOP_BW

#define AD9545_DPLL0_LOOP_BW   0x1204

◆ AD9545_DPLL0_MOD

#define AD9545_DPLL0_MOD   0x1213

◆ AD9545_DPLL0_MODE

#define AD9545_DPLL0_MODE   0x2105

◆ AD9545_DPLL0_N_DIV

#define AD9545_DPLL0_N_DIV   0x120C

◆ AD9545_DPLL0_SLEW_RATE

#define AD9545_DPLL0_SLEW_RATE   0x1011

◆ AD9545_DPLL0_SOURCE

#define AD9545_DPLL0_SOURCE   0x1201

◆ AD9545_DPLL0_ZERO_DELAY_FB

#define AD9545_DPLL0_ZERO_DELAY_FB   0x1202

◆ AD9545_DPLL_MAX_FRAC

#define AD9545_DPLL_MAX_FRAC   16777215

◆ AD9545_DPLL_MAX_MOD

#define AD9545_DPLL_MAX_MOD   16777215

◆ AD9545_DPLL_MAX_N

#define AD9545_DPLL_MAX_N   1073741823

◆ AD9545_DPLLX_EN

#define AD9545_DPLLX_EN (   x,
  y 
)    (AD9545_DPLL0_EN + ((x) * 0x400) + ((y) * 0x20))

◆ AD9545_DPLLX_FAST_L1

#define AD9545_DPLLX_FAST_L1 (   x,
  y 
)    (AD9545_DPLL0_FAST_L1 + ((x) * 0x400) + ((y) * 0x20))

◆ AD9545_DPLLX_FAST_L2

#define AD9545_DPLLX_FAST_L2 (   x,
  y 
)    (AD9545_DPLL0_FAST_L2 + ((x) * 0x400) + ((y) * 0x20))

◆ AD9545_DPLLX_FAST_MODE

#define AD9545_DPLLX_FAST_MODE (   x)    (AD9545_DPLL0_FAST_MODE + ((x) * 0x100))

◆ AD9545_DPLLX_FB_MODE

#define AD9545_DPLLX_FB_MODE (   x,
  y 
)    (AD9545_DPLL0_FB_MODE + ((x) * 0x400) + ((y) * 0x20))

◆ AD9545_DPLLX_FB_PATH

#define AD9545_DPLLX_FB_PATH (   x,
  y 
)    (AD9545_DPLL0_ZERO_DELAY_FB + ((x) * 0x400) + ((y) * 0x20))

◆ AD9545_DPLLX_FRAC_DIV

#define AD9545_DPLLX_FRAC_DIV (   x,
  y 
)    (AD9545_DPLL0_FRAC + ((x) * 0x400) + ((y) * 0x20))

◆ AD9545_DPLLX_FTW

#define AD9545_DPLLX_FTW (   x)    (AD9545_DPLL0_FTW + ((x) * 0x400))

◆ AD9545_DPLLX_HITLESS_N

#define AD9545_DPLLX_HITLESS_N (   x,
  y 
)    (AD9545_DPLL0_HITLESS_N + ((x) * 0x400) + ((y) * 0x20))

◆ AD9545_DPLLX_LOOP_BW

#define AD9545_DPLLX_LOOP_BW (   x,
  y 
)    (AD9545_DPLL0_LOOP_BW + ((x) * 0x400) + ((y) * 0x20))

◆ AD9545_DPLLX_MOD_DIV

#define AD9545_DPLLX_MOD_DIV (   x,
  y 
)    (AD9545_DPLL0_MOD + ((x) * 0x400) + ((y) * 0x20))

◆ AD9545_DPLLX_N_DIV

#define AD9545_DPLLX_N_DIV (   x,
  y 
)    (AD9545_DPLL0_N_DIV + ((x) * 0x400) + ((y) * 0x20))

◆ AD9545_DPLLX_SLEW_RATE

#define AD9545_DPLLX_SLEW_RATE (   x)    (AD9545_DPLL0_SLEW_RATE + ((x) * 0x400))

◆ AD9545_DPLLX_SOURCE

#define AD9545_DPLLX_SOURCE (   x,
  y 
)    (AD9545_DPLL0_SOURCE + ((x) * 0x400) + ((y) * 0x20))

◆ AD9545_DRIVER_0A_CONF

#define AD9545_DRIVER_0A_CONF   0x10D7

◆ AD9545_DRIVER_1A_CONF

#define AD9545_DRIVER_1A_CONF   0x14D7

◆ AD9545_EN_HITLESS_MSK

#define AD9545_EN_HITLESS_MSK   NO_OS_BIT(0)

◆ AD9545_EN_PROFILE_MSK

#define AD9545_EN_PROFILE_MSK   NO_OS_BIT(0)

◆ AD9545_FB_PATH_TAG

#define AD9545_FB_PATH_TAG   2

◆ AD9545_FREQ_LOCK_DRAIN_RATE

#define AD9545_FREQ_LOCK_DRAIN_RATE   0x0809

◆ AD9545_FREQ_LOCK_FILL_RATE

#define AD9545_FREQ_LOCK_FILL_RATE   0x0808

◆ AD9545_FREQ_LOCK_THRESH

#define AD9545_FREQ_LOCK_THRESH   0x0805

◆ AD9545_IN_MAX_TDC_FREQ_HZ

#define AD9545_IN_MAX_TDC_FREQ_HZ   200000

◆ AD9545_IO_UPDATE

#define AD9545_IO_UPDATE   0x000F

◆ AD9545_M0_PIN

#define AD9545_M0_PIN   0x0102

◆ AD9545_MAX_DIV_RATIO

#define AD9545_MAX_DIV_RATIO   256

◆ AD9545_MAX_DPLL_PROFILES

#define AD9545_MAX_DPLL_PROFILES   6

◆ AD9545_MAX_NSHOT_PULSES

#define AD9545_MAX_NSHOT_PULSES   63

◆ AD9545_MAX_REFS

#define AD9545_MAX_REFS   4

◆ AD9545_MAX_SYS_CLK_FREQ

#define AD9545_MAX_SYS_CLK_FREQ   2415

◆ AD9545_MAX_ZERO_DELAY_RATE

#define AD9545_MAX_ZERO_DELAY_RATE   200000000

◆ AD9545_MIN_DIV_RATIO

#define AD9545_MIN_DIV_RATIO   4

◆ AD9545_MIN_SYS_CLK_FREQ

#define AD9545_MIN_SYS_CLK_FREQ   2250

◆ AD9545_MISC

#define AD9545_MISC   0x3002

◆ AD9545_MISC_AUX_NC0_ERR_MSK

#define AD9545_MISC_AUX_NC0_ERR_MSK   NO_OS_GENMASK(5, 4)

◆ AD9545_MISC_AUX_NC1_ERR_MSK

#define AD9545_MISC_AUX_NC1_ERR_MSK   NO_OS_GENMASK(7, 6)

◆ AD9545_MODULATION_COUNTER_A0

#define AD9545_MODULATION_COUNTER_A0   0x10C2

◆ AD9545_MODULATION_COUNTER_A1

#define AD9545_MODULATION_COUNTER_A1   0x14C2

◆ AD9545_MODULATION_COUNTER_B0

#define AD9545_MODULATION_COUNTER_B0   0x10C6

◆ AD9545_MODULATION_COUNTER_B1

#define AD9545_MODULATION_COUNTER_B1   0x14C6

◆ AD9545_MODULATION_COUNTER_C0

#define AD9545_MODULATION_COUNTER_C0   0x10CA

◆ AD9545_MODULATOR_A0

#define AD9545_MODULATOR_A0   0x10CF

◆ AD9545_MODULATOR_A1

#define AD9545_MODULATOR_A1   0x14CF

◆ AD9545_MODULATOR_B0

#define AD9545_MODULATOR_B0   0x10D0

◆ AD9545_MODULATOR_B1

#define AD9545_MODULATOR_B1   0x14D0

◆ AD9545_MODULATOR_C0

#define AD9545_MODULATOR_C0   0x10D1

◆ AD9545_MODULATOR_EN

#define AD9545_MODULATOR_EN   NO_OS_BIT(0)

◆ AD9545_MX_PIN

#define AD9545_MX_PIN (   x)    (AD9545_M0_PIN + (x))

◆ AD9545_MX_TO_TDCX

#define AD9545_MX_TO_TDCX (   x)    (0x30 + (x))

◆ AD9545_NCO0

#define AD9545_NCO0   0

◆ AD9545_NCO0_CENTER_FREQ

#define AD9545_NCO0_CENTER_FREQ   0x2800

◆ AD9545_NCO0_CYCLE_ADJUST

#define AD9545_NCO0_CYCLE_ADJUST   0x2819

◆ AD9545_NCO0_DELTA_ADJUST

#define AD9545_NCO0_DELTA_ADJUST   0x2814

◆ AD9545_NCO0_DELTA_RATE_LIMIT

#define AD9545_NCO0_DELTA_RATE_LIMIT   0x2810

◆ AD9545_NCO0_OFFSET_FREQ

#define AD9545_NCO0_OFFSET_FREQ   0x2807

◆ AD9545_NCO0_TAG_DELTA

#define AD9545_NCO0_TAG_DELTA   0x280D

◆ AD9545_NCO0_TAG_RATIO

#define AD9545_NCO0_TAG_RATIO   0x280B

◆ AD9545_NCO0_TYPE_ADJUST

#define AD9545_NCO0_TYPE_ADJUST   0x280F

◆ AD9545_NCO1

#define AD9545_NCO1   1

◆ AD9545_NCO_CENTER_FREQ_FRAC_MAX

#define AD9545_NCO_CENTER_FREQ_FRAC_MAX   no_os_field_max_u64(AD9545_NCO_CENTER_FREQ_FRAC_MSK)

◆ AD9545_NCO_CENTER_FREQ_FRAC_MSK

#define AD9545_NCO_CENTER_FREQ_FRAC_MSK   NO_OS_GENMASK_ULL(AD9545_NCO_CENTER_FREQ_FRAC_WIDTH - 1, 0)

◆ AD9545_NCO_CENTER_FREQ_FRAC_WIDTH

#define AD9545_NCO_CENTER_FREQ_FRAC_WIDTH   40

◆ AD9545_NCO_CENTER_FREQ_INT_MAX

#define AD9545_NCO_CENTER_FREQ_INT_MAX   no_os_field_max_u64(AD9545_NCO_CENTER_FREQ_INT_MSK)

◆ AD9545_NCO_CENTER_FREQ_INT_MSK

#define AD9545_NCO_CENTER_FREQ_INT_MSK
Value:
NO_OS_GENMASK_ULL(AD9545_NCO_CENTER_FREQ_WIDTH - 1, \
AD9545_NCO_CENTER_FREQ_FRAC_WIDTH)

◆ AD9545_NCO_CENTER_FREQ_INT_WIDTH

#define AD9545_NCO_CENTER_FREQ_INT_WIDTH   16

◆ AD9545_NCO_CENTER_FREQ_MAX

#define AD9545_NCO_CENTER_FREQ_MAX   no_os_field_max_u64(AD9545_NCO_CENTER_FREQ_MSK)

◆ AD9545_NCO_CENTER_FREQ_MSK

#define AD9545_NCO_CENTER_FREQ_MSK   NO_OS_GENMASK_ULL(AD9545_NCO_CENTER_FREQ_WIDTH - 1, 0)

◆ AD9545_NCO_CENTER_FREQ_WIDTH

#define AD9545_NCO_CENTER_FREQ_WIDTH
Value:
(AD9545_NCO_CENTER_FREQ_INT_WIDTH + \
AD9545_NCO_CENTER_FREQ_FRAC_WIDTH)

◆ AD9545_NCO_FREQ_INT_MAX

#define AD9545_NCO_FREQ_INT_MAX
Value:
(AD9545_NCO_CENTER_FREQ_INT_MAX + \
AD9545_NCO_OFFSET_FREQ_INT_MAX)

◆ AD9545_NCO_OFFSET_FREQ_FRAC_MAX

#define AD9545_NCO_OFFSET_FREQ_FRAC_MAX   no_os_field_max(AD9545_NCO_OFFSET_FREQ_FRAC_MSK)

◆ AD9545_NCO_OFFSET_FREQ_FRAC_MSK

#define AD9545_NCO_OFFSET_FREQ_FRAC_MSK   NO_OS_GENMASK_ULL(AD9545_NCO_OFFSET_FREQ_FRAC_WIDTH - 1, 0)

◆ AD9545_NCO_OFFSET_FREQ_FRAC_WIDTH

#define AD9545_NCO_OFFSET_FREQ_FRAC_WIDTH   24

◆ AD9545_NCO_OFFSET_FREQ_INT_MAX

#define AD9545_NCO_OFFSET_FREQ_INT_MAX   no_os_field_max(AD9545_NCO_OFFSET_FREQ_INT_MSK)

◆ AD9545_NCO_OFFSET_FREQ_INT_MSK

#define AD9545_NCO_OFFSET_FREQ_INT_MSK
Value:
NO_OS_GENMASK_ULL(AD9545_NCO_OFFSET_FREQ_WIDTH - 1, \
AD9545_NCO_OFFSET_FREQ_FRAC_WIDTH)

◆ AD9545_NCO_OFFSET_FREQ_INT_WIDTH

#define AD9545_NCO_OFFSET_FREQ_INT_WIDTH   8

◆ AD9545_NCO_OFFSET_FREQ_MAX

#define AD9545_NCO_OFFSET_FREQ_MAX   no_os_field_max(AD9545_NCO_OFFSET_FREQ_MSK)

◆ AD9545_NCO_OFFSET_FREQ_MSK

#define AD9545_NCO_OFFSET_FREQ_MSK   NO_OS_GENMASK_ULL(AD9545_NCO_OFFSET_FREQ_WIDTH - 1, 0)

◆ AD9545_NCO_OFFSET_FREQ_WIDTH

#define AD9545_NCO_OFFSET_FREQ_WIDTH
Value:
(AD9545_NCO_OFFSET_FREQ_INT_WIDTH + \
AD9545_NCO_OFFSET_FREQ_FRAC_WIDTH)

◆ AD9545_NCOX_CENTER_FREQ

#define AD9545_NCOX_CENTER_FREQ (   x)    (AD9545_NCO0_CENTER_FREQ + ((x) * 0x40))

◆ AD9545_NCOX_CYCLE_ADJUST

#define AD9545_NCOX_CYCLE_ADJUST (   x)    (AD9545_NCO0_CYCLE_ADJUST + ((x) * 0x40))

◆ AD9545_NCOX_DELTA_ADJUST

#define AD9545_NCOX_DELTA_ADJUST (   x)    (AD9545_NCO0_DELTA_ADJUST + ((x) * 0x40))

◆ AD9545_NCOX_DELTA_RATE_LIMIT

#define AD9545_NCOX_DELTA_RATE_LIMIT (   x)    (AD9545_NCO0_DELTA_RATE_LIMIT + ((x) * 0x40))

◆ AD9545_NCOX_FREQ_THRESH

#define AD9545_NCOX_FREQ_THRESH (   x)    (AD9545_SOURCEX_FREQ_THRESH((x) + 4))

◆ AD9545_NCOX_OFFSET_FREQ

#define AD9545_NCOX_OFFSET_FREQ (   x)    (AD9545_NCO0_OFFSET_FREQ + ((x) * 0x40))

◆ AD9545_NCOX_PHASE_THRESH

#define AD9545_NCOX_PHASE_THRESH (   x)    (AD9545_SOURCEX_PHASE_THRESH((x) + 4))

◆ AD9545_NCOX_TAG_DELTA

#define AD9545_NCOX_TAG_DELTA (   x)    (AD9545_NCO0_TAG_DELTA + ((x) * 0x40))

◆ AD9545_NCOX_TAG_RATIO

#define AD9545_NCOX_TAG_RATIO (   x)    (AD9545_NCO0_TAG_RATIO + ((x) * 0x40))

◆ AD9545_NCOX_TYPE_ADJUST

#define AD9545_NCOX_TYPE_ADJUST (   x)    (AD9545_NCO0_TYPE_ADJUST + ((x) * 0x40))

◆ AD9545_NO_TAGGING

#define AD9545_NO_TAGGING   0

◆ AD9545_NSHOT_EN_AB0

#define AD9545_NSHOT_EN_AB0   0x10D4

◆ AD9545_NSHOT_EN_AB1

#define AD9545_NSHOT_EN_AB1   0x14D4

◆ AD9545_NSHOT_EN_C0

#define AD9545_NSHOT_EN_C0   0x10D5

◆ AD9545_NSHOT_NR_MSK

#define AD9545_NSHOT_NR_MSK   NO_OS_GENMASK(5, 0)

◆ AD9545_NSHOT_REQ_CH

#define AD9545_NSHOT_REQ_CH (   x)    (AD9545_NSHOT_REQ_CH0 + ((x) * 0x400))

◆ AD9545_NSHOT_REQ_CH0

#define AD9545_NSHOT_REQ_CH0   0x10D3

◆ AD9545_PHASE_LOCK_DRAIN_RATE

#define AD9545_PHASE_LOCK_DRAIN_RATE   0x0804

◆ AD9545_PHASE_LOCK_FILL_RATE

#define AD9545_PHASE_LOCK_FILL_RATE   0x0803

◆ AD9545_PHASE_LOCK_THRESH

#define AD9545_PHASE_LOCK_THRESH   0x0800

◆ AD9545_PLL0

#define AD9545_PLL0   0

◆ AD9545_PLL0_OPERATION

#define AD9545_PLL0_OPERATION   0x3101

◆ AD9545_PLL0_STATUS

#define AD9545_PLL0_STATUS   0x3100

◆ AD9545_PLL1

#define AD9545_PLL1   1

◆ AD9545_PLL_ACTIVE

#define AD9545_PLL_ACTIVE   NO_OS_BIT(3)

◆ AD9545_PLL_ACTIVE_PROFILE

#define AD9545_PLL_ACTIVE_PROFILE   NO_OS_GENMASK(6, 4)

◆ AD9545_PLL_FREERUN

#define AD9545_PLL_FREERUN   NO_OS_BIT(0)

◆ AD9545_PLL_HOLDOVER

#define AD9545_PLL_HOLDOVER   NO_OS_BIT(1)

◆ AD9545_PLL_LOCKED

#define AD9545_PLL_LOCKED   NO_OS_BIT(0)

◆ AD9545_PLL_STATUS

#define AD9545_PLL_STATUS   0x3001

◆ AD9545_PLLX_LOCK

#define AD9545_PLLX_LOCK (   x,
  y 
)    ((1 << (4 + (x))) & (y))

◆ AD9545_PLLX_OPERATION

#define AD9545_PLLX_OPERATION (   x)    (AD9545_PLL0_OPERATION + ((x) * 0x100))

◆ AD9545_PLLX_STATUS

#define AD9545_PLLX_STATUS (   x)    (AD9545_PLL0_STATUS + ((x) * 0x100))

◆ AD9545_POWER_DOWN_REF

#define AD9545_POWER_DOWN_REF   0x2001

◆ AD9545_PRODUCT_ID_HIGH

#define AD9545_PRODUCT_ID_HIGH   0x0005

◆ AD9545_PRODUCT_ID_LOW

#define AD9545_PRODUCT_ID_LOW   0x0004

◆ AD9545_PROFILE_SEL_MODE

#define AD9545_PROFILE_SEL_MODE (   x)    no_os_field_prep(AD9545_PROFILE_SEL_MODE_MSK, x)

◆ AD9545_PROFILE_SEL_MODE_MSK

#define AD9545_PROFILE_SEL_MODE_MSK   NO_OS_GENMASK(3, 2)

◆ AD9545_PWR_CALIB_CH0

#define AD9545_PWR_CALIB_CH0   0x2100

◆ AD9545_PWR_CALIB_CHX

#define AD9545_PWR_CALIB_CHX (   x)    (AD9545_PWR_CALIB_CH0 + ((x) * 0x100))

◆ AD9545_PWR_DOWN_CH

#define AD9545_PWR_DOWN_CH   NO_OS_BIT(0)

◆ AD9545_Q0_DIV

#define AD9545_Q0_DIV (   x)    (AD9545_Q0A_DIV + ((x) * 0x9))

◆ AD9545_Q0_PHASE

#define AD9545_Q0_PHASE (   x)    (AD9545_Q0A_PHASE + ((x) * 0x9))

◆ AD9545_Q0_PHASE_CONF

#define AD9545_Q0_PHASE_CONF (   x)    (AD9545_Q0A_PHASE_CONF + ((x) * 0x9))

◆ AD9545_Q0A

#define AD9545_Q0A   0

◆ AD9545_Q0A_DIV

#define AD9545_Q0A_DIV   0x1100

◆ AD9545_Q0A_PHASE

#define AD9545_Q0A_PHASE   0x1104

◆ AD9545_Q0A_PHASE_CONF

#define AD9545_Q0A_PHASE_CONF   0x1108

◆ AD9545_Q0AA

#define AD9545_Q0AA   1

◆ AD9545_Q0B

#define AD9545_Q0B   2

◆ AD9545_Q0BB

#define AD9545_Q0BB   3

◆ AD9545_Q0C

#define AD9545_Q0C   4

◆ AD9545_Q0CC

#define AD9545_Q0CC   5

◆ AD9545_Q1_DIV

#define AD9545_Q1_DIV (   x)    (AD9545_Q1A_DIV + ((x) * 0x9))

◆ AD9545_Q1_PHASE

#define AD9545_Q1_PHASE (   x)    (AD9545_Q1A_PHASE + ((x) * 0x9))

◆ AD9545_Q1_PHASE_CONF

#define AD9545_Q1_PHASE_CONF (   x)    (AD9545_Q1A_PHASE_CONF + ((x) * 0x9))

◆ AD9545_Q1A

#define AD9545_Q1A   6

◆ AD9545_Q1A_DIV

#define AD9545_Q1A_DIV   0x1500

◆ AD9545_Q1A_PHASE

#define AD9545_Q1A_PHASE   0x1504

◆ AD9545_Q1A_PHASE_CONF

#define AD9545_Q1A_PHASE_CONF   0x1508

◆ AD9545_Q1AA

#define AD9545_Q1AA   7

◆ AD9545_Q1B

#define AD9545_Q1B   8

◆ AD9545_Q1BB

#define AD9545_Q1BB   9

◆ AD9545_QX_DIV

#define AD9545_QX_DIV (   x)
Value:
({ \
typeof(x) x_ = (x); \
\
(x_ > 5) ? AD9545_Q1_DIV(x_ - 6) : AD9545_Q0_DIV(x_); \
})

◆ AD9545_QX_HALF_DIV_MSK

#define AD9545_QX_HALF_DIV_MSK   NO_OS_BIT(5)

◆ AD9545_QX_PHASE

#define AD9545_QX_PHASE (   x)
Value:
({ \
typeof(x) x_ = (x); \
\
(x_ > 5) ? AD9545_Q1_PHASE(x_ - 6) : AD9545_Q0_PHASE(x_); \
})

◆ AD9545_QX_PHASE_32_MSK

#define AD9545_QX_PHASE_32_MSK   NO_OS_BIT(6)

◆ AD9545_QX_PHASE_CONF

#define AD9545_QX_PHASE_CONF (   x)
Value:
({ \
typeof(x) x_ = (x); \
\
(x_ > 5) ? AD9545_Q1_PHASE_CONF(x_ - 6) : AD9545_Q0_PHASE_CONF(x_); \
})

◆ AD9545_R_DIV_MAX

#define AD9545_R_DIV_MAX   0x40000000

◆ AD9545_R_DIV_MSK

#define AD9545_R_DIV_MSK   NO_OS_GENMASK(29, 0)

◆ AD9545_REF_A_CTRL

#define AD9545_REF_A_CTRL   0x0300

◆ AD9545_REF_A_MONITOR_HYST

#define AD9545_REF_A_MONITOR_HYST   0x040F

◆ AD9545_REF_A_OFFSET_LIMIT

#define AD9545_REF_A_OFFSET_LIMIT   0x040C

◆ AD9545_REF_A_PERIOD

#define AD9545_REF_A_PERIOD   0x0404

◆ AD9545_REF_A_RDIV

#define AD9545_REF_A_RDIV   0x0400

◆ AD9545_REF_A_VALID_TIMER

#define AD9545_REF_A_VALID_TIMER   0x0410

◆ AD9545_REF_CTRL_DIF_MSK

#define AD9545_REF_CTRL_DIF_MSK   NO_OS_GENMASK(3, 2)

◆ AD9545_REF_CTRL_REFA_MSK

#define AD9545_REF_CTRL_REFA_MSK   NO_OS_GENMASK(5, 4)

◆ AD9545_REF_CTRL_REFAA_MSK

#define AD9545_REF_CTRL_REFAA_MSK   NO_OS_GENMASK(7, 6)

◆ AD9545_REF_X_FREQ_LOCK_DRAIN

#define AD9545_REF_X_FREQ_LOCK_DRAIN (   x)    (AD9545_FREQ_LOCK_DRAIN_RATE + ((x) * 0x20))

◆ AD9545_REF_X_FREQ_LOCK_FILL

#define AD9545_REF_X_FREQ_LOCK_FILL (   x)    (AD9545_FREQ_LOCK_FILL_RATE + ((x) * 0x20))

◆ AD9545_REF_X_MONITOR_HYST

#define AD9545_REF_X_MONITOR_HYST (   x)    (AD9545_REF_A_MONITOR_HYST + ((x) * 0x20))

◆ AD9545_REF_X_OFFSET_LIMIT

#define AD9545_REF_X_OFFSET_LIMIT (   x)    (AD9545_REF_A_OFFSET_LIMIT + ((x) * 0x20))

◆ AD9545_REF_X_PERIOD

#define AD9545_REF_X_PERIOD (   x)    (AD9545_REF_A_PERIOD + ((x) * 0x20))

◆ AD9545_REF_X_PHASE_LOCK_DRAIN

#define AD9545_REF_X_PHASE_LOCK_DRAIN (   x)    (AD9545_PHASE_LOCK_DRAIN_RATE + ((x) * 0x20))

◆ AD9545_REF_X_PHASE_LOCK_FILL

#define AD9545_REF_X_PHASE_LOCK_FILL (   x)    (AD9545_PHASE_LOCK_FILL_RATE + ((x) * 0x20))

◆ AD9545_REF_X_RDIV

#define AD9545_REF_X_RDIV (   x)    (AD9545_REF_A_RDIV + ((x) * 0x20))

◆ AD9545_REF_X_VALID_TIMER

#define AD9545_REF_X_VALID_TIMER (   x)    (AD9545_REF_A_VALID_TIMER + ((x) * 0x20))

◆ AD9545_REFA_STATUS

#define AD9545_REFA_STATUS   0x3005

◆ AD9545_REFX_FAST_MSK

#define AD9545_REFX_FAST_MSK   NO_OS_BIT(1)

◆ AD9545_REFX_FAULT_MSK

#define AD9545_REFX_FAULT_MSK   NO_OS_BIT(3)

◆ AD9545_REFX_JITTER_MSK

#define AD9545_REFX_JITTER_MSK   NO_OS_BIT(2)

◆ AD9545_REFX_LOS_MSK

#define AD9545_REFX_LOS_MSK   NO_OS_BIT(5)

◆ AD9545_REFX_SLOW_MSK

#define AD9545_REFX_SLOW_MSK   NO_OS_BIT(0)

◆ AD9545_REFX_STATUS

#define AD9545_REFX_STATUS (   x)    (AD9545_REFA_STATUS + (x))

◆ AD9545_REFX_VALID_MSK

#define AD9545_REFX_VALID_MSK   NO_OS_BIT(4)

◆ AD9545_RESET_REGS

#define AD9545_RESET_REGS   0x81

◆ AD9545_SEL_PRIORITY_MSK

#define AD9545_SEL_PRIORITY_MSK   NO_OS_GENMASK(5, 1)

◆ AD9545_SOURCEX_FREQ_THRESH

#define AD9545_SOURCEX_FREQ_THRESH (   x)    (AD9545_FREQ_LOCK_THRESH + ((x) * 0x20))

◆ AD9545_SOURCEX_PHASE_THRESH

#define AD9545_SOURCEX_PHASE_THRESH (   x)    (AD9545_PHASE_LOCK_THRESH + ((x) * 0x20))

◆ AD9545_STABILITY_TIMER

#define AD9545_STABILITY_TIMER   0x0207

◆ AD9545_SYNC_CTRL0

#define AD9545_SYNC_CTRL0   0x10DB

◆ AD9545_SYNC_CTRL_DPLL_REF_MSK

#define AD9545_SYNC_CTRL_DPLL_REF_MSK   NO_OS_BIT(2)

◆ AD9545_SYNC_CTRL_MODE_MSK

#define AD9545_SYNC_CTRL_MODE_MSK   NO_OS_GENMASK(1, 0)

◆ AD9545_SYNC_CTRLX

#define AD9545_SYNC_CTRLX (   x)    (AD9545_SYNC_CTRL0 + ((x) * 0x400))

◆ AD9545_SYS_CLK_FB_DIV

#define AD9545_SYS_CLK_FB_DIV   0x0200

◆ AD9545_SYS_CLK_INPUT

#define AD9545_SYS_CLK_INPUT   0x0201

◆ AD9545_SYS_CLK_REF_FREQ

#define AD9545_SYS_CLK_REF_FREQ   0x0202

◆ AD9545_SYS_CLK_STABILITY_MS

#define AD9545_SYS_CLK_STABILITY_MS   50

◆ AD9545_SYS_CLK_STABILITY_PERIOD_MASK

#define AD9545_SYS_CLK_STABILITY_PERIOD_MASK   NO_OS_GENMASK(19, 0)

◆ AD9545_SYS_PLL_STABLE

#define AD9545_SYS_PLL_STABLE (   x)    (((x) & AD9545_SYS_PLL_STABLE_MSK) == 0x3)

◆ AD9545_SYS_PLL_STABLE_MSK

#define AD9545_SYS_PLL_STABLE_MSK   NO_OS_GENMASK(1, 0)

◆ AD9545_TAG_MODE_MSK

#define AD9545_TAG_MODE_MSK   NO_OS_GENMASK(4, 2)

◆ AD9545_TDC0_DIV

#define AD9545_TDC0_DIV   0x2A00

◆ AD9545_TDC0_PERIOD

#define AD9545_TDC0_PERIOD   0x2A01

◆ AD9545_TDCX_DIV

#define AD9545_TDCX_DIV (   x)    (AD9545_TDC0_DIV + ((x) * 0x9))

◆ AD9545_TDCX_PERIOD

#define AD9545_TDCX_PERIOD (   x)    (AD9545_TDC0_PERIOD + ((x) * 0x9))

◆ AD9545_TEMP0

#define AD9545_TEMP0   0x3003

◆ AD9545_UPDATE_REGS

#define AD9545_UPDATE_REGS   0x1

◆ BYTE_ADDR_H

#define BYTE_ADDR_H   NO_OS_GENMASK(14, 8)

◆ BYTE_ADDR_L

#define BYTE_ADDR_L   NO_OS_GENMASK(7, 0)

◆ DRIVER_MODE_AC_COUPLED

#define DRIVER_MODE_AC_COUPLED   0

◆ DRIVER_MODE_AC_COUPLED_IF

#define DRIVER_MODE_AC_COUPLED_IF   0

◆ DRIVER_MODE_DC_COUPLED

#define DRIVER_MODE_DC_COUPLED   1

◆ DRIVER_MODE_DC_COUPLED_1V2

#define DRIVER_MODE_DC_COUPLED_1V2   1

◆ DRIVER_MODE_DC_COUPLED_1V8

#define DRIVER_MODE_DC_COUPLED_1V8   2

◆ DRIVER_MODE_DC_COUPLED_LVDS

#define DRIVER_MODE_DC_COUPLED_LVDS   2

◆ DRIVER_MODE_DUAL_DIV

#define DRIVER_MODE_DUAL_DIV   2

◆ DRIVER_MODE_IN_PULL_UP

#define DRIVER_MODE_IN_PULL_UP   3

◆ DRIVER_MODE_SINGLE_DIV

#define DRIVER_MODE_SINGLE_DIV   1

◆ DRIVER_MODE_SINGLE_DIV_DIF

#define DRIVER_MODE_SINGLE_DIV_DIF   0

Typedef Documentation

◆ ad9545_reg_read_func

typedef int32_t(* ad9545_reg_read_func) (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data)

◆ ad9545_reg_read_multi_func

typedef int32_t(* ad9545_reg_read_multi_func) (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data, uint16_t count)

◆ ad9545_reg_write_func

typedef int32_t(* ad9545_reg_write_func) (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t reg_data)

◆ ad9545_reg_write_multi_func

typedef int32_t(* ad9545_reg_write_multi_func) (struct ad9545_dev *dev, uint16_t reg_addr, uint8_t *reg_data, uint16_t count)

Enumeration Type Documentation

◆ ad9545_comm_type

enum ad9545_comm_type
Enumerator
SPI 
I2C 

◆ ad9545_diferential_config

enum ad9545_diferential_config
Enumerator
AD9545_AC_COUPLED 
AD9545_DC_COUPLED 
AD9545_DC_COUPLED_LVDS 

◆ ad9545_output_mode

enum ad9545_output_mode
Enumerator
AD9545_SINGLE_DIV_DIF 
AD9545_SINGLE_DIV 
AD9545_DUAL_DIV 

◆ ad9545_ref_mode

enum ad9545_ref_mode
Enumerator
AD9545_SINGLE_ENDED 
AD9545_DIFFERENTIAL 

◆ ad9545_single_ended_config

enum ad9545_single_ended_config
Enumerator
AD9545_AC_COUPLED_IF 
AD9545_DC_COUPLED_1V2 
AD9545_DC_COUPLED_1V8 
AD9545_IN_PULL_UP 

Function Documentation

◆ ad9545_calib_aplls()

int ad9545_calib_aplls ( struct ad9545_dev *  dev)
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◆ ad9545_i2c_reg_read()

int32_t ad9545_i2c_reg_read ( struct ad9545_dev *  dev,
uint16_t  reg_addr,
uint8_t *  reg_data 
)

Read from device.

Parameters
dev- The device structure.
reg_addr- The register address.
reg_data- The register data.
Returns
0 in case of success, negative error code otherwise.
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◆ ad9545_i2c_reg_read_multiple()

int32_t ad9545_i2c_reg_read_multiple ( struct ad9545_dev *  dev,
uint16_t  reg_addr,
uint8_t *  reg_data,
uint16_t  count 
)

Multibyte read from device. A register read begins with the address and autoincrements for each aditional byte in the transfer.

Parameters
dev- The device structure.
reg_addr- The register address.
reg_data- The register data.
count- Number of bytes to read.
Returns
0 in case of success, negative error code otherwise.
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◆ ad9545_i2c_reg_write()

int32_t ad9545_i2c_reg_write ( struct ad9545_dev *  dev,
uint16_t  reg_addr,
uint8_t  reg_data 
)

Write to device.

Parameters
dev- The device structure.
reg_addr- The register address.
reg_data- The register data.
Returns
0 in case of success, negative error code otherwise.
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◆ ad9545_i2c_reg_write_multiple()

int32_t ad9545_i2c_reg_write_multiple ( struct ad9545_dev *  dev,
uint16_t  reg_addr,
uint8_t *  reg_data,
uint16_t  count 
)

Multibyte write to device. A register write begins with the address and autoincrements for each aditional byte in the transfer.

Parameters
dev- The device structure.
reg_addr- The register address.
reg_data- The register data.
count- Number of bytes to write.
Returns
0 in case of success, negative error code otherwise.
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◆ ad9545_init()

int32_t ad9545_init ( struct ad9545_dev **  device,
struct ad9545_init_param *  init_param 
)

Initialize the device.

Parameters
device- The device structure.
init_param- The structure that contains the device initial parameters.
Returns
0 in case of success, negative error code otherwise.
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◆ ad9545_remove()

int32_t ad9545_remove ( struct ad9545_dev *  dev)

Free the memory allocated by ad9545_init().

Parameters
[in]dev- Pointer to the device handler.
Returns
0 in case of success, -1 otherwise
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◆ ad9545_setup()

int32_t ad9545_setup ( struct ad9545_dev *  dev)
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◆ ad9545_spi_reg_read()

int32_t ad9545_spi_reg_read ( struct ad9545_dev *  dev,
uint16_t  reg_addr,
uint8_t *  reg_data 
)

Read from device.

Parameters
dev- The device structure.
reg_addr- The register address.
reg_data- The register data.
Returns
0 in case of success, negative error code otherwise.
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◆ ad9545_spi_reg_read_multiple()

int32_t ad9545_spi_reg_read_multiple ( struct ad9545_dev *  dev,
uint16_t  reg_addr,
uint8_t *  reg_data,
uint16_t  count 
)

Multibyte read from device. A register read begins with the address and autoincrements for each aditional byte in the transfer.

Parameters
dev- The device structure.
reg_addr- The register address.
reg_data- The register data.
count- Number of bytes to read.
Returns
0 in case of success, negative error code otherwise.
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◆ ad9545_spi_reg_write()

int32_t ad9545_spi_reg_write ( struct ad9545_dev *  dev,
uint16_t  reg_addr,
uint8_t  reg_data 
)

Write to device.

Parameters
dev- The device structure.
reg_addr- The register address.
reg_data- The register data.
Returns
0 in case of success, negative error code otherwise.
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◆ ad9545_spi_reg_write_multiple()

int32_t ad9545_spi_reg_write_multiple ( struct ad9545_dev *  dev,
uint16_t  reg_addr,
uint8_t *  reg_data,
uint16_t  count 
)

Write Multiple bytes to the device. A register write begins with the address and autoincrements for each aditional byte in the transfer.

Parameters
dev- The device structure.
reg_addr- The register address.
reg_data- The register data.
count- Number of bytes to write.
Returns
0 in case of success, negative error code otherwise.
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◆ ad9545_write_mask()

int32_t ad9545_write_mask ( struct ad9545_dev *  dev,
uint16_t  reg_addr,
uint32_t  mask,
uint8_t  data 
)

Write to device using a mask.

Parameters
dev- The device structure.
reg_addr- The register address.
mask- The mask.
data- The register data.
Returns
0 in case of success, negative error code otherwise.
AD9545_Q0_PHASE
#define AD9545_Q0_PHASE(x)
Definition: ad9545.h:243
AD9545_DIV_OPS_Q0
#define AD9545_DIV_OPS_Q0(x)
Definition: ad9545.h:274
AD9545_NCO_CENTER_FREQ_INT_MAX
#define AD9545_NCO_CENTER_FREQ_INT_MAX
Definition: ad9545.h:316
AD9545_NCO_OFFSET_FREQ_INT_WIDTH
#define AD9545_NCO_OFFSET_FREQ_INT_WIDTH
Definition: ad9545.h:323
AD9545_Q1_PHASE_CONF
#define AD9545_Q1_PHASE_CONF(x)
Definition: ad9545.h:252
AD9545_Q0_DIV
#define AD9545_Q0_DIV(x)
Definition: ad9545.h:235
AD9545_NCO_OFFSET_FREQ_WIDTH
#define AD9545_NCO_OFFSET_FREQ_WIDTH
Definition: ad9545.h:325
AD9545_Q1_DIV
#define AD9545_Q1_DIV(x)
Definition: ad9545.h:236
NO_OS_GENMASK_ULL
#define NO_OS_GENMASK_ULL(h, l)
Definition: no_os_util.h:94
AD9545_NCO_CENTER_FREQ_WIDTH
#define AD9545_NCO_CENTER_FREQ_WIDTH
Definition: ad9545.h:307
AD9545_NCO_CENTER_FREQ_INT_WIDTH
#define AD9545_NCO_CENTER_FREQ_INT_WIDTH
Definition: ad9545.h:305
AD9545_Q1_PHASE
#define AD9545_Q1_PHASE(x)
Definition: ad9545.h:244
AD9545_DIV_OPS_Q1
#define AD9545_DIV_OPS_Q1(x)
Definition: ad9545.h:275
AD9545_NCO_CENTER_FREQ_FRAC_WIDTH
#define AD9545_NCO_CENTER_FREQ_FRAC_WIDTH
Definition: ad9545.h:306
AD9545_NCO_OFFSET_FREQ_FRAC_WIDTH
#define AD9545_NCO_OFFSET_FREQ_FRAC_WIDTH
Definition: ad9545.h:324
AD9545_Q0_PHASE_CONF
#define AD9545_Q0_PHASE_CONF(x)
Definition: ad9545.h:251
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