Implementation of ADF4368 Driver. More...
#include <stdint.h>#include <string.h>#include "no_os_units.h"#include "no_os_util.h"#include "no_os_spi.h"
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Classes | |
| struct | adf4368_init_param |
| ADF4368 Initialization Parameters structure. More... | |
| struct | adf4368_dev |
| ADF4368 Device Descriptor. More... | |
Functions | |
| int | adf4368_spi_write (struct adf4368_dev *dev, uint16_t reg_addr, uint8_t data) |
| Writes data to ADF4368 over SPI. | |
| int | adf4368_spi_read (struct adf4368_dev *dev, uint16_t reg_addr, uint8_t *data) |
| Reads data from ADF4368 over SPI. | |
| int | adf4368_spi_update_bits (struct adf4368_dev *dev, uint16_t reg_addr, uint8_t mask, uint8_t data) |
| Updates the values of the ADF4368 register. | |
| int | adf4368_reg_dump (struct adf4368_dev *dev) |
| Will output on the terminal the values of all the ADF4368 registers. | |
| int | adf4368_set_out_power (struct adf4368_dev *dev, uint8_t ch, int32_t pwr) |
| Set the output power register value of a channel and reset everything over to maximum supported value of 15 to the max. value. | |
| int | adf4368_get_out_power (struct adf4368_dev *dev, uint8_t ch, int32_t *pwr) |
| Gets the output power register value. | |
| int | adf4368_set_en_chan (struct adf4368_dev *dev, uint8_t ch, bool en) |
| Set the output channel to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable. | |
| int | adf4368_get_en_chan (struct adf4368_dev *dev, uint8_t ch, bool *en) |
| Gets the value the output channel if it is enabled or disable. | |
| int | adf4368_set_ref_clk (struct adf4368_dev *dev, uint64_t val) |
| Set the desired reference frequency and reset everything over to maximum supported value of 4GHz to the max. value and everything under the minimum supported value of 10MHz to the min. value. | |
| int | adf4368_get_ref_clk (struct adf4368_dev *dev, uint64_t *val) |
| Gets the user proposed reference frequency. | |
| int | adf4368_set_en_ref_doubler (struct adf4368_dev *dev, bool en) |
| Set the reference doubler to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable. | |
| int | adf4368_get_en_ref_doubler (struct adf4368_dev *dev, bool *en) |
| Gets the value the doubler if it is enabled or disable and stores it it the dev structure. | |
| int | adf4368_set_ref_div (struct adf4368_dev *dev, int32_t div) |
| Set the reference divider value and reset everything over to maximum supported value of 63 to the max. value. | |
| int | adf4368_get_ref_div (struct adf4368_dev *dev, int32_t *div) |
| Gets the value the reference divider. | |
| int | adf4368_set_cp_i (struct adf4368_dev *dev, int32_t reg_val) |
| Set the charge pump value which will be written to the register. The value will be between 0 and 15 on 8 bits. For more information please consult the Datasheet. | |
| int | adf4368_get_cp_i (struct adf4368_dev *dev, int32_t *reg_val) |
| Gets the charge pump value from the register. The value will be between 0 and 15 on 8 bits. For more information please consult the Datasheet. | |
| int | adf4368_set_bleed_word (struct adf4368_dev *dev, int32_t word) |
| Set the bleed word, which represents the value of the bleed current written to the register space. | |
| int | adf4368_get_bleed_word (struct adf4368_dev *dev, int32_t *word) |
| Gets the value of the bleed word. | |
| int | adf4368_set_rfout (struct adf4368_dev *dev, uint64_t val) |
| Set the desired output frequency and reset everything over to maximum supported value of 12.8GHz to the max. value and everything under the minimum supported value of 800MHz to the min. value. | |
| int | adf4368_get_rfout (struct adf4368_dev *dev, uint64_t *val) |
| Gets the user proposed output frequency. | |
| int | adf4368_set_sync_setup (struct adf4368_dev *dev, bool en) |
| Set EZSYNC and Timed SYNC features' initial state. Waits for SW_SYNC toggle or SYNC pin. | |
| int | adf4368_get_sync_setup (struct adf4368_dev *dev, bool *en) |
| Gets the value of the SYNC features' powerdown bit. | |
| int | adf4368_set_sw_sync (struct adf4368_dev *dev, uint8_t sw_sync) |
| Set Software SYNC Request. Setting SW_SYNC resets the RF block. Clearing SW_SYNC makes ready for a new reference clock. | |
| int | adf4368_get_sw_sync (struct adf4368_dev *dev, uint8_t *sw_sync) |
| Gets the value of the SW_SYNC bit. | |
| int | adf4368_set_temperature (struct adf4368_dev *dev, bool en) |
| Set Temperature Readback feature's initial state. This feature should be disabled after reading temperature. | |
| int | adf4368_get_temperature (struct adf4368_dev *dev, int32_t *temp) |
| Gets the value of the approximate die temperature. | |
| int | adf4368_set_phase_sdm (struct adf4368_dev *dev, uint32_t phase_fs) |
| Set the phase adjustment in femto-seconds with Sigma Delta Modulation. This approach only support MAX %22 in degree phase. Recommend to use in fractional mode. | |
| int | adf4368_get_phase_sdm (struct adf4368_dev *dev, uint32_t *phase_fs) |
| Get the phase adjustment in femto-seconds with Sigma Delta Modulation. | |
| int | adf4368_set_phase_bleedi (struct adf4368_dev *dev, uint32_t phase_fs, bool phase_pol) |
| Set the phase adjustment in femto-seconds. The phase adjust will enable the Bleed current. Recommend to use in integer mode. | |
| int | adf4368_set_phase (struct adf4368_dev *dev, uint32_t phase_fs, bool phase_pol) |
| Set the phase adjustment in femto-seconds. Function choose the phase adjustment method according to Integer mode. | |
| int | adf4368_get_phase (struct adf4368_dev *dev, uint32_t *phase_fs, bool *phase_pol) |
| Get the phase adjustment in femto-seconds. Function choose the phase adjustment method according to Integer mode. | |
| int | adf4368_set_default_regs (struct adf4368_dev *dev, bool spi_4wire) |
| Applys a softreset, sets the SPI 4 wire mode and writes the default registers. | |
| int | adf4368_get_default_regs (struct adf4368_dev *dev, bool *spi_4wire) |
| Reads and Checks the registers values equal to default values. | |
| int | adf4368_set_freq (struct adf4368_dev *dev) |
| Set the output frequency. | |
| int | adf4368_init (struct adf4368_dev **device, struct adf4368_init_param *init_param) |
| Initializes the adf4368. | |
| int | adf4368_remove (struct adf4368_dev *dev) |
| Free resources allocated for ADF4368. | |
Detailed Description
Implementation of ADF4368 Driver.
Copyright 2024(c) Analog Devices, Inc.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
- Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Macro Definition Documentation
◆ ADF4368_ADC_A_CONV_MSK
| #define ADF4368_ADC_A_CONV_MSK NO_OS_BIT(0) |
◆ ADF4368_ADC_BUSY_MSK
| #define ADF4368_ADC_BUSY_MSK NO_OS_BIT(2) |
◆ ADF4368_ADC_CLK_DIV_MSK
| #define ADF4368_ADC_CLK_DIV_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_ADC_CLK_SEL_MSK
| #define ADF4368_ADC_CLK_SEL_MSK NO_OS_BIT(6) |
◆ ADF4368_ADC_ST_CNV_MSK
| #define ADF4368_ADC_ST_CNV_MSK NO_OS_BIT(1) |
◆ ADF4368_ADDR_ASC_AUTO_DECR
| #define ADF4368_ADDR_ASC_AUTO_DECR 0x0 |
◆ ADF4368_ADDR_ASC_AUTO_INCR
| #define ADF4368_ADDR_ASC_AUTO_INCR 0x1 |
◆ ADF4368_ADDRESS_ASC_MSK
| #define ADF4368_ADDRESS_ASC_MSK NO_OS_BIT(2) |
◆ ADF4368_ADDRESS_ASC_R_MSK
| #define ADF4368_ADDRESS_ASC_R_MSK NO_OS_BIT(5) |
◆ ADF4368_ADJ_POL_MSK
| #define ADF4368_ADJ_POL_MSK NO_OS_BIT(6) |
◆ ADF4368_BLEED_MSB_MSK
| #define ADF4368_BLEED_MSB_MSK |
Value:
◆ ADF4368_BLEED_N_INT_TH
| #define ADF4368_BLEED_N_INT_TH 35 |
◆ ADF4368_BLEED_POL_MSK
| #define ADF4368_BLEED_POL_MSK NO_OS_BIT(5) |
◆ ADF4368_BLEED_WORD_MAX
| #define ADF4368_BLEED_WORD_MAX 8191 |
◆ ADF4368_BST_REF_MSK
| #define ADF4368_BST_REF_MSK NO_OS_BIT(7) |
◆ ADF4368_BUFF_SIZE_BYTES
| #define ADF4368_BUFF_SIZE_BYTES 3 |
◆ ADF4368_CHANNEL_SPACING_MAX
| #define ADF4368_CHANNEL_SPACING_MAX 78125U |
◆ ADF4368_CHIP_TEMP_LSB_MSK
| #define ADF4368_CHIP_TEMP_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_CHIP_TEMP_MSB_MSK
| #define ADF4368_CHIP_TEMP_MSB_MSK NO_OS_BIT(0) |
◆ ADF4368_CHIP_TYPE
| #define ADF4368_CHIP_TYPE 0x06 |
◆ ADF4368_CLK1_OPWR_MSK
| #define ADF4368_CLK1_OPWR_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4368_CLK2_OPWR_MSK
| #define ADF4368_CLK2_OPWR_MSK NO_OS_GENMASK(7, 4) |
◆ ADF4368_CLKODIV_DB_MSK
| #define ADF4368_CLKODIV_DB_MSK NO_OS_BIT(7) |
◆ ADF4368_CLKOUT_DIV_MSK
| #define ADF4368_CLKOUT_DIV_MSK NO_OS_GENMASK(7, 6) |
◆ ADF4368_CLKOUT_DIV_REG_VAL_MAX
| #define ADF4368_CLKOUT_DIV_REG_VAL_MAX 3 |
◆ ADF4368_CMOS_OV_MSK
| #define ADF4368_CMOS_OV_MSK NO_OS_BIT(1) |
◆ ADF4368_COARSE_BLEED_CNST
| #define ADF4368_COARSE_BLEED_CNST 202 |
◆ ADF4368_COARSE_BLEED_MSK
| #define ADF4368_COARSE_BLEED_MSK NO_OS_GENMASK(4, 1) |
◆ ADF4368_CP_DOWN_MSK
| #define ADF4368_CP_DOWN_MSK NO_OS_BIT(1) |
◆ ADF4368_CP_I_MSK
| #define ADF4368_CP_I_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4368_CP_UP_MSK
| #define ADF4368_CP_UP_MSK NO_OS_BIT(0) |
◆ ADF4368_CPI_VAL_MAX
| #define ADF4368_CPI_VAL_MAX 15 |
◆ ADF4368_DCLK_DIV1_0_MAX
| #define ADF4368_DCLK_DIV1_0_MAX 160000000U |
◆ ADF4368_DCLK_DIV1_1_MAX
| #define ADF4368_DCLK_DIV1_1_MAX 320000000U |
◆ ADF4368_DCLK_DIV1_MSK
| #define ADF4368_DCLK_DIV1_MSK NO_OS_GENMASK(5, 4) |
◆ ADF4368_DCLK_DIV_DB_MSK
| #define ADF4368_DCLK_DIV_DB_MSK NO_OS_BIT(6) |
◆ ADF4368_DCLK_MODE_MSK
| #define ADF4368_DCLK_MODE_MSK NO_OS_BIT(2) |
◆ ADF4368_DEL_CTRL_DB_MSK
| #define ADF4368_DEL_CTRL_DB_MSK NO_OS_BIT(7) |
◆ ADF4368_DNCLK_DEL_MSK
| #define ADF4368_DNCLK_DEL_MSK NO_OS_GENMASK(2, 0) |
◆ ADF4368_DRCLK_DEL_MSK
| #define ADF4368_DRCLK_DEL_MSK NO_OS_GENMASK(5, 3) |
◆ ADF4368_EN_ADC_CLK_MSK
| #define ADF4368_EN_ADC_CLK_MSK NO_OS_BIT(3) |
◆ ADF4368_EN_ADC_CNV_MSK
| #define ADF4368_EN_ADC_CNV_MSK NO_OS_BIT(7) |
◆ ADF4368_EN_ADC_MSK
| #define ADF4368_EN_ADC_MSK NO_OS_BIT(1) |
◆ ADF4368_EN_AUTOCAL_MSK
| #define ADF4368_EN_AUTOCAL_MSK NO_OS_BIT(7) |
◆ ADF4368_EN_BLEED_MSK
| #define ADF4368_EN_BLEED_MSK NO_OS_BIT(4) |
◆ ADF4368_EN_CLK1_MSK
| #define ADF4368_EN_CLK1_MSK NO_OS_BIT(6) |
◆ ADF4368_EN_CLK2_MSK
| #define ADF4368_EN_CLK2_MSK NO_OS_BIT(7) |
◆ ADF4368_EN_CPTEST_MSK
| #define ADF4368_EN_CPTEST_MSK NO_OS_BIT(2) |
◆ ADF4368_EN_DNCLK_MSK
| #define ADF4368_EN_DNCLK_MSK NO_OS_BIT(7) |
◆ ADF4368_EN_DRCLK_MSK
| #define ADF4368_EN_DRCLK_MSK NO_OS_BIT(6) |
◆ ADF4368_EN_LDWIN_MSK
| #define ADF4368_EN_LDWIN_MSK NO_OS_BIT(4) |
◆ ADF4368_EN_LOL_MSK
| #define ADF4368_EN_LOL_MSK NO_OS_BIT(5) |
◆ ADF4368_EN_PHASE_RESYNC_MSK
| #define ADF4368_EN_PHASE_RESYNC_MSK NO_OS_BIT(7) |
◆ ADF4368_EN_RDBLR_MSK
| #define ADF4368_EN_RDBLR_MSK NO_OS_BIT(6) |
◆ ADF4368_EN_REF_RST_MSK
| #define ADF4368_EN_REF_RST_MSK NO_OS_BIT(6) |
◆ ADF4368_FILT_REF_MSK
| #define ADF4368_FILT_REF_MSK NO_OS_BIT(6) |
◆ ADF4368_FINE_BLEED_CNST1
| #define ADF4368_FINE_BLEED_CNST1 250 |
◆ ADF4368_FINE_BLEED_CNST2
| #define ADF4368_FINE_BLEED_CNST2 512 |
◆ ADF4368_FINE_BLEED_CNST3
| #define ADF4368_FINE_BLEED_CNST3 567 |
◆ ADF4368_FINE_BLEED_LSB_MSK
| #define ADF4368_FINE_BLEED_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_FINE_BLEED_MSB_MSK
| #define ADF4368_FINE_BLEED_MSB_MSK NO_OS_BIT(0) |
◆ ADF4368_FRAC1WORD_LSB_MSK
| #define ADF4368_FRAC1WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_FRAC1WORD_MID_MSK
| #define ADF4368_FRAC1WORD_MID_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_FRAC1WORD_MSB
| #define ADF4368_FRAC1WORD_MSB NO_OS_BIT(0) |
◆ ADF4368_FRAC1WORD_MSB_MSK
| #define ADF4368_FRAC1WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_FRAC2WORD_LSB_MSK
| #define ADF4368_FRAC2WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_FRAC2WORD_MID_MSK
| #define ADF4368_FRAC2WORD_MID_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_FRAC2WORD_MSB_MSK
| #define ADF4368_FRAC2WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_FRAC_N_INT_MIN
| #define ADF4368_FRAC_N_INT_MIN 19 |
◆ ADF4368_FSM_BUSY_MSK
| #define ADF4368_FSM_BUSY_MSK NO_OS_BIT(1) |
◆ ADF4368_INT_MODE_MSK
| #define ADF4368_INT_MODE_MSK NO_OS_BIT(5) |
◆ ADF4368_INT_N_INT_MIN
| #define ADF4368_INT_N_INT_MIN 4 |
◆ ADF4368_INV_CLK_OUT_MSK
| #define ADF4368_INV_CLK_OUT_MSK NO_OS_BIT(4) |
◆ ADF4368_LD_COUNT_MSK
| #define ADF4368_LD_COUNT_MSK NO_OS_GENMASK(4, 0) |
◆ ADF4368_LDWIN_PW_MSK
| #define ADF4368_LDWIN_PW_MSK NO_OS_GENMASK(7, 5) |
◆ ADF4368_LKD_DELAY_MS
| #define ADF4368_LKD_DELAY_MS 9 |
◆ ADF4368_LOCKED_MSK
| #define ADF4368_LOCKED_MSK NO_OS_BIT(0) |
◆ ADF4368_LSB_FIRST_LSB
| #define ADF4368_LSB_FIRST_LSB 0x1 |
◆ ADF4368_LSB_FIRST_MSB
| #define ADF4368_LSB_FIRST_MSB 0x0 |
◆ ADF4368_LSB_FIRST_MSK
| #define ADF4368_LSB_FIRST_MSK NO_OS_BIT(1) |
◆ ADF4368_LSB_FIRST_R_MSK
| #define ADF4368_LSB_FIRST_R_MSK NO_OS_BIT(6) |
◆ ADF4368_LSB_P1
| #define ADF4368_LSB_P1 NO_OS_BIT(6) |
◆ ADF4368_M_VCO_BAND_MSK
| #define ADF4368_M_VCO_BAND_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_M_VCO_BIAS_MSK
| #define ADF4368_M_VCO_BIAS_MSK NO_OS_GENMASK(5, 2) |
◆ ADF4368_M_VCO_CORE_MSK
| #define ADF4368_M_VCO_CORE_MSK NO_OS_GENMASK(7, 6) |
◆ ADF4368_MASTER_RB_CTRL_MSK
| #define ADF4368_MASTER_RB_CTRL_MSK NO_OS_BIT(5) |
◆ ADF4368_MHZ
| #define ADF4368_MHZ MEGA |
◆ ADF4368_MOD1WORD
| #define ADF4368_MOD1WORD 0x2000000U |
◆ ADF4368_MOD2WORD_LSB_MSK
| #define ADF4368_MOD2WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_MOD2WORD_MAX
| #define ADF4368_MOD2WORD_MAX 0xFFFFFFU |
◆ ADF4368_MOD2WORD_MID_MSK
| #define ADF4368_MOD2WORD_MID_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_MOD2WORD_MSB_MSK
| #define ADF4368_MOD2WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_MS_TO_S
| #define ADF4368_MS_TO_S MILLI |
◆ ADF4368_MUTE_CLKOUT1_MSK
| #define ADF4368_MUTE_CLKOUT1_MSK NO_OS_GENMASK(2, 0) |
◆ ADF4368_MUTE_CLKOUT2_MSK
| #define ADF4368_MUTE_CLKOUT2_MSK NO_OS_GENMASK(5, 3) |
◆ ADF4368_MUTE_NCLK_MSK
| #define ADF4368_MUTE_NCLK_MSK NO_OS_BIT(7) |
◆ ADF4368_MUXOUT_MSK
| #define ADF4368_MUXOUT_MSK NO_OS_GENMASK(7, 4) |
◆ ADF4368_N_INT_LSB_MSK
| #define ADF4368_N_INT_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_N_INT_MSB_MSK
| #define ADF4368_N_INT_MSB_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4368_NS_TO_PS
| #define ADF4368_NS_TO_PS KHZ_PER_MHZ |
◆ ADF4368_NS_TO_S
| #define ADF4368_NS_TO_S NANO |
◆ ADF4368_O_VCO_BAND_MSK
| #define ADF4368_O_VCO_BAND_MSK NO_OS_BIT(3) |
◆ ADF4368_O_VCO_BIAS_MSK
| #define ADF4368_O_VCO_BIAS_MSK NO_OS_BIT(1) |
◆ ADF4368_O_VCO_CORE_MSK
| #define ADF4368_O_VCO_CORE_MSK NO_OS_BIT(2) |
◆ ADF4368_O_VCO_DB_MSK
| #define ADF4368_O_VCO_DB_MSK NO_OS_BIT(7) |
◆ ADF4368_OUT_PWR_MAX
| #define ADF4368_OUT_PWR_MAX 15 |
◆ ADF4368_PD_ALL
| #define ADF4368_PD_ALL NO_OS_BIT(7) |
◆ ADF4368_PD_CLKOUT1_MSK
| #define ADF4368_PD_CLKOUT1_MSK NO_OS_BIT(1) |
◆ ADF4368_PD_CLKOUT2_MSK
| #define ADF4368_PD_CLKOUT2_MSK NO_OS_BIT(0) |
◆ ADF4368_PD_LD
| #define ADF4368_PD_LD NO_OS_BIT(3) |
◆ ADF4368_PD_RDET
| #define ADF4368_PD_RDET NO_OS_BIT(2) |
◆ ADF4368_PD_SYNC
| #define ADF4368_PD_SYNC NO_OS_BIT(4) |
◆ ADF4368_PD_SYNC_MON_MSK
| #define ADF4368_PD_SYNC_MON_MSK NO_OS_BIT(6) |
◆ ADF4368_PFD_FREQ_FRAC_MAX
| #define ADF4368_PFD_FREQ_FRAC_MAX 250000000U |
◆ ADF4368_PFD_FREQ_MAX
| #define ADF4368_PFD_FREQ_MAX 625000000U |
◆ ADF4368_PHASE_ADJ_MSK
| #define ADF4368_PHASE_ADJ_MSK NO_OS_BIT(6) |
◆ ADF4368_PHASE_ADJUSTMENT_MSK
| #define ADF4368_PHASE_ADJUSTMENT_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_PHASE_BLEED_CNST
| #define ADF4368_PHASE_BLEED_CNST 2044000 |
◆ ADF4368_PHASE_RESYNC_MOD2WORD_MAX
| #define ADF4368_PHASE_RESYNC_MOD2WORD_MAX 0x1FFFFU |
◆ ADF4368_PHASE_WORD_LSB_MSK
| #define ADF4368_PHASE_WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_PHASE_WORD_MID_MSK
| #define ADF4368_PHASE_WORD_MID_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_PHASE_WORD_MSB_MSK
| #define ADF4368_PHASE_WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_POR_DELAY_US
| #define ADF4368_POR_DELAY_US 200 |
◆ ADF4368_PRODUCT_ID_LSB
| #define ADF4368_PRODUCT_ID_LSB 0x0005 |
◆ ADF4368_PRODUCT_ID_MSB
| #define ADF4368_PRODUCT_ID_MSB 0x0005 |
◆ ADF4368_PS_TO_NS
| #define ADF4368_PS_TO_NS KHZ_PER_MHZ |
◆ ADF4368_PS_TO_S
| #define ADF4368_PS_TO_S PICO |
◆ ADF4368_PS_TO_US
| #define ADF4368_PS_TO_US MICRO |
◆ ADF4368_R_DIV_MSK
| #define ADF4368_R_DIV_MSK NO_OS_GENMASK(5, 0) |
◆ ADF4368_REF_CLK_MAX
| #define ADF4368_REF_CLK_MAX 4000000000U |
◆ ADF4368_REF_CLK_MIN
| #define ADF4368_REF_CLK_MIN 10000000 |
◆ ADF4368_REF_DIV_MAX
| #define ADF4368_REF_DIV_MAX 63 |
◆ ADF4368_REF_OK_MSK
| #define ADF4368_REF_OK_MSK NO_OS_BIT(3) |
◆ ADF4368_REF_SEL_MSK
| #define ADF4368_REF_SEL_MSK NO_OS_BIT(5) |
◆ ADF4368_REG28_RSV1
| #define ADF4368_REG28_RSV1 NO_OS_BIT(7) |
◆ ADF4368_REG28_RSV2
| #define ADF4368_REG28_RSV2 NO_OS_GENMASK(4, 2) |
◆ ADF4368_REG28_RSV3
| #define ADF4368_REG28_RSV3 NO_OS_BIT(1) |
◆ ADF4368_REG28_RSV4
| #define ADF4368_REG28_RSV4 NO_OS_BIT(0) |
◆ ADF4368_REG2A_RSV1
| #define ADF4368_REG2A_RSV1 NO_OS_BIT(0) |
◆ ADF4368_REG2A_RSV2
| #define ADF4368_REG2A_RSV2 NO_OS_BIT(1) |
◆ ADF4368_REG2A_RSV3
| #define ADF4368_REG2A_RSV3 NO_OS_BIT(3) |
◆ ADF4368_REG2A_RSV4
| #define ADF4368_REG2A_RSV4 NO_OS_BIT(5) |
◆ ADF4368_REG2A_RSV5
| #define ADF4368_REG2A_RSV5 NO_OS_BIT(7) |
◆ ADF4368_REG2B_RSV1
| #define ADF4368_REG2B_RSV1 NO_OS_BIT(2) |
◆ ADF4368_REG2B_RSV2
| #define ADF4368_REG2B_RSV2 NO_OS_BIT(4) |
◆ ADF4368_REG2B_RSV3
| #define ADF4368_REG2B_RSV3 NO_OS_BIT(5) |
◆ ADF4368_REG2B_RSV4
| #define ADF4368_REG2B_RSV4 NO_OS_BIT(6) |
◆ ADF4368_REG2D_RSV1
| #define ADF4368_REG2D_RSV1 NO_OS_GENMASK(1, 0) |
◆ ADF4368_REG2D_RSV2
| #define ADF4368_REG2D_RSV2 NO_OS_BIT(3) |
◆ ADF4368_REG2E_RSV1
| #define ADF4368_REG2E_RSV1 NO_OS_BIT(3) |
◆ ADF4368_REG2F_RSV1
| #define ADF4368_REG2F_RSV1 NO_OS_GENMASK(3, 0) |
◆ ADF4368_REG2F_RSV2
| #define ADF4368_REG2F_RSV2 NO_OS_BIT(5) |
◆ ADF4368_REG30_RSV3
| #define ADF4368_REG30_RSV3 NO_OS_BIT(6) |
◆ ADF4368_REG31_RSV1
| #define ADF4368_REG31_RSV1 NO_OS_BIT(0) |
◆ ADF4368_REG31_RSV2
| #define ADF4368_REG31_RSV2 NO_OS_BIT(1) |
◆ ADF4368_REG31_RSV3
| #define ADF4368_REG31_RSV3 NO_OS_BIT(2) |
◆ ADF4368_REG35_RSV1
| #define ADF4368_REG35_RSV1 NO_OS_BIT(0) |
◆ ADF4368_REG35_RSV2
| #define ADF4368_REG35_RSV2 NO_OS_BIT(1) |
◆ ADF4368_REG35_RSV3
| #define ADF4368_REG35_RSV3 NO_OS_GENMASK(6, 3) |
◆ ADF4368_REG35_RSV4
| #define ADF4368_REG35_RSV4 NO_OS_BIT(7) |
◆ ADF4368_REG36_RSV1
| #define ADF4368_REG36_RSV1 NO_OS_GENMASK(3, 0) |
◆ ADF4368_REG36_RSV2
| #define ADF4368_REG36_RSV2 NO_OS_BIT(4) |
◆ ADF4368_REG36_RSV3
| #define ADF4368_REG36_RSV3 NO_OS_BIT(5) |
◆ ADF4368_REG3F_RSV1
| #define ADF4368_REG3F_RSV1 NO_OS_BIT(2) |
◆ ADF4368_REG3F_RSV2
| #define ADF4368_REG3F_RSV2 NO_OS_BIT(3) |
◆ ADF4368_REG3F_RSV3
| #define ADF4368_REG3F_RSV3 NO_OS_BIT(4) |
◆ ADF4368_REG3F_RSV4
| #define ADF4368_REG3F_RSV4 NO_OS_BIT(5) |
◆ ADF4368_REG3F_RSV5
| #define ADF4368_REG3F_RSV5 NO_OS_BIT(6) |
◆ ADF4368_REG40_RSV1
| #define ADF4368_REG40_RSV1 NO_OS_GENMASK(5, 3) |
◆ ADF4368_REG43_RSV1
| #define ADF4368_REG43_RSV1 NO_OS_GENMASK(2, 0) |
◆ ADF4368_REG43_RSV2
| #define ADF4368_REG43_RSV2 NO_OS_BIT(3) |
◆ ADF4368_REG43_RSV3
| #define ADF4368_REG43_RSV3 NO_OS_BIT(4) |
◆ ADF4368_REG43_RSV4
| #define ADF4368_REG43_RSV4 NO_OS_BIT(5) |
◆ ADF4368_REG43_RSV5
| #define ADF4368_REG43_RSV5 NO_OS_BIT(7) |
◆ ADF4368_REG4E_RSV1
| #define ADF4368_REG4E_RSV1 NO_OS_BIT(0) |
◆ ADF4368_REG4E_RSV2
| #define ADF4368_REG4E_RSV2 NO_OS_GENMASK(7, 6) |
◆ ADF4368_REG53_RSV1
| #define ADF4368_REG53_RSV1 NO_OS_GENMASK(3, 0) |
◆ ADF4368_REG53_RSV2
| #define ADF4368_REG53_RSV2 NO_OS_BIT(7) |
◆ ADF4368_REG54_RSV1
| #define ADF4368_REG54_RSV1 NO_OS_GENMASK(7, 1) |
◆ ADF4368_REG58_RSV1
| #define ADF4368_REG58_RSV1 NO_OS_BIT(4) |
◆ ADF4368_REG5A_RSV1
| #define ADF4368_REG5A_RSV1 NO_OS_GENMASK(7, 2) |
◆ ADF4368_REG5C_RSV1
| #define ADF4368_REG5C_RSV1 NO_OS_GENMASK(7, 1) |
◆ ADF4368_REG60_RSV1
| #define ADF4368_REG60_RSV1 NO_OS_GENMASK(7, 4) |
◆ ADF4368_RESET_CMD
| #define ADF4368_RESET_CMD 0x81 |
◆ ADF4368_RESYNC_WAIT_LSB_MSK
| #define ADF4368_RESYNC_WAIT_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_RESYNC_WAIT_MID_MSK
| #define ADF4368_RESYNC_WAIT_MID_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_RESYNC_WAIT_MSB_MSK
| #define ADF4368_RESYNC_WAIT_MSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_RFOUT_MAX
| #define ADF4368_RFOUT_MAX 12800000000U |
◆ ADF4368_RFOUT_MIN
| #define ADF4368_RFOUT_MIN 800000000U |
◆ ADF4368_RST_LD_MSK
| #define ADF4368_RST_LD_MSK NO_OS_BIT(2) |
◆ ADF4368_RST_SYNC_MON_MSK
| #define ADF4368_RST_SYNC_MON_MSK NO_OS_BIT(4) |
◆ ADF4368_RST_SYS_MSK
| #define ADF4368_RST_SYS_MSK NO_OS_BIT(4) |
◆ ADF4368_S_TO_NS
| #define ADF4368_S_TO_NS NANO |
◆ ADF4368_SCRATCHPAD_MSK
| #define ADF4368_SCRATCHPAD_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_SDO_ACTIVE_MSK
| #define ADF4368_SDO_ACTIVE_MSK NO_OS_BIT(3) |
◆ ADF4368_SDO_ACTIVE_R_MSK
| #define ADF4368_SDO_ACTIVE_R_MSK NO_OS_BIT(4) |
◆ ADF4368_SDO_ACTIVE_SPI_3W
| #define ADF4368_SDO_ACTIVE_SPI_3W 0x0 |
◆ ADF4368_SDO_ACTIVE_SPI_4W
| #define ADF4368_SDO_ACTIVE_SPI_4W 0x1 |
◆ ADF4368_SIGMA_DELTA_MOD_CNST
| #define ADF4368_SIGMA_DELTA_MOD_CNST 4096 |
◆ ADF4368_SINGLE_INSTR_MSK
| #define ADF4368_SINGLE_INSTR_MSK NO_OS_BIT(7) |
◆ ADF4368_SOFT_RESET_EN
| #define ADF4368_SOFT_RESET_EN 0x1 |
◆ ADF4368_SOFT_RESET_MSK
| #define ADF4368_SOFT_RESET_MSK NO_OS_BIT(0) |
◆ ADF4368_SOFT_RESET_N_OP
| #define ADF4368_SOFT_RESET_N_OP 0x0 |
◆ ADF4368_SOFT_RESET_R_MSK
| #define ADF4368_SOFT_RESET_R_MSK NO_OS_BIT(7) |
◆ ADF4368_SPI_4W_CFG
| #define ADF4368_SPI_4W_CFG | ( | x | ) |
Value:
(no_os_field_prep(ADF4368_SDO_ACTIVE_MSK, x) | \
no_os_field_prep(ADF4368_SDO_ACTIVE_R_MSK, x))
uint32_t no_os_field_prep(uint32_t mask, uint32_t val)
◆ ADF4368_SPI_DUMMY_DATA
| #define ADF4368_SPI_DUMMY_DATA 0x00 |
◆ ADF4368_SPI_LSB_CFG
| #define ADF4368_SPI_LSB_CFG | ( | x | ) |
Value:
(no_os_field_prep(ADF4368_LSB_FIRST_MSK, x) | \
no_os_field_prep(ADF4368_LSB_FIRST_R_MSK, x))
◆ ADF4368_SPI_READ_CMD
| #define ADF4368_SPI_READ_CMD 0x8000 |
◆ ADF4368_SPI_SCRATCHPAD_TEST
| #define ADF4368_SPI_SCRATCHPAD_TEST 0x5A |
◆ ADF4368_SPI_STREAM_DIS
| #define ADF4368_SPI_STREAM_DIS 0x1 |
◆ ADF4368_SPI_STREAM_EN
| #define ADF4368_SPI_STREAM_EN 0x0 |
◆ ADF4368_SPI_WRITE_CMD
| #define ADF4368_SPI_WRITE_CMD 0x0 |
◆ ADF4368_SW_SYNC_MSK
| #define ADF4368_SW_SYNC_MSK NO_OS_BIT(7) |
◆ ADF4368_SYNC_DEL_MSK
| #define ADF4368_SYNC_DEL_MSK NO_OS_GENMASK(7, 5) |
◆ ADF4368_SYNC_OK_MSK
| #define ADF4368_SYNC_OK_MSK NO_OS_BIT(5) |
◆ ADF4368_SYNC_SEL_MSK
| #define ADF4368_SYNC_SEL_MSK NO_OS_BIT(5) |
◆ ADF4368_SYNTH_LOCK_TIMEOUT_LSB_MSK
| #define ADF4368_SYNTH_LOCK_TIMEOUT_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_SYNTH_LOCK_TIMEOUT_MSB_MSK
| #define ADF4368_SYNTH_LOCK_TIMEOUT_MSB_MSK NO_OS_GENMASK(6, 0) |
◆ ADF4368_TIMED_SYNC_MSK
| #define ADF4368_TIMED_SYNC_MSK NO_OS_BIT(5) |
◆ ADF4368_US_TO_FS
| #define ADF4368_US_TO_FS NANO |
◆ ADF4368_US_TO_MS
| #define ADF4368_US_TO_MS MILLI |
◆ ADF4368_VAR_MOD_EN_MSK
| #define ADF4368_VAR_MOD_EN_MSK NO_OS_BIT(5) |
◆ ADF4368_VCO_ALC_TIMEOUT_LSB_MSK
| #define ADF4368_VCO_ALC_TIMEOUT_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_VCO_ALC_TIMEOUT_MSB_MSK
| #define ADF4368_VCO_ALC_TIMEOUT_MSB_MSK NO_OS_GENMASK(6, 0) |
◆ ADF4368_VCO_BAND_DIV
| #define ADF4368_VCO_BAND_DIV NO_OS_GENMASK(7, 0) |
◆ ADF4368_VCO_BAND_MSK
| #define ADF4368_VCO_BAND_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4368_VCO_BIAS_MSK
| #define ADF4368_VCO_BIAS_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4368_VCO_CORE_MSK
| #define ADF4368_VCO_CORE_MSK NO_OS_GENMASK(1, 0) |
◆ ADF4368_VCO_FREQ_MAX
| #define ADF4368_VCO_FREQ_MAX 12800000000U |
◆ ADF4368_VCO_FREQ_MIN
| #define ADF4368_VCO_FREQ_MIN 6400000000U |
◆ ADF4368_VERSION_MSK
| #define ADF4368_VERSION_MSK NO_OS_GENMASK(7, 0) |
Function Documentation
◆ adf4368_get_bleed_word()
| int adf4368_get_bleed_word | ( | struct adf4368_dev * | dev, |
| int32_t * | word ) |
Gets the value of the bleed word.
ADF4368 Get bleed current attribute
- Parameters
-
dev - The device structure. word - The read bleed current register value.
- Returns
- - Result of the reading procedure, error code otherwise.
◆ adf4368_get_cp_i()
| int adf4368_get_cp_i | ( | struct adf4368_dev * | dev, |
| int32_t * | reg_val ) |
Gets the charge pump value from the register. The value will be between 0 and 15 on 8 bits. For more information please consult the Datasheet.
ADF4368 Get charge pump current attribute
- Parameters
-
dev - The device structure. reg_val - The read charge pump register value.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_get_default_regs()
| int adf4368_get_default_regs | ( | struct adf4368_dev * | dev, |
| bool * | check ) |
Reads and Checks the registers values equal to default values.
ADF4368 Get default registers and check
- Parameters
-
dev - The device structure check - default state value
- Returns
- - 0 in case of success, negative error code otherwise.
◆ adf4368_get_en_chan()
| int adf4368_get_en_chan | ( | struct adf4368_dev * | dev, |
| uint8_t | ch, | ||
| bool * | en ) |
Gets the value the output channel if it is enabled or disable.
ADF4368 Get channel enable attributes
- Parameters
-
dev - The device structure. ch - The channel to get state. en - The status of the output channel.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_get_en_ref_doubler()
| int adf4368_get_en_ref_doubler | ( | struct adf4368_dev * | dev, |
| bool * | en ) |
Gets the value the doubler if it is enabled or disable and stores it it the dev structure.
ADF4368 Get reference doubler attribute
- Parameters
-
dev - The device structure. en - The read value of the reference doubler.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_get_out_power()
| int adf4368_get_out_power | ( | struct adf4368_dev * | dev, |
| uint8_t | ch, | ||
| int32_t * | pwr ) |
Gets the output power register value.
ADF4368 Get output power attributes
- Parameters
-
dev - The device structure. ch - The channel to get the power off. pwr - The output power register value.
- Returns
- - Result of the reading procedure, error code otherwise.
◆ adf4368_get_phase()
| int adf4368_get_phase | ( | struct adf4368_dev * | dev, |
| uint32_t * | phase_fs, | ||
| bool * | phase_pol ) |
Get the phase adjustment in femto-seconds. Function choose the phase adjustment method according to Integer mode.
ADF4368 Get phase adjustment value
- Parameters
-
dev - The device structure. phase_fs - The phase adjustment in femto-seconds. phase_pol - The phase adjustment value's sign.
- Returns
- - 0 in case of success, negative error code otherwise.
◆ adf4368_get_phase_sdm()
| int adf4368_get_phase_sdm | ( | struct adf4368_dev * | dev, |
| uint32_t * | phase_fs ) |
Get the phase adjustment in femto-seconds with Sigma Delta Modulation.
ADF4368 Get phase adjust in frac mode attribute
- Parameters
-
dev - The device structure. phase_fs - The Read value of the phase adjustment in femto-seconds.
- Returns
- - 0 in case of success, negative error code otherwise.
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◆ adf4368_get_ref_clk()
| int adf4368_get_ref_clk | ( | struct adf4368_dev * | dev, |
| uint64_t * | val ) |
Gets the user proposed reference frequency.
ADF4368 Get reference frequency attribute
- Parameters
-
dev - The device structure. val - The set value of the reference frequency in Hz.
- Returns
- - Reference frequency in KHz.
◆ adf4368_get_ref_div()
| int adf4368_get_ref_div | ( | struct adf4368_dev * | dev, |
| int32_t * | div ) |
Gets the value the reference divider.
ADF4368 Get reference divider attribute
- Parameters
-
dev - The device structure. div - The read reference divider value.
- Returns
- - Result of the reading procedure, error code otherwise.
◆ adf4368_get_rfout()
| int adf4368_get_rfout | ( | struct adf4368_dev * | dev, |
| uint64_t * | val ) |
Gets the user proposed output frequency.
ADF4368 Get output frequency attribute
- Parameters
-
dev - The device structure. val - The value of the output frequency in Hz.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_get_sw_sync()
| int adf4368_get_sw_sync | ( | struct adf4368_dev * | dev, |
| uint8_t * | sw_sync ) |
Gets the value of the SW_SYNC bit.
ADF4368 Get sw_sync attribute
- Parameters
-
dev - The device structure. sw_sync - The read value of the SW_SYNC.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_get_sync_setup()
| int adf4368_get_sync_setup | ( | struct adf4368_dev * | dev, |
| bool * | en ) |
Gets the value of the SYNC features' powerdown bit.
ADF4368 Get sync_setup attribute
- Parameters
-
dev - The device structure. en - The read value of the SYNC features' powerdown.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_get_temperature()
| int adf4368_get_temperature | ( | struct adf4368_dev * | dev, |
| int32_t * | temp ) |
Gets the value of the approximate die temperature.
ADF4368 Get temperature readback attribute
- Parameters
-
dev - The device structure. temp - The read value of the Temperature Readback.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_init()
| int adf4368_init | ( | struct adf4368_dev ** | dev, |
| struct adf4368_init_param * | init_param ) |
Initializes the adf4368.
ADF4368 Initialization
- Parameters
-
dev - The device structure. init_param - The structure containing the device initial parameters.
- Returns
- - 0 in case of success or negative error code.
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◆ adf4368_reg_dump()
| int adf4368_reg_dump | ( | struct adf4368_dev * | dev | ) |
Will output on the terminal the values of all the ADF4368 registers.
ADF4368 Register dump
- Parameters
-
dev - The device structure.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_remove()
| int adf4368_remove | ( | struct adf4368_dev * | dev | ) |
Free resources allocated for ADF4368.
ADF4368 Remove
- Parameters
-
dev - The device structure.
- Returns
- - 0 in case of success or negative error code.
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◆ adf4368_set_bleed_word()
| int adf4368_set_bleed_word | ( | struct adf4368_dev * | dev, |
| int32_t | word ) |
Set the bleed word, which represents the value of the bleed current written to the register space.
ADF4368 Set bleed current attribute
- Parameters
-
dev - The device structure. word - The bleed current register value.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_set_cp_i()
| int adf4368_set_cp_i | ( | struct adf4368_dev * | dev, |
| int32_t | reg_val ) |
Set the charge pump value which will be written to the register. The value will be between 0 and 15 on 8 bits. For more information please consult the Datasheet.
ADF4368 Set charge pump current attribute
- Parameters
-
dev - The device structure. reg_val - The desired charge pump register value.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_set_default_regs()
| int adf4368_set_default_regs | ( | struct adf4368_dev * | dev, |
| bool | spi_4wire ) |
Applys a softreset, sets the SPI 4 wire mode and writes the default registers.
ADF4368 Set default registers and SPI 4 Wire mode
- Parameters
-
dev - The device structure spi_4wire - SPI 4 wire feature enable input
- Returns
- - 0 in case of success, negative error code otherwise.
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◆ adf4368_set_en_chan()
| int adf4368_set_en_chan | ( | struct adf4368_dev * | dev, |
| uint8_t | ch, | ||
| bool | en ) |
Set the output channel to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable.
ADF4368 Set channel enable attributes
- Parameters
-
dev - The device structure. ch - The channel to set state. en - The enable or disable value of the output channel.
- Returns
- - Result of the writing procedure, error code otherwise.
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◆ adf4368_set_en_ref_doubler()
| int adf4368_set_en_ref_doubler | ( | struct adf4368_dev * | dev, |
| bool | en ) |
Set the reference doubler to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable.
ADF4368 Set reference doubler attribute
- Parameters
-
dev - The device structure. en - The enable or disable value of the reference doubler.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_set_freq()
| int adf4368_set_freq | ( | struct adf4368_dev * | dev | ) |
Set the output frequency.
ADF4368 Sets frequency
- Parameters
-
dev - The device structure.
- Returns
- - 0 in case of success, negative error code otherwise.
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◆ adf4368_set_out_power()
| int adf4368_set_out_power | ( | struct adf4368_dev * | dev, |
| uint8_t | ch, | ||
| int32_t | pwr ) |
Set the output power register value of a channel and reset everything over to maximum supported value of 15 to the max. value.
ADF4368 Set output power attributes
- Parameters
-
dev - The device structure. ch - The channel to set the power off. pwr - The output power register value.
- Returns
- - Result of the writing procedure, error code otherwise.
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◆ adf4368_set_phase()
| int adf4368_set_phase | ( | struct adf4368_dev * | dev, |
| uint32_t | phase_fs, | ||
| bool | phase_pol ) |
Set the phase adjustment in femto-seconds. Function choose the phase adjustment method according to Integer mode.
ADF4368 Set phase adjustment value
- Parameters
-
dev - The device structure. phase_fs - The phase adjustment in femto-seconds. phase_pol - The phase adjustment value's sign.
- Returns
- - 0 in case of success, negative error code otherwise.
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◆ adf4368_set_phase_bleedi()
| int adf4368_set_phase_bleedi | ( | struct adf4368_dev * | dev, |
| uint32_t | phase_fs, | ||
| bool | phase_pol ) |
Set the phase adjustment in femto-seconds. The phase adjust will enable the Bleed current. Recommend to use in integer mode.
ADF4368 Set phase adjust in int mode attribute
- Parameters
-
dev - The device structure. phase_fs - The phase adjustment in femto-seconds. phase_pol - The phase adjustment value's sign.
- Returns
- - 0 in case of success, negative error code otherwise.
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◆ adf4368_set_phase_sdm()
| int adf4368_set_phase_sdm | ( | struct adf4368_dev * | dev, |
| uint32_t | phase_fs ) |
Set the phase adjustment in femto-seconds with Sigma Delta Modulation. This approach only support MAX %22 in degree phase. Recommend to use in fractional mode.
ADF4368 Set phase adjust in frac mode attribute
- Parameters
-
dev - The device structure. phase_fs - The phase adjustment in femto-seconds.
- Returns
- - 0 in case of success, negative error code otherwise.
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◆ adf4368_set_ref_clk()
| int adf4368_set_ref_clk | ( | struct adf4368_dev * | dev, |
| uint64_t | val ) |
Set the desired reference frequency and reset everything over to maximum supported value of 4GHz to the max. value and everything under the minimum supported value of 10MHz to the min. value.
ADF4368 Set reference frequency attribute
- Parameters
-
dev - The device structure. val - The desired reference frequency in Hz.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_set_ref_div()
| int adf4368_set_ref_div | ( | struct adf4368_dev * | dev, |
| int32_t | div ) |
Set the reference divider value and reset everything over to maximum supported value of 63 to the max. value.
ADF4368 Set reference divider attribute
- Parameters
-
dev - The device structure. div - The reference divider value.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_set_rfout()
| int adf4368_set_rfout | ( | struct adf4368_dev * | dev, |
| uint64_t | val ) |
Set the desired output frequency and reset everything over to maximum supported value of 12.8GHz to the max. value and everything under the minimum supported value of 800MHz to the min. value.
ADF4368 Set output frequency attribute
- Parameters
-
dev - The device structure. val - The desired output frequency in Hz.
- Returns
- - 0 in case of success or negative error code.
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◆ adf4368_set_sw_sync()
| int adf4368_set_sw_sync | ( | struct adf4368_dev * | dev, |
| uint8_t | sw_sync ) |
Set Software SYNC Request. Setting SW_SYNC resets the RF block. Clearing SW_SYNC makes ready for a new reference clock.
ADF4368 Set sw_sync attribute
- Parameters
-
dev - The device structure. sw_sync - Set send SW_SYNC request
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_set_sync_setup()
| int adf4368_set_sync_setup | ( | struct adf4368_dev * | dev, |
| bool | en ) |
Set EZSYNC and Timed SYNC features' initial state. Waits for SW_SYNC toggle or SYNC pin.
ADF4368 Set sync_setup attribute
- Parameters
-
dev - The device structure. en - The enable or disable SYNC feature.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_set_temperature()
| int adf4368_set_temperature | ( | struct adf4368_dev * | dev, |
| bool | en ) |
Set Temperature Readback feature's initial state. This feature should be disabled after reading temperature.
ADF4368 Set temperature readback setup attribute
- Parameters
-
dev - The device structure. en - The enable or disable Temperature readback feature.
- Returns
- - 0 in case of success or negative error code.
◆ adf4368_spi_read()
| int adf4368_spi_read | ( | struct adf4368_dev * | dev, |
| uint16_t | reg_addr, | ||
| uint8_t * | data ) |
Reads data from ADF4368 over SPI.
ADF4368 SPI Read
- Parameters
-
dev - The device structure. reg_addr - The register address. data - Data read from the device.
- Returns
- - 0 in case of success or negative error code otherwise.
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◆ adf4368_spi_update_bits()
| int adf4368_spi_update_bits | ( | struct adf4368_dev * | dev, |
| uint16_t | reg_addr, | ||
| uint8_t | mask, | ||
| uint8_t | data ) |
Updates the values of the ADF4368 register.
ADF4368 updates a bit in the register space over SPI
- Parameters
-
dev - The device structure. reg_addr - The register address. mask - Bits to be updated. data - Update value for the mask.
- Returns
- - 0 in case of success or negative error code otherwise.
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◆ adf4368_spi_write()
| int adf4368_spi_write | ( | struct adf4368_dev * | dev, |
| uint16_t | reg_addr, | ||
| uint8_t | data ) |
Writes data to ADF4368 over SPI.
ADF4368 SPI write
- Parameters
-
dev - The device structure. reg_addr - The register address. data - Data value to write.
- Returns
- - 0 in case of success or negative error code otherwise.
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