Implementation of adf4382 Driver. More...
#include <stdint.h>#include <string.h>#include "no_os_units.h"#include "no_os_util.h"#include "no_os_spi.h"
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Classes | |
| struct | adf4382_init_param |
| ADF4382 Initialization Parameters structure. More... | |
| struct | adf4382_dev |
| ADF4382 Device Descriptor. More... | |
| struct | reg_sequence |
| ADF4382 register format structure for default values. More... | |
Enumerations | |
| enum | adf4382_dev_id { ID_ADF4382, ID_ADF4382A } |
| Supported device ids. More... | |
Functions | |
| int | adf4382_spi_write (struct adf4382_dev *dev, uint16_t reg_addr, uint8_t data) |
| Writes data to ADF4382 over SPI. More... | |
| int | adf4382_spi_read (struct adf4382_dev *dev, uint16_t reg_addr, uint8_t *data) |
| Reads data from ADF4382 over SPI. More... | |
| int | adf4382_spi_update_bits (struct adf4382_dev *dev, uint16_t reg_addr, uint8_t mask, uint8_t data) |
| Updates the values of the ADF4382 register. More... | |
| int | adf4382_reg_dump (struct adf4382_dev *dev) |
| Will output on the terminal the values of all the ADF4382 registers. More... | |
| int | adf4382_set_ref_clk (struct adf4382_dev *dev, uint64_t val) |
| Set the desired reference frequency and reset everything over to maximum supported value of 5GHz to the max. value and everything under the minimum supported value of 10MHz to the min. value. More... | |
| int | adf4382_get_ref_clk (struct adf4382_dev *dev, uint64_t *val) |
| Gets the user proposed reference frequency. More... | |
| int | adf4382_set_en_ref_doubler (struct adf4382_dev *dev, bool en) |
| Set the reference doubler to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable. More... | |
| int | adf4382_get_en_ref_doubler (struct adf4382_dev *dev, bool *en) |
| Gets the value the doubler if it is enabled or disable and stores it it the dev structure. More... | |
| int | adf4382_set_ref_div (struct adf4382_dev *dev, int32_t div) |
| Set the reference divider value and reset everything over to maximum supported value of 63 to the max. value. More... | |
| int | adf4382_get_ref_div (struct adf4382_dev *dev, int32_t *div) |
| Gets the value the reference divider. More... | |
| int | adf4382_set_cp_i (struct adf4382_dev *dev, int32_t reg_val) |
| Set the charge pump value which will be written to the register. The value will be between 0 and 15 on 8 bits. For more information please consult the Datasheet. More... | |
| int | adf4382_get_cp_i (struct adf4382_dev *dev, int32_t *reg_val) |
| Gets the charge pump value from the register. The value will be between 0 and 15 on 8 bits. For more information please consult the Datasheet. More... | |
| int | adf4382_set_bleed_word (struct adf4382_dev *dev, int32_t word) |
| Set the bleed word, which represents the value of the bleed current written to the register space. More... | |
| int | adf4382_get_bleed_word (struct adf4382_dev *dev, int32_t *word) |
| Gets the value of the set bleed word. More... | |
| int | adf4382_set_rfout (struct adf4382_dev *dev, uint64_t val) |
| Set the desired output frequency and reset everything over to maximum supported value of 22GHz (21GHz for ADF4382A) to the max. value and everything under the minimum supported value of 687.5MHz (2.875GHz for ADF4382A) to the min. value. More... | |
| int | adf4382_get_rfout (struct adf4382_dev *dev, uint64_t *val) |
| Gets the user proposed output frequency. More... | |
| int | adf4382_set_out_power (struct adf4382_dev *dev, uint8_t ch, int32_t pwr) |
| Set the output power register value of a channel and reset everything over to maximum supported value of 15 to the max. value. More... | |
| int | adf4382_get_out_power (struct adf4382_dev *dev, uint8_t ch, int32_t *pwr) |
| Gets the output power register value. More... | |
| int | adf4382_set_en_chan (struct adf4382_dev *dev, uint8_t ch, bool en) |
| Set the output channel to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable. More... | |
| int | adf4382_get_en_chan (struct adf4382_dev *dev, uint8_t ch, bool *en) |
| Gets the value the output channel if it is enabled or disable. More... | |
| int | adf4382_set_en_sync (struct adf4382_dev *dev, bool en) |
| Set the sync to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable. More... | |
| int | adf4382_get_en_sync (struct adf4382_dev *dev, bool *en) |
| Gets the value the sync if it is enabled or disable. More... | |
| int | adf4382_set_freq (struct adf4382_dev *dev) |
| Set the output frequency. More... | |
| int | adf4382_set_phase_adjust (struct adf4382_dev *dev, uint32_t phase_ps) |
| Set the phase adjustment in pico-seconds. The phase adjust will enable the Bleed current option as well as delay mode to 0. More... | |
| int | adf4382_set_phase_pol (struct adf4382_dev *dev, bool polarity) |
| Set the phase polarity. If pol = 0 then it will add the phase value otherwise it will subtract the phase value. More... | |
| int | adf4382_get_phase_pol (struct adf4382_dev *dev, bool *polarity) |
| Gets the polarity of the phase adjust. More... | |
| int | adf4382_init (struct adf4382_dev **device, struct adf4382_init_param *init_param) |
| Initializes the ADF4382. More... | |
| int | adf4382_remove (struct adf4382_dev *dev) |
| Free resources allocated for ADF4382. More... | |
Detailed Description
Implementation of adf4382 Driver.
Copyright 2024(c) Analog Devices, Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
- Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
- The use of this software may or may not infringe the patent rights of one or more patent holders. This license does not release you from the requirement that you obtain separate licenses from these patent holders to use this software.
- Use of the software either in source or binary form, must be run on or directly connected to an Analog Devices Inc. component.
THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Macro Definition Documentation
◆ ADF4382_ABPW_WD_MSK
| #define ADF4382_ABPW_WD_MSK NO_OS_BIT(3) |
◆ ADF4382_ADC_C_CONV_MSK
| #define ADF4382_ADC_C_CONV_MSK NO_OS_BIT(2) |
◆ ADF4382_ADC_CLK_DIV_MSK
| #define ADF4382_ADC_CLK_DIV_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_ADC_CLK_TEST_SEL_MSK
| #define ADF4382_ADC_CLK_TEST_SEL_MSK NO_OS_BIT(6) |
◆ ADF4382_ADC_F_CONV_MSK
| #define ADF4382_ADC_F_CONV_MSK NO_OS_BIT(3) |
◆ ADF4382_ADC_MUX_SEL_MSK
| #define ADF4382_ADC_MUX_SEL_MSK NO_OS_BIT(4) |
◆ ADF4382_ADC_ST_CNV_MSK
| #define ADF4382_ADC_ST_CNV_MSK NO_OS_BIT(0) |
◆ ADF4382_ADC_VTEST_SEL_MSK
| #define ADF4382_ADC_VTEST_SEL_MSK NO_OS_BIT(5) |
◆ ADF4382_ADDR_ASC_AUTO_DECR
| #define ADF4382_ADDR_ASC_AUTO_DECR 0x0 |
◆ ADF4382_ADDR_ASC_AUTO_INCR
| #define ADF4382_ADDR_ASC_AUTO_INCR 0x1 |
◆ ADF4382_ADDRESS_ASC_MSK
| #define ADF4382_ADDRESS_ASC_MSK NO_OS_BIT(2) |
◆ ADF4382_ADDRESS_ASC_R_MSK
| #define ADF4382_ADDRESS_ASC_R_MSK NO_OS_BIT(5) |
◆ ADF4382_BIAS_DEC_MODE_MSK
| #define ADF4382_BIAS_DEC_MODE_MSK NO_OS_GENMASK(5, 3) |
◆ ADF4382_BLEED_ADJ_CAL_MSK
| #define ADF4382_BLEED_ADJ_CAL_MSK NO_OS_BIT(6) |
◆ ADF4382_BLEED_ADJ_SCALE_MSK
| #define ADF4382_BLEED_ADJ_SCALE_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4382_BLEED_MSB_MSK
| #define ADF4382_BLEED_MSB_MSK |
Value:
ADF4382_FINE_BLEED_MSB_MSK)
◆ ADF4382_BLEED_POL_MSK
| #define ADF4382_BLEED_POL_MSK NO_OS_BIT(5) |
◆ ADF4382_BLEED_WORD_MAX
| #define ADF4382_BLEED_WORD_MAX 8191 |
◆ ADF4382_BST_REF_MSK
| #define ADF4382_BST_REF_MSK NO_OS_BIT(7) |
◆ ADF4382_BUFF_SIZE_BYTES
| #define ADF4382_BUFF_SIZE_BYTES 3 |
◆ ADF4382_CAL_BLEED_FINE_MAX_MSK
| #define ADF4382_CAL_BLEED_FINE_MAX_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_CAL_BLEED_FINE_MIN_MSK
| #define ADF4382_CAL_BLEED_FINE_MIN_MSK NO_OS_GENMASK(7, 4) |
◆ ADF4382_CAL_COUNT_TO_MSK
| #define ADF4382_CAL_COUNT_TO_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_CAL_CT_SEL_MSK
| #define ADF4382_CAL_CT_SEL_MSK NO_OS_BIT(1) |
◆ ADF4382_CAL_VCO_TO_LSB_MSK
| #define ADF4382_CAL_VCO_TO_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_CAL_VCO_TO_MSB_MSK
| #define ADF4382_CAL_VCO_TO_MSB_MSK NO_OS_GENMASK(6, 0) |
◆ ADF4382_CAL_VTUNE_TO_LSB_MSK
| #define ADF4382_CAL_VTUNE_TO_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_CAL_VTUNE_TO_MSB_MSK
| #define ADF4382_CAL_VTUNE_TO_MSB_MSK NO_OS_GENMASK(6, 0) |
◆ ADF4382_CAP_TEST_STATE_MSK
| #define ADF4382_CAP_TEST_STATE_MSK NO_OS_BIT(1) |
◆ ADF4382_CHANNEL_SPACING_MAX
| #define ADF4382_CHANNEL_SPACING_MAX 78125U |
◆ ADF4382_CHIP_TYPE
| #define ADF4382_CHIP_TYPE 0x06 |
◆ ADF4382_CLK1_OPWR_MSK
| #define ADF4382_CLK1_OPWR_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4382_CLK2_OPWR_MSK
| #define ADF4382_CLK2_OPWR_MSK NO_OS_GENMASK(7, 4) |
◆ ADF4382_CLKODIV_DB_MSK
| #define ADF4382_CLKODIV_DB_MSK NO_OS_BIT(7) |
◆ ADF4382_CLKOUT_BST_MSK
| #define ADF4382_CLKOUT_BST_MSK NO_OS_BIT(5) |
◆ ADF4382_CLKOUT_DIV_MSK
| #define ADF4382_CLKOUT_DIV_MSK NO_OS_GENMASK(7, 5) |
◆ ADF4382_CLKOUT_DIV_REG_VAL_MAX
| #define ADF4382_CLKOUT_DIV_REG_VAL_MAX 4 |
◆ ADF4382_CMOS_OV_MSK
| #define ADF4382_CMOS_OV_MSK NO_OS_BIT(5) |
◆ ADF4382_CNTR_DIV_WORD_MSB_MSK
| #define ADF4382_CNTR_DIV_WORD_MSB_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4382_CNTR_DIV_WORD_MSK
| #define ADF4382_CNTR_DIV_WORD_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_COARSE_BLEED_MSK
| #define ADF4382_COARSE_BLEED_MSK NO_OS_GENMASK(4, 1) |
◆ ADF4382_CP_DOWN_MSK
| #define ADF4382_CP_DOWN_MSK NO_OS_BIT(1) |
◆ ADF4382_CP_I_MSK
| #define ADF4382_CP_I_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4382_CP_UP_MSK
| #define ADF4382_CP_UP_MSK NO_OS_BIT(0) |
◆ ADF4382_CPI_VAL_MAX
| #define ADF4382_CPI_VAL_MAX 15 |
◆ ADF4382_DCLK_DIV1_0_MAX
| #define ADF4382_DCLK_DIV1_0_MAX 160000000U |
◆ ADF4382_DCLK_DIV1_1_MAX
| #define ADF4382_DCLK_DIV1_1_MAX 320000000U |
◆ ADF4382_DCLK_DIV1_MSK
| #define ADF4382_DCLK_DIV1_MSK NO_OS_GENMASK(1, 0) |
◆ ADF4382_DCLK_DIV_DB_MSK
| #define ADF4382_DCLK_DIV_DB_MSK NO_OS_BIT(6) |
◆ ADF4382_DCLK_DIV_SEL_MSK
| #define ADF4382_DCLK_DIV_SEL_MSK NO_OS_BIT(4) |
◆ ADF4382_DCLK_MODE_MSK
| #define ADF4382_DCLK_MODE_MSK NO_OS_BIT(0) |
◆ ADF4382_DEL_CTRL_DB_MSK
| #define ADF4382_DEL_CTRL_DB_MSK NO_OS_BIT(7) |
◆ ADF4382_DEL_MODE_MSK
| #define ADF4382_DEL_MODE_MSK NO_OS_BIT(5) |
◆ ADF4382_DITHER1_SCALE_MSK
| #define ADF4382_DITHER1_SCALE_MSK NO_OS_GENMASK(4, 2) |
◆ ADF4382_DNCLK_DEL_MSK
| #define ADF4382_DNCLK_DEL_MSK NO_OS_GENMASK(3, 1) |
◆ ADF4382_DNCLK_DIV1_MSK
| #define ADF4382_DNCLK_DIV1_MSK NO_OS_GENMASK(3, 2) |
◆ ADF4382_DRCLK_DEL_MSK
| #define ADF4382_DRCLK_DEL_MSK NO_OS_GENMASK(6, 4) |
◆ ADF4382_EFM3_MODE_MSK
| #define ADF4382_EFM3_MODE_MSK NO_OS_GENMASK(2, 0) |
◆ ADF4382_EN_ADC_CLK_MSK
| #define ADF4382_EN_ADC_CLK_MSK NO_OS_BIT(3) |
◆ ADF4382_EN_ADC_CNV_MSK
| #define ADF4382_EN_ADC_CNV_MSK NO_OS_BIT(7) |
◆ ADF4382_EN_ADC_MSK
| #define ADF4382_EN_ADC_MSK NO_OS_BIT(1) |
◆ ADF4382_EN_ADC_VTEST_MSK
| #define ADF4382_EN_ADC_VTEST_MSK NO_OS_BIT(6) |
◆ ADF4382_EN_AUTO_ALIGN_MSK
| #define ADF4382_EN_AUTO_ALIGN_MSK NO_OS_BIT(4) |
◆ ADF4382_EN_AUTOCAL_MSK
| #define ADF4382_EN_AUTOCAL_MSK NO_OS_BIT(7) |
◆ ADF4382_EN_BLEED_MSK
| #define ADF4382_EN_BLEED_MSK NO_OS_BIT(4) |
◆ ADF4382_EN_CALGEN_CAP_TEST_MSK
| #define ADF4382_EN_CALGEN_CAP_TEST_MSK NO_OS_BIT(3) |
◆ ADF4382_EN_CP_CAP_TEST_MSK
| #define ADF4382_EN_CP_CAP_TEST_MSK NO_OS_BIT(2) |
◆ ADF4382_EN_CPTEST_MSK
| #define ADF4382_EN_CPTEST_MSK NO_OS_BIT(2) |
◆ ADF4382_EN_DITHER1_MSK
| #define ADF4382_EN_DITHER1_MSK NO_OS_BIT(0) |
◆ ADF4382_EN_DITHER2_MSK
| #define ADF4382_EN_DITHER2_MSK NO_OS_BIT(1) |
◆ ADF4382_EN_DNCLK_MSK
| #define ADF4382_EN_DNCLK_MSK NO_OS_BIT(7) |
◆ ADF4382_EN_DRCLK_MSK
| #define ADF4382_EN_DRCLK_MSK NO_OS_BIT(6) |
◆ ADF4382_EN_LDWIN_MSK
| #define ADF4382_EN_LDWIN_MSK NO_OS_BIT(4) |
◆ ADF4382_EN_LOL_MSK
| #define ADF4382_EN_LOL_MSK NO_OS_BIT(5) |
◆ ADF4382_EN_LUT_CAL_MSK
| #define ADF4382_EN_LUT_CAL_MSK NO_OS_BIT(0) |
◆ ADF4382_EN_LUT_GEN_MSK
| #define ADF4382_EN_LUT_GEN_MSK NO_OS_BIT(1) |
◆ ADF4382_EN_PHASE_RESYNC_MSK
| #define ADF4382_EN_PHASE_RESYNC_MSK NO_OS_BIT(7) |
◆ ADF4382_EN_RDBLR_MSK
| #define ADF4382_EN_RDBLR_MSK NO_OS_BIT(6) |
◆ ADF4382_EN_REF_RST_MSK
| #define ADF4382_EN_REF_RST_MSK NO_OS_BIT(6) |
◆ ADF4382_EN_TWO_PASS_CAL_MSK
| #define ADF4382_EN_TWO_PASS_CAL_MSK NO_OS_BIT(4) |
◆ ADF4382_EN_VCAL_MSK
| #define ADF4382_EN_VCAL_MSK NO_OS_BIT(2) |
◆ ADF4382_EN_VCO_CAP_TEST_MSK
| #define ADF4382_EN_VCO_CAP_TEST_MSK NO_OS_BIT(4) |
◆ ADF4382_EXT_DIV_DEC_SEL_MSK
| #define ADF4382_EXT_DIV_DEC_SEL_MSK NO_OS_BIT(7) |
◆ ADF4382_EXT_DIV_MSK
| #define ADF4382_EXT_DIV_MSK NO_OS_GENMASK(7, 5) |
◆ ADF4382_FILT_REF_MSK
| #define ADF4382_FILT_REF_MSK NO_OS_BIT(6) |
◆ ADF4382_FINE_BLEED_LSB_MSK
| #define ADF4382_FINE_BLEED_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_FINE_BLEED_MSB_MSK
| #define ADF4382_FINE_BLEED_MSB_MSK NO_OS_BIT(0) |
◆ ADF4382_FN_DBL_MSK
| #define ADF4382_FN_DBL_MSK NO_OS_BIT(7) |
◆ ADF4382_FRAC1WORD_LSB_MSK
| #define ADF4382_FRAC1WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_FRAC1WORD_MID_MSK
| #define ADF4382_FRAC1WORD_MID_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_FRAC1WORD_MSB
| #define ADF4382_FRAC1WORD_MSB NO_OS_BIT(0) |
◆ ADF4382_FRAC1WORD_MSB_MSK
| #define ADF4382_FRAC1WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_FRAC2WORD_LSB_MSK
| #define ADF4382_FRAC2WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_FRAC2WORD_MID_MSK
| #define ADF4382_FRAC2WORD_MID_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_FRAC2WORD_MSB_MSK
| #define ADF4382_FRAC2WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_INT_MODE_MSK
| #define ADF4382_INT_MODE_MSK NO_OS_BIT(2) |
◆ ADF4382_INV_CLK_OUT_MSK
| #define ADF4382_INV_CLK_OUT_MSK NO_OS_BIT(4) |
◆ ADF4382_INV_RDBLR_MSK
| #define ADF4382_INV_RDBLR_MSK NO_OS_BIT(4) |
◆ ADF4382_LD_COUNT_OPWR_MSK
| #define ADF4382_LD_COUNT_OPWR_MSK NO_OS_GENMASK(4, 0) |
◆ ADF4382_LD_O_CTRL_MSK
| #define ADF4382_LD_O_CTRL_MSK NO_OS_GENMASK(1, 0) |
◆ ADF4382_LDWIN_PW_MSK
| #define ADF4382_LDWIN_PW_MSK NO_OS_GENMASK(7, 5) |
◆ ADF4382_LKD_DELAY_US
| #define ADF4382_LKD_DELAY_US 500 |
◆ ADF4382_LOCKED_MSK
| #define ADF4382_LOCKED_MSK NO_OS_BIT(0) |
◆ ADF4382_LSB_FIRST_LSB
| #define ADF4382_LSB_FIRST_LSB 0x1 |
◆ ADF4382_LSB_FIRST_MSB
| #define ADF4382_LSB_FIRST_MSB 0x0 |
◆ ADF4382_LSB_FIRST_MSK
| #define ADF4382_LSB_FIRST_MSK NO_OS_BIT(1) |
◆ ADF4382_LSB_FIRST_R_MSK
| #define ADF4382_LSB_FIRST_R_MSK NO_OS_BIT(6) |
◆ ADF4382_LSB_P1_MSK
| #define ADF4382_LSB_P1_MSK NO_OS_BIT(6) |
◆ ADF4382_LUT_SCALE_MSK
| #define ADF4382_LUT_SCALE_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_M_S_TRANSF_NO_OS_BIT_MSK
| #define ADF4382_M_S_TRANSF_NO_OS_BIT_MSK NO_OS_BIT(0) |
◆ ADF4382_M_VCO_BAND_LSB_MSK
| #define ADF4382_M_VCO_BAND_LSB_MSK NO_OS_BIT(7) |
◆ ADF4382_M_VCO_BAND_MSB_MSK
| #define ADF4382_M_VCO_BAND_MSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_M_VCO_BIAS_MSK
| #define ADF4382_M_VCO_BIAS_MSK NO_OS_GENMASK(5, 0) |
◆ ADF4382_M_VCO_CORE_MSK
| #define ADF4382_M_VCO_CORE_MSK NO_OS_BIT(6) |
◆ ADF4382_MARGIN_MSK
| #define ADF4382_MARGIN_MSK NO_OS_GENMASK(1, 0) |
◆ ADF4382_MASTER_RB_CTRL_MSK
| #define ADF4382_MASTER_RB_CTRL_MSK NO_OS_BIT(5) |
◆ ADF4382_MOD1WORD
| #define ADF4382_MOD1WORD 0x2000000U |
◆ ADF4382_MOD2WORD_LSB_MSK
| #define ADF4382_MOD2WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_MOD2WORD_MAX
| #define ADF4382_MOD2WORD_MAX 0xFFFFFFU |
◆ ADF4382_MOD2WORD_MID_MSK
| #define ADF4382_MOD2WORD_MID_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_MOD2WORD_MSB_MSK
| #define ADF4382_MOD2WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_MUTE_CLKOUT1_MSK
| #define ADF4382_MUTE_CLKOUT1_MSK NO_OS_GENMASK(2, 0) |
◆ ADF4382_MUTE_CLKOUT2_MSK
| #define ADF4382_MUTE_CLKOUT2_MSK NO_OS_GENMASK(5, 3) |
◆ ADF4382_MUTE_NCLK_MSK
| #define ADF4382_MUTE_NCLK_MSK NO_OS_BIT(7) |
◆ ADF4382_MUTE_RCLK_MSK
| #define ADF4382_MUTE_RCLK_MSK NO_OS_BIT(6) |
◆ ADF4382_MUXOUT_MSK
| #define ADF4382_MUXOUT_MSK NO_OS_GENMASK(7, 4) |
◆ ADF4382_N_INT_LSB_MSK
| #define ADF4382_N_INT_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_N_INT_MSB_MSK
| #define ADF4382_N_INT_MSB_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4382_NDIV_PWRUP_TIMEOUT_MSK
| #define ADF4382_NDIV_PWRUP_TIMEOUT_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_NVMADDR_MSK
| #define ADF4382_NVMADDR_MSK NO_OS_GENMASK(6, 3) |
◆ ADF4382_NVMDIN_MSK
| #define ADF4382_NVMDIN_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_NVMDOUT_MSK
| #define ADF4382_NVMDOUT_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_NVMNO_OS_BIT_SEL
| #define ADF4382_NVMNO_OS_BIT_SEL NO_OS_GENMASK(2, 0) |
◆ ADF4382_NVMON_MSK
| #define ADF4382_NVMON_MSK NO_OS_BIT(2) |
◆ ADF4382_NVMPROG_MSK
| #define ADF4382_NVMPROG_MSK NO_OS_BIT(5) |
◆ ADF4382_NVMRD_MSK
| #define ADF4382_NVMRD_MSK NO_OS_BIT(4) |
◆ ADF4382_NVMSTART_MSK
| #define ADF4382_NVMSTART_MSK NO_OS_BIT(3) |
◆ ADF4382_NVMTEST_MSK
| #define ADF4382_NVMTEST_MSK NO_OS_BIT(6) |
◆ ADF4382_O_VCO_BAND_MSK
| #define ADF4382_O_VCO_BAND_MSK NO_OS_BIT(1) |
◆ ADF4382_O_VCO_BIAS_MSK
| #define ADF4382_O_VCO_BIAS_MSK NO_OS_BIT(2) |
◆ ADF4382_O_VCO_CORE_MSK
| #define ADF4382_O_VCO_CORE_MSK NO_OS_BIT(0) |
◆ ADF4382_O_VCO_DB_MSK
| #define ADF4382_O_VCO_DB_MSK NO_OS_BIT(7) |
◆ ADF4382_OUT_PWR_MAX
| #define ADF4382_OUT_PWR_MAX 15 |
◆ ADF4382_PD_ADC_MSK
| #define ADF4382_PD_ADC_MSK NO_OS_BIT(1) |
◆ ADF4382_PD_ALL_MSK
| #define ADF4382_PD_ALL_MSK NO_OS_BIT(7) |
◆ ADF4382_PD_CALGEN_MSK
| #define ADF4382_PD_CALGEN_MSK NO_OS_BIT(0) |
◆ ADF4382_PD_CLK_MSK
| #define ADF4382_PD_CLK_MSK NO_OS_BIT(3) |
◆ ADF4382_PD_CLKOUT1_MSK
| #define ADF4382_PD_CLKOUT1_MSK NO_OS_BIT(1) |
◆ ADF4382_PD_CLKOUT2_MSK
| #define ADF4382_PD_CLKOUT2_MSK NO_OS_BIT(0) |
◆ ADF4382_PD_LD_MSK
| #define ADF4382_PD_LD_MSK NO_OS_BIT(3) |
◆ ADF4382_PD_NDIV_MSK
| #define ADF4382_PD_NDIV_MSK NO_OS_BIT(5) |
◆ ADF4382_PD_NDIV_TL_MSK
| #define ADF4382_PD_NDIV_TL_MSK NO_OS_BIT(6) |
◆ ADF4382_PD_PFDCP_MSK
| #define ADF4382_PD_PFDCP_MSK NO_OS_BIT(2) |
◆ ADF4382_PD_RDET_MSK
| #define ADF4382_PD_RDET_MSK NO_OS_BIT(2) |
◆ ADF4382_PD_RDIV_TL_MSK
| #define ADF4382_PD_RDIV_TL_MSK NO_OS_BIT(6) |
◆ ADF4382_PD_SYNC_MON_MSK
| #define ADF4382_PD_SYNC_MON_MSK NO_OS_BIT(6) |
◆ ADF4382_PD_SYNC_MSK
| #define ADF4382_PD_SYNC_MSK NO_OS_BIT(4) |
◆ ADF4382_PD_VCO_MSK
| #define ADF4382_PD_VCO_MSK NO_OS_BIT(4) |
◆ ADF4382_PDET_POL_MSK
| #define ADF4382_PDET_POL_MSK NO_OS_BIT(3) |
◆ ADF4382_PFD_FREQ_FRAC_MAX
| #define ADF4382_PFD_FREQ_FRAC_MAX 250000000U |
◆ ADF4382_PFD_FREQ_MAX
| #define ADF4382_PFD_FREQ_MAX 625000000U |
◆ ADF4382_PFD_FREQ_MIN
| #define ADF4382_PFD_FREQ_MIN 5400000U |
◆ ADF4382_PFD_POL_MSK
| #define ADF4382_PFD_POL_MSK NO_OS_BIT(1) |
◆ ADF4382_PH_RESYNC_RB_SEL_MSK
| #define ADF4382_PH_RESYNC_RB_SEL_MSK NO_OS_BIT(7) |
◆ ADF4382_PHASE_ADJ_MSK
| #define ADF4382_PHASE_ADJ_MSK NO_OS_BIT(7) |
◆ ADF4382_PHASE_ADJ_POL_MSK
| #define ADF4382_PHASE_ADJ_POL_MSK NO_OS_BIT(3) |
◆ ADF4382_PHASE_ADJUST_MSK
| #define ADF4382_PHASE_ADJUST_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_PHASE_BLEED_CNST
| #define ADF4382_PHASE_BLEED_CNST 2044000 |
◆ ADF4382_PHASE_RESYNC_MOD2WORD_MAX
| #define ADF4382_PHASE_RESYNC_MOD2WORD_MAX 0x1FFFFU |
◆ ADF4382_PHASE_WORD_LSB_MSK
| #define ADF4382_PHASE_WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_PHASE_WORD_MID_MSK
| #define ADF4382_PHASE_WORD_MID_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_PHASE_WORD_MSB_MSK
| #define ADF4382_PHASE_WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_POR_DELAY_US
| #define ADF4382_POR_DELAY_US 200 |
◆ ADF4382_PRODUCT_ID_LSB
| #define ADF4382_PRODUCT_ID_LSB 0x0005 |
◆ ADF4382_PRODUCT_ID_MSB
| #define ADF4382_PRODUCT_ID_MSB 0x0005 |
◆ ADF4382_R_DIV_MSK
| #define ADF4382_R_DIV_MSK NO_OS_GENMASK(5, 0) |
◆ ADF4382_RB_MASTER_REG
| #define ADF4382_RB_MASTER_REG 0x1 |
◆ ADF4382_RB_SLAVE_REG
| #define ADF4382_RB_SLAVE_REG 0x0 |
◆ ADF4382_RDBLR_DC_MSK
| #define ADF4382_RDBLR_DC_MSK NO_OS_GENMASK(5, 0) |
◆ ADF4382_RDBLR_DEL_SEL_MSK
| #define ADF4382_RDBLR_DEL_SEL_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4382_READ_MODE_MSK
| #define ADF4382_READ_MODE_MSK NO_OS_BIT(4) |
◆ ADF4382_REF_CLK_MAX
| #define ADF4382_REF_CLK_MAX 5000000000U |
◆ ADF4382_REF_CLK_MIN
| #define ADF4382_REF_CLK_MIN 10000000 |
◆ ADF4382_REF_DIV_MAX
| #define ADF4382_REF_DIV_MAX 63 |
◆ ADF4382_REF_SEL_MSK
| #define ADF4382_REF_SEL_MSK NO_OS_BIT(5) |
◆ ADF4382_RESET_CMD
| #define ADF4382_RESET_CMD 0x81 |
◆ ADF4382_RESYNC_WAIT_LSB_MSK
| #define ADF4382_RESYNC_WAIT_LSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_RESYNC_WAIT_MSB_MSK
| #define ADF4382_RESYNC_WAIT_MSB_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_RFOUT_MAX
| #define ADF4382_RFOUT_MAX 22000000000U |
◆ ADF4382_RFOUT_MIN
| #define ADF4382_RFOUT_MIN 687500000U |
◆ ADF4382_RST_CNTR_MSK
| #define ADF4382_RST_CNTR_MSK NO_OS_BIT(0) |
◆ ADF4382_RST_LD_MSK
| #define ADF4382_RST_LD_MSK NO_OS_BIT(2) |
◆ ADF4382_RST_SYNC_MON_MSK
| #define ADF4382_RST_SYNC_MON_MSK NO_OS_BIT(4) |
◆ ADF4382_RST_SYS_MSK
| #define ADF4382_RST_SYS_MSK NO_OS_BIT(4) |
◆ ADF4382_SCAN_MODE_CODE_MSK
| #define ADF4382_SCAN_MODE_CODE_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_SCRATCHPAD_MSK
| #define ADF4382_SCRATCHPAD_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_SDO_ACTIVE_MSK
| #define ADF4382_SDO_ACTIVE_MSK NO_OS_BIT(3) |
◆ ADF4382_SDO_ACTIVE_R_MSK
| #define ADF4382_SDO_ACTIVE_R_MSK NO_OS_BIT(4) |
◆ ADF4382_SDO_ACTIVE_SPI_3W
| #define ADF4382_SDO_ACTIVE_SPI_3W 0x0 |
◆ ADF4382_SDO_ACTIVE_SPI_4W
| #define ADF4382_SDO_ACTIVE_SPI_4W 0x1 |
◆ ADF4382_SINGLE_INSTR_MSK
| #define ADF4382_SINGLE_INSTR_MSK NO_OS_BIT(7) |
◆ ADF4382_SOFT_RESET_EN
| #define ADF4382_SOFT_RESET_EN 0x1 |
◆ ADF4382_SOFT_RESET_MSK
| #define ADF4382_SOFT_RESET_MSK NO_OS_BIT(0) |
◆ ADF4382_SOFT_RESET_N_OP
| #define ADF4382_SOFT_RESET_N_OP 0x0 |
◆ ADF4382_SOFT_RESET_R_MSK
| #define ADF4382_SOFT_RESET_R_MSK NO_OS_BIT(7) |
◆ ADF4382_SPARE0_MSK
| #define ADF4382_SPARE0_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_SPARE1_MSK
| #define ADF4382_SPARE1_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_SPARE_1F_MSK
| #define ADF4382_SPARE_1F_MSK NO_OS_BIT(6) |
◆ ADF4382_SPARE_24_MSK
| #define ADF4382_SPARE_24_MSK NO_OS_GENMASK(7, 5) |
◆ ADF4382_SPARE_32_MSK
| #define ADF4382_SPARE_32_MSK NO_OS_BIT(7) |
◆ ADF4382_SPARE_35_MSK
| #define ADF4382_SPARE_35_MSK NO_OS_GENMASK(7, 6) |
◆ ADF4382_SPARE_36_MSK
| #define ADF4382_SPARE_36_MSK NO_OS_GENMASK(5, 2) |
◆ ADF4382_SPARE_3D_MSK
| #define ADF4382_SPARE_3D_MSK NO_OS_BIT(7) |
◆ ADF4382_SPARE_3F_MSK
| #define ADF4382_SPARE_3F_MSK NO_OS_BIT(0) |
◆ ADF4382_SPARE_45_MSK
| #define ADF4382_SPARE_45_MSK NO_OS_BIT(7) |
◆ ADF4382_SPARE_47_MSK
| #define ADF4382_SPARE_47_MSK NO_OS_BIT(7) |
◆ ADF4382_SPARE_4C_MSK
| #define ADF4382_SPARE_4C_MSK NO_OS_GENMASK(7, 6) |
◆ ADF4382_SPARE_4D_MSK
| #define ADF4382_SPARE_4D_MSK NO_OS_GENMASK(4, 3) |
◆ ADF4382_SPARE_4E_MSK
| #define ADF4382_SPARE_4E_MSK NO_OS_GENMASK(7, 5) |
◆ ADF4382_SPARE_53_MSK
| #define ADF4382_SPARE_53_MSK NO_OS_BIT(7) |
◆ ADF4382_SPI_3W_CFG
| #define ADF4382_SPI_3W_CFG | ( | x | ) |
Value:
(no_os_field_prep(ADF4382_SDO_ACTIVE_MSK, x) | \
no_os_field_prep(ADF4382_SDO_ACTIVE_R_MSK, x))
◆ ADF4382_SPI_DUMMY_DATA
| #define ADF4382_SPI_DUMMY_DATA 0x00 |
◆ ADF4382_SPI_READ_CMD
| #define ADF4382_SPI_READ_CMD 0x8000 |
◆ ADF4382_SPI_SCRATCHPAD_TEST
| #define ADF4382_SPI_SCRATCHPAD_TEST 0x5A |
◆ ADF4382_SPI_STREAM_DIS
| #define ADF4382_SPI_STREAM_DIS 0x1 |
◆ ADF4382_SPI_STREAM_EN
| #define ADF4382_SPI_STREAM_EN 0x0 |
◆ ADF4382_SPI_WRITE_CMD
| #define ADF4382_SPI_WRITE_CMD 0x0 |
◆ ADF4382_SW_SYNC_MSK
| #define ADF4382_SW_SYNC_MSK NO_OS_BIT(7) |
◆ ADF4382_SYNC_DEL_MSK
| #define ADF4382_SYNC_DEL_MSK NO_OS_GENMASK(7, 5) |
◆ ADF4382_SYNC_MON_DEL_MSK
| #define ADF4382_SYNC_MON_DEL_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4382_SYNC_REF_SPARE_MSK
| #define ADF4382_SYNC_REF_SPARE_MSK NO_OS_GENMASK(7, 4) |
◆ ADF4382_SYNC_SEL_MSK
| #define ADF4382_SYNC_SEL_MSK NO_OS_BIT(5) |
◆ ADF4382_SYNC_SH_DEL_MSK
| #define ADF4382_SYNC_SH_DEL_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4382_SYNC_SP_DB_MSK
| #define ADF4382_SYNC_SP_DB_MSK NO_OS_BIT(6) |
◆ ADF4382_TEMP_OFFSET_MSK
| #define ADF4382_TEMP_OFFSET_MSK NO_OS_GENMASK(7, 0) |
◆ ADF4382_TEMP_SLOPE_MSK
| #define ADF4382_TEMP_SLOPE_MSK NO_OS_GENMASK(5, 0) |
◆ ADF4382_TIMED_SYNC_MSK
| #define ADF4382_TIMED_SYNC_MSK NO_OS_BIT(5) |
◆ ADF4382_TRANS_LOOP_SEL_MSK
| #define ADF4382_TRANS_LOOP_SEL_MSK NO_OS_BIT(0) |
◆ ADF4382_TRIM_LATCH_MSK
| #define ADF4382_TRIM_LATCH_MSK NO_OS_BIT(7) |
◆ ADF4382_TWO_PASS_BAND_START_MSK
| #define ADF4382_TWO_PASS_BAND_START_MSK NO_OS_GENMASK(3, 0) |
◆ ADF4382_VAR_MOD_EN_MSK
| #define ADF4382_VAR_MOD_EN_MSK NO_OS_BIT(5) |
◆ ADF4382_VCAL_ZERO_MSK
| #define ADF4382_VCAL_ZERO_MSK NO_OS_BIT(7) |
◆ ADF4382_VCO_CAL_ALC
| #define ADF4382_VCO_CAL_ALC 250 |
◆ ADF4382_VCO_CAL_CNT
| #define ADF4382_VCO_CAL_CNT 202 |
◆ ADF4382_VCO_CAL_VTUNE
| #define ADF4382_VCO_CAL_VTUNE 124 |
◆ ADF4382_VCO_FREQ_MAX
| #define ADF4382_VCO_FREQ_MAX 22000000000U |
◆ ADF4382_VCO_FREQ_MIN
| #define ADF4382_VCO_FREQ_MIN 11000000000U |
◆ ADF4382_VCO_FSM_TEST_MUX_MSK
| #define ADF4382_VCO_FSM_TEST_MUX_MSK NO_OS_GENMASK(7, 5) |
◆ ADF4382_VCTAT_CALGEN_MSK
| #define ADF4382_VCTAT_CALGEN_MSK NO_OS_GENMASK(6, 0) |
◆ ADF4382_VENDOR_ID_LSB
| #define ADF4382_VENDOR_ID_LSB 0x56 |
◆ ADF4382_VENDOR_ID_MSB
| #define ADF4382_VENDOR_ID_MSB 0x04 |
◆ ADF4382_VPTAT_CALGEN_MSK
| #define ADF4382_VPTAT_CALGEN_MSK NO_OS_GENMASK(6, 0) |
◆ ADF4382A_CLKOUT_DIV_REG_VAL_MAX
| #define ADF4382A_CLKOUT_DIV_REG_VAL_MAX 2 |
◆ ADF4382A_RFOUT_MAX
| #define ADF4382A_RFOUT_MAX 21000000000U |
◆ ADF4382A_RFOUT_MIN
| #define ADF4382A_RFOUT_MIN 2875000000U |
◆ ADF4382A_VCO_FREQ_MAX
| #define ADF4382A_VCO_FREQ_MAX 21000000000U |
◆ ADF4382A_VCO_FREQ_MIN
| #define ADF4382A_VCO_FREQ_MIN 11500000000U |
◆ MHZ
| #define MHZ MEGA |
◆ NS_TO_PS
| #define NS_TO_PS KHZ_PER_MHZ |
◆ S_TO_NS
| #define S_TO_NS NANO |
Enumeration Type Documentation
◆ adf4382_dev_id
| enum adf4382_dev_id |
Function Documentation
◆ adf4382_get_bleed_word()
| int adf4382_get_bleed_word | ( | struct adf4382_dev * | dev, |
| int32_t * | word | ||
| ) |
Gets the value of the set bleed word.
ADF4382 Get bleed current attribute
- Parameters
-
dev - The device structure. word - The read bleed current register value.
- Returns
- - Result of the reading procedure, error code otherwise.
◆ adf4382_get_cp_i()
| int adf4382_get_cp_i | ( | struct adf4382_dev * | dev, |
| int32_t * | reg_val | ||
| ) |
Gets the charge pump value from the register. The value will be between 0 and 15 on 8 bits. For more information please consult the Datasheet.
ADF4382 Get charge pump current attribute
- Parameters
-
dev - The device structure. reg_val - The read charge pump register value.
- Returns
- - 0 in case of success or negative error code.
◆ adf4382_get_en_chan()
| int adf4382_get_en_chan | ( | struct adf4382_dev * | dev, |
| uint8_t | ch, | ||
| bool * | en | ||
| ) |
Gets the value the output channel if it is enabled or disable.
ADF4382 Get channel enable attributes
- Parameters
-
dev - The device structure. ch - The channel to get state. en - The status of the output channel.
- Returns
- - 0 in case of success or negative error code.
◆ adf4382_get_en_ref_doubler()
| int adf4382_get_en_ref_doubler | ( | struct adf4382_dev * | dev, |
| bool * | en | ||
| ) |
Gets the value the doubler if it is enabled or disable and stores it it the dev structure.
ADF4382 Get reference doubler attribute
- Parameters
-
dev - The device structure. en - The read value of the reference doubler.
- Returns
- - 0 in case of success or negative error code.
◆ adf4382_get_en_sync()
| int adf4382_get_en_sync | ( | struct adf4382_dev * | dev, |
| bool * | en | ||
| ) |
Gets the value the sync if it is enabled or disable.
ADF4382 Get sync enable attributes
- Parameters
-
dev - The device structure. en - The read status of the sync enable.
- Returns
- - 0 in case of success or negative error code.
◆ adf4382_get_out_power()
| int adf4382_get_out_power | ( | struct adf4382_dev * | dev, |
| uint8_t | ch, | ||
| int32_t * | pwr | ||
| ) |
Gets the output power register value.
ADF4382 Get output power attributes
- Parameters
-
dev - The device structure. ch - The channel to get the power off. pwr - The output power register value.
- Returns
- - Result of the reading procedure, error code otherwise.
◆ adf4382_get_phase_pol()
| int adf4382_get_phase_pol | ( | struct adf4382_dev * | dev, |
| bool * | polarity | ||
| ) |
Gets the polarity of the phase adjust.
ADF4382 Gets Phase adjustment polarity
uint8_t pol;
- Parameters
-
dev - The device structure. polarity - The read polarity of the phase.
- Returns
- - Result of the tesint procedure, negative error code otherwise.
◆ adf4382_get_ref_clk()
| int adf4382_get_ref_clk | ( | struct adf4382_dev * | dev, |
| uint64_t * | val | ||
| ) |
Gets the user proposed reference frequency.
ADF4382 Get reference frequency attribute
- Parameters
-
dev - The device structure. val - The set value of the reference frequency in Hz.
- Returns
- - Reference frequency in KHz.
◆ adf4382_get_ref_div()
| int adf4382_get_ref_div | ( | struct adf4382_dev * | dev, |
| int32_t * | div | ||
| ) |
Gets the value the reference divider.
ADF4382 Get reference divider attribute
- Parameters
-
dev - The device structure. div - The read reference divider value.
- Returns
- - Result of the reading procedure, error code otherwise.
◆ adf4382_get_rfout()
| int adf4382_get_rfout | ( | struct adf4382_dev * | dev, |
| uint64_t * | val | ||
| ) |
Gets the user proposed output frequency.
ADF4382 Get output frequency attribute
- Parameters
-
dev - The device structure. val - The set value of the output frequency in Hz.
- Returns
- - 0 in case of success or negative error code.
◆ adf4382_init()
| int adf4382_init | ( | struct adf4382_dev ** | dev, |
| struct adf4382_init_param * | init_param | ||
| ) |
Initializes the ADF4382.
ADF4382 Initialization
- Parameters
-
dev - The device structure. init_param - The structure containing the device initial parameters.
- Returns
- - 0 in case of success or negative error code.
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◆ adf4382_reg_dump()
| int adf4382_reg_dump | ( | struct adf4382_dev * | dev | ) |
Will output on the terminal the values of all the ADF4382 registers.
ADF4382 Register dump
- Parameters
-
dev - The device structure.
- Returns
- - 0 in case of success or negative error code.
◆ adf4382_remove()
| int adf4382_remove | ( | struct adf4382_dev * | dev | ) |
Free resources allocated for ADF4382.
ADF4382 Remove
- Parameters
-
dev - The device structure.
- Returns
- - 0 in case of success or negative error code.
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◆ adf4382_set_bleed_word()
| int adf4382_set_bleed_word | ( | struct adf4382_dev * | dev, |
| int32_t | word | ||
| ) |
Set the bleed word, which represents the value of the bleed current written to the register space.
ADF4382 Set bleed current attribute
- Parameters
-
dev - The device structure. word - The bleed current register value.
- Returns
- - 0 in case of success or negative error code.
◆ adf4382_set_cp_i()
| int adf4382_set_cp_i | ( | struct adf4382_dev * | dev, |
| int32_t | reg_val | ||
| ) |
Set the charge pump value which will be written to the register. The value will be between 0 and 15 on 8 bits. For more information please consult the Datasheet.
ADF4382 Set charge pump current attribute
- Parameters
-
dev - The device structure. reg_val - The desired charge pump register value.
- Returns
- - 0 in case of success or negative error code.
◆ adf4382_set_en_chan()
| int adf4382_set_en_chan | ( | struct adf4382_dev * | dev, |
| uint8_t | ch, | ||
| bool | en | ||
| ) |
Set the output channel to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable.
ADF4382 Set channel enable attributes
- Parameters
-
dev - The device structure. ch - The channel to set state. en - The enable or disable value of the output channel.
- Returns
- - Result of the writing procedure, error code otherwise.
◆ adf4382_set_en_ref_doubler()
| int adf4382_set_en_ref_doubler | ( | struct adf4382_dev * | dev, |
| bool | en | ||
| ) |
Set the reference doubler to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable.
ADF4382 Set reference doubler attribute
- Parameters
-
dev - The device structure. en - The enable or disable value of the reference doubler.
- Returns
- - 0 in case of success or negative error code.
◆ adf4382_set_en_sync()
| int adf4382_set_en_sync | ( | struct adf4382_dev * | dev, |
| bool | en | ||
| ) |
Set the sync to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable.
ADF4382 Set sync enable attributes
- Parameters
-
dev - The device structure. en - The enable or disable sync.
- Returns
- - Result of the writing procedure, error code otherwise.
◆ adf4382_set_freq()
| int adf4382_set_freq | ( | struct adf4382_dev * | dev | ) |
Set the output frequency.
ADF4382 Sets frequency
- Parameters
-
dev - The device structure.
- Returns
- - 0 in case of success, negative error code otherwise.
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◆ adf4382_set_out_power()
| int adf4382_set_out_power | ( | struct adf4382_dev * | dev, |
| uint8_t | ch, | ||
| int32_t | pwr | ||
| ) |
Set the output power register value of a channel and reset everything over to maximum supported value of 15 to the max. value.
ADF4382 Set output power attributes
- Parameters
-
dev - The device structure. ch - The channel to set the power off. pwr - The output power register value.
- Returns
- - Result of the writing procedure, error code otherwise.
◆ adf4382_set_phase_adjust()
| int adf4382_set_phase_adjust | ( | struct adf4382_dev * | dev, |
| uint32_t | phase_ps | ||
| ) |
Set the phase adjustment in pico-seconds. The phase adjust will enable the Bleed current option as well as delay mode to 0.
ADF4382 Sets Phase adjustment
- Parameters
-
dev - The device structure. phase_ps - The phase adjustment in pico-seconds.
- Returns
- - 0 in case of success, negative error code otherwise.
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◆ adf4382_set_phase_pol()
| int adf4382_set_phase_pol | ( | struct adf4382_dev * | dev, |
| bool | polarity | ||
| ) |
Set the phase polarity. If pol = 0 then it will add the phase value otherwise it will subtract the phase value.
ADF4382 Sets Phase adjustment polarity
- Parameters
-
dev - The device structure. polarity - The polarity to be set.
- Returns
- - Result of the writing procedure, error code otherwise.
◆ adf4382_set_ref_clk()
| int adf4382_set_ref_clk | ( | struct adf4382_dev * | dev, |
| uint64_t | val | ||
| ) |
Set the desired reference frequency and reset everything over to maximum supported value of 5GHz to the max. value and everything under the minimum supported value of 10MHz to the min. value.
ADF4382 Set reference frequency attribute
- Parameters
-
dev - The device structure. val - The desired reference frequency in Hz.
- Returns
- - 0 in case of success or negative error code.
◆ adf4382_set_ref_div()
| int adf4382_set_ref_div | ( | struct adf4382_dev * | dev, |
| int32_t | div | ||
| ) |
Set the reference divider value and reset everything over to maximum supported value of 63 to the max. value.
ADF4382 Set reference divider attribute
- Parameters
-
dev - The device structure. div - The reference divider value.
- Returns
- - 0 in case of success or negative error code.
◆ adf4382_set_rfout()
| int adf4382_set_rfout | ( | struct adf4382_dev * | dev, |
| uint64_t | val | ||
| ) |
Set the desired output frequency and reset everything over to maximum supported value of 22GHz (21GHz for ADF4382A) to the max. value and everything under the minimum supported value of 687.5MHz (2.875GHz for ADF4382A) to the min. value.
ADF4382 Set output frequency attribute
- Parameters
-
dev - The device structure. val - The desired output frequency in Hz.
- Returns
- - 0 in case of success or negative error code.
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◆ adf4382_spi_read()
| int adf4382_spi_read | ( | struct adf4382_dev * | dev, |
| uint16_t | reg_addr, | ||
| uint8_t * | data | ||
| ) |
Reads data from ADF4382 over SPI.
ADF4382 SPI Read
- Parameters
-
dev - The device structure. reg_addr - The register address. data - Data read from the device.
- Returns
- - 0 in case of success or negative error code otherwise.
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◆ adf4382_spi_update_bits()
| int adf4382_spi_update_bits | ( | struct adf4382_dev * | dev, |
| uint16_t | reg_addr, | ||
| uint8_t | mask, | ||
| uint8_t | data | ||
| ) |
Updates the values of the ADF4382 register.
ADF4382 updates a bit in the register space over SPI
- Parameters
-
dev - The device structure. reg_addr - The register address. mask - Bits to be updated. data - Update value for the mask.
- Returns
- - 0 in case of success or negative error code otherwise.
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◆ adf4382_spi_write()
| int adf4382_spi_write | ( | struct adf4382_dev * | dev, |
| uint16_t | reg_addr, | ||
| uint8_t | data | ||
| ) |
Writes data to ADF4382 over SPI.
ADF4382 SPI write
- Parameters
-
dev - The device structure. reg_addr - The register address. data - Data value to write.
- Returns
- - 0 in case of success or negative error code otherwise.
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