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39 #ifndef __APP_TRANSCEIVER_H
40 #define __APP_TRANSCEIVER_H
46 uint32_t tx_lane_rate_khz,
47 uint32_t rx_os_lane_rate_khz,
48 uint32_t device_clock);
int adxcvr_clk_enable(struct adxcvr *xcvr)
AXI ADXCVR Clock Enable.
Definition: axi_adxcvr.c:485
#define ADXCVR_REFCLK
Definition: axi_adxcvr.h:61
const char * name
Definition: altera_adxcvr.h:96
struct adxcvr * tx_adxcvr
Definition: app_jesd.c:59
ADI JESD204B/C AXI_ADXCVR Highspeed Transceiver Device structure.
Definition: altera_adxcvr.h:95
JESD setup and initialization routines.
Contains Talise ADI HAL function prototypes type definitions for adi_hal.c.
adiHalErr_t fpga_xcvr_init(uint32_t rx_lane_rate_khz, uint32_t tx_lane_rate_khz, uint32_t rx_os_lane_rate_khz, uint32_t device_clock)
Definition: app_transceiver.c:68
#define RX_OS_XCVR_BASEADDR
Definition: parameters.h:136
Driver for the ADI AXI-ADXCVR Module.
#define TX_XCVR_BASEADDR
Definition: parameters.h:64
Driver for the Altera ADXCVR Configuration.
Definition: altera_adxcvr.h:108
const char * name
Definition: altera_adxcvr.h:109
@ ADIHAL_OK
Definition: adi_hal.h:43
void fpga_xcvr_deinit(void)
Definition: app_transceiver.c:193
struct adxcvr * rx_adxcvr
Definition: app_jesd.c:58
#define RX_XCVR_BASEADDR
Definition: parameters.h:72
#define ADXCVR_SYS_CLK_CPLL
Definition: axi_adxcvr.h:54
void fpga_xcvr_deinit(void)
Definition: app_transceiver.c:193
#define ADXCVR_SYS_CLK_QPLL0
Definition: axi_adxcvr.h:56
int32_t adxcvr_remove(struct adxcvr *xcvr)
adxcvr_remove
Definition: altera_adxcvr.c:495
@ ADIHAL_ERR
Definition: adi_hal.h:50
Header file of utility functions.
adiHalErr_t fpga_xcvr_init(uint32_t rx_lane_rate_khz, uint32_t tx_lane_rate_khz, uint32_t rx_os_lane_rate_khz, uint32_t device_clock)
Definition: app_transceiver.c:68
int32_t adxcvr_init(struct adxcvr **ad_xcvr, const struct adxcvr_init *init)
adxcvr_init
Definition: altera_adxcvr.c:444
adiHalErr_t
Enum of possible Errors Detected by HAL layer to be communicated to ADI APIs.
Definition: adi_hal.h:42
