common.h

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#ifndef _COMMON_H_
#define _COMMON_H_
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* build project settings include the path to the desired platform folder for correct includes */
#include "stdint.h"
 
#define THROW_ERROR()
 
#define SPIARRAYSIZE 1024
 
/* assuming 3 byte SPI message - integer math enforces floor() */
#define SPIARRAYTRIPSIZE ((SPIARRAYSIZE / 3) * 3)
 
/*========================================
 * Enums and structures
 *=======================================*/
/* proposed to increase number of error return values to make unique for each return */
typedef enum {
    ADIERR_OK = 0,
    ADIERR_INV_PARM,
    ADIERR_FAILED
} ADI_ERR;
typedef enum {…};

typedef enum {
    COMMONERR_OK = 0,
    COMMONERR_FAILED
} commonErr_t;
typedef enum {…};
 
/* bit 0 is MESSAGE, bit 1 is WARNING, bit 2 is ERROR */
typedef enum {
    ADIHAL_LOG_NONE  = 0x0,
    ADIHAL_LOG_MESSAGE = 0x1,
    ADIHAL_LOG_WARNING = 0x2,
    ADIHAL_LOG_ERROR   = 0x4,
    ADIHAL_LOG_SPI     = 0x8,
    ADIHAL_LOG_AXI_REG = 0x10,
    ADIHAL_LOG_AXI_MEM = 0x20,
    ADIHAL_LOG_ALL     = 0x3F
} ADI_LOGLEVEL;
typedef enum {…};

typedef struct {
    uint8_t chipSelectIndex;     
    uint8_t writeBitPolarity;       
    uint8_t longInstructionWord; 
    uint8_t MSBFirst;               
    uint8_t CPHA;                   
    uint8_t CPOL;                   
    uint8_t enSpiStreaming;           
    uint8_t autoIncAddrUp;         
    uint8_t fourWireMode;           
    uint32_t spiClkFreq_Hz;            
} spiSettings_t;
typedef struct  {…};
 
/* global variable so application layer can set the log level */
extern ADI_LOGLEVEL CMB_LOGLEVEL;
 
/* close hardware pointers */
commonErr_t CMB_closeHardware(void);
 
/* GPIO function */
commonErr_t CMB_setGPIO(uint32_t GPIO);
 
/* hardware reset function */
commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex);
 
/* SPI read/write functions */
commonErr_t CMB_setSPIOptions(spiSettings_t
                  *spiSettings); /* allows the platform HAL to work with devices with various SPI settings */
commonErr_t CMB_setSPIChannel(uint16_t
                  chipSelectIndex);   /* value of 0 deasserts all chip selects */
commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr,
                 uint8_t data); /* single SPI byte write function */
commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr,
                  uint8_t *data, uint32_t count);
commonErr_t CMB_SPIReadByte(spiSettings_t *spiSettings, uint16_t addr,
                uint8_t *readdata); /* single SPI byte read function */
commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr,
                  uint8_t  field_val, uint8_t mask,
                  uint8_t start_bit); /* write a field in a single register */
commonErr_t CMB_SPIReadField(spiSettings_t *spiSettings, uint16_t addr,
                 uint8_t *field_val, uint8_t mask,
                 uint8_t start_bit);    /* read a field in a single register */
 
/* platform timer functions */
commonErr_t CMB_wait_ms(uint32_t time_ms);
commonErr_t CMB_wait_us(uint32_t time_us);
commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms);
commonErr_t CMB_setTimeout_us(uint32_t timeOut_us);
commonErr_t CMB_hasTimeoutExpired();
 
/* platform logging functions */
commonErr_t CMB_openLog(const char *filename);
commonErr_t CMB_closeLog(void);
commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex,
               uint32_t errorCode, const char *comment);
commonErr_t CMB_flushLog(void);
 
/* platform FPGA AXI register read/write functions */
commonErr_t CMB_regRead(uint32_t offset, uint32_t *data);
commonErr_t CMB_regWrite(uint32_t offset, uint32_t data);
 
/* platform DDR3 memory read/write functions */
commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len);
commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len);
 
int32_t platform_init(void);
int32_t platform_remove(void);
 
#ifdef __cplusplus
}
#endif
#endif