34#ifndef SPI_ENGINE_PRIVATE_H
35#define SPI_ENGINE_PRIVATE_H
43#define SPI_ENGINE_REG_VERSION 0x00
44#define SPI_ENGINE_REG_DATA_WIDTH 0x0C
45#define SPI_ENGINE_REG_RESET 0x40
46#define SPI_ENGINE_REG_INT_ENABLE 0x80
47#define SPI_ENGINE_REG_INT_PENDING 0x84
48#define SPI_ENGINE_REG_INT_SOURCE 0x88
49#define SPI_ENGINE_REG_SYNC_ID 0xC0
50#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xD0
51#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xD4
52#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xD8
53#define SPI_ENGINE_REG_CMD_FIFO 0xE0
54#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xE4
55#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xE8
56#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xEC
59#define SPI_ENGINE_REG_NUM_OF_SDI_MSK NO_OS_GENMASK(23, 16)
60#define SPI_ENGINE_REG_DATA_WIDTH_MSK NO_OS_GENMASK(15, 0)
62#define SPI_ENGINE_INST_TRANSFER 0x00
63#define SPI_ENGINE_INST_ASSERT 0x01
64#define SPI_ENGINE_INST_CONFIG 0x02
65#define SPI_ENGINE_INST_SYNC_SLEEP 0x03
66#define SPI_ENGINE_INST_MISC 0x03
67#define SPI_ENGINE_CMD_REG_CLK_DIV 0x00
68#define SPI_ENGINE_CMD_REG_CONFIG 0x01
69#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN 0x02
70#define SPI_ENGINE_MISC_SYNC 0x00
71#define SPI_ENGINE_MISC_SLEEP 0x01
72#define SPI_ENGINE_SYNC_TRANSFER_BEGIN NO_OS_BIT(1)
73#define SPI_ENGINE_SYNC_TRANSFER_END NO_OS_BIT(2)
74#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY NO_OS_BIT(0)
75#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY NO_OS_BIT(1)
76#define SPI_ENGINE_INT_SDI_ALMOST_FULL NO_OS_BIT(2)
77#define SPI_ENGINE_INT_SYNC NO_OS_BIT(3)
78#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE NO_OS_BIT(0)
79#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED NO_OS_BIT(0)
80#define SPI_ENGINE_CONFIG_CPHA NO_OS_BIT(0)
81#define SPI_ENGINE_CONFIG_CPOL NO_OS_BIT(1)
82#define SPI_ENGINE_CONFIG_3WIRE NO_OS_BIT(2)
83#define SPI_ENGINE_CONFIG_SDO_IDLE NO_OS_BIT(3)
84#define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff)
85#define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff)
86#define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff)
88#define SPI_ENGINE_INSTRUCTION_TRANSFER_W 0x01
89#define SPI_ENGINE_INSTRUCTION_TRANSFER_R 0x02
90#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW 0x03
92#define SPI_ENGINE_REG_OFFLOAD_CTRL(x) (0x100 + (0x20 * x))
93#define SPI_ENGINE_REG_OFFLOAD_STATUS(x) (0x104 + (0x20 * x))
94#define SPI_ENGINE_REG_OFFLOAD_RESET(x) (0x108 + (0x20 * x))
95#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x) (0x110 + (0x20 * x))
96#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM(x) (0x114 + (0x20 * x))
98#define SPI_ENGINE_CMD(inst, arg1, arg2) \
99 (((inst & 0x03) << 12) | \
100 ((arg1 & 0x03) << 8) | arg2 )
98#define SPI_ENGINE_CMD(inst, arg1, arg2) \ …
102#define SPI_ENGINE_CMD_TRANSFER(readwrite, n) \
103 SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, \
102#define SPI_ENGINE_CMD_TRANSFER(readwrite, n) \ …
106#define SPI_ENGINE_CMD_ASSERT(delay, cs) \
107 SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, \
106#define SPI_ENGINE_CMD_ASSERT(delay, cs) \ …
110#define SPI_ENGINE_CMD_CONFIG(reg, val) \
111 SPI_ENGINE_CMD(SPI_ENGINE_INST_CONFIG, \
110#define SPI_ENGINE_CMD_CONFIG(reg, val) \ …
114#define SPI_ENGINE_CMD_SLEEP(delay) \
115 SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \
116 SPI_ENGINE_MISC_SLEEP, \
114#define SPI_ENGINE_CMD_SLEEP(delay) \ …
119#define SPI_ENGINE_CMD_SYNC(id) \
120 SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \
121 SPI_ENGINE_MISC_SYNC, \
119#define SPI_ENGINE_CMD_SYNC(id) \ …
Header file of SPI Interface.
Header file of utility functions.
Definition spi_engine_private.h:124
uint32_t cmd
Definition spi_engine_private.h:125
struct spi_engine_cmd_queue * next
Definition spi_engine_private.h:126
Definition spi_engine_private.h:129
uint32_t * rx_buf
Definition spi_engine_private.h:131
uint32_t * tx_buf
Definition spi_engine_private.h:130
struct spi_engine_cmd_queue * cmds
Definition spi_engine_private.h:133
uint32_t length
Definition spi_engine_private.h:132