no-OS
ad9528.h
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1 /***************************************************************************/
39 #ifndef _AD9528_H_
40 #define _AD9528_H_
41 
42 /******************************************************************************/
43 /***************************** Include Files **********************************/
44 /******************************************************************************/
45 #include <stdint.h>
46 #include <stdbool.h>
47 #include "no_os_delay.h"
48 #include "no_os_spi.h"
49 #include "no_os_gpio.h"
50 
51 /******************************************************************************/
52 /****************************** AD9528 ****************************************/
53 /******************************************************************************/
54 /* Registers */
55 
56 #define AD9528_READ (1 << 15)
57 #define AD9528_WRITE (0 << 15)
58 #define AD9528_CNT(x) (((x) - 1) << 13)
59 #define AD9528_ADDR(x) ((x) & 0xFFF)
60 
61 #define AD9528_1B(x) ((1 << 16) | ((x) + 0))
62 #define AD9528_2B(x) ((2 << 16) | ((x) + 1))
63 #define AD9528_3B(x) ((3 << 16) | ((x) + 2))
64 #define AD9528_4B(x) ((4 << 16) | ((x) + 3))
65 #define AD9528_TRANSF_LEN(x) ((x) >> 16)
66 
67 #define AD9528_SERIAL_PORT_CONFIG AD9528_1B(0x0)
68 #define AD9528_SERIAL_PORT_CONFIG_B AD9528_1B(0x1)
69 #define AD9528_CHIP_ID AD9528_4B(0x3)
70 #define AD9528_IO_UPDATE AD9528_1B(0xF)
71 
72 #define AD9528_PLL1_REF_A_DIVIDER AD9528_2B(0x100)
73 #define AD9528_PLL1_REF_B_DIVIDER AD9528_2B(0x102)
74 #define AD9528_PLL1_FEEDBACK_DIVIDER AD9528_2B(0x104)
75 #define AD9528_PLL1_CHARGE_PUMP_CTRL AD9528_2B(0x106)
76 #define AD9528_PLL1_CTRL AD9528_3B(0x108)
77 
78 #define AD9528_PLL2_CHARGE_PUMP AD9528_1B(0x200)
79 #define AD9528_PLL2_FEEDBACK_DIVIDER_AB AD9528_1B(0x201)
80 #define AD9528_PLL2_CTRL AD9528_1B(0x202)
81 #define AD9528_PLL2_VCO_CTRL AD9528_1B(0x203)
82 #define AD9528_PLL2_VCO_DIVIDER AD9528_1B(0x204)
83 #define AD9528_PLL2_LOOP_FILTER_CTRL AD9528_2B(0x205)
84 #define AD9528_PLL2_R1_DIVIDER AD9528_1B(0x207)
85 #define AD9528_PLL2_N2_DIVIDER AD9528_1B(0x208)
86 
87 #define AD9528_CHANNEL_OUTPUT(ch) AD9528_3B(0x300 + 3 * ch)
88 #define AD9528_CHANNEL_SYNC AD9528_1B(0x32A)
89 #define AD9528_CHANNEL_SYNC_IGNORE AD9528_2B(0x32B)
90 
91 #define AD9528_SYSREF_RESAMPLE_CTRL AD9528_2B(0x32D)
92 
93 #define AD9528_SYSREF_K_DIVIDER AD9528_2B(0x400)
94 #define AD9528_SYSREF_CTRL AD9528_2B(0x402)
95 
96 #define AD9528_PD_EN AD9528_1B(0x500)
97 #define AD9528_CHANNEL_PD_EN AD9528_2B(0x501)
98 
99 #define AD9528_STAT_MON0 AD9528_1B(0x505)
100 #define AD9528_STAT_MON1 AD9528_1B(0x506)
101 #define AD9528_STAT_PIN_EN AD9528_1B(0x507)
102 #define AD9528_READBACK AD9528_2B(0x508)
103 
104 /* AD9528_SERIAL_PORT_CONFIG */
105 #define AD9528_SER_CONF_SOFT_RESET ((1 << 0) | (1 << 7))
106 #define AD9528_SER_CONF_LSB_FIRST ((1 << 1) | (1 << 6))
107 #define AD9528_SER_CONF_ADDR_INCREMENT ((1 << 2) | (1 << 5))
108 #define AD9528_SER_CONF_SDO_ACTIVE ((1 << 3) | (1 << 4))
109 
110 /* AD9528_SERIAL_PORT_CONFIG_B */
111 #define AD9528_SER_CONF_READ_BUFFERED (1 << 5)
112 #define AD9528_SER_CONF_RESET_SANS_REGMAP (1 << 2)
113 
114 /* AD9528_IO_UPDATE */
115 #define AD9528_IO_UPDATE_EN (1 << 0)
116 
117 /* AD9528_PLL1_CHARGE_PUMP_CTRL */
118 #define AD9528_PLL1_CHARGE_PUMP_AUTO_TRISTATE_DIS (1 << 12)
119 #define AD9528_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)
120 #define AD9528_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8)
121 #define AD9528_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8)
122 #define AD9528_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8)
123 #define AD9528_PLL1_CHARGE_PUMP_TRISTATE (1 << 7)
124 #define AD9528_PLL1_CHARGE_PUMP_CURRENT_nA(x) (((x) / 500) & 0x7F)
125 
126 /* AD9528_PLL1_CTRL */
127 #define AD9528_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 18)
128 #define AD9528_PLL1_REF_MODE(x) ((x) << 16)
129 #define AD9528_PLL1_FEEDBACK_BYPASS_EN (1 << 13)
130 #define AD9528_PLL1_REFB_BYPASS_EN (1 << 12)
131 #define AD9528_PLL1_REFA_BYPASS_EN (1 << 11)
132 #define AD9528_PLL1_SOURCE_VCXO (1 << 10)
133 #define AD9528_PLL1_REFB_CMOS_NEG_INP_EN (1 << 9)
134 #define AD9528_PLL1_REFA_CMOS_NEG_INP_EN (1 << 8)
135 #define AD9528_PLL1_FREQ_DETECTOR_PD_EN (1 << 7)
136 #define AD9528_PLL1_REFB_DIFF_RCV_EN (1 << 6)
137 #define AD9528_PLL1_REFA_DIFF_RCV_EN (1 << 5)
138 #define AD9528_PLL1_REFB_RCV_EN (1 << 4)
139 #define AD9528_PLL1_REFA_RCV_EN (1 << 3)
140 #define AD9528_PLL1_VCXO_RCV_PD_EN (1 << 2)
141 #define AD9528_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1)
142 #define AD9528_PLL1_OSC_IN_DIFF_EN (1 << 0)
143 
144 /* AD9528_PLL2_CHARGE_PUMP */
145 #define AD9528_PLL2_CHARGE_PUMP_CURRENT_nA(x) ((x) / 3500)
146 
147 /* AD9528_PLL2_FEEDBACK_DIVIDER_AB */
148 #define AD9528_PLL2_FB_NDIV_A_CNT(x) (((x) & 0x3) << 6)
149 #define AD9528_PLL2_FB_NDIV_B_CNT(x) (((x) & 0x3F) << 0)
150 #define AD9528_PLL2_FB_NDIV(a, b) (4 * (b) + (a))
151 
152 /* AD9528_PLL2_CTRL */
153 #define AD9528_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)
154 #define AD9528_PLL2_FREQ_DOUBLER_EN (1 << 5)
155 #define AD9528_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)
156 #define AD9528_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0)
157 #define AD9528_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0)
158 #define AD9528_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0)
159 
160 /* AD9528_PLL2_VCO_CTRL */
161 #define AD9528_PLL2_DOUBLER_R1_EN (1 << 4)
162 #define AD9528_PLL2_FORCE_REFERENCE_VALID (1 << 2)
163 #define AD9528_PLL2_FORCE_VCO_MIDSCALE (1 << 1)
164 #define AD9528_PLL2_VCO_CALIBRATE (1 << 0)
165 
166 /* AD9528_PLL2_VCO_DIVIDER */
167 #define AD9528_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 3)
168 #define AD9528_PLL2_VCO_DIV_M1(x) (((x) & 0x7) << 0)
169 
170 /* AD9528_PLL2_LOOP_FILTER_CTRL */
171 #define AD9528_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)
172 #define AD9528_PLL2_LOOP_FILTER_RPOLE2(x) (((x) & 0x3) << 6)
173 #define AD9528_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3)
174 #define AD9528_PLL2_LOOP_FILTER_CPOLE1(x) (((x) & 0x7) << 0)
175 
176 /* AD9528_PLL2_R1_DIVIDER */
177 #define AD9528_PLL2_R1_DIV(x) (((x) & 0x1F) << 0)
178 
179 /* AD9528_PLL2_N2_DIVIDER */
180 #define AD9528_PLL2_N2_DIV(x) ((((x) - 1) & 0xFF) << 0)
181 
182 /* AD9528_CHANNEL_OUTPUT */
183 #define AD9528_CLK_DIST_DIV_MIN 1
184 #define AD9528_CLK_DIST_DIV_MAX 256
185 #define AD9528_CLK_DIST_DIV(x) ((((x) - 1) & 0xFF) << 16)
186 #define AD9528_CLK_DIST_DIV_REV(x) ((((x) >> 16) & 0xFF) + 1)
187 #define AD9528_CLK_DIST_DRIVER_MODE(x) (((x) & 0x3) << 14)
188 #define AD9528_CLK_DIST_DRIVER_MODE_REV(x) (((x) >> 14) & 0x3)
189 #define AD9528_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 8)
190 #define AD9528_CLK_DIST_DIV_PHASE_REV(x) (((x) >> 8) & 0x3F)
191 #define AD9528_CLK_DIST_CTRL(x) (((x) & 0x7) << 5)
192 #define AD9528_CLK_DIST_CTRL_REV(x) (((x) >> 5) & 0x7)
193 
194 #if 0
195 /* Leftovers */
196 #define AD9528_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7)
197 #endif
198 
199 /* AD9528_CHANNEL_SYNC */
200 #define AD9528_CHANNEL_SYNC_SET (1 << 0)
201 
202 /* AD9528_CHANNEL_SYNC_IGNORE */
203 #define AD9528_CHANNEL_IGNORE_MASK(x) (((x) & 0x3FFF) << 0)
204 #define AD9528_CHANNEL_IGNORE_MASK_REV(x) (((x) >> 0) & 0x3FFF)
205 
206 /* AD9528_SYSREF_K_DIVIDER */
207 #define AD9528_SYSREF_K_DIV(x) (((x) & 0xFFFF) << 0)
208 #define AD9528_SYSREF_K_DIV_MIN (0u)
209 #define AD9528_SYSREF_K_DIV_MAX (65535u)
210 
211 /* AD9528_SYSREF_CTRL */
212 #define AD9528_SYSREF_SOURCE(x) (((x) & 0x3) << 14)
213 #define AD9528_SYSREF_PATTERN_MODE(x) (((x) & 0x3) << 12)
214 #define AD9528_SYSREF_NSHOT_MODE(x) (((x) & 0x7) << 9)
215 #define AD9528_SYSREF_PATTERN_REQ (1 << 8)
216 #define AD9528_SYSREF_REQUEST_BY_PIN (1 << 7)
217 #define AD9528_SYSREF_PATTERN_TRIGGER_CTRL(x) (((x) & 0x3) << 5)
218 #define AD9528_SYSREF_RESAMPLER_CLK_SRC_PLL1 (1 << 4)
219 #define AD9528_SYSREF_PATTERN_CLK_SRC_PLL1 (1 << 3)
220 #define AD9528_SYSREF_TEST_MODE(x) (((x) & 0x3) << 1)
221 #define AD9528_SYSREF_RESET (1 << 0)
222 
223 /* AD9528_PD_EN */
224 #define AD9528_PD_BIAS (1 << 4)
225 #define AD9528_PD_PLL2 (1 << 3)
226 #define AD9528_PD_PLL1 (1 << 2)
227 #define AD9528_PD_OUT_CLOCKS (1 << 1)
228 #define AD9528_PD_CHIP (1 << 0)
229 
230 /* AD9528_CHANNEL_PD_EN */
231 #define AD9528_CHANNEL_PD_MASK(x) (((x) & 0x3FFF) << 0)
232 #define AD9528_CHANNEL_PD_MASK_REV(x) (((x) >> 0) & 0x3FFF)
233 
234 
235 /* AD9528_READBACK */
236 #define AD9528_IS_CALIBRATING (1 << 8)
237 #define AD9528_PLL2_OK (1 << 7)
238 #define AD9528_PLL1_OK (1 << 6)
239 #define AD9528_VCXO_OK (1 << 5)
240 #define AD9528_REFA_REFB_NOK (1 << 4)
241 #define AD9528_REFB_OK (1 << 3)
242 #define AD9528_REFA_OK (1 << 2)
243 #define AD9528_PLL2_LOCKED (1 << 1)
244 #define AD9528_PLL1_LOCKED (1 << 0)
245 
246 /* AD9528_STAT_PIN_EN */
247 #define AD9528_STAT0_PIN_EN (1 << 2)
248 #define AD9528_STAT1_PIN_EN (1 << 3)
249 #define AD9528_STAT0_DIV_EN (1 << 1)
250 #define AD9528_STAT1_DIV_EN (1 << 0)
251 
252 #define AD9528_NUM_CHAN 14
253 
254 #define AD9528_SPI_MAGIC 0x00FF05
255 
256 /* Output Driver Mode */
257 #define DRIVER_MODE_LVDS 0
258 #define DRIVER_MODE_LVDS_BOOST 1
259 #define DRIVER_MODE_HSTL 2
260 
261 /* Output Signal Source */
262 #define SOURCE_VCO 0
263 #define SOURCE_VCXO 1
264 #define SOURCE_SYSREF_VCO 2
265 #define SOURCE_SYSREF_VCXO 3
266 #define SOURCE_VCXO_INV 5
267 #define SOURCE_SYSREF_VCXO_INV 7
268 
269 /* Reference Selection Mode */
270 #define REF_MODE_STAY_ON_REFB 0
271 #define REF_MODE_REVERT_TO_REFA 1
272 #define REF_MODE_SELECT_REFA 2
273 #define REF_MODE_SELECT_REFB 3
274 #define REF_MODE_EXT_REF 4
275 
276 /* Sysref Source */
277 #define SYSREF_SRC_EXTERNAL 0
278 #define SYSREF_SRC_EXTERNAL_RESAMPLED 1
279 #define SYSREF_SRC_INTERNAL 2
280 
281 /* Sysref Pattern Mode */
282 #define SYSREF_PATTERN_NSHOT 0
283 #define SYSREF_PATTERN_CONTINUOUS 1
284 #define SYSREF_PATTERN_PRBS 2
285 #define SYSREF_PATTERN_STOP 3
286 
287 /* Sysref NSHOT Mode
288  * Use for adi,sysref-nshot-mode */
289 #define SYSREF_NSHOT_1_PULSE 1
290 #define SYSREF_NSHOT_2_PULSES 2
291 #define SYSREF_NSHOT_4_PULSES 3
292 #define SYSREF_NSHOT_6_PULSES 4
293 #define SYSREF_NSHOT_8_PULSES 5
294 
295 /* Sysref Trigger Mode
296  * Use for adi,sysref-request-trigger-mode */
297 #define SYSREF_LEVEL_HIGH 0
298 #define SYSREF_EDGE_RISING 2
299 #define SYSREF_EDGE_FALLING 3
300 
301 /* Rpole2 resistor */
302 #define RPOLE2_900_OHM 0
303 #define RPOLE2_450_OHM 1
304 #define RPOLE2_300_OHM 2
305 #define RPOLE2_225_OHM 3
306 
307 /* Rzero resistor */
308 #define RZERO_3250_OHM 0
309 #define RZERO_2750_OHM 1
310 #define RZERO_2250_OHM 2
311 #define RZERO_2100_OHM 3
312 #define RZERO_3000_OHM 4
313 #define RZERO_2500_OHM 5
314 #define RZERO_2000_OHM 6
315 #define RZERO_1850_OHM 7
316 
317 /* Cpole1 capacitor */
318 #define CPOLE1_0_PF 0
319 #define CPOLE1_8_PF 1
320 #define CPOLE1_16_PF 2
321 #define CPOLE1_24_PF 3
322 #define CPOLE1_32_PF 5
323 #define CPOLE1_40_PF 6
324 #define CPOLE1_48_PF 7
325 
326 /******************************************************************************/
327 /************************ Types Definitions ***********************************/
328 /******************************************************************************/
329 
336  uint8_t channel_num;
338  uint8_t sync_ignore_en;
340  uint8_t output_dis;
342  uint8_t driver_mode;
343  uint8_t signal_source;
347  uint8_t divider_phase;
349  uint16_t channel_divider;
351  int8_t extended_name[16];
352 };
353 
360  uint32_t vcxo_freq;
362  uint8_t spi3wire;
363 
365  uint8_t refa_en;
367  uint8_t refb_en;
368 
374  uint8_t osc_in_diff_en;
375 
376  /*
377  * Valid if differential input disabled
378  * if false defaults to pos input
379  */
386 
387  /* PLL1 Setting */
389  uint16_t refa_r_div;
391  uint16_t refb_r_div;
399  uint8_t pll1_bypass_en;
400 
401  /* Reference */
403  uint8_t ref_mode;
405  uint8_t sysref_src;
409  uint16_t sysref_k_div;
416 
417  /* PLL2 Setting */
427  uint8_t pll2_r1_div;
429  uint8_t pll2_n2_div;
434 
435  /* Loop Filter PLL2 */
437  uint8_t rpole2;
439  uint8_t rzero;
441  uint8_t cpole1;
444 
445  /* Output Channel Configuration */
447  uint32_t num_channels;
450 
455 };
456 
457 enum {
467 };
468 
469 enum {
474 };
475 
476 struct ad9528_state {
478 };
479 
480 struct ad9528_dev {
481  /* SPI */
483  /* GPIO */
485  /* Device Settings */
488 };
489 
491  /* SPI */
493  /* GPIO */
495  /* Device Settings */
497 };
498 
499 /* Helpers to avoid excess line breaks */
500 #define AD_IFE(_pde, _a, _b) ((dev->pdata->_pde) ? _a : _b)
501 #define AD_IF(_pde, _a) AD_IFE(_pde, _a, 0)
502 
503 /******************************************************************************/
504 /************************ Functions Declarations ******************************/
505 /******************************************************************************/
506 
507 int32_t ad9528_init(struct ad9528_init_param *init_param);
508 int32_t ad9528_setup(struct ad9528_dev **device,
510 int32_t ad9528_spi_read(struct ad9528_dev *dev,
511  uint32_t reg_addr,
512  uint32_t *reg_data);
513 int32_t ad9528_spi_write(struct ad9528_dev *dev,
514  uint32_t reg_addr,
515  uint32_t reg_data);
516 int32_t ad9528_spi_read_n(struct ad9528_dev *dev,
517  uint32_t reg_addr,
518  uint32_t *reg_data);
519 int32_t ad9528_spi_write_n(struct ad9528_dev *dev,
520  uint32_t reg_addr,
521  uint32_t reg_data);
522 int32_t ad9528_poll(struct ad9528_dev *dev,
523  uint32_t reg_addr,
524  uint32_t mask,
525  uint32_t data);
526 int32_t ad9528_io_update(struct ad9528_dev *dev);
527 int32_t ad9528_sync(struct ad9528_dev *dev);
528 uint32_t ad9528_clk_round_rate(struct ad9528_dev *dev, uint32_t chan,
529  uint32_t rate);
530 int32_t ad9528_clk_set_rate(struct ad9528_dev *dev, uint32_t chan,
531  uint32_t rate);
532 int32_t ad9528_reset(struct ad9528_dev *dev);
533 int32_t ad9528_remove(struct ad9528_dev *dev);
534 
535 #endif // __AD9528_H__
SYSREF_SRC_INTERNAL
#define SYSREF_SRC_INTERNAL
Definition: ad9528.h:279
ADI_ERR
ADI_ERR
Definition: common.h:34
AD9528_ADDR_STATUS0_CTRL
#define AD9528_ADDR_STATUS0_CTRL
Definition: t_ad9528.h:69
DIFFERENTIAL
@ DIFFERENTIAL
Definition: t_ad9528.h:94
ad9528_platform_data::refb_cmos_neg_inp_en
uint8_t refb_cmos_neg_inp_en
Definition: ad9528.h:383
ad9528_channel_spec::channel_divider
uint16_t channel_divider
Definition: ad9528.h:349
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
ad9528_platform_data::rzero_bypass_en
uint8_t rzero_bypass_en
Definition: ad9528.h:443
AD9528_CHANNEL_PD_EN
#define AD9528_CHANNEL_PD_EN
Definition: ad9528.h:97
ADIERR_OK
@ ADIERR_OK
Definition: common.h:35
AD9528_SYSREF
@ AD9528_SYSREF
Definition: ad9528.h:472
ad9528_dev::pdata
struct ad9528_platform_data * pdata
Definition: ad9528.h:487
AD9528_ADDR_STATUS1_CTRL
#define AD9528_ADDR_STATUS1_CTRL
Definition: t_ad9528.h:70
AD9528_ADDR_INPUT_RECEIVERS1
#define AD9528_ADDR_INPUT_RECEIVERS1
Definition: t_ad9528.h:33
AD9528_ADDR_CH_POWERDOWN1
#define AD9528_ADDR_CH_POWERDOWN1
Definition: t_ad9528.h:65
AD9528_VCXO
@ AD9528_VCXO
Definition: ad9528.h:471
ad9528_platform_data::refa_cmos_neg_inp_en
uint8_t refa_cmos_neg_inp_en
Definition: ad9528.h:381
NSHOT
@ NSHOT
Definition: t_ad9528.h:144
AD9528_PLL2_LOOP_FILTER_RPOLE2
#define AD9528_PLL2_LOOP_FILTER_RPOLE2(x)
Definition: ad9528.h:172
AD9528_PLL1_CHARGE_PUMP_MODE_NORMAL
#define AD9528_PLL1_CHARGE_PUMP_MODE_NORMAL
Definition: ad9528.h:119
AD9528_ADDR_MASK_SYNC2
#define AD9528_ADDR_MASK_SYNC2
Definition: t_ad9528.h:54
AD9528_IO_UPDATE_EN
#define AD9528_IO_UPDATE_EN
Definition: ad9528.h:115
CHANNEL_DIV
@ CHANNEL_DIV
Definition: t_ad9528.h:80
AD9528_PD_BIAS
#define AD9528_PD_BIAS
Definition: ad9528.h:224
AD9528_PLL2_VCO_CTRL
#define AD9528_PLL2_VCO_CTRL
Definition: ad9528.h:81
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:82
AD9528_CLK_DIST_DIV
#define AD9528_CLK_DIST_DIV(x)
Definition: ad9528.h:185
ad9528_init_param::spi_init
no_os_spi_init_param spi_init
Definition: ad9528.h:492
AD9528_SYSREF_K_DIV_MIN
#define AD9528_SYSREF_K_DIV_MIN
Definition: ad9528.h:208
AD9528_IS_CALIBRATING
#define AD9528_IS_CALIBRATING
Definition: ad9528.h:236
AD9528_STAT_PLL2_LD
@ AD9528_STAT_PLL2_LD
Definition: ad9528.h:459
AD9528_PLL1_CTRL
#define AD9528_PLL1_CTRL
Definition: ad9528.h:76
CMB_writeToLog
commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex, uint32_t errorCode, const char *comment)
Definition: common.c:248
sysrefNshotMode_t
sysrefNshotMode_t
Enum to select the SYSREF output # of pulses for NSHOT mode.
Definition: t_ad9528.h:154
AD9528_PLL2_VCO_DIV_M1_PWR_DOWN_EN
#define AD9528_PLL2_VCO_DIV_M1_PWR_DOWN_EN
Definition: ad9528.h:167
no_os_spi.h
Header file of SPI Interface.
AD9528_ADDR_STATUS_READBACK0
#define AD9528_ADDR_STATUS_READBACK0
Definition: t_ad9528.h:72
ad9528_spi_write_n
int32_t ad9528_spi_write_n(struct ad9528_dev *dev, uint32_t reg_addr, uint32_t reg_data)
Writes a value to the selected register.
Definition: ad9528.c:169
RPOLE2_900_OHM
@ RPOLE2_900_OHM
Definition: ad9523.h:342
ad9528_platform_data::pll2_charge_pump_current_nA
uint32_t pll2_charge_pump_current_nA
Definition: ad9528.h:419
ad9528_channel_spec
Output channel configuration.
Definition: ad9528.h:334
AD9528_ADDR_PLL2_LF_CTRL1
#define AD9528_ADDR_PLL2_LF_CTRL1
Definition: t_ad9528.h:43
AD9528_SYSREF_RESAMPLE_CTRL
#define AD9528_SYSREF_RESAMPLE_CTRL
Definition: ad9528.h:91
ONE_PULSE
@ ONE_PULSE
Definition: t_ad9528.h:156
ad9528_platform_data::pll2_bypass_en
bool pll2_bypass_en
Definition: ad9528.h:433
ad9528_reset
int32_t ad9528_reset(struct ad9528_dev *dev)
Performs a hard reset on the AD9528.
Definition: ad9528.c:880
ADIHAL_LOG_ERROR
@ ADIHAL_LOG_ERROR
Definition: common.h:51
AD9528_ADDR_SYSERF_DIV_MSB
#define AD9528_ADDR_SYSERF_DIV_MSB
Definition: t_ad9528.h:59
AD9528_ADDR_PLL2_REPLICA_DIV_PHASE
#define AD9528_ADDR_PLL2_REPLICA_DIV_PHASE
Definition: t_ad9528.h:47
ad9528_platform_data::num_channels
uint32_t num_channels
Definition: ad9528.h:447
ad9528_setup
int32_t ad9528_setup(struct ad9528_dev **device, struct ad9528_init_param init_param)
Initializes the AD9528.
Definition: ad9528.c:355
no_os_delay.h
Header file of Delay functions.
AD9528_STAT_PLL2_FB_CLK
@ AD9528_STAT_PLL2_FB_CLK
Definition: ad9528.h:465
ad9528_clk_set_rate
int32_t ad9528_clk_set_rate(struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
Set channel rate.
Definition: ad9528.c:794
ad9528_platform_data::refa_en
uint8_t refa_en
Definition: ad9528.h:365
ad9528_platform_data::pll2_r1_div
uint8_t pll2_r1_div
Definition: ad9528.h:427
AD9528_ADDR_SYSERF_DIV_LSB
#define AD9528_ADDR_SYSERF_DIV_LSB
Definition: t_ad9528.h:58
AD9528_STAT1_PIN_EN
#define AD9528_STAT1_PIN_EN
Definition: ad9528.h:248
AD9528_PLL2_VCO_DIVIDER
#define AD9528_PLL2_VCO_DIVIDER
Definition: ad9528.h:82
AD9528_SYSREF_CTRL
#define AD9528_SYSREF_CTRL
Definition: ad9528.h:94
AD9528_ADDR_MASK_SYNC1
#define AD9528_ADDR_MASK_SYNC1
Definition: t_ad9528.h:53
AD9528_PLL1_CHARGE_PUMP_CURRENT_nA
#define AD9528_PLL1_CHARGE_PUMP_CURRENT_nA(x)
Definition: ad9528.h:124
AD9528_PLL2_DOUBLER_R1_EN
#define AD9528_PLL2_DOUBLER_R1_EN
Definition: ad9528.h:161
AD9528_TRANSF_LEN
#define AD9528_TRANSF_LEN(x)
Definition: ad9528.h:65
ad9528_platform_data::spi3wire
uint8_t spi3wire
Definition: ad9528.h:362
CMB_hasTimeoutExpired
commonErr_t CMB_hasTimeoutExpired()
Definition: common.c:317
ad9528_clk_set_rate
int32_t ad9528_clk_set_rate(struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
Set channel rate.
Definition: ad9528.c:794
device
Definition: ad9361_util.h:75
AD9528_ADDR_PLL2_REPLICA_CHDIV
#define AD9528_ADDR_PLL2_REPLICA_CHDIV
Definition: t_ad9528.h:46
ad9528_init_param
Definition: ad9528.h:490
ADIERR_INV_PARM
@ ADIERR_INV_PARM
Definition: common.h:36
AD9528_CLK_DIST_DRIVER_MODE
#define AD9528_CLK_DIST_DRIVER_MODE(x)
Definition: ad9528.h:187
CMB_setTimeout_ms
commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms)
Definition: common.c:299
ad9528_spi_write_n
int32_t ad9528_spi_write_n(struct ad9528_dev *dev, uint32_t reg_addr, uint32_t reg_data)
Writes a value to the selected register.
Definition: ad9528.c:169
AD9528_ADDR_SYSREF_CTRL5
#define AD9528_ADDR_SYSREF_CTRL5
Definition: t_ad9528.h:62
AD9528_PLL2_N2_DIVIDER
#define AD9528_PLL2_N2_DIVIDER
Definition: ad9528.h:85
ad9528_spi_write
int32_t ad9528_spi_write(struct ad9528_dev *dev, uint32_t reg_addr, uint32_t reg_data)
Writes a value to the selected register.
Definition: ad9528.c:104
ad9528_platform_data::rpole2
uint8_t rpole2
Definition: ad9528.h:437
AD9528_ADDR_PLL2_VCO_CTRL
#define AD9528_ADDR_PLL2_VCO_CTRL
Definition: t_ad9528.h:41
ad9528_clk_round_rate
uint32_t ad9528_clk_round_rate(struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
Calculate closest possible rate.
Definition: ad9528.c:755
AD9528_IO_UPDATE
#define AD9528_IO_UPDATE
Definition: ad9528.h:70
DRIVER_MODE_LVDS
#define DRIVER_MODE_LVDS
Definition: ad9528.h:257
ad9528_sync
int32_t ad9528_sync(struct ad9528_dev *dev)
Updates the AD9528 configuration.
Definition: ad9528.c:246
AD9528_PLL1_REFB_BYPASS_EN
#define AD9528_PLL1_REFB_BYPASS_EN
Definition: ad9528.h:130
AD9528_ADDR_LDO_ENABLES1
#define AD9528_ADDR_LDO_ENABLES1
Definition: t_ad9528.h:67
AD9528_ADDR_PLL1_CHARGEPUMP
#define AD9528_ADDR_PLL1_CHARGEPUMP
Definition: t_ad9528.h:31
CPOLE1_16_PF
@ CPOLE1_16_PF
Definition: ad9523.h:362
ADIHAL_LOG_MESSAGE
@ ADIHAL_LOG_MESSAGE
Definition: common.h:49
AD9528_PLL2_LOCKED
#define AD9528_PLL2_LOCKED
Definition: ad9528.h:243
AD9528_SYSREF_K_DIVIDER
#define AD9528_SYSREF_K_DIVIDER
Definition: ad9528.h:93
ad9528_platform_data::sysref_req_en
bool sysref_req_en
Definition: ad9528.h:415
AD9528_PLL1_REF_MODE
#define AD9528_PLL1_REF_MODE(x)
Definition: ad9528.h:128
ad9528_platform_data::sysref_req_trigger_mode
uint8_t sysref_req_trigger_mode
Definition: ad9528.h:413
AD9528_ADDR_CH_OUT0_CHDIV
#define AD9528_ADDR_CH_OUT0_CHDIV
Definition: t_ad9528.h:51
AD9528_PLL2_R1_DIV
#define AD9528_PLL2_R1_DIV(x)
Definition: ad9528.h:177
AD9528_ADDR_PLL2_CTRL
#define AD9528_ADDR_PLL2_CTRL
Definition: t_ad9528.h:40
AD9528_STAT_REFB
@ AD9528_STAT_REFB
Definition: ad9528.h:461
ADIERR_FAILED
@ ADIERR_FAILED
Definition: common.h:37
LEVEL_ACTIVE_HIGH
@ LEVEL_ACTIVE_HIGH
Definition: t_ad9528.h:150
CMB_SPIWriteByte
commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr, uint8_t data)
Definition: common.c:171
ad9528_platform_data::sysref_k_div
uint16_t sysref_k_div
Definition: ad9528.h:409
AD9528_CHIP_ID
#define AD9528_CHIP_ID
Definition: ad9528.h:69
AD9528_PLL2_FB_NDIV_B_CNT
#define AD9528_PLL2_FB_NDIV_B_CNT(x)
Definition: ad9528.h:149
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: delay.c:130
AD9528_PLL2_CHARGE_PUMP
#define AD9528_PLL2_CHARGE_PUMP
Definition: ad9528.h:78
AD9528_PLL1_CHARGE_PUMP_AUTO_TRISTATE_DIS
#define AD9528_PLL1_CHARGE_PUMP_AUTO_TRISTATE_DIS
Definition: ad9528.h:118
ad9528_poll
int32_t ad9528_poll(struct ad9528_dev *dev, uint32_t reg_addr, uint32_t mask, uint32_t data)
Poll register.
Definition: ad9528.c:202
ad9528_platform_data::vcxo_freq
uint32_t vcxo_freq
Definition: ad9528.h:360
AD_IF
#define AD_IF(_pde, _a)
Definition: ad9523.c:50
AD9528_SPI_MAGIC
#define AD9528_SPI_MAGIC
Definition: ad9528.h:254
AD9528_ADDR_CH_POWERDOWN2
#define AD9528_ADDR_CH_POWERDOWN2
Definition: t_ad9528.h:66
ad9528_platform_data::pll2_vco_div_m1
uint8_t pll2_vco_div_m1
Definition: ad9528.h:431
ad9528_calc_out_div
uint32_t ad9528_calc_out_div(uint32_t rate, uint32_t parent_rate)
Calculate the output channel divider.
Definition: ad9528.c:731
ad9528_platform_data::osc_in_cmos_neg_inp_en
uint8_t osc_in_cmos_neg_inp_en
Definition: ad9528.h:385
AD9528_VCO
@ AD9528_VCO
Definition: ad9528.h:470
AD9528_STAT_REFAB_MISSING
@ AD9528_STAT_REFAB_MISSING
Definition: ad9528.h:462
AD9528_ADDR_INPUT_RECEIVERS3
#define AD9528_ADDR_INPUT_RECEIVERS3
Definition: t_ad9528.h:35
ad9528_platform_data::sysref_nshot_mode
uint8_t sysref_nshot_mode
Definition: ad9528.h:411
AD9528_SER_CONF_READ_BUFFERED
#define AD9528_SER_CONF_READ_BUFFERED
Definition: ad9528.h:111
AD9528_PLL2_LOOP_FILTER_RZERO_BYPASS_EN
#define AD9528_PLL2_LOOP_FILTER_RZERO_BYPASS_EN
Definition: ad9528.h:171
AD9528_PLL2_CHARGE_PUMP_CURRENT_nA
#define AD9528_PLL2_CHARGE_PUMP_CURRENT_nA(x)
Definition: ad9528.h:145
AD9528_PLL2_R1_DIVIDER
#define AD9528_PLL2_R1_DIVIDER
Definition: ad9528.h:84
ad9528_platform_data::refb_r_div
uint16_t refb_r_div
Definition: ad9528.h:391
ad9528_init_param::gpio_resetb
no_os_gpio_init_param * gpio_resetb
Definition: ad9528.h:494
AD9528_VCXO_OK
#define AD9528_VCXO_OK
Definition: ad9528.h:239
ad9528Device_t
Structure to hold AD9528 settings.
Definition: t_ad9528.h:179
ad9528_platform_data::refb_diff_rcv_en
uint8_t refb_diff_rcv_en
Definition: ad9528.h:372
AD9528_PLL2_CHARGE_PUMP_MODE_TRISTATE
#define AD9528_PLL2_CHARGE_PUMP_MODE_TRISTATE
Definition: ad9528.h:158
ad9528_platform_data::pll2_ndiv_a_cnt
uint8_t pll2_ndiv_a_cnt
Definition: ad9528.h:421
AD9528_PLL2_LOOP_FILTER_CPOLE1
#define AD9528_PLL2_LOOP_FILTER_CPOLE1(x)
Definition: ad9528.h:174
ad9528_spi_read_n
int32_t ad9528_spi_read_n(struct ad9528_dev *dev, uint32_t reg_addr, uint32_t *reg_data)
Reads the value of the selected register.
Definition: ad9528.c:133
AD9528_ADDR_REF_B_DIVIDER_MSB
#define AD9528_ADDR_REF_B_DIVIDER_MSB
Definition: t_ad9528.h:28
ad9528_platform_data::pll1_feedback_src_vcxo
uint8_t pll1_feedback_src_vcxo
Definition: ad9528.h:395
ad9528_spi_read
int32_t ad9528_spi_read(struct ad9528_dev *dev, uint32_t reg_addr, uint32_t *reg_data)
Reads the value of the selected register.
Definition: ad9528.c:74
AD9528_PLL2_VCO_DIV_M1
#define AD9528_PLL2_VCO_DIV_M1(x)
Definition: ad9528.h:168
AD9528_SER_CONF_SDO_ACTIVE
#define AD9528_SER_CONF_SDO_ACTIVE
Definition: ad9528.h:108
ad9528_platform_data::osc_in_diff_en
uint8_t osc_in_diff_en
Definition: ad9528.h:374
AD9528_ADDR_PLL2_VCO_DIV
#define AD9528_ADDR_PLL2_VCO_DIV
Definition: t_ad9528.h:42
ad9528_poll
int32_t ad9528_poll(struct ad9528_dev *dev, uint32_t reg_addr, uint32_t mask, uint32_t data)
Poll register.
Definition: ad9528.c:202
ad9528_clk_round_rate
uint32_t ad9528_clk_round_rate(struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
Calculate closest possible rate.
Definition: ad9528.c:755
AD9528_ADDR_REF_A_DIVIDER_LSB
#define AD9528_ADDR_REF_A_DIVIDER_LSB
Definition: t_ad9528.h:25
ad9528_platform_data
platform specific information
Definition: ad9528.h:358
AD9528_readPllStatus
ADI_ERR AD9528_readPllStatus(ad9528Device_t *device, uint8_t *status)
Reads the Lock Status of the PLLs and present detect of the reference clocks.
Definition: ad9528.c:629
AD9528_PLL1_FEEDBACK_DIVIDER
#define AD9528_PLL1_FEEDBACK_DIVIDER
Definition: ad9528.h:74
ad9528_sync
int32_t ad9528_sync(struct ad9528_dev *dev)
Updates the AD9528 configuration.
Definition: ad9528.c:246
CMB_SPIWriteField
commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr, uint8_t field_val, uint8_t mask, uint8_t start_bit)
Definition: common.c:217
AD9528_STAT_VCXO
@ AD9528_STAT_VCXO
Definition: ad9528.h:463
SYSREF_PATTERN_CONTINUOUS
#define SYSREF_PATTERN_CONTINUOUS
Definition: ad9528.h:283
AD9528_PLL1_OSC_IN_CMOS_NEG_INP_EN
#define AD9528_PLL1_OSC_IN_CMOS_NEG_INP_EN
Definition: ad9528.h:141
ad9528_channel_spec::extended_name
int8_t extended_name[16]
Definition: ad9528.h:351
AD9528_CLK_DIST_DIV_PHASE
#define AD9528_CLK_DIST_DIV_PHASE(x)
Definition: ad9528.h:189
ad9528_platform_data::rzero
uint8_t rzero
Definition: ad9528.h:439
AD9528_CLK_DIST_DIV_MAX
#define AD9528_CLK_DIST_DIV_MAX
Definition: ad9528.h:184
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:132
ad9528_platform_data::ref_mode
uint8_t ref_mode
Definition: ad9528.h:403
AD9528_ADDR_PLL2_CHARGEPUMP
#define AD9528_ADDR_PLL2_CHARGEPUMP
Definition: t_ad9528.h:38
ad9528_dev::gpio_resetb
no_os_gpio_desc * gpio_resetb
Definition: ad9528.h:484
AD9528_PLL1_REFA_BYPASS_EN
#define AD9528_PLL1_REFA_BYPASS_EN
Definition: ad9528.h:131
ad9528_reset
int32_t ad9528_reset(struct ad9528_dev *dev)
Performs a hard reset on the AD9528.
Definition: ad9528.c:880
AD9528_ADDR_PLL2_RDIV
#define AD9528_ADDR_PLL2_RDIV
Definition: t_ad9528.h:45
ad9528_state::vco_out_freq
uint32_t vco_out_freq[AD9528_NUM_CLK_SRC]
Definition: ad9528.h:477
ad9528_platform_data::sysref_pattern_mode
uint8_t sysref_pattern_mode
Definition: ad9528.h:407
AD9528_ADDR_ADI_SPI_CONFIG_B
#define AD9528_ADDR_ADI_SPI_CONFIG_B
Definition: t_ad9528.h:22
AD9528_ADDR_PLL1_N_DIV_LSB
#define AD9528_ADDR_PLL1_N_DIV_LSB
Definition: t_ad9528.h:29
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
ad9528_init
int32_t ad9528_init(struct ad9528_init_param *init_param)
Initializes the AD9528.
Definition: ad9528.c:295
AD9528_PLL2_FREQ_DOUBLER_EN
#define AD9528_PLL2_FREQ_DOUBLER_EN
Definition: ad9528.h:154
AD9528_PLL2_FEEDBACK_DIVIDER_AB
#define AD9528_PLL2_FEEDBACK_DIVIDER_AB
Definition: ad9528.h:79
AD9528_ADDR_PLL1_CP_CTRL2
#define AD9528_ADDR_PLL1_CP_CTRL2
Definition: t_ad9528.h:32
ad9528_state
Definition: ad9528.h:476
AD9528_ADDR_EN_OUTPUT_PATH_SEL1
#define AD9528_ADDR_EN_OUTPUT_PATH_SEL1
Definition: t_ad9528.h:55
AD9528_waitForPllLock
ADI_ERR AD9528_waitForPllLock(ad9528Device_t *device)
Waits for PLL1 and PLL2 to lock and the REFA and VCXO clocks to be present.
Definition: ad9528.c:597
AD9528_SYSREF_K_DIV
#define AD9528_SYSREF_K_DIV(x)
Definition: ad9528.h:207
AD9528_ADDR_PLL1_N_DIV_MSB
#define AD9528_ADDR_PLL1_N_DIV_MSB
Definition: t_ad9528.h:30
AD9528_PD_PLL1
#define AD9528_PD_PLL1
Definition: ad9528.h:226
SINGLE_ENDED
@ SINGLE_ENDED
Definition: t_ad9528.h:94
AD9528_NUM_CLK_SRC
@ AD9528_NUM_CLK_SRC
Definition: ad9528.h:473
AD9528_resetDevice
ADI_ERR AD9528_resetDevice(ad9528Device_t *device)
Performs a hard reset on the AD9528 DUT.
Definition: ad9528.c:26
AD_IFE
#define AD_IFE(_pde, _a, _b)
Definition: ad9523.c:49
AD9528_setSpiSettings
ADI_ERR AD9528_setSpiSettings(ad9528Device_t *device)
Sets the AD9528 device SPI settings (3wire/4wire, MSBFirst, etc).
Definition: ad9528.c:56
AD9528_ADDR_LDO_ENABLES2
#define AD9528_ADDR_LDO_ENABLES2
Definition: t_ad9528.h:68
AD9528_PD_PLL2
#define AD9528_PD_PLL2
Definition: ad9528.h:225
AD9528_ADDR_SYSREF_CTRL4
#define AD9528_ADDR_SYSREF_CTRL4
Definition: t_ad9528.h:61
AD9528_CHANNEL_OUTPUT
#define AD9528_CHANNEL_OUTPUT(ch)
Definition: ad9528.h:87
SYSREF_SRC_EXTERNAL
#define SYSREF_SRC_EXTERNAL
Definition: ad9528.h:277
AD9528_ADDR_INPUT_RECEIVERS2
#define AD9528_ADDR_INPUT_RECEIVERS2
Definition: t_ad9528.h:34
ad9528_platform_data::cpole1
uint8_t cpole1
Definition: ad9528.h:441
ad9528_platform_data::pll2_n2_div
uint8_t pll2_n2_div
Definition: ad9528.h:429
no_os_clamp_t
#define no_os_clamp_t(type, val, min_val, max_val)
Definition: no_os_util.h:75
AD9528_PLL1_CHARGE_PUMP_CTRL
#define AD9528_PLL1_CHARGE_PUMP_CTRL
Definition: ad9528.h:75
SOURCE_VCO
#define SOURCE_VCO
Definition: ad9528.h:262
ad9528_spi_write
int32_t ad9528_spi_write(struct ad9528_dev *dev, uint32_t reg_addr, uint32_t reg_data)
Writes a value to the selected register.
Definition: ad9528.c:104
AD9528_CHANNEL_SYNC_IGNORE
#define AD9528_CHANNEL_SYNC_IGNORE
Definition: ad9528.h:89
AD9528_CHANNEL_SYNC
#define AD9528_CHANNEL_SYNC
Definition: ad9528.h:88
AD9528_PLL1_REFB_RCV_EN
#define AD9528_PLL1_REFB_RCV_EN
Definition: ad9528.h:138
AD9528_ADDR_REF_B_DIVIDER_LSB
#define AD9528_ADDR_REF_B_DIVIDER_LSB
Definition: t_ad9528.h:27
ad9528_platform_data::refa_r_div
uint16_t refa_r_div
Definition: ad9528.h:389
CMB_hardReset
commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex)
Definition: common.c:136
ad9528_dev
Definition: ad9528.h:480
ad9528_remove
int32_t ad9528_remove(struct ad9528_dev *dev)
Free the resources allocated by ad9528_setup().
Definition: ad9528.c:712
AD9528_STAT_PLL1_FB_CLK
@ AD9528_STAT_PLL1_FB_CLK
Definition: ad9528.h:464
AD9528_PLL1_REF_B_DIVIDER
#define AD9528_PLL1_REF_B_DIVIDER
Definition: ad9528.h:73
AD9528_PLL1_REF_A_DIVIDER
#define AD9528_PLL1_REF_A_DIVIDER
Definition: ad9528.h:72
AD9528_ADDR_PLL2_N_DIV
#define AD9528_ADDR_PLL2_N_DIV
Definition: t_ad9528.h:39
AD9528_ADDR_PLL2_LF_CTRL2
#define AD9528_ADDR_PLL2_LF_CTRL2
Definition: t_ad9528.h:44
AD9528_SYNC
@ AD9528_SYNC
Definition: ad9528.h:466
ad9528.h
Contains function declarations and ad9528Device_t structure typedef for ad9528.c.
ad9528_channel_spec::divider_phase
uint8_t divider_phase
Definition: ad9528.h:347
ad9528_channel_spec::driver_mode
uint8_t driver_mode
Definition: ad9528.h:342
CMB_SPIReadByte
commonErr_t CMB_SPIReadByte(spiSettings_t *spiSettings, uint16_t addr, uint8_t *readdata)
Definition: common.c:200
INTERNAL
@ INTERNAL
Definition: t_ad9528.h:138
AD9528_requestSysref
ADI_ERR AD9528_requestSysref(ad9528Device_t *device, uint8_t enableSYSREF)
Send a SPI message to request a SYSREF pulse or continuous SYSREF from the AD9528.
Definition: ad9528.c:501
ad9528_platform_data::sysref_src
uint8_t sysref_src
Definition: ad9528.h:405
SYSREF
@ SYSREF
Definition: t_ad9528.h:81
AD9528_PLL2_VCO_CALIBRATE
#define AD9528_PLL2_VCO_CALIBRATE
Definition: ad9528.h:164
AD9528_ADDR_SYSREF_CTRL3
#define AD9528_ADDR_SYSREF_CTRL3
Definition: t_ad9528.h:60
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:96
AD9528_SER_CONF_SOFT_RESET
#define AD9528_SER_CONF_SOFT_RESET
Definition: ad9528.h:105
AD9528_STAT_MON0
#define AD9528_STAT_MON0
Definition: ad9528.h:99
AD9528_ADDR_ADI_SPI_CONFIG_A
#define AD9528_ADDR_ADI_SPI_CONFIG_A
Definition: t_ad9528.h:21
ad9528_platform_data::pll1_feedback_div
uint16_t pll1_feedback_div
Definition: ad9528.h:393
AD9528_setupSYSREF
ADI_ERR AD9528_setupSYSREF(ad9528Device_t *device, uint16_t divideFromPll1Out, sysrefPatternMode_t sysrefPatternMode, sysrefNshotMode_t nShotPulses)
Allow changing the 9528 SYSREF frequency and pattern mode(CONTINUOUS, PRBS vs NSHOT mode)
Definition: ad9528.c:535
AD9528_PLL1_REFA_RCV_EN
#define AD9528_PLL1_REFA_RCV_EN
Definition: ad9528.h:139
ad9528_init_param::pdata
struct ad9528_platform_data * pdata
Definition: ad9528.h:496
AD9528_SERIAL_PORT_CONFIG
#define AD9528_SERIAL_PORT_CONFIG
Definition: ad9528.h:67
AD9528_PLL1_REFA_CMOS_NEG_INP_EN
#define AD9528_PLL1_REFA_CMOS_NEG_INP_EN
Definition: ad9528.h:134
AD9528_ADDR_STATUS_OE
#define AD9528_ADDR_STATUS_OE
Definition: t_ad9528.h:71
ad9528_io_update
int32_t ad9528_io_update(struct ad9528_dev *dev)
Updates the AD9528 configuration.
Definition: ad9528.c:232
ad9528_platform_data::pll2_freq_doubler_en
uint8_t pll2_freq_doubler_en
Definition: ad9528.h:425
AD9528_PLL1_CHARGE_PUMP_TRISTATE
#define AD9528_PLL1_CHARGE_PUMP_TRISTATE
Definition: ad9528.h:123
AD9528_CLK_DIST_CTRL
#define AD9528_CLK_DIST_CTRL(x)
Definition: ad9528.h:191
ad9528_init
int32_t ad9528_init(struct ad9528_init_param *init_param)
Initializes the AD9528.
Definition: ad9528.c:295
AD9528_PLL1_OSC_IN_DIFF_EN
#define AD9528_PLL1_OSC_IN_DIFF_EN
Definition: ad9528.h:142
ad9528_platform_data::pll2_ndiv_b_cnt
uint8_t pll2_ndiv_b_cnt
Definition: ad9528.h:423
NEG_SINGLE_ENDED
@ NEG_SINGLE_ENDED
Definition: t_ad9528.h:94
sysrefPatternMode_t
sysrefPatternMode_t
Enum to choose the SYSREF pattern mode.
Definition: t_ad9528.h:142
ad9528_platform_data::stat0_pin_func_sel
uint8_t stat0_pin_func_sel
Definition: ad9528.h:452
ad9528_platform_data::refa_diff_rcv_en
uint8_t refa_diff_rcv_en
Definition: ad9528.h:370
DISABLED
@ DISABLED
Definition: t_ad9528.h:94
AD9528_ADDR_PLL1_FASTLOCK
#define AD9528_ADDR_PLL1_FASTLOCK
Definition: t_ad9528.h:36
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:70
ad9528.h
Header file of AD9528 Driver.
ad9528_platform_data::channels
struct ad9528_channel_spec * channels
Definition: ad9528.h:449
AD9528_PLL1_SOURCE_VCXO
#define AD9528_PLL1_SOURCE_VCXO
Definition: ad9528.h:132
AD9528_PLL1_REFA_DIFF_RCV_EN
#define AD9528_PLL1_REFA_DIFF_RCV_EN
Definition: ad9528.h:137
ad9528_platform_data::stat1_pin_func_sel
uint8_t stat1_pin_func_sel
Definition: ad9528.h:454
AD9528_ADDR_CH_OUT0_CTRL2
#define AD9528_ADDR_CH_OUT0_CTRL2
Definition: t_ad9528.h:50
AD9528_PLL2_CTRL
#define AD9528_PLL2_CTRL
Definition: ad9528.h:80
no_os_gpio.h
Header file of GPIO Interface.
ad9528_io_update
int32_t ad9528_io_update(struct ad9528_dev *dev)
Updates the AD9528 configuration.
Definition: ad9528.c:232
AD9528_PLL2_LOOP_FILTER_CTRL
#define AD9528_PLL2_LOOP_FILTER_CTRL
Definition: ad9528.h:83
AD9528_STAT_PIN_EN
#define AD9528_STAT_PIN_EN
Definition: ad9528.h:101
ad9528_dev::ad9528_st
struct ad9528_state ad9528_st
Definition: ad9528.h:486
AD9528_ADDR_OUTPUT_SYNC
#define AD9528_ADDR_OUTPUT_SYNC
Definition: t_ad9528.h:52
AD9528_ADDR_IO_UPDATE
#define AD9528_ADDR_IO_UPDATE
Definition: t_ad9528.h:23
ad9528_channel_spec::output_dis
uint8_t output_dis
Definition: ad9528.h:340
ad9528_remove
int32_t ad9528_remove(struct ad9528_dev *dev)
Free the resources allocated by ad9528_setup().
Definition: ad9528.c:712
AD9528_NUM_CHAN
#define AD9528_NUM_CHAN
Definition: ad9528.h:252
AD9528_ADDR_REF_A_DIVIDER_MSB
#define AD9528_ADDR_REF_A_DIVIDER_MSB
Definition: t_ad9528.h:26
AD9528_PLL2_LOOP_FILTER_RZERO
#define AD9528_PLL2_LOOP_FILTER_RZERO(x)
Definition: ad9528.h:173
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:51
ad9528_spi_read_n
int32_t ad9528_spi_read_n(struct ad9528_dev *dev, uint32_t reg_addr, uint32_t *reg_data)
Reads the value of the selected register.
Definition: ad9528.c:133
AD9528_SERIAL_PORT_CONFIG_B
#define AD9528_SERIAL_PORT_CONFIG_B
Definition: ad9528.h:68
AD9528_ADDR_POWERDOWN_CTRL
#define AD9528_ADDR_POWERDOWN_CTRL
Definition: t_ad9528.h:64
AD9528_PLL1_REFB_DIFF_RCV_EN
#define AD9528_PLL1_REFB_DIFF_RCV_EN
Definition: ad9528.h:136
AD9528_SYSREF_K_DIV_MAX
#define AD9528_SYSREF_K_DIV_MAX
Definition: ad9528.h:209
ad9528_spi_read
int32_t ad9528_spi_read(struct ad9528_dev *dev, uint32_t reg_addr, uint32_t *reg_data)
Reads the value of the selected register.
Definition: ad9528.c:74
AD9528_SYSREF_PATTERN_REQ
#define AD9528_SYSREF_PATTERN_REQ
Definition: ad9528.h:215
AD9528_SYSREF_PATTERN_MODE
#define AD9528_SYSREF_PATTERN_MODE(x)
Definition: ad9528.h:213
no_os_util.h
Implementation of utility functions.
AD9528_PLL1_REFB_CMOS_NEG_INP_EN
#define AD9528_PLL1_REFB_CMOS_NEG_INP_EN
Definition: ad9528.h:133
AD9528_PLL2_CHARGE_PUMP_MODE_NORMAL
#define AD9528_PLL2_CHARGE_PUMP_MODE_NORMAL
Definition: ad9528.h:155
ad9528_platform_data::refb_en
uint8_t refb_en
Definition: ad9528.h:367
SPI
@ SPI
Definition: adxl372.h:322
AD9528_STAT0_PIN_EN
#define AD9528_STAT0_PIN_EN
Definition: ad9528.h:247
ad9528_channel_spec::signal_source
uint8_t signal_source
Definition: ad9528.h:343
ad9528_platform_data::pll1_charge_pump_current_nA
uint16_t pll1_charge_pump_current_nA
Definition: ad9528.h:397
ad9528_platform_data::pll1_bypass_en
uint8_t pll1_bypass_en
Definition: ad9528.h:399
AD9528_ADDR_EN_OUTPUT_PATH_SEL2
#define AD9528_ADDR_EN_OUTPUT_PATH_SEL2
Definition: t_ad9528.h:56
AD9528_CHANNEL_PD_MASK
#define AD9528_CHANNEL_PD_MASK(x)
Definition: ad9528.h:231
ad9528_channel_spec::sync_ignore_en
uint8_t sync_ignore_en
Definition: ad9528.h:338
ad9528_channel_spec::channel_num
uint8_t channel_num
Definition: ad9528.h:336
AD9528_CHANNEL_IGNORE_MASK
#define AD9528_CHANNEL_IGNORE_MASK(x)
Definition: ad9528.h:203
no_os_gpio_direction_output
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:124
AD9528_PLL2_N2_DIV
#define AD9528_PLL2_N2_DIV(x)
Definition: ad9528.h:180
AD9528_ADDR_CH_OUT0_CTRL1
#define AD9528_ADDR_CH_OUT0_CTRL1
Definition: t_ad9528.h:49
AD9528_STAT_PLL1_LD
@ AD9528_STAT_PLL1_LD
Definition: ad9528.h:458
AD9528_PD_EN
#define AD9528_PD_EN
Definition: ad9528.h:96
AD9528_READBACK
#define AD9528_READBACK
Definition: ad9528.h:102
ad9528_setup
int32_t ad9528_setup(struct ad9528_dev **device, struct ad9528_init_param init_param)
Initializes the AD9528.
Definition: ad9528.c:355
AD9528_SYSREF_SOURCE
#define AD9528_SYSREF_SOURCE(x)
Definition: ad9528.h:212
AD9528_reportClockRates
ADI_ERR AD9528_reportClockRates(ad9528Device_t *device)
Debug function to print out summary of AD9528 setup.
Definition: ad9528.c:281
AD9528_CLK_DIST_DIV_MIN
#define AD9528_CLK_DIST_DIV_MIN
Definition: ad9528.h:183
RZERO_1850_OHM
@ RZERO_1850_OHM
Definition: ad9523.h:356
LVDS
@ LVDS
Definition: ad9517.h:371
AD9528_PLL2_FB_NDIV_A_CNT
#define AD9528_PLL2_FB_NDIV_A_CNT(x)
Definition: ad9528.h:148
AD9528_initialize
ADI_ERR AD9528_initialize(ad9528Device_t *device)
Initializes the AD9528 by writing all SPI registers.
Definition: ad9528.c:303
AD9528_STAT_REFA
@ AD9528_STAT_REFA
Definition: ad9528.h:460
ad9528_dev::spi_desc
no_os_spi_desc * spi_desc
Definition: ad9528.h:482
AD9528_enableClockOutputs
ADI_ERR AD9528_enableClockOutputs(ad9528Device_t *device, uint16_t clkEnable)
Update the AD9528 clock outputs that are enabled.
Definition: ad9528.c:573
NO_OS_DIV_ROUND_CLOSEST
#define NO_OS_DIV_ROUND_CLOSEST(x, y)
Definition: no_os_util.h:58
AD9528_initDeviceDataStruct
ADI_ERR AD9528_initDeviceDataStruct(ad9528Device_t *device, uint32_t vcxoFrequency_Hz, uint32_t refAFrequency_Hz, uint32_t outputDeviceClock_Hz)
Helper function for ADI transceiver eval boards to init the AD9528 data structure.
Definition: ad9528.c:115
AD9528_CHANNEL_SYNC_SET
#define AD9528_CHANNEL_SYNC_SET
Definition: ad9528.h:200
AD9528_STAT_MON1
#define AD9528_STAT_MON1
Definition: ad9528.h:100
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:112
AD9528_PLL1_FEEDBACK_BYPASS_EN
#define AD9528_PLL1_FEEDBACK_BYPASS_EN
Definition: ad9528.h:129
no_os_div_u64
uint64_t no_os_div_u64(uint64_t dividend, uint32_t divisor)
no_os_gpio_get_optional
int32_t no_os_gpio_get_optional(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Get the value of an optional GPIO.
Definition: no_os_gpio.c:75