no-OS
common.h
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1 
13 #ifndef _COMMON_H_
14 #define _COMMON_H_
15 
16 #ifdef __cplusplus
17 extern "C" {
18 #endif
19 
20 /* build project settings include the path to the desired platform folder for correct includes */
21 #include "stdint.h"
22 
23 #define THROW_ERROR()
24 
25 #define SPIARRAYSIZE 1024
26 
27 /* assuming 3 byte SPI message - integer math enforces floor() */
28 #define SPIARRAYTRIPSIZE ((SPIARRAYSIZE / 3) * 3)
29 
30 /*========================================
31  * Enums and structures
32  *=======================================*/
33 /* proposed to increase number of error return values to make unique for each return */
34 typedef enum {
38 } ADI_ERR;
39 
41 typedef enum {
44 } commonErr_t;
45 
46 /* bit 0 is MESSAGE, bit 1 is WARNING, bit 2 is ERROR */
47 typedef enum {
56 } ADI_LOGLEVEL;
57 
61 typedef struct {
62  uint8_t chipSelectIndex;
63  uint8_t writeBitPolarity;
65  uint8_t MSBFirst;
66  uint8_t CPHA;
67  uint8_t CPOL;
68  uint8_t enSpiStreaming;
69  uint8_t autoIncAddrUp;
70  uint8_t fourWireMode;
71  uint32_t spiClkFreq_Hz;
73 
74 /* global variable so application layer can set the log level */
76 
77 /* close hardware pointers */
79 
80 /* GPIO function */
81 commonErr_t CMB_setGPIO(uint32_t GPIO);
82 
83 /* hardware reset function */
84 commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex);
85 
86 /* SPI read/write functions */
88  *spiSettings); /* allows the platform HAL to work with devices with various SPI settings */
90  chipSelectIndex ); /* value of 0 deasserts all chip selects */
91 commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr,
92  uint8_t data); /* single SPI byte write function */
93 commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr,
94  uint8_t *data, uint32_t count);
95 commonErr_t CMB_SPIReadByte (spiSettings_t *spiSettings, uint16_t addr,
96  uint8_t *readdata); /* single SPI byte read function */
97 commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr,
98  uint8_t field_val, uint8_t mask,
99  uint8_t start_bit); /* write a field in a single register */
100 commonErr_t CMB_SPIReadField (spiSettings_t *spiSettings, uint16_t addr,
101  uint8_t *field_val, uint8_t mask,
102  uint8_t start_bit); /* read a field in a single register */
103 
104 /* platform timer functions */
105 commonErr_t CMB_wait_ms(uint32_t time_ms);
106 commonErr_t CMB_wait_us(uint32_t time_us);
107 commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms);
108 commonErr_t CMB_setTimeout_us(uint32_t timeOut_us);
110 
111 /* platform logging functions */
112 commonErr_t CMB_openLog(const char *filename);
114 commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex,
115  uint32_t errorCode, const char *comment);
117 
118 /* platform FPGA AXI register read/write functions */
119 commonErr_t CMB_regRead(uint32_t offset, uint32_t *data);
120 commonErr_t CMB_regWrite(uint32_t offset, uint32_t data);
121 
122 /* platform DDR3 memory read/write functions */
123 commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len);
124 commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len);
125 
126 int32_t platform_init(void);
127 int32_t platform_remove(void);
128 
129 #ifdef __cplusplus
130 }
131 #endif
132 #endif
ADI_ERR
ADI_ERR
Definition: common.h:34
ADIERR_OK
@ ADIERR_OK
Definition: common.h:35
COMMONERR_OK
@ COMMONERR_OK
Definition: common.h:42
CMB_setSPIChannel
commonErr_t CMB_setSPIChannel(uint16_t chipSelectIndex)
Definition: common.c:166
CMB_wait_us
commonErr_t CMB_wait_us(uint32_t time_us)
Definition: common.c:292
ADIHAL_LOG_ERROR
@ ADIHAL_LOG_ERROR
Definition: common.h:51
spiSettings_t::chipSelectIndex
uint8_t chipSelectIndex
valid 1~8
Definition: common.h:62
spiSettings_t::MSBFirst
uint8_t MSBFirst
1 = MSBFirst, 0 = LSBFirst
Definition: common.h:65
ADIERR_INV_PARM
@ ADIERR_INV_PARM
Definition: common.h:36
CMB_regWrite
commonErr_t CMB_regWrite(uint32_t offset, uint32_t data)
Definition: common.c:333
CMB_flushLog
commonErr_t CMB_flushLog(void)
Definition: common.c:280
ADIHAL_LOG_MESSAGE
@ ADIHAL_LOG_MESSAGE
Definition: common.h:49
ADIERR_FAILED
@ ADIERR_FAILED
Definition: common.h:37
CMB_SPIWriteByte
commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr, uint8_t data)
Definition: common.c:171
platform_remove
int32_t platform_remove(void)
Definition: common.c:113
CMB_setTimeout_us
commonErr_t CMB_setTimeout_us(uint32_t timeOut_us)
Definition: common.c:310
commonErr_t
commonErr_t
Definition: common.h:41
CMB_closeHardware
commonErr_t CMB_closeHardware(void)
Definition: common.c:126
ADIHAL_LOG_SPI
@ ADIHAL_LOG_SPI
Definition: common.h:52
CMB_memRead
commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len)
Definition: common.c:338
CMB_setSPIOptions
commonErr_t CMB_setSPIOptions(spiSettings_t *spiSettings)
Definition: common.c:161
spiSettings_t
Data structure to hold SPI settings for all system device types.
Definition: common.h:61
CMB_regRead
commonErr_t CMB_regRead(uint32_t offset, uint32_t *data)
Definition: common.c:328
spiSettings_t::writeBitPolarity
uint8_t writeBitPolarity
the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation
Definition: common.h:63
CMB_SPIWriteBytes
commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr, uint8_t *data, uint32_t count)
Definition: common.c:187
platform_init
int32_t platform_init(void)
Initialize the power controller and set the core and peripherals clock divider.
Definition: platform_init.c:50
ADIHAL_LOG_AXI_MEM
@ ADIHAL_LOG_AXI_MEM
Definition: common.h:54
CMB_LOGLEVEL
ADI_LOGLEVEL CMB_LOGLEVEL
Definition: common.c:31
CMB_wait_ms
commonErr_t CMB_wait_ms(uint32_t time_ms)
Definition: common.c:285
ADIHAL_LOG_AXI_REG
@ ADIHAL_LOG_AXI_REG
Definition: common.h:53
CMB_memWrite
commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len)
Definition: common.c:343
ADIHAL_LOG_WARNING
@ ADIHAL_LOG_WARNING
Definition: common.h:50
spiSettings_t::longInstructionWord
uint8_t longInstructionWord
1 = 16bit instruction word, 0 = 8bit instruction word
Definition: common.h:64
CMB_setGPIO
commonErr_t CMB_setGPIO(uint32_t GPIO)
Definition: common.c:131
CMB_openLog
commonErr_t CMB_openLog(const char *filename)
Definition: common.c:270
CMB_writeToLog
commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex, uint32_t errorCode, const char *comment)
Definition: common.c:248
ADI_LOGLEVEL
ADI_LOGLEVEL
Definition: common.h:47
spiSettings_t::autoIncAddrUp
uint8_t autoIncAddrUp
Not implemented. For SPI Streaming, set address increment direction. 1= next addr = addr+1,...
Definition: common.h:69
spiSettings_t::enSpiStreaming
uint8_t enSpiStreaming
Not implemented. SW feature to improve SPI throughput.
Definition: common.h:68
ADIHAL_LOG_NONE
@ ADIHAL_LOG_NONE
Definition: common.h:48
CMB_SPIWriteField
commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr, uint8_t field_val, uint8_t mask, uint8_t start_bit)
Definition: common.c:217
spiSettings_t::CPHA
uint8_t CPHA
clock phase, sets which clock edge the data updates (valid 0 or 1)
Definition: common.h:66
spiSettings_t::fourWireMode
uint8_t fourWireMode
1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4...
Definition: common.h:70
CMB_closeLog
commonErr_t CMB_closeLog(void)
Definition: common.c:275
CMB_setTimeout_ms
commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms)
Definition: common.c:299
CMB_SPIReadField
commonErr_t CMB_SPIReadField(spiSettings_t *spiSettings, uint16_t addr, uint8_t *field_val, uint8_t mask, uint8_t start_bit)
Definition: common.c:234
ADIHAL_LOG_ALL
@ ADIHAL_LOG_ALL
Definition: common.h:55
CMB_hasTimeoutExpired
commonErr_t CMB_hasTimeoutExpired()
Definition: common.c:317
COMMONERR_FAILED
@ COMMONERR_FAILED
Definition: common.h:43
CMB_hardReset
commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex)
Definition: common.c:136
CMB_SPIReadByte
commonErr_t CMB_SPIReadByte(spiSettings_t *spiSettings, uint16_t addr, uint8_t *readdata)
Definition: common.c:200
spiSettings_t::spiClkFreq_Hz
uint32_t spiClkFreq_Hz
SPI Clk frequency in Hz (default 25000000), platform will use next lowest frequency that it's baud ra...
Definition: common.h:71
spiSettings_t::CPOL
uint8_t CPOL
clock polarity 0 = clock starts low, 1 = clock starts high
Definition: common.h:67