no-OS
Classes | Macros | Typedefs
spi_engine_private.h File Reference
#include <stdint.h>
#include <stdbool.h>
#include "no-os/spi.h"
#include "no-os/util.h"
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Classes

struct  spi_engine_cmd_queue
 
struct  spi_engine_msg
 

Macros

#define SPI_ENGINE_REG_VERSION   0x00
 
#define SPI_ENGINE_REG_DATA_WIDTH   0x0C
 
#define SPI_ENGINE_REG_RESET   0x40
 
#define SPI_ENGINE_REG_INT_ENABLE   0x80
 
#define SPI_ENGINE_REG_INT_PENDING   0x84
 
#define SPI_ENGINE_REG_INT_SOURCE   0x88
 
#define SPI_ENGINE_REG_SYNC_ID   0xC0
 
#define SPI_ENGINE_REG_CMD_FIFO_ROOM   0xD0
 
#define SPI_ENGINE_REG_SDO_FIFO_ROOM   0xD4
 
#define SPI_ENGINE_REG_SDI_FIFO_LEVEL   0xD8
 
#define SPI_ENGINE_REG_CMD_FIFO   0xE0
 
#define SPI_ENGINE_REG_SDO_DATA_FIFO   0xE4
 
#define SPI_ENGINE_REG_SDI_DATA_FIFO   0xE8
 
#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK   0xEC
 
#define SPI_ENGINE_INST_TRANSFER   0x00
 
#define SPI_ENGINE_INST_ASSERT   0x01
 
#define SPI_ENGINE_INST_CONFIG   0x02
 
#define SPI_ENGINE_INST_SYNC_SLEEP   0x03
 
#define SPI_ENGINE_INST_MISC   0x03
 
#define SPI_ENGINE_CMD_REG_CLK_DIV   0x00
 
#define SPI_ENGINE_CMD_REG_CONFIG   0x01
 
#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN   0x02
 
#define SPI_ENGINE_MISC_SYNC   0x00
 
#define SPI_ENGINE_MISC_SLEEP   0x01
 
#define SPI_ENGINE_SYNC_TRANSFER_BEGIN   BIT(1)
 
#define SPI_ENGINE_SYNC_TRANSFER_END   BIT(2)
 
#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY   BIT(0)
 
#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY   BIT(1)
 
#define SPI_ENGINE_INT_SDI_ALMOST_FULL   BIT(2)
 
#define SPI_ENGINE_INT_SYNC   BIT(3)
 
#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE   BIT(0)
 
#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED   BIT(0)
 
#define SPI_ENGINE_CONFIG_CPHA   BIT(0)
 
#define SPI_ENGINE_CONFIG_CPOL   BIT(1)
 
#define SPI_ENGINE_CONFIG_3WIRE   BIT(2)
 
#define SPI_ENGINE_VERSION_MAJOR(x)   ((x >> 16) & 0xff)
 
#define SPI_ENGINE_VERSION_MINOR(x)   ((x >> 8) & 0xff)
 
#define SPI_ENGINE_VERSION_PATCH(x)   (x & 0xff)
 
#define SPI_ENGINE_INSTRUCTION_TRANSFER_W   0x01
 
#define SPI_ENGINE_INSTRUCTION_TRANSFER_R   0x02
 
#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW   0x03
 
#define SPI_ENGINE_REG_OFFLOAD_CTRL(x)   (0x100 + (0x20 * x))
 
#define SPI_ENGINE_REG_OFFLOAD_STATUS(x)   (0x104 + (0x20 * x))
 
#define SPI_ENGINE_REG_OFFLOAD_RESET(x)   (0x108 + (0x20 * x))
 
#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x)   (0x110 + (0x20 * x))
 
#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM(x)   (0x114 + (0x20 * x))
 
#define SPI_ENGINE_CMD(inst, arg1, arg2)
 
#define SPI_ENGINE_CMD_TRANSFER(readwrite, n)
 
#define SPI_ENGINE_CMD_ASSERT(delay, cs)
 
#define SPI_ENGINE_CMD_CONFIG(reg, val)
 
#define SPI_ENGINE_CMD_SLEEP(delay)
 
#define SPI_ENGINE_CMD_SYNC(id)
 

Typedefs

typedef struct spi_engine_cmd_queue spi_engine_cmd_queue
 
typedef struct spi_engine_msg spi_engine_msg
 

Macro Definition Documentation

◆ SPI_ENGINE_CMD

#define SPI_ENGINE_CMD (   inst,
  arg1,
  arg2 
)
Value:
(((inst & 0x03) << 12) | \
((arg1 & 0x03) << 8) | arg2 )

◆ SPI_ENGINE_CMD_ASSERT

#define SPI_ENGINE_CMD_ASSERT (   delay,
  cs 
)
Value:

◆ SPI_ENGINE_CMD_CONFIG

#define SPI_ENGINE_CMD_CONFIG (   reg,
  val 
)
Value:

◆ SPI_ENGINE_CMD_DATA_TRANSFER_LEN

#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN   0x02

◆ SPI_ENGINE_CMD_REG_CLK_DIV

#define SPI_ENGINE_CMD_REG_CLK_DIV   0x00

◆ SPI_ENGINE_CMD_REG_CONFIG

#define SPI_ENGINE_CMD_REG_CONFIG   0x01

◆ SPI_ENGINE_CMD_SLEEP

#define SPI_ENGINE_CMD_SLEEP (   delay)

◆ SPI_ENGINE_CMD_SYNC

#define SPI_ENGINE_CMD_SYNC (   id)

◆ SPI_ENGINE_CMD_TRANSFER

#define SPI_ENGINE_CMD_TRANSFER (   readwrite,
 
)
Value:

◆ SPI_ENGINE_CONFIG_3WIRE

#define SPI_ENGINE_CONFIG_3WIRE   BIT(2)

◆ SPI_ENGINE_CONFIG_CPHA

#define SPI_ENGINE_CONFIG_CPHA   BIT(0)

◆ SPI_ENGINE_CONFIG_CPOL

#define SPI_ENGINE_CONFIG_CPOL   BIT(1)

◆ SPI_ENGINE_INST_ASSERT

#define SPI_ENGINE_INST_ASSERT   0x01

◆ SPI_ENGINE_INST_CONFIG

#define SPI_ENGINE_INST_CONFIG   0x02

◆ SPI_ENGINE_INST_MISC

#define SPI_ENGINE_INST_MISC   0x03

◆ SPI_ENGINE_INST_SYNC_SLEEP

#define SPI_ENGINE_INST_SYNC_SLEEP   0x03

◆ SPI_ENGINE_INST_TRANSFER

#define SPI_ENGINE_INST_TRANSFER   0x00

◆ SPI_ENGINE_INSTRUCTION_TRANSFER_R

#define SPI_ENGINE_INSTRUCTION_TRANSFER_R   0x02

◆ SPI_ENGINE_INSTRUCTION_TRANSFER_RW

#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW   0x03

◆ SPI_ENGINE_INSTRUCTION_TRANSFER_W

#define SPI_ENGINE_INSTRUCTION_TRANSFER_W   0x01

◆ SPI_ENGINE_INT_CMD_ALMOST_EMPTY

#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY   BIT(0)

◆ SPI_ENGINE_INT_SDI_ALMOST_FULL

#define SPI_ENGINE_INT_SDI_ALMOST_FULL   BIT(2)

◆ SPI_ENGINE_INT_SDO_ALMOST_EMPTY

#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY   BIT(1)

◆ SPI_ENGINE_INT_SYNC

#define SPI_ENGINE_INT_SYNC   BIT(3)

◆ SPI_ENGINE_MISC_SLEEP

#define SPI_ENGINE_MISC_SLEEP   0x01

◆ SPI_ENGINE_MISC_SYNC

#define SPI_ENGINE_MISC_SYNC   0x00

◆ SPI_ENGINE_OFFLOAD_CTRL_ENABLE

#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE   BIT(0)

◆ SPI_ENGINE_OFFLOAD_STATUS_ENABLED

#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED   BIT(0)

◆ SPI_ENGINE_REG_CMD_FIFO

#define SPI_ENGINE_REG_CMD_FIFO   0xE0

◆ SPI_ENGINE_REG_CMD_FIFO_ROOM

#define SPI_ENGINE_REG_CMD_FIFO_ROOM   0xD0

◆ SPI_ENGINE_REG_DATA_WIDTH

#define SPI_ENGINE_REG_DATA_WIDTH   0x0C

◆ SPI_ENGINE_REG_INT_ENABLE

#define SPI_ENGINE_REG_INT_ENABLE   0x80

◆ SPI_ENGINE_REG_INT_PENDING

#define SPI_ENGINE_REG_INT_PENDING   0x84

◆ SPI_ENGINE_REG_INT_SOURCE

#define SPI_ENGINE_REG_INT_SOURCE   0x88

◆ SPI_ENGINE_REG_OFFLOAD_CMD_MEM

#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM (   x)    (0x110 + (0x20 * x))

◆ SPI_ENGINE_REG_OFFLOAD_CTRL

#define SPI_ENGINE_REG_OFFLOAD_CTRL (   x)    (0x100 + (0x20 * x))

◆ SPI_ENGINE_REG_OFFLOAD_RESET

#define SPI_ENGINE_REG_OFFLOAD_RESET (   x)    (0x108 + (0x20 * x))

◆ SPI_ENGINE_REG_OFFLOAD_SDO_MEM

#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM (   x)    (0x114 + (0x20 * x))

◆ SPI_ENGINE_REG_OFFLOAD_STATUS

#define SPI_ENGINE_REG_OFFLOAD_STATUS (   x)    (0x104 + (0x20 * x))

◆ SPI_ENGINE_REG_RESET

#define SPI_ENGINE_REG_RESET   0x40

◆ SPI_ENGINE_REG_SDI_DATA_FIFO

#define SPI_ENGINE_REG_SDI_DATA_FIFO   0xE8

◆ SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK

#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK   0xEC

◆ SPI_ENGINE_REG_SDI_FIFO_LEVEL

#define SPI_ENGINE_REG_SDI_FIFO_LEVEL   0xD8

◆ SPI_ENGINE_REG_SDO_DATA_FIFO

#define SPI_ENGINE_REG_SDO_DATA_FIFO   0xE4

◆ SPI_ENGINE_REG_SDO_FIFO_ROOM

#define SPI_ENGINE_REG_SDO_FIFO_ROOM   0xD4

◆ SPI_ENGINE_REG_SYNC_ID

#define SPI_ENGINE_REG_SYNC_ID   0xC0

◆ SPI_ENGINE_REG_VERSION

#define SPI_ENGINE_REG_VERSION   0x00

◆ SPI_ENGINE_SYNC_TRANSFER_BEGIN

#define SPI_ENGINE_SYNC_TRANSFER_BEGIN   BIT(1)

◆ SPI_ENGINE_SYNC_TRANSFER_END

#define SPI_ENGINE_SYNC_TRANSFER_END   BIT(2)

◆ SPI_ENGINE_VERSION_MAJOR

#define SPI_ENGINE_VERSION_MAJOR (   x)    ((x >> 16) & 0xff)

◆ SPI_ENGINE_VERSION_MINOR

#define SPI_ENGINE_VERSION_MINOR (   x)    ((x >> 8) & 0xff)

◆ SPI_ENGINE_VERSION_PATCH

#define SPI_ENGINE_VERSION_PATCH (   x)    (x & 0xff)

Typedef Documentation

◆ spi_engine_cmd_queue

◆ spi_engine_msg

SPI_ENGINE_MISC_SYNC
#define SPI_ENGINE_MISC_SYNC
Definition: spi_engine_private.h:80
SPI_ENGINE_INST_ASSERT
#define SPI_ENGINE_INST_ASSERT
Definition: spi_engine_private.h:73
SPI_ENGINE_MISC_SLEEP
#define SPI_ENGINE_MISC_SLEEP
Definition: spi_engine_private.h:81
SPI_ENGINE_INST_TRANSFER
#define SPI_ENGINE_INST_TRANSFER
Definition: spi_engine_private.h:72
SPI_ENGINE_INST_CONFIG
#define SPI_ENGINE_INST_CONFIG
Definition: spi_engine_private.h:74
SPI_ENGINE_INST_MISC
#define SPI_ENGINE_INST_MISC
Definition: spi_engine_private.h:76
SPI_ENGINE_CMD
#define SPI_ENGINE_CMD(inst, arg1, arg2)
Definition: spi_engine_private.h:111