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Public Attributes | List of all members
adxcvr_init Struct Reference

#include <altera_adxcvr.h>

Public Attributes

const char * name
 
uint32_t base
 
uint32_t adxcfg_base [4]
 
uint32_t atx_pll_base
 
uint32_t lane_rate_khz
 
uint32_t parent_rate_khz
 
uint32_t sys_clk_sel
 
uint32_t out_clk_sel
 
bool cpll_enable
 
bool lpm_enable
 
uint32_t ref_rate_khz
 

Member Data Documentation

◆ adxcfg_base

uint32_t adxcvr_init::adxcfg_base[4]

◆ atx_pll_base

uint32_t adxcvr_init::atx_pll_base

◆ base

uint32_t adxcvr_init::base

Base address

◆ cpll_enable

bool adxcvr_init::cpll_enable

Enable CPLL for the transceiver

◆ lane_rate_khz

uint32_t adxcvr_init::lane_rate_khz

Lane rate in KHz

◆ lpm_enable

bool adxcvr_init::lpm_enable

Enable LPM mode for the transceiver. Otherwise use DFE.

◆ name

const char * adxcvr_init::name

Device Name

◆ out_clk_sel

uint32_t adxcvr_init::out_clk_sel

Controls the OUTCLKSEL multiplexer, controlling what will be forwarded to OUTCLK pin.

◆ parent_rate_khz

uint32_t adxcvr_init::parent_rate_khz

◆ ref_rate_khz

uint32_t adxcvr_init::ref_rate_khz

Reference Clock rate

◆ sys_clk_sel

uint32_t adxcvr_init::sys_clk_sel

Select the PLL reference clock source to be forwarded to the OUTCLK MUX: 0-CPLL, 3-QPLL0.


The documentation for this struct was generated from the following files: