no-OS
Macros | Functions
xilinx_transceiver.c File Reference

Driver for the Xilinx High-speed transceiver dynamic reconfiguration. More...

#include <stdlib.h>
#include <stdio.h>
#include <inttypes.h>
#include "no_os_util.h"
#include "no_os_error.h"
#include "axi_adxcvr.h"
#include "xilinx_transceiver.h"
Include dependency graph for xilinx_transceiver.c:

Macros

#define OUT_DIV_ADDR   0x88
 
#define OUT_DIV_TX_OFFSET   0x4
 
#define OUT_DIV_RX_OFFSET   0x0
 
#define RXCDR_CFG0_ADDR   0xa8
 
#define RXCDR_CFG0_MASK   0xffff
 
#define RXCDR_CFG1_ADDR   0xa9
 
#define RXCDR_CFG1_MASK   0xffff
 
#define RXCDR_CFG2_ADDR   0xaa
 
#define RXCDR_CFG2_MASK   0xffff
 
#define RXCDR_CFG3_ADDR   0xab
 
#define RXCDR_CFG3_MASK   0xffff
 
#define RXCDR_CFG4_ADDR   0xac
 
#define RXCDR_CFG4_MASK   0x00ff
 
#define RX_DFE_LPM_CFG_ADDR   0x29
 
#define RX_DFE_LPM_CFG_MASK   0xffff
 
#define QPLL_CFG0_ADDR   0x32
 
#define QPLL_CFG0_LOWBAND_MASK   0x0040
 
#define QPLL_CFG1_ADDR   0x33
 
#define QPLL_REFCLK_DIV_M_MASK   0xf800
 
#define QPLL_REFCLK_DIV_M_OFFSET   11
 
#define QPLL_REFCLK_DIV_M(x)   ((x) << 11)
 
#define QPLL_FBDIV_N_ADDR   0x36
 
#define QPLL_FBDIV_N_MASK   0x03ff
 
#define QPLL_FBDIV_RATIO_ADDR   0x37
 
#define QPLL_FBDIV_RATIO_MASK   0x0040
 
#define CPLL_CFG0_ADDR   0x5c
 
#define CPLL_CFG0_MASK   0xff00
 
#define CPLL_CFG1_ADDR   0x5d
 
#define CPLL_CFG1_MASK   0xffff
 
#define CPLL_REFCLK_DIV_M_ADDR   0x5e
 
#define CPLL_REFCLK_DIV_M_MASK   0x1f00
 
#define CPLL_FB_DIV_45_N1_MASK   0x0080
 
#define CPLL_FBDIV_N2_MASK   0x007f
 
#define RX_CLK25_DIV   0x11
 
#define RX_CLK25_DIV_OFFSET   6
 
#define RX_CLK25_DIV_MASK   0x07c0
 
#define TX_CLK25_DIV   0x6a
 
#define TX_CLK25_DIV_MASK   0x1f
 
#define QPLL0_FBDIV_DIV   0x14
 
#define QPLL0_REFCLK_DIV   0x18
 
#define QPLL1_FBDIV   0x94
 
#define QPLL1_REFCLK_DIV   0x98
 
#define QPLL_FBDIV(x)   (0x14 + (x) * 0x80)
 
#define QPLL_REFCLK_DIV(x)   (0x18 + (x) * 0x80)
 

Functions

int32_t xilinx_xcvr_write (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t reg_addr, uint32_t reg_val)
 xilinx_xcvr_write More...
 
int32_t xilinx_xcvr_read (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t reg_addr, uint32_t *reg_val)
 xilinx_xcvr_read More...
 
int32_t xilinx_xcvr_drp_read (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t reg, uint32_t *val)
 xilinx_xcvr_drp_read More...
 
int32_t xilinx_xcvr_drp_write (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t reg, uint32_t val)
 xilinx_xcvr_drp_write More...
 
int32_t xilinx_xcvr_drp_update (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t reg, uint32_t mask, uint32_t val)
 xilinx_xcvr_drp_update More...
 
int32_t xilinx_xcvr_gth3_configure_cdr (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t out_div)
 xilinx_xcvr_gth3_configure_cdr More...
 
int32_t xilinx_xcvr_gtx2_configure_cdr (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t lane_rate, uint32_t out_div, bool lpm_enable)
 xilinx_xcvr_gtx2_configure_cdr More...
 
int32_t xilinx_xcvr_configure_cdr (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t lane_rate, uint32_t out_div, bool lpm_enable)
 xilinx_xcvr_configure_cdr More...
 
int32_t xilinx_xcvr_check_lane_rate (struct xilinx_xcvr *xcvr, uint32_t lane_rate_khz)
 xilinx_xcvr_check_lane_rate More...
 
int32_t xilinx_xcvr_configure_lpm_dfe_mode (struct xilinx_xcvr *xcvr, uint32_t drp_port, bool lpm)
 xilinx_xcvr_configure_lpm_dfe_mode More...
 
int32_t xilinx_xcvr_calc_cpll_config (struct xilinx_xcvr *xcvr, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_cpll_config *conf, uint32_t *out_div)
 xilinx_xcvr_calc_cpll_config More...
 
int32_t xilinx_xcvr_calc_qpll_config (struct xilinx_xcvr *xcvr, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_qpll_config *conf, uint32_t *out_div)
 xilinx_xcvr_calc_qpll_config More...
 
int32_t xilinx_xcvr_gth34_cpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_cpll_config *conf)
 xilinx_xcvr_gth34_cpll_read_config More...
 
int32_t xilinx_xcvr_gtx2_cpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_cpll_config *conf)
 xilinx_xcvr_gtx2_cpll_read_config More...
 
int32_t xilinx_xcvr_cpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_cpll_config *conf)
 xilinx_xcvr_cpll_read_config More...
 
int32_t xilinx_xcvr_gth34_cpll_write_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_cpll_config *conf)
 xilinx_xcvr_gth34_cpll_write_config More...
 
int32_t xilinx_xcvr_gtx2_cpll_write_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_cpll_config *conf)
 xilinx_xcvr_gtx2_cpll_write_config More...
 
int32_t xilinx_xcvr_cpll_write_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_cpll_config *conf)
 xilinx_xcvr_cpll_write_config More...
 
int32_t xilinx_xcvr_cpll_calc_lane_rate (struct xilinx_xcvr *xcvr, uint32_t refclk_khz, const struct xilinx_xcvr_cpll_config *conf, uint32_t out_div)
 xilinx_xcvr_cpll_calc_lane_rate More...
 
int32_t xilinx_xcvr_gth34_qpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_qpll_config *conf)
 xilinx_xcvr_gth34_qpll_read_config More...
 
int32_t xilinx_xcvr_gtx2_qpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_qpll_config *conf)
 xilinx_xcvr_gtx2_qpll_read_config More...
 
int32_t xilinx_xcvr_qpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_qpll_config *conf)
 xilinx_xcvr_qpll_read_config More...
 
int32_t xilinx_xcvr_gth34_qpll_write_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_qpll_config *conf)
 xilinx_xcvr_gth34_qpll_write_config More...
 
int32_t xilinx_xcvr_gtx2_qpll_write_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_qpll_config *conf)
 xilinx_xcvr_gtx2_qpll_write_config More...
 
int32_t xilinx_xcvr_qpll_write_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_qpll_config *conf)
 xilinx_xcvr_qpll_write_config More...
 
int32_t xilinx_xcvr_qpll_calc_lane_rate (struct xilinx_xcvr *xcvr, uint32_t refclk_khz, const struct xilinx_xcvr_qpll_config *conf, uint32_t out_div)
 xilinx_xcvr_qpll_calc_lane_rate More...
 
int32_t xilinx_xcvr_gth34_read_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t *rx_out_div, uint32_t *tx_out_div)
 xilinx_xcvr_gth34_read_out_div More...
 
int32_t xilinx_xcvr_gtx2_read_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t *rx_out_div, uint32_t *tx_out_div)
 xilinx_xcvr_gtx2_read_out_div More...
 
int32_t xilinx_xcvr_read_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t *rx_out_div, uint32_t *tx_out_div)
 xilinx_xcvr_read_out_div More...
 
uint32_t xilinx_xcvr_out_div_to_val (uint32_t out_div)
 xilinx_xcvr_out_div_to_val More...
 
int32_t xilinx_xcvr_gth34_write_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_out_div, int32_t tx_out_div)
 xilinx_xcvr_gth34_write_out_div More...
 
int32_t xilinx_xcvr_gtx2_write_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_out_div, int32_t tx_out_div)
 xilinx_xcvr_gtx2_write_out_div More...
 
int32_t xilinx_xcvr_write_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_out_div, int32_t tx_out_div)
 xilinx_xcvr_write_out_div More...
 
int32_t xilinx_xcvr_write_rx_clk25_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
 xilinx_xcvr_write_rx_clk25_div More...
 
int32_t xilinx_xcvr_write_tx_clk25_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
 xilinx_xcvr_write_tx_clk25_div More...
 

Detailed Description

Driver for the Xilinx High-speed transceiver dynamic reconfiguration.

Author
DBogdan (drago.nosp@m.s.bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)

Copyright 2018(c) Analog Devices, Inc.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ CPLL_CFG0_ADDR

#define CPLL_CFG0_ADDR   0x5c

◆ CPLL_CFG0_MASK

#define CPLL_CFG0_MASK   0xff00

◆ CPLL_CFG1_ADDR

#define CPLL_CFG1_ADDR   0x5d

◆ CPLL_CFG1_MASK

#define CPLL_CFG1_MASK   0xffff

◆ CPLL_FB_DIV_45_N1_MASK

#define CPLL_FB_DIV_45_N1_MASK   0x0080

◆ CPLL_FBDIV_N2_MASK

#define CPLL_FBDIV_N2_MASK   0x007f

◆ CPLL_REFCLK_DIV_M_ADDR

#define CPLL_REFCLK_DIV_M_ADDR   0x5e

◆ CPLL_REFCLK_DIV_M_MASK

#define CPLL_REFCLK_DIV_M_MASK   0x1f00

◆ OUT_DIV_ADDR

#define OUT_DIV_ADDR   0x88

◆ OUT_DIV_RX_OFFSET

#define OUT_DIV_RX_OFFSET   0x0

◆ OUT_DIV_TX_OFFSET

#define OUT_DIV_TX_OFFSET   0x4

◆ QPLL0_FBDIV_DIV

#define QPLL0_FBDIV_DIV   0x14

◆ QPLL0_REFCLK_DIV

#define QPLL0_REFCLK_DIV   0x18

◆ QPLL1_FBDIV

#define QPLL1_FBDIV   0x94

◆ QPLL1_REFCLK_DIV

#define QPLL1_REFCLK_DIV   0x98

◆ QPLL_CFG0_ADDR

#define QPLL_CFG0_ADDR   0x32

◆ QPLL_CFG0_LOWBAND_MASK

#define QPLL_CFG0_LOWBAND_MASK   0x0040

◆ QPLL_CFG1_ADDR

#define QPLL_CFG1_ADDR   0x33

◆ QPLL_FBDIV

#define QPLL_FBDIV (   x)    (0x14 + (x) * 0x80)

◆ QPLL_FBDIV_N_ADDR

#define QPLL_FBDIV_N_ADDR   0x36

◆ QPLL_FBDIV_N_MASK

#define QPLL_FBDIV_N_MASK   0x03ff

◆ QPLL_FBDIV_RATIO_ADDR

#define QPLL_FBDIV_RATIO_ADDR   0x37

◆ QPLL_FBDIV_RATIO_MASK

#define QPLL_FBDIV_RATIO_MASK   0x0040

◆ QPLL_REFCLK_DIV

#define QPLL_REFCLK_DIV (   x)    (0x18 + (x) * 0x80)

◆ QPLL_REFCLK_DIV_M

#define QPLL_REFCLK_DIV_M (   x)    ((x) << 11)

◆ QPLL_REFCLK_DIV_M_MASK

#define QPLL_REFCLK_DIV_M_MASK   0xf800

◆ QPLL_REFCLK_DIV_M_OFFSET

#define QPLL_REFCLK_DIV_M_OFFSET   11

◆ RX_CLK25_DIV

#define RX_CLK25_DIV   0x11

◆ RX_CLK25_DIV_MASK

#define RX_CLK25_DIV_MASK   0x07c0

◆ RX_CLK25_DIV_OFFSET

#define RX_CLK25_DIV_OFFSET   6

◆ RX_DFE_LPM_CFG_ADDR

#define RX_DFE_LPM_CFG_ADDR   0x29

◆ RX_DFE_LPM_CFG_MASK

#define RX_DFE_LPM_CFG_MASK   0xffff

◆ RXCDR_CFG0_ADDR

#define RXCDR_CFG0_ADDR   0xa8

◆ RXCDR_CFG0_MASK

#define RXCDR_CFG0_MASK   0xffff

◆ RXCDR_CFG1_ADDR

#define RXCDR_CFG1_ADDR   0xa9

◆ RXCDR_CFG1_MASK

#define RXCDR_CFG1_MASK   0xffff

◆ RXCDR_CFG2_ADDR

#define RXCDR_CFG2_ADDR   0xaa

◆ RXCDR_CFG2_MASK

#define RXCDR_CFG2_MASK   0xffff

◆ RXCDR_CFG3_ADDR

#define RXCDR_CFG3_ADDR   0xab

◆ RXCDR_CFG3_MASK

#define RXCDR_CFG3_MASK   0xffff

◆ RXCDR_CFG4_ADDR

#define RXCDR_CFG4_ADDR   0xac

◆ RXCDR_CFG4_MASK

#define RXCDR_CFG4_MASK   0x00ff

◆ TX_CLK25_DIV

#define TX_CLK25_DIV   0x6a

◆ TX_CLK25_DIV_MASK

#define TX_CLK25_DIV_MASK   0x1f

Function Documentation

◆ xilinx_xcvr_calc_cpll_config()

int32_t xilinx_xcvr_calc_cpll_config ( struct xilinx_xcvr xcvr,
uint32_t  refclk_khz,
uint32_t  lane_rate_khz,
struct xilinx_xcvr_cpll_config conf,
uint32_t *  out_div 
)

xilinx_xcvr_calc_cpll_config

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◆ xilinx_xcvr_calc_qpll_config()

int32_t xilinx_xcvr_calc_qpll_config ( struct xilinx_xcvr xcvr,
uint32_t  refclk_khz,
uint32_t  lane_rate_khz,
struct xilinx_xcvr_qpll_config conf,
uint32_t *  out_div 
)

xilinx_xcvr_calc_qpll_config

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◆ xilinx_xcvr_check_lane_rate()

int32_t xilinx_xcvr_check_lane_rate ( struct xilinx_xcvr xcvr,
uint32_t  lane_rate_khz 
)

xilinx_xcvr_check_lane_rate

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◆ xilinx_xcvr_configure_cdr()

int32_t xilinx_xcvr_configure_cdr ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  lane_rate,
uint32_t  out_div,
bool  lpm_enable 
)

xilinx_xcvr_configure_cdr

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◆ xilinx_xcvr_configure_lpm_dfe_mode()

int32_t xilinx_xcvr_configure_lpm_dfe_mode ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
bool  lpm 
)

xilinx_xcvr_configure_lpm_dfe_mode

◆ xilinx_xcvr_cpll_calc_lane_rate()

int32_t xilinx_xcvr_cpll_calc_lane_rate ( struct xilinx_xcvr xcvr,
uint32_t  refclk_khz,
const struct xilinx_xcvr_cpll_config conf,
uint32_t  out_div 
)

xilinx_xcvr_cpll_calc_lane_rate

◆ xilinx_xcvr_cpll_read_config()

int32_t xilinx_xcvr_cpll_read_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
struct xilinx_xcvr_cpll_config conf 
)

xilinx_xcvr_cpll_read_config

◆ xilinx_xcvr_cpll_write_config()

int32_t xilinx_xcvr_cpll_write_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
const struct xilinx_xcvr_cpll_config conf 
)

xilinx_xcvr_cpll_write_config

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◆ xilinx_xcvr_drp_read()

int32_t xilinx_xcvr_drp_read ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  reg,
uint32_t *  val 
)

xilinx_xcvr_drp_read

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◆ xilinx_xcvr_drp_update()

int32_t xilinx_xcvr_drp_update ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  reg,
uint32_t  mask,
uint32_t  val 
)

xilinx_xcvr_drp_update

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◆ xilinx_xcvr_drp_write()

int32_t xilinx_xcvr_drp_write ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  reg,
uint32_t  val 
)

xilinx_xcvr_drp_write

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◆ xilinx_xcvr_gth34_cpll_read_config()

int32_t xilinx_xcvr_gth34_cpll_read_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
struct xilinx_xcvr_cpll_config conf 
)

xilinx_xcvr_gth34_cpll_read_config

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◆ xilinx_xcvr_gth34_cpll_write_config()

int32_t xilinx_xcvr_gth34_cpll_write_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
const struct xilinx_xcvr_cpll_config conf 
)

xilinx_xcvr_gth34_cpll_write_config

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◆ xilinx_xcvr_gth34_qpll_read_config()

int32_t xilinx_xcvr_gth34_qpll_read_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
struct xilinx_xcvr_qpll_config conf 
)

xilinx_xcvr_gth34_qpll_read_config

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◆ xilinx_xcvr_gth34_qpll_write_config()

int32_t xilinx_xcvr_gth34_qpll_write_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
const struct xilinx_xcvr_qpll_config conf 
)

xilinx_xcvr_gth34_qpll_write_config

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◆ xilinx_xcvr_gth34_read_out_div()

int32_t xilinx_xcvr_gth34_read_out_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t *  rx_out_div,
uint32_t *  tx_out_div 
)

xilinx_xcvr_gth34_read_out_div

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◆ xilinx_xcvr_gth34_write_out_div()

int32_t xilinx_xcvr_gth34_write_out_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
int32_t  rx_out_div,
int32_t  tx_out_div 
)

xilinx_xcvr_gth34_write_out_div

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◆ xilinx_xcvr_gth3_configure_cdr()

int32_t xilinx_xcvr_gth3_configure_cdr ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  out_div 
)

xilinx_xcvr_gth3_configure_cdr

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◆ xilinx_xcvr_gtx2_configure_cdr()

int32_t xilinx_xcvr_gtx2_configure_cdr ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  lane_rate,
uint32_t  out_div,
bool  lpm_enable 
)

xilinx_xcvr_gtx2_configure_cdr

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◆ xilinx_xcvr_gtx2_cpll_read_config()

int32_t xilinx_xcvr_gtx2_cpll_read_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
struct xilinx_xcvr_cpll_config conf 
)

xilinx_xcvr_gtx2_cpll_read_config

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◆ xilinx_xcvr_gtx2_cpll_write_config()

int32_t xilinx_xcvr_gtx2_cpll_write_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
const struct xilinx_xcvr_cpll_config conf 
)

xilinx_xcvr_gtx2_cpll_write_config

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◆ xilinx_xcvr_gtx2_qpll_read_config()

int32_t xilinx_xcvr_gtx2_qpll_read_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
struct xilinx_xcvr_qpll_config conf 
)

xilinx_xcvr_gtx2_qpll_read_config

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◆ xilinx_xcvr_gtx2_qpll_write_config()

int32_t xilinx_xcvr_gtx2_qpll_write_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
const struct xilinx_xcvr_qpll_config conf 
)

xilinx_xcvr_gtx2_qpll_write_config

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◆ xilinx_xcvr_gtx2_read_out_div()

int32_t xilinx_xcvr_gtx2_read_out_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t *  rx_out_div,
uint32_t *  tx_out_div 
)

xilinx_xcvr_gtx2_read_out_div

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◆ xilinx_xcvr_gtx2_write_out_div()

int32_t xilinx_xcvr_gtx2_write_out_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
int32_t  rx_out_div,
int32_t  tx_out_div 
)

xilinx_xcvr_gtx2_write_out_div

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◆ xilinx_xcvr_out_div_to_val()

uint32_t xilinx_xcvr_out_div_to_val ( uint32_t  out_div)

xilinx_xcvr_out_div_to_val

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◆ xilinx_xcvr_qpll_calc_lane_rate()

int32_t xilinx_xcvr_qpll_calc_lane_rate ( struct xilinx_xcvr xcvr,
uint32_t  refclk_khz,
const struct xilinx_xcvr_qpll_config conf,
uint32_t  out_div 
)

xilinx_xcvr_qpll_calc_lane_rate

◆ xilinx_xcvr_qpll_read_config()

int32_t xilinx_xcvr_qpll_read_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
struct xilinx_xcvr_qpll_config conf 
)

xilinx_xcvr_qpll_read_config

◆ xilinx_xcvr_qpll_write_config()

int32_t xilinx_xcvr_qpll_write_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
const struct xilinx_xcvr_qpll_config conf 
)

xilinx_xcvr_qpll_write_config

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◆ xilinx_xcvr_read()

int32_t xilinx_xcvr_read ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  reg_addr,
uint32_t *  reg_val 
)

xilinx_xcvr_read

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◆ xilinx_xcvr_read_out_div()

int32_t xilinx_xcvr_read_out_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t *  rx_out_div,
uint32_t *  tx_out_div 
)

xilinx_xcvr_read_out_div

◆ xilinx_xcvr_write()

int32_t xilinx_xcvr_write ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  reg_addr,
uint32_t  reg_val 
)

xilinx_xcvr_write

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◆ xilinx_xcvr_write_out_div()

int32_t xilinx_xcvr_write_out_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
int32_t  rx_out_div,
int32_t  tx_out_div 
)

xilinx_xcvr_write_out_div

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◆ xilinx_xcvr_write_rx_clk25_div()

int32_t xilinx_xcvr_write_rx_clk25_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  div 
)

xilinx_xcvr_write_rx_clk25_div

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◆ xilinx_xcvr_write_tx_clk25_div()

int32_t xilinx_xcvr_write_tx_clk25_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  div 
)

xilinx_xcvr_write_tx_clk25_div

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