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xilinx_transceiver.h File Reference

Driver for the Xilinx High-speed transceiver dynamic reconfiguration. More...

#include <stdint.h>
#include <stdbool.h>
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Classes

struct  xilinx_xcvr
 
struct  xilinx_xcvr_cpll_config
 
struct  xilinx_xcvr_qpll_config
 

Macros

#define AXI_PCORE_VER(major, minor, letter)   ((major << 16) | (minor << 8) | letter)
 
#define AXI_PCORE_VER_MAJOR(version)   (version >> 16)
 
#define AXI_PCORE_VER_MINOR(version)   ((version >> 8) & 0xff)
 
#define AXI_PCORE_VER_LETTER(version)   (version & 0xff)
 
#define AXI_REG_VERSION   0x0000
 
#define AXI_VERSION(x)   (((x) & 0xffffffff) << 0)
 
#define AXI_VERSION_IS(x, y, z)   ((x) << 16 | (y) << 8 | (z))
 
#define AXI_VERSION_MAJOR(x)   ((x) >> 16)
 
#define AXI_REG_FPGA_INFO   0x001C
 
#define AXI_REG_FPGA_VOLTAGE   0x0140
 
#define AXI_INFO_FPGA_TECH(info)   ((info) >> 24)
 
#define AXI_INFO_FPGA_FAMILY(info)   (((info) >> 16) & 0xff)
 
#define AXI_INFO_FPGA_SPEED_GRADE(info)   (((info) >> 8) & 0xff)
 
#define AXI_INFO_FPGA_DEV_PACKAGE(info)   ((info) & 0xff)
 
#define AXI_INFO_FPGA_VOLTAGE(val)   ((val) & 0xffff)
 
#define ENC_8B10B   810
 

Enumerations

enum  xilinx_xcvr_type {
  XILINX_XCVR_TYPE_S7_GTX2 = 2,
  XILINX_XCVR_TYPE_US_GTH3 = 5,
  XILINX_XCVR_TYPE_US_GTH4 = 8,
  XILINX_XCVR_TYPE_US_GTY4 = 9
}
 
enum  xilinx_xcvr_legacy_type {
  XILINX_XCVR_LEGACY_TYPE_S7_GTX2,
  XILINX_XCVR_LEGACY_TYPE_US_GTH3,
  XILINX_XCVR_LEGACY_TYPE_US_GTH4,
  XILINX_XCVR_LEGACY_TYPE_US_GTY4 = 4
}
 
enum  xilinx_xcvr_refclk_ppm {
  PM_200,
  PM_700,
  PM_1250
}
 
enum  axi_fgpa_technology {
  AXI_FPGA_TECH_UNKNOWN = 0,
  AXI_FPGA_TECH_SERIES7,
  AXI_FPGA_TECH_ULTRASCALE,
  AXI_FPGA_TECH_ULTRASCALE_PLUS,
  AXI_FPGA_TECH_UNKNOWN = 0,
  AXI_FPGA_TECH_SERIES7,
  AXI_FPGA_TECH_ULTRASCALE,
  AXI_FPGA_TECH_ULTRASCALE_PLUS
}
 
enum  axi_fpga_family {
  AXI_FPGA_FAMILY_UNKNOWN = 0,
  AXI_FPGA_FAMILY_ARTIX,
  AXI_FPGA_FAMILY_KINTEX,
  AXI_FPGA_FAMILY_VIRTEX,
  AXI_FPGA_FAMILY_ZYNQ,
  AXI_FPGA_FAMILY_UNKNOWN = 0,
  AXI_FPGA_FAMILY_ARTIX,
  AXI_FPGA_FAMILY_KINTEX,
  AXI_FPGA_FAMILY_VIRTEX,
  AXI_FPGA_FAMILY_ZYNQ
}
 
enum  axi_fpga_speed_grade {
  AXI_FPGA_SPEED_UNKNOWN = 0,
  AXI_FPGA_SPEED_1 = 10,
  AXI_FPGA_SPEED_1L = 11,
  AXI_FPGA_SPEED_1H = 12,
  AXI_FPGA_SPEED_1HV = 13,
  AXI_FPGA_SPEED_1LV = 14,
  AXI_FPGA_SPEED_2 = 20,
  AXI_FPGA_SPEED_2L = 21,
  AXI_FPGA_SPEED_2LV = 22,
  AXI_FPGA_SPEED_3 = 30,
  AXI_FPGA_SPEED_UNKNOWN = 0,
  AXI_FPGA_SPEED_1 = 10,
  AXI_FPGA_SPEED_1L = 11,
  AXI_FPGA_SPEED_1H = 12,
  AXI_FPGA_SPEED_1HV = 13,
  AXI_FPGA_SPEED_1LV = 14,
  AXI_FPGA_SPEED_2 = 20,
  AXI_FPGA_SPEED_2L = 21,
  AXI_FPGA_SPEED_2LV = 22,
  AXI_FPGA_SPEED_3 = 30
}
 
enum  axi_fpga_dev_pack {
  AXI_FPGA_DEV_UNKNOWN = 0,
  AXI_FPGA_DEV_RF,
  AXI_FPGA_DEV_FL,
  AXI_FPGA_DEV_FF,
  AXI_FPGA_DEV_FB,
  AXI_FPGA_DEV_HC,
  AXI_FPGA_DEV_FH,
  AXI_FPGA_DEV_CS,
  AXI_FPGA_DEV_CP,
  AXI_FPGA_DEV_FT,
  AXI_FPGA_DEV_FG,
  AXI_FPGA_DEV_SB,
  AXI_FPGA_DEV_RB,
  AXI_FPGA_DEV_RS,
  AXI_FPGA_DEV_CL,
  AXI_FPGA_DEV_SF,
  AXI_FPGA_DEV_BA,
  AXI_FPGA_DEV_FA
}
 

Functions

int32_t xilinx_xcvr_check_lane_rate (struct xilinx_xcvr *xcvr, uint32_t lane_rate_khz)
 xilinx_xcvr_check_lane_rate More...
 
int32_t xilinx_xcvr_configure_cdr (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t lane_rate, uint32_t out_div, bool lpm_enable)
 xilinx_xcvr_configure_cdr More...
 
int32_t xilinx_xcvr_configure_lpm_dfe_mode (struct xilinx_xcvr *xcvr, uint32_t drp_port, bool lpm)
 xilinx_xcvr_configure_lpm_dfe_mode More...
 
int32_t xilinx_xcvr_calc_cpll_config (struct xilinx_xcvr *xcvr, uint32_t refclk_hz, uint32_t lane_rate_khz, struct xilinx_xcvr_cpll_config *conf, uint32_t *out_div)
 xilinx_xcvr_calc_cpll_config More...
 
int32_t xilinx_xcvr_cpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_cpll_config *conf)
 xilinx_xcvr_cpll_read_config More...
 
int32_t xilinx_xcvr_cpll_write_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_cpll_config *conf)
 xilinx_xcvr_cpll_write_config More...
 
int32_t xilinx_xcvr_cpll_calc_lane_rate (struct xilinx_xcvr *xcvr, uint32_t refclk_khz, const struct xilinx_xcvr_cpll_config *conf, uint32_t out_div)
 xilinx_xcvr_cpll_calc_lane_rate More...
 
int32_t xilinx_xcvr_calc_qpll_config (struct xilinx_xcvr *xcvr, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_qpll_config *conf, uint32_t *out_div)
 xilinx_xcvr_calc_qpll_config More...
 
int32_t xilinx_xcvr_qpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_qpll_config *conf)
 xilinx_xcvr_qpll_read_config More...
 
int32_t xilinx_xcvr_qpll_write_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_qpll_config *conf)
 xilinx_xcvr_qpll_write_config More...
 
int32_t xilinx_xcvr_qpll_calc_lane_rate (struct xilinx_xcvr *xcvr, uint32_t refclk_hz, const struct xilinx_xcvr_qpll_config *conf, uint32_t out_div)
 xilinx_xcvr_qpll_calc_lane_rate More...
 
int32_t xilinx_xcvr_read_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t *rx_out_div, uint32_t *tx_out_div)
 xilinx_xcvr_read_out_div More...
 
int32_t xilinx_xcvr_write_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_out_div, int32_t tx_out_div)
 xilinx_xcvr_write_out_div More...
 
int32_t xilinx_xcvr_write_rx_clk25_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
 xilinx_xcvr_write_rx_clk25_div More...
 
int32_t xilinx_xcvr_write_tx_clk25_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
 xilinx_xcvr_write_tx_clk25_div More...
 

Detailed Description

Driver for the Xilinx High-speed transceiver dynamic reconfiguration.

Author
DBogdan (drago.nosp@m.s.bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)

Copyright 2018(c) Analog Devices, Inc.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ AXI_INFO_FPGA_DEV_PACKAGE

#define AXI_INFO_FPGA_DEV_PACKAGE (   info)    ((info) & 0xff)

◆ AXI_INFO_FPGA_FAMILY

#define AXI_INFO_FPGA_FAMILY (   info)    (((info) >> 16) & 0xff)

◆ AXI_INFO_FPGA_SPEED_GRADE

#define AXI_INFO_FPGA_SPEED_GRADE (   info)    (((info) >> 8) & 0xff)

◆ AXI_INFO_FPGA_TECH

#define AXI_INFO_FPGA_TECH (   info)    ((info) >> 24)

◆ AXI_INFO_FPGA_VOLTAGE

#define AXI_INFO_FPGA_VOLTAGE (   val)    ((val) & 0xffff)

◆ AXI_PCORE_VER

#define AXI_PCORE_VER (   major,
  minor,
  letter 
)    ((major << 16) | (minor << 8) | letter)

◆ AXI_PCORE_VER_LETTER

#define AXI_PCORE_VER_LETTER (   version)    (version & 0xff)

◆ AXI_PCORE_VER_MAJOR

#define AXI_PCORE_VER_MAJOR (   version)    (version >> 16)

◆ AXI_PCORE_VER_MINOR

#define AXI_PCORE_VER_MINOR (   version)    ((version >> 8) & 0xff)

◆ AXI_REG_FPGA_INFO

#define AXI_REG_FPGA_INFO   0x001C

◆ AXI_REG_FPGA_VOLTAGE

#define AXI_REG_FPGA_VOLTAGE   0x0140

◆ AXI_REG_VERSION

#define AXI_REG_VERSION   0x0000

◆ AXI_VERSION

#define AXI_VERSION (   x)    (((x) & 0xffffffff) << 0)

◆ AXI_VERSION_IS

#define AXI_VERSION_IS (   x,
  y,
 
)    ((x) << 16 | (y) << 8 | (z))

◆ AXI_VERSION_MAJOR

#define AXI_VERSION_MAJOR (   x)    ((x) >> 16)

◆ ENC_8B10B

#define ENC_8B10B   810

Enumeration Type Documentation

◆ axi_fgpa_technology

Enumerator
AXI_FPGA_TECH_UNKNOWN 
AXI_FPGA_TECH_SERIES7 
AXI_FPGA_TECH_ULTRASCALE 
AXI_FPGA_TECH_ULTRASCALE_PLUS 
AXI_FPGA_TECH_UNKNOWN 
AXI_FPGA_TECH_SERIES7 
AXI_FPGA_TECH_ULTRASCALE 
AXI_FPGA_TECH_ULTRASCALE_PLUS 

◆ axi_fpga_dev_pack

Enumerator
AXI_FPGA_DEV_UNKNOWN 
AXI_FPGA_DEV_RF 
AXI_FPGA_DEV_FL 
AXI_FPGA_DEV_FF 
AXI_FPGA_DEV_FB 
AXI_FPGA_DEV_HC 
AXI_FPGA_DEV_FH 
AXI_FPGA_DEV_CS 
AXI_FPGA_DEV_CP 
AXI_FPGA_DEV_FT 
AXI_FPGA_DEV_FG 
AXI_FPGA_DEV_SB 
AXI_FPGA_DEV_RB 
AXI_FPGA_DEV_RS 
AXI_FPGA_DEV_CL 
AXI_FPGA_DEV_SF 
AXI_FPGA_DEV_BA 
AXI_FPGA_DEV_FA 

◆ axi_fpga_family

Enumerator
AXI_FPGA_FAMILY_UNKNOWN 
AXI_FPGA_FAMILY_ARTIX 
AXI_FPGA_FAMILY_KINTEX 
AXI_FPGA_FAMILY_VIRTEX 
AXI_FPGA_FAMILY_ZYNQ 
AXI_FPGA_FAMILY_UNKNOWN 
AXI_FPGA_FAMILY_ARTIX 
AXI_FPGA_FAMILY_KINTEX 
AXI_FPGA_FAMILY_VIRTEX 
AXI_FPGA_FAMILY_ZYNQ 

◆ axi_fpga_speed_grade

Enumerator
AXI_FPGA_SPEED_UNKNOWN 
AXI_FPGA_SPEED_1 
AXI_FPGA_SPEED_1L 
AXI_FPGA_SPEED_1H 
AXI_FPGA_SPEED_1HV 
AXI_FPGA_SPEED_1LV 
AXI_FPGA_SPEED_2 
AXI_FPGA_SPEED_2L 
AXI_FPGA_SPEED_2LV 
AXI_FPGA_SPEED_3 
AXI_FPGA_SPEED_UNKNOWN 
AXI_FPGA_SPEED_1 
AXI_FPGA_SPEED_1L 
AXI_FPGA_SPEED_1H 
AXI_FPGA_SPEED_1HV 
AXI_FPGA_SPEED_1LV 
AXI_FPGA_SPEED_2 
AXI_FPGA_SPEED_2L 
AXI_FPGA_SPEED_2LV 
AXI_FPGA_SPEED_3 

◆ xilinx_xcvr_legacy_type

Enumerator
XILINX_XCVR_LEGACY_TYPE_S7_GTX2 
XILINX_XCVR_LEGACY_TYPE_US_GTH3 
XILINX_XCVR_LEGACY_TYPE_US_GTH4 
XILINX_XCVR_LEGACY_TYPE_US_GTY4 

◆ xilinx_xcvr_refclk_ppm

Enumerator
PM_200 
PM_700 
PM_1250 

◆ xilinx_xcvr_type

Enumerator
XILINX_XCVR_TYPE_S7_GTX2 
XILINX_XCVR_TYPE_US_GTH3 
XILINX_XCVR_TYPE_US_GTH4 
XILINX_XCVR_TYPE_US_GTY4 

Function Documentation

◆ xilinx_xcvr_calc_cpll_config()

int32_t xilinx_xcvr_calc_cpll_config ( struct xilinx_xcvr xcvr,
uint32_t  refclk_hz,
uint32_t  lane_rate_khz,
struct xilinx_xcvr_cpll_config conf,
uint32_t *  out_div 
)

xilinx_xcvr_calc_cpll_config

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◆ xilinx_xcvr_calc_qpll_config()

int32_t xilinx_xcvr_calc_qpll_config ( struct xilinx_xcvr xcvr,
uint32_t  refclk_khz,
uint32_t  lane_rate_khz,
struct xilinx_xcvr_qpll_config conf,
uint32_t *  out_div 
)

xilinx_xcvr_calc_qpll_config

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◆ xilinx_xcvr_check_lane_rate()

int32_t xilinx_xcvr_check_lane_rate ( struct xilinx_xcvr xcvr,
uint32_t  lane_rate_khz 
)

xilinx_xcvr_check_lane_rate

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◆ xilinx_xcvr_configure_cdr()

int32_t xilinx_xcvr_configure_cdr ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  lane_rate,
uint32_t  out_div,
bool  lpm_enable 
)

xilinx_xcvr_configure_cdr

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◆ xilinx_xcvr_configure_lpm_dfe_mode()

int32_t xilinx_xcvr_configure_lpm_dfe_mode ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
bool  lpm 
)

xilinx_xcvr_configure_lpm_dfe_mode

◆ xilinx_xcvr_cpll_calc_lane_rate()

int32_t xilinx_xcvr_cpll_calc_lane_rate ( struct xilinx_xcvr xcvr,
uint32_t  refclk_khz,
const struct xilinx_xcvr_cpll_config conf,
uint32_t  out_div 
)

xilinx_xcvr_cpll_calc_lane_rate

◆ xilinx_xcvr_cpll_read_config()

int32_t xilinx_xcvr_cpll_read_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
struct xilinx_xcvr_cpll_config conf 
)

xilinx_xcvr_cpll_read_config

◆ xilinx_xcvr_cpll_write_config()

int32_t xilinx_xcvr_cpll_write_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
const struct xilinx_xcvr_cpll_config conf 
)

xilinx_xcvr_cpll_write_config

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◆ xilinx_xcvr_qpll_calc_lane_rate()

int32_t xilinx_xcvr_qpll_calc_lane_rate ( struct xilinx_xcvr xcvr,
uint32_t  refclk_hz,
const struct xilinx_xcvr_qpll_config conf,
uint32_t  out_div 
)

xilinx_xcvr_qpll_calc_lane_rate

◆ xilinx_xcvr_qpll_read_config()

int32_t xilinx_xcvr_qpll_read_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
struct xilinx_xcvr_qpll_config conf 
)

xilinx_xcvr_qpll_read_config

◆ xilinx_xcvr_qpll_write_config()

int32_t xilinx_xcvr_qpll_write_config ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
const struct xilinx_xcvr_qpll_config conf 
)

xilinx_xcvr_qpll_write_config

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◆ xilinx_xcvr_read_out_div()

int32_t xilinx_xcvr_read_out_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t *  rx_out_div,
uint32_t *  tx_out_div 
)

xilinx_xcvr_read_out_div

◆ xilinx_xcvr_write_out_div()

int32_t xilinx_xcvr_write_out_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
int32_t  rx_out_div,
int32_t  tx_out_div 
)

xilinx_xcvr_write_out_div

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◆ xilinx_xcvr_write_rx_clk25_div()

int32_t xilinx_xcvr_write_rx_clk25_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  div 
)

xilinx_xcvr_write_rx_clk25_div

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◆ xilinx_xcvr_write_tx_clk25_div()

int32_t xilinx_xcvr_write_tx_clk25_div ( struct xilinx_xcvr xcvr,
uint32_t  drp_port,
uint32_t  div 
)

xilinx_xcvr_write_tx_clk25_div

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