ad9265 Reference Design Integration

This page outlines the HDL reference design integration for the ad9265 reference design for the Analog Devices AD9265 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants:

• Base reference design documentation
• Supported FPGA carriers:
  • ZC706
• Supported design variants:
  • RX

Reference Design

HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.

The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above.

HDL Worflow Advisor Port Mappings

When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core:

Type	Target Platform Interface (MATLAB)	Reference Design Connection (Vivado)	Width	Reference Design Variant
VALID-OUT	IP Data Valid OUT	axi_ad9265_dma/fifo_wr_en	1	RX
VALID-IN	IP Valid Rx Data IN	axi_ad9265/adc_valid	1	RX
DATA-OUT	IP Data 0 OUT	axi_ad9265_dma/fifo_wr_din	16	RX
DATA-IN	AD9265 ADC Data 0 IN	axi_ad9265/adc_data	16	RX